Wistron JV50-TR8 Schematic

5

4

3

2

1

Project code: 91.4FN01.001

JV50-TR_8VRAM Block Diagram

PCB P/N : 48.4FN02.001 REVISION : 09927-1

DDR2

D D

667/800 MHz

16,17

DDR2

667/800 MHz

CLK GEN.

ICS9LPRS480BKLFT 71.09480.A03 RTM880N-796-VB-GRT 71.00880.A03

C C

B B

A A

INT MIC

30

Line In

30

MIC In

30

INT.SPKR

30

Line Out (SPDIF)

30

RJ11

5

16,17

3

Codec

ALC888S

OP AMP

MAX9789

MODEM

MDC Card

667/800MHz

AZALIA

28

29

31

HDD SATA

ODD SATA

22

23

AMD Caspian CPU S1G3 (35W)

638-Pin uFCPGA638

OUT

4,5,6,7

IN

North Bridge

AMD RS880M

CPU I/F INTEGRATED GRAHPICS

LVDS, CRT I/F

8,9,10

South Bridge

AMD SB710

USB 2.0/1.1 ports

(10/100/1000Mb)ETHERNET

High Definition Audio

ATA 66/100

ACPI 1.1 LPC I/F

PCI/PCI BRIDGE

11,12,13,14,15

SATA

Mini USB Blue Tooth

Finger Printer

4

16X16

A-Link 4X4

USB

24

31

G792

16X

PCIex1

CardReader Realtek RTS5159

USB 2 Port

Camera

25

3

35

LPC BUS

Touch Pad

Daughter Board USB Board

CRT

LCD

HDMI

55,56,57,58,59

LAN

Giga LAN

BCM5784

New card

DY

KBC

Winbond

WPC773

38 36

08649-1

36

INT. KB

MS/MS Pro/xD /MMC/SD

5 in 1

20

19

21

Madison

VRAM DDR3

TXFM RJ45

26

34 28

27 27

PWR SW W83L351YG

Mini Card

WLAN

Mini Card

DY

BIOS

MXIC MX25L1605

37

3232

Daughter Board LED Board

08651-1

LPC

DEBUG CONN.

2

60,61,62,63

DY

33

37

Daughter Board Finger Printer Board

08650-1

Daughter Board Mini sensor Board

08696-1

PCB STACKUP

TOP

VCC

S

GND

BOTTOM

SYSTEM DC/DC

RT8205A

INPUTS

DCBATOUT

OUTPUTS

5V_S5(6A) 3D3V_S5(6A)

SYSTEM DC/DC

TPS51124

INPUTS OUTPUTS

DCBATOUT

1D1V_S0(7.5A) 1D2V_S0(4A)

SYSTEM DC/DC

RT8209B

INPUTS OUTPUTS

DCBATOUT 1D8V_S3(11A)

G9661

5V_S5

RT9161

3D3V_S0 2D5V_S0

G957

3D3V_S0

G9161

3D3V_S5

CHARGER

DCBATOUT

CPU DC/DC

INPUTS

DCBATOUT

JV50-TR8

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet of

BLOCK DIAGRAM

A3

JV50-TR8

Taipei Hsien 221, Taiwan, R.O.C.

1

1D1V_M92

(200mA)

1D5V_S0 (1A)

1D2V_S5 (400mA)

MAX8731

OUTPUTSINPUTS CHG_PWR

18V 6.0A

UP+5V

5V 100mA

ISL6265AHR

OUTPUTS

VCC_CORE_S0_0

0~1.55V 18A

VCC_CORE_S0_1

0~1.55V 18A

VDDNB

0~1.55V 18A

1 63Monday, October 05, 2009

46

47

48

49

50

45

-1

5

D D

C C

4

3

2

1

B B

JV50-TR8

A A

5

4

3

2

JV50-TR8

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet of

USB/PCIE Routing

A3

JV50-TR8

Taipei Hsien 221, Taiwan, R.O.C.

2 63Monday, October 05, 2009

1

-1

5

4

3

2

1

3D3V_S0 3D3V_CLK_VDD

R215

1 2

0R0603-PAD

12

C500

12

C501

SC10U10V5ZY-1GP

12

C502

C467

SCD1U10V2KX-4GP

DY

SCD1U10V2KX-4GP

SC10U10V5ZY-1GP

12

C453

12

C476

C462

SCD1U10V2KX-4GP

DY

SCD1U10V2KX-4GP

12

C492

12

C504

SCD1U10V2KX-4GP

3D3V_S0

R221

1 2

2R3J-GP

DY

12

C511

3D3V_48MPWR_S0

12

C506

C506 SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC4D7U6D3V3KX-GP

Due to PLL issue on current clock chip, the SBlink clock need to come from SRC clocks for RS740 and RS780. Future clock chip revision will fix this.

3000mA.80ohm

D D

3D3V_S0

R197

1 2

0R0603-PAD

C C

R231

R225

CLK_PCIE_SB11

CLK_PCIE_SB#11

CLK_PCIE_LAN26

CLK_PCIE_LAN#26

CLK_NB_GPPSB9

CLK_NB_GPPSB#9

CLK_PCIE_MINI133

CLK_PCIE_MINI1#33

CLK_PCIE_MINI233

CLK_PCIE_MINI2#33

CLK_PCIE_NEW34

CLK_PCIE_NEW#34

DY

10KR2J-3-GP

1 2

10KR2J-3-GP

1 2

R230

R224

3D3V_S0

SB A-Link

LAN

NB A-Link

MINI1

MINI2

NEW

JTAG_TCK56

B B

DY

10KR2J-3-GP

A A

10KR2J-3-GP

12

C459

SC10U6D3V3MX-GP

10KR2J-3-GP

1 2

10KR2J-3-GP

1 2

5

1D1V_CLK_VDDIO

12

C460

C454

SC10U6D3V3MX-GP

TP247TPAD14-GP TP247TPAD14-GP

CLK_NBHT_CLK9 CLK_NBHT_CLK#9

NB HT

R228

1 2

DY

R223

1 2

12

C461

SCD1U10V2KX-4GP

3D3V_CLK_VDD

SC1U10V2KX-1GP

R191 0R0402-PADR191 0R0402-PAD

1 2

R192 0R0402-PADR192 0R0402-PAD

1 2

R193 0R0402-PADR193 0R0402-PAD

1 2

R194 0R0402-PADR194 0R0402-PAD

1 2

R198 0R0402-PADR198 0R0402-PAD

1 2

R199 0R0402-PADR199 0R0402-PAD

1 2

R200 0R0402-PADR200 0R0402-PAD

1 2

R204 0R0402-PADR204 0R0402-PAD

1 2

R205 0R0402-PADR205 0R0402-PAD

1 2

R206 0R0402-PADR206 0R0402-PAD

1 2

R211 0R0402-PADR211 0R0402-PAD

1 2

R208 0R0402-PADR208 0R0402-PAD

1 2 1

0R2J-2-GP

REF0 REF1 REF2

12

C472

SCD1U10V2KX-4GP

R238

1 2

0R0603-PAD

DY

3D3V_S5

12

C495

C464

SCD1U10V2KX-4GP

12

C505

CLK_PCIE_SB_1 CLK_PCIE_SB#_1

CLK_PCIE_LAN_1 CLK_PCIE_LAN#_1

CLK_NB_GPPSB_1 CLK_NB_GPPSB#_1

CLK_PCIE_MINI1_1 CLK_PCIE_MINI1#_1

CLK_PCIE_MINI2_1 CLK_PCIE_MINI2#_1

CLK_PCIE_NEW_1 CLK_PCIE_NEW#_1

CLK_SRC0T_LPRS

1 2 1 2

8 7 6

SEL_27 REF2

SEL_SATA REF1

SEL_HTT66 REF0

CLK_SRC0C_LPRS

RN70

SRN10KJ-6-GP

R353

12

R217 0R0402-PADR217 0R0402-PAD R216 0R0402-PADR216 0R0402-PAD

3D3V_S0

CPU_CLK(200MHz)

3D3V_CLK_VDD

U20

1D1V_CLK_VDDIO

VDD_REF

3D3V_48MPWR_S0

CLK_NBHT_CLK_1 CLK_NBHT_CLK#_1

PD#

1

WLAN_CLKREQ#

2

WLAN2_CLKREQ#

3

RUNPWROK_D

45

27MHz non-spreading singled clock on pin 5

1

and 27MHz spread clock on pin 6

0 100MHz differential spreading SRC clock

*

1

100MHz non-spreading differential SATA clock 100MHz differential spreading SRC clock

*0

66MHz 3.3V single ended HTT clock

1 0 * 100MHz differential HTT clock

4

U20

26

VDDATIG

25

VDDATIG_IO

48

VDDCPU

47

VDDCPU_IO

16

VDDSRC

17

VDDSRC_IO

11

VDDSRC_IO

35

VDDSB_SRC

34

VDDSB_SRC_IO

40

VDDSATA

4

VDD

55

VDDHTT

56

VDDREF

63

VDD48

PD#

51

PD#

22

SRC0T_LPRS

21

SRC0C_LPRS

20

SRC1T_LPRS

19

SRC1C_LPRS

15

SRC2T_LPRS

14

SRC2C_LPRS

13

SRC3T_LPRS

12

SRC3C_LPRS

9

SRC4T_LPRS

8

SRC4C_LPRS SRC6T/SATAT_LPRS42GNDSATA

41

SRC6C/SATAC_LPRS

6

SRC7T_LPRS/27MHZ_SS

5

SRC7C_LPRS/27MHZ_NS

37

SB_SRC0T_LPRS

36

SB_SRC0C_LPRS

32

SB_SRC1T_LPRS

31

SB_SRC1C_LPRS

54

HTT0T_LPRS/66M

53

HTT0C_LPRS/66M

ICS9LPRS480BKLFT-GP

71.09480.A03

2ND = 71.00880.A03

RUNPWROK_D 42

ATIG0T_LPRS ATIG0C_LPRS ATIG1T_LPRS ATIG1C_LPRS

CPUKG0T_LPRS CPUKG0C_LPRS

REF0/SEL_HTT66

REF1/SEL_SATA

REF2/SEL_27

-1

SMBCLK SMBDAT

CLKREQ0# CLKREQ1# CLKREQ2# CLKREQ3# CLKREQ4#

48MHZ_0

GNDATIG

GND

GNDHTT GNDREF GNDCPU

GND48

GNDSRC GNDSRC

GNDSB_SRC

GND

REF0

X1 X2

61

GEN_XTAL_OUT

62

2 3

30 29 28 27

23 45 44 39 38

50 49

CLK_48

64

REF0

59

REF1

58

REF2

57

43 24 7 52 60 46 1

10 18

33 65

GEN_XTAL_IN

CLK_SMBCLK CLK_SMBDAT

CLK_PCIE_PEG_1

CLK_PCIE_PEG#_1 CLK_NB_GFX_1 CLK_NB_GFX#_1

CLKREQ0# CLKREQ2#

CPU_CLK_1 CPU_CLK#_1

R232

R232 150R2F-1-GP

150R2F-1-GP

12

75R2F-2-GP

OSC_14M_NB

1.1V 158R/90.9RRS780M

3

R218

1 2

DY

10MR2J-L-GP

CL=20pF±0.2pF

R214 0R0402-PADR214 0R0402-PAD

1 2

R213 0R0402-PADR213 0R0402-PAD

1 2

R187 0R0402-PADR187 0R0402-PAD R188 0R0402-PADR188 0R0402-PAD R189 0R0402-PADR189 0R0402-PAD R190 0R0402-PADR190 0R0402-PAD

TP153 TPAD14-GPTP153 TPAD14-GP

LAN_CLKREQ# 26

TP159 TPAD14-GPTP159 TPAD14-GP

WLAN_CLKREQ# 33 WLAN2_CLKREQ# 33

R222 0R0402-PADR222 0R0402-PAD R220 0R0402-PADR220 0R0402-PAD

R169 10R2J-2-GPR169 10R2J-2-GP

1 2

R170 33R2J-2-GPR170 33R2J-2-GP

SB

for TR

REF1

12

R235

X-14D31818M-35GP

1 2

1 2 1 2 1 2

1

DY

-

12

EC50

1 2 1 2

For SB710

R229

1 2

33R2F-3-GP

R234

75R2F-2-GP

CLK_NB_14M 9

C508

C508 SC39P50V2JN-1GP

SC39P50V2JN-1GP

1 2

X5

12

1 2

SC39P50V2JN-1GP

SMBC0_SB 12,16,17 SMBD0_SB 12,16,17

CLK_NB_GFX 9

CLK_NB_GFX# 9

82.30005.891

C509

2ND = 82.30005.951

CLK_PCIE_PEG 55

CLK_PCIE_PEG# 55

CLKREQ# Internal pull Low

CPU_CLK 6 CPU_CLK# 6

CLK48_USB 12

EC49

SC22P50V2JN-4GP

CLK48_5158E 32

CLK_SB_14M 11

2

12

DY

SC22P50V2JN-4GP

DY

12

SB

NB CLOCK INPUT TABLE

NB CLOCKS HT_REFCLKP HT_REFCLKN REFCLK_P REFCLK_N GFX_REFCLK GPP_REFCLK GPPSB_REFCLK 100M DIFF 100M DIFF

* RS780 can be used as clock buffer to output two PCIE referecence clocks By deault, chip will configured as input mode, BIOS can program it to output mode.

Clock chip has internal serial terminations for differencial pairs, external resistors are reserved for debug purpose.

RS740 RX780 RS780

66M SE(SINGLE END)

NC

14M SE (3.3V) 14M SE (1.8V) 14M SE (1.1V) NC NC vref

100M DIFF NC 100M DIFF

JV50-TR8

Title

ize Document Number Rev

Size Document Number Rev

S

A3

Date: Sheet of

100M DIFF 100M DIFF

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

CLKGEN_ICS9LPRS480

JV50-TR8

3 63Wednesday, November 04, 2009

1

100M DIFF 100M DIFF

100M DIFF(IN/OUT)*

NC or 100M DIFF OUTPUT

-1

5

D D

1D2V_S0

Place close to socket

12

C705

C704

SC4D7U6D3V3MX-2GP

C C

B B

C706

SC4D7U6D3V3MX-2GP

12

C707

SCD22U6D3V2KX-1GP

DY

4

3

2

1

1.5Amp

12

C703

SCD22U6D3V2KX-1GP

DY

12

C174

SC180P50V2JN-1GP

HT_NB_CPU_CAD_H08 HT_NB_CPU_CAD_L08 HT_NB_CPU_CAD_H18 HT_NB_CPU_CAD_L18 HT_NB_CPU_CAD_H28 HT_NB_CPU_CAD_L28 HT_NB_CPU_CAD_H38 HT_NB_CPU_CAD_L38 HT_NB_CPU_CAD_H48 HT_NB_CPU_CAD_L48 HT_NB_CPU_CAD_H58 HT_NB_CPU_CAD_L58 HT_NB_CPU_CAD_H68 HT_NB_CPU_CAD_L68 HT_NB_CPU_CAD_H78 HT_NB_CPU_CAD_L78 HT_NB_CPU_CAD_H88 HT_NB_CPU_CAD_L88 HT_NB_CPU_CAD_H98 HT_NB_CPU_CAD_L98 HT_NB_CPU_CAD_H108 HT_NB_CPU_CAD_L108 HT_NB_CPU_CAD_H118 HT_NB_CPU_CAD_L118 HT_NB_CPU_CAD_H128 HT_NB_CPU_CAD_L128 HT_NB_CPU_CAD_H138 HT_NB_CPU_CAD_L138 HT_NB_CPU_CAD_H148 HT_NB_CPU_CAD_L148 HT_NB_CPU_CAD_H158 HT_NB_CPU_CAD_L158

HT_NB_CPU_CLK_H08 HT_NB_CPU_CLK_L08 HT_NB_CPU_CLK_H18 HT_NB_CPU_CLK_L18

HT_NB_CPU_CTL_H08 HT_NB_CPU_CTL_L08 HT_NB_CPU_CTL_H18 HT_NB_CPU_CTL_L18

12

C177

SC180P50V2JN-1GP

DY

ACPU1A

D1

VLDT_A0

D2

VLDT_A1

D3

VLDT_A2

D4

VLDT_A3

E3

L0_CADIN_H0

E2

L0_CADIN_L0

E1

L0_CADIN_H1

F1

L0_CADIN_L1

G3

L0_CADIN_H2

G2

L0_CADIN_L2

G1

L0_CADIN_H3

H1

L0_CADIN_L3

J1

L0_CADIN_H4

K1

L0_CADIN_L4

L3

L0_CADIN_H5

L2

L0_CADIN_L5

L1

L0_CADIN_H6

M1

L0_CADIN_L6

N3

L0_CADIN_H7

N2

L0_CADIN_L7

E5

L0_CADIN_H8

F5

L0_CADIN_L8

F3

L0_CADIN_H9

F4

L0_CADIN_L9

G5

L0_CADIN_H10

H5

L0_CADIN_L10

H3

L0_CADIN_H11

H4

L0_CADIN_L11

K3

L0_CADIN_H12

K4

L0_CADIN_L12

L5

L0_CADIN_H13

M5

L0_CADIN_L13

M3

L0_CADIN_H14

M4

L0_CADIN_L14

N5

L0_CADIN_H15

P5

L0_CADIN_L15

J3

L0_CLKIN_H0

J2

L0_CLKIN_L0

J5

L0_CLKIN_H1

K5

L0_CLKIN_L1

N1

L0_CTLIN_H0

P1

L0_CTLIN_L0

P3

L0_CTLIN_H1

P4

L0_CTLIN_L1

SKT-CPU638P,DANUB

62.10055.111

2ND = 62.10055.251

HT LINK

VLDT_B0 VLDT_B1 VLDT_B2 VLDT_B3

L0_CADOUT_H0 L0_CADOUT_L0 L0_CADOUT_H1 L0_CADOUT_L1 L0_CADOUT_H2 L0_CADOUT_L2 L0_CADOUT_H3 L0_CADOUT_L3 L0_CADOUT_H4 L0_CADOUT_L4 L0_CADOUT_H5 L0_CADOUT_L5 L0_CADOUT_H6 L0_CADOUT_L6 L0_CADOUT_H7 L0_CADOUT_L7 L0_CADOUT_H8 L0_CADOUT_L8 L0_CADOUT_H9 L0_CADOUT_L9

L0_CADOUT_H10

L0_CADOUT_L10

L0_CADOUT_H11

L0_CADOUT_L11

L0_CADOUT_H12

L0_CADOUT_L12

L0_CADOUT_H13

L0_CADOUT_L13

L0_CADOUT_H14

L0_CADOUT_L14

L0_CADOUT_H15

L0_CADOUT_L15

L0_CLKOUT_H0

L0_CLKOUT_L0

L0_CLKOUT_H1

L0_CLKOUT_L1

L0_CTLOUT_H0

L0_CTLOUT_L0

L0_CTLOUT_H1

L0_CTLOUT_L1

AE2 AE3 AE4 AE5

AD1 AC1 AC2 AC3 AB1 AA1 AA2 AA3 W2 W3 V1 U1 U2 U3 T1 R1 AD4 AD3 AD5 AC5 AB4 AB3 AB5 AA5 Y5 W5 V4 V3 V5 U5 T4 T3

Y1 W1 Y4 Y3

R2 R3 T5 R5

HT_CPU_NB_CAD_H0 8 HT_CPU_NB_CAD_L0 8 HT_CPU_NB_CAD_H1 8 HT_CPU_NB_CAD_L1 8 HT_CPU_NB_CAD_H2 8 HT_CPU_NB_CAD_L2 8 HT_CPU_NB_CAD_H3 8 HT_CPU_NB_CAD_L3 8 HT_CPU_NB_CAD_H4 8 HT_CPU_NB_CAD_L4 8 HT_CPU_NB_CAD_H5 8 HT_CPU_NB_CAD_L5 8 HT_CPU_NB_CAD_H6 8 HT_CPU_NB_CAD_L6 8 HT_CPU_NB_CAD_H7 8 HT_CPU_NB_CAD_L7 8 HT_CPU_NB_CAD_H8 8 HT_CPU_NB_CAD_L8 8 HT_CPU_NB_CAD_H9 8 HT_CPU_NB_CAD_L9 8 HT_CPU_NB_CAD_H10 8 HT_CPU_NB_CAD_L10 8 HT_CPU_NB_CAD_H11 8 HT_CPU_NB_CAD_L11 8 HT_CPU_NB_CAD_H12 8 HT_CPU_NB_CAD_L12 8 HT_CPU_NB_CAD_H13 8 HT_CPU_NB_CAD_L13 8 HT_CPU_NB_CAD_H14 8 HT_CPU_NB_CAD_L14 8 HT_CPU_NB_CAD_H15 8 HT_CPU_NB_CAD_L15 8

HT_CPU_NB_CLK_H0 8 HT_CPU_NB_CLK_L0 8 HT_CPU_NB_CLK_H1 8 HT_CPU_NB_CLK_L1 8

HT_CPU_NB_CTL_H0 8 HT_CPU_NB_CTL_L0 8 HT_CPU_NB_CTL_H1 8 HT_CPU_NB_CTL_L1 8

SKT-BGA638H176

A A

5

4

3

2

JV50-TR8

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

CPU_HT_LINK I/F_(1/4)

Taipei Hsien 221, Taiwan, R.O.C.

JV50-TR8

4 63Monday, October 26, 2009

1

-1

5

Place near to CPU

D D

C262

SC4D7U6D3V3MX-2GP

1D8V_S3

C C

B B

A A

4.7u x 4 0.22u X 2 180P x 6

12

DY

MEM_MA0_ODT016,18 MEM_MA0_ODT116,18

MEM_MA0_CS#016,18 MEM_MA0_CS#116,18

MEM_MA_CKE016,18 MEM_MA_CKE116,18

MEM_MA_CLK0_P16 MEM_MA_CLK0_N16 MEM_MA_CLK1_P16 MEM_MA_CLK1_N16

MEM_MA_ADD016,18 MEM_MA_ADD116,18 MEM_MA_ADD216,18 MEM_MA_ADD316,18 MEM_MA_ADD416,18 MEM_MA_ADD516,18 MEM_MA_ADD616,18 MEM_MA_ADD716,18 MEM_MA_ADD816,18 MEM_MA_ADD916,18 MEM_MA_ADD1016,18 MEM_MA_ADD1116,18 MEM_MA_ADD1216,18 MEM_MA_ADD1316,18 MEM_MA_ADD1416,18 MEM_MA_ADD1516,18

MEM_MA_BANK016,18 MEM_MA_BANK116,18 MEM_MA_BANK216,18

MEM_MA_RAS#16,18 MEM_MA_CAS#16,18 MEM_MA_WE#16,18

12

C736

SC4D7U6D3V3MX-2GP

DY

R381

R381 39D2R2F-L-GP

39D2R2F-L-GP

1 2 1 2

R383

R383 39D2R2F-L-GP

39D2R2F-L-GP

C737

SC4D7U6D3V3MX-2GP

TP111TP111

12

C258

SC4D7U6D3V3MX-2GP

1

C258

SCD22U6D3V2KX-1GP

0D9V_S3

MEMZP MEMZN

MEM_RSVD_M1

C263

12

C254

DY

D10 C10 B10

AD10

AF10

AE10

H16 T19

V22 U21 V19

T20 U19 U20 V20

N19 N20 E16 F16 Y16

AA16

P19 P20

N21 M20 N22 M19 M22

M24

K22 R21

K20 V24 K24 K19

R20 R23

R19 T22 T24

12

SCD22U6D3V2KX-1GP

DY

ACPU1B

VTT1 VTT2 VTT3 VTT4

MEMZP MEMZN

RSVD_M1 MA0_ODT0

MA0_ODT1 MA1_ODT0 MA1_ODT1

MA0_CS_L0 MA0_CS_L1 MA1_CS_L0 MA1_CS_L1

J22

MA_CKE0

J20

MA_CKE1 MA_CLK_H5

MA_CLK_L5 MA_CLK_H1 MA_CLK_L1 MA_CLK_H7 MA_CLK_L7 MA_CLK_H4 MA_CLK_L4

MA_ADD0 MA_ADD1 MA_ADD2 MA_ADD3 MA_ADD4

L20

MA_ADD5 MA_ADD6

L21

MA_ADD7

L19

MA_ADD8 MA_ADD9 MA_ADD10

L22

MA_ADD11 MA_ADD12 MA_ADD13 MA_ADD14 MA_ADD15

MA_BANK0 MA_BANK1

J21

MA_BANK2 MA_RAS_L

MA_CAS_L MA_WE_L

SKT-CPU638P,DANUB

62.10055.111

12

C249

SC180P50V2JN-1GP

750 mA

MEM:CMD/CTRL/CLK

C255

SC180P50V2JN-1GP

VTT_SENSE

MEMVREF

RSVD_M2

MB0_ODT0 MB0_ODT1 MB1_ODT0

MB0_CS_L0 MB0_CS_L1 MB1_CS_L0

MB_CLK_H5 MB_CLK_L5 MB_CLK_H1 MB_CLK_L1 MB_CLK_H7 MB_CLK_L7 MB_CLK_H4 MB_CLK_L4

MB_ADD0 MB_ADD1 MB_ADD2 MB_ADD3 MB_ADD4 MB_ADD5 MB_ADD6 MB_ADD7 MB_ADD8

MB_ADD9 MB_ADD10 MB_ADD11 MB_ADD12 MB_ADD13 MB_ADD14 MB_ADD15

MB_BANK0 MB_BANK1 MB_BANK2

MB_RAS_L MB_CAS_L

MB_WE_L

12

VTT5 VTT6 VTT7 VTT8 VTT9

MB_CKE0 MB_CKE1

C250

4

12

C256

C251

DY

SC180P50V2JN-1GP

C251

SC180P50V2JN-1GP

C252

12

SC180P50V2JN-1GP

DY

CLOSE TO CPU

W10 AC10 AB10 AA10 A10

Y10 W17 B18 W26

W23 Y26

V26 W25 U22

J25 H26

P22 R22 A17 A18 AF18 AF17 R26 R25

P24 N24 P26 N23 N26 L23 N25 L24 M26 K26 T26 L26 L25 W24 J23 J24

R24 U26 J26

U25 U24 U23

VTT_SENSE

MEM_RSVD_M2

MEM_MB0_ODT0 17,18 MEM_MB0_ODT1 17,18

MEM_MB0_CS#0 17,18 MEM_MB0_CS#1 17,18

MEM_MB_CKE0 17,18 MEM_MB_CKE1 17,18

MEM_MB_CLK0_P 17 MEM_MB_CLK0_N 17 MEM_MB_CLK1_P 17 MEM_MB_CLK1_N 17

MEM_MB_ADD0 17,18 MEM_MB_ADD1 17,18 MEM_MB_ADD2 17,18 MEM_MB_ADD3 17,18 MEM_MB_ADD4 17,18 MEM_MB_ADD5 17,18 MEM_MB_ADD6 17,18 MEM_MB_ADD7 17,18 MEM_MB_ADD8 17,18 MEM_MB_ADD9 17,18 MEM_MB_ADD10 17,18 MEM_MB_ADD11 17,18 MEM_MB_ADD12 17,18 MEM_MB_ADD13 17,18 MEM_MB_ADD14 17,18 MEM_MB_ADD15 17,18

MEM_MB_BANK0 17,18 MEM_MB_BANK1 17,18 MEM_MB_BANK2 17,18

MEM_MB_RAS# 17,18 MEM_MB_CAS# 17,18 MEM_MB_WE# 17,18

1

TP106TPAD14-GPTP106TPAD14-GP

TP112TP112

SCD1U10V2KX-4GP

VREF_DDR_CLAW

C391

SC1KP50V2KX-1GP

3

MEM_MA_DATA016 MEM_MA_DATA116 MEM_MA_DATA216 MEM_MA_DATA316 MEM_MA_DATA416 MEM_MA_DATA516 MEM_MA_DATA616 MEM_MA_DATA716 MEM_MA_DATA816 MEM_MA_DATA916 MEM_MA_DATA1016 MEM_MA_DATA1116 MEM_MA_DATA1216 MEM_MA_DATA1316 MEM_MA_DATA1416 MEM_MA_DATA1516 MEM_MA_DATA1616 MEM_MA_DATA1716 MEM_MA_DATA1816 MEM_MA_DATA1916 MEM_MA_DATA2016 MEM_MA_DATA2116 MEM_MA_DATA2216 MEM_MA_DATA2316 MEM_MA_DATA2416 MEM_MA_DATA2516 MEM_MA_DATA2616 MEM_MA_DATA2716 MEM_MA_DATA2816 MEM_MA_DATA2916 MEM_MA_DATA3016 MEM_MA_DATA3116

1D8V_S3

12

C397

RN48

1

4

2 3

SRN1KJ-7-GP

C388

12

SRN1KJ-7-GP

12

SCD1U10V2KX-4GP

MEM_MA_DATA3216 MEM_MA_DATA3316 MEM_MA_DATA3416 MEM_MA_DATA3516 MEM_MA_DATA3616 MEM_MA_DATA3716 MEM_MA_DATA3816 MEM_MA_DATA3916 MEM_MA_DATA4016 MEM_MA_DATA4116 MEM_MA_DATA4216 MEM_MA_DATA4316 MEM_MA_DATA4416 MEM_MA_DATA4516 MEM_MA_DATA4616 MEM_MA_DATA4716 MEM_MA_DATA4816 MEM_MA_DATA4916 MEM_MA_DATA5016 MEM_MA_DATA5116 MEM_MA_DATA5216 MEM_MA_DATA5316 MEM_MA_DATA5416 MEM_MA_DATA5516 MEM_MA_DATA5616 MEM_MA_DATA5716 MEM_MA_DATA5816 MEM_MA_DATA5916 MEM_MA_DATA6016 MEM_MA_DATA6116 MEM_MA_DATA6216 MEM_MA_DATA6316

MEM_MA_DM016 MEM_MA_DM116 MEM_MA_DM216 MEM_MA_DM316 MEM_MA_DM416 MEM_MA_DM516 MEM_MA_DM616 MEM_MA_DM716

MEM_MA_DQS0_P16 MEM_MA_DQS0_N16 MEM_MA_DQS1_P16 MEM_MA_DQS1_N16 MEM_MA_DQS2_P16 MEM_MA_DQS2_N16 MEM_MA_DQS3_P16 MEM_MA_DQS3_N16 MEM_MA_DQS4_P16 MEM_MA_DQS4_N16 MEM_MA_DQS5_P16 MEM_MA_DQS5_N16 MEM_MA_DQS6_P16 MEM_MA_DQS6_N16 MEM_MA_DQS7_P16 MEM_MA_DQS7_N16

2

ACPU1C

G12 F12 H14 G14 H11 H12 C13 E13 H15 E15 E17 H17 E14 F14 C17 G17 G18 C19 D22 E20 E18 F18 B22 C23 F20 F22 H24

J19 E21 E22 H20 H22 Y24

AB24 AB22 AA21

W22 W21

Y22

AA22

Y20

AA20 AA18 AB18 AB21 AD21 AD19

Y18

AD17

W16 W14

Y14 Y17

AB17 AB15 AD15 AB13 AD13

Y12

W11 AB14 AA14 AB12 AA12

E12 C15 E19 F24

AC24

Y19

AB16

Y13 G13

H13 G16 G15 C22 C21 G22

G21 AD23 AC23 AB19 AB20

Y15

W15 W12 W13

SKT-CPU638P,DANUB

MA_DATA0 MA_DATA1 MA_DATA2 MA_DATA3 MA_DATA4 MA_DATA5 MA_DATA6 MA_DATA7 MA_DATA8 MA_DATA9 MA_DATA10 MA_DATA11 MA_DATA12 MA_DATA13 MA_DATA14 MA_DATA15 MA_DATA16 MA_DATA17 MA_DATA18 MA_DATA19 MA_DATA20 MA_DATA21 MA_DATA22 MA_DATA23 MA_DATA24 MA_DATA25 MA_DATA26 MA_DATA27 MA_DATA28 MA_DATA29 MA_DATA30 MA_DATA31 MA_DATA32 MA_DATA33 MA_DATA34 MA_DATA35 MA_DATA36 MA_DATA37 MA_DATA38 MA_DATA39 MA_DATA40 MA_DATA41 MA_DATA42 MA_DATA43 MA_DATA44 MA_DATA45 MA_DATA46 MA_DATA47 MA_DATA48 MA_DATA49 MA_DATA50 MA_DATA51 MA_DATA52 MA_DATA53 MA_DATA54 MA_DATA55 MA_DATA56 MA_DATA57 MA_DATA58 MA_DATA59 MA_DATA60 MA_DATA61 MA_DATA62 MA_DATA63

MA_DM0 MA_DM1 MA_DM2 MA_DM3 MA_DM4 MA_DM5 MA_DM6 MA_DM7

MA_DQS_H0 MA_DQS_L0 MA_DQS_H1 MA_DQS_L1 MA_DQS_H2 MA_DQS_L2 MA_DQS_H3 MA_DQS_L3 MA_DQS_H4 MA_DQS_L4 MA_DQS_H5 MA_DQS_L5 MA_DQS_H6 MA_DQS_L6 MA_DQS_H7 MA_DQS_L7

JV50-TR8

MEM:DATA

MB_DATA0 MB_DATA1 MB_DATA2 MB_DATA3 MB_DATA4 MB_DATA5 MB_DATA6 MB_DATA7 MB_DATA8

MB_DATA9 MB_DATA10 MB_DATA11 MB_DATA12 MB_DATA13 MB_DATA14 MB_DATA15 MB_DATA16 MB_DATA17 MB_DATA18 MB_DATA19 MB_DATA20 MB_DATA21 MB_DATA22 MB_DATA23 MB_DATA24 MB_DATA25 MB_DATA26 MB_DATA27 MB_DATA28 MB_DATA29 MB_DATA30 MB_DATA31 MB_DATA32 MB_DATA33 MB_DATA34 MB_DATA35 MB_DATA36 MB_DATA37 MB_DATA38 MB_DATA39 MB_DATA40 MB_DATA41 MB_DATA42 MB_DATA43 MB_DATA44 MB_DATA45 MB_DATA46 MB_DATA47 MB_DATA48 MB_DATA49 MB_DATA50 MB_DATA51 MB_DATA52 MB_DATA53 MB_DATA54 MB_DATA55 MB_DATA56 MB_DATA57 MB_DATA58 MB_DATA59 MB_DATA60 MB_DATA61 MB_DATA62 MB_DATA63

MB_DM0 MB_DM1 MB_DM2 MB_DM3 MB_DM4 MB_DM5 MB_DM6 MB_DM7

MB_DQS_H0

MB_DQS_L0

MB_DQS_H1

MB_DQS_L1

MB_DQS_H2

MB_DQS_L2

MB_DQS_H3

MB_DQS_L3

MB_DQS_H4

MB_DQS_L4

MB_DQS_H5

MB_DQS_L5

MB_DQS_H6

MB_DQS_L6

MB_DQS_H7

MB_DQS_L7

C11 A11 A14 B14 G11 E11 D12 A13 A15 A16 A19 A20 C14 D14 C18 D18 D20 A21 D24 C25 B20 C20 B24 C24 E23 E24 G25 G26 C26 D26 G23 G24 AA24 AA23 AD24 AE24 AA26 AA25 AD26 AE25 AC22 AD22 AE20 AF20 AF24 AF23 AC20 AD20 AD18 AE18 AC14 AD14 AF19 AC18 AF16 AF15 AF13 AC12 AB11 Y11 AE14 AF14 AF11 AD11

A12 B16 A22 E25 AB26 AE22 AC16 AD12

C12 B12 D16 C16 A24 A23 F26 E26 AC25 AC26 AF21 AF22 AE16 AD16 AF12 AE12

1

MEM_MB_DATA0 17 MEM_MB_DATA1 17 MEM_MB_DATA2 17 MEM_MB_DATA3 17 MEM_MB_DATA4 17 MEM_MB_DATA5 17 MEM_MB_DATA6 17 MEM_MB_DATA7 17 MEM_MB_DATA8 17 MEM_MB_DATA9 17 MEM_MB_DATA10 17 MEM_MB_DATA11 17 MEM_MB_DATA12 17 MEM_MB_DATA13 17 MEM_MB_DATA14 17 MEM_MB_DATA15 17 MEM_MB_DATA16 17 MEM_MB_DATA17 17 MEM_MB_DATA18 17 MEM_MB_DATA19 17 MEM_MB_DATA20 17 MEM_MB_DATA21 17 MEM_MB_DATA22 17 MEM_MB_DATA23 17 MEM_MB_DATA24 17 MEM_MB_DATA25 17 MEM_MB_DATA26 17 MEM_MB_DATA27 17 MEM_MB_DATA28 17 MEM_MB_DATA29 17 MEM_MB_DATA30 17 MEM_MB_DATA31 17 MEM_MB_DATA32 17 MEM_MB_DATA33 17 MEM_MB_DATA34 17 MEM_MB_DATA35 17 MEM_MB_DATA36 17 MEM_MB_DATA37 17 MEM_MB_DATA38 17 MEM_MB_DATA39 17 MEM_MB_DATA40 17 MEM_MB_DATA41 17 MEM_MB_DATA42 17 MEM_MB_DATA43 17 MEM_MB_DATA44 17 MEM_MB_DATA45 17 MEM_MB_DATA46 17 MEM_MB_DATA47 17 MEM_MB_DATA48 17 MEM_MB_DATA49 17 MEM_MB_DATA50 17 MEM_MB_DATA51 17 MEM_MB_DATA52 17 MEM_MB_DATA53 17 MEM_MB_DATA54 17 MEM_MB_DATA55 17 MEM_MB_DATA56 17 MEM_MB_DATA57 17 MEM_MB_DATA58 17 MEM_MB_DATA59 17 MEM_MB_DATA60 17 MEM_MB_DATA61 17 MEM_MB_DATA62 17 MEM_MB_DATA63 17

MEM_MB_DM0 17 MEM_MB_DM1 17 MEM_MB_DM2 17 MEM_MB_DM3 17 MEM_MB_DM4 17 MEM_MB_DM5 17 MEM_MB_DM6 17 MEM_MB_DM7 17

MEM_MB_DQS0_P 17 MEM_MB_DQS0_N 17 MEM_MB_DQS1_P 17 MEM_MB_DQS1_N 17 MEM_MB_DQS2_P 17 MEM_MB_DQS2_N 17 MEM_MB_DQS3_P 17 MEM_MB_DQS3_N 17 MEM_MB_DQS4_P 17 MEM_MB_DQS4_N 17 MEM_MB_DQS5_P 17 MEM_MB_DQS5_N 17 MEM_MB_DQS6_P 17 MEM_MB_DQS6_N 17 MEM_MB_DQS7_P 17 MEM_MB_DQS7_N 17

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

5

4

3

2

Date: Sheet of

CPU_DDR_(2/4)

Taipei Hsien 221, Taiwan, R.O.C.

JV50-TR8

-1

5 63Monday, October 26, 2009

1

-1

5

4

3

2

1

1D8V_S0

The Processor has reached a preset maximum operating

678

RN40

RN40 SRN300J-1-GP

SRN300J-1-GP

-1

123

4 5

R78

1D8V_S3

1 2

510R2J-1-GP

1 2

510R2J-1-GP

1D8V_S3

1 2

510R2J-1-GP

1 2

1D8V_S3

3D3V_S0

12

DY

Q8

CBE

MMBT3904-4-GP

1 2

1 2 1 2 1 2

R72 0R2J-2-GP

1D8V_S3

1 2

DY

R616

R617

DY

R614

R615

12

R81

R81 2K2R2J-2-GP

2K2R2J-2-GP

DY

LDT_PW ROK_G

DY

SCD1U16V2ZY-2GP

D D

C C

CPU_LDT_RST#11,52

CPU_PW RGD11,52

CPU_LDT_STOP#11

ALLOW_LDTSTOP9

for TR

B B

CPU_PW RGD_SVID_REG45

R101

10KR2J-3-GP

Near CPU PIN

R375

1 2

0R0402-PAD

PLT_RST1#9,11,26,33,36,55

12

R1312

R1312 17K8R2F-GP

17K8R2F-GP

A A

12

R1313

R1313 20KR2F-L-GP

20KR2F-L-GP

5

0R0402-PAD

0R0402-PAD R86

R86

0R0402-PAD

R79

0R0402-PAD

DY

R364

R364 390R2J-1-GP

390R2J-1-GP

CPU_SIC

CPU_TEST25_H

CPU_TEST25_L

CPU_TEST25_H

510R2J-1-GP

LDT_PW ROK

LDT_PW ROKCPU_PW RGD_SVID_REG

LDT_PW ROK_R

1 2

DY

C196

C196 SC100P50V2JN-3GP

SC100P50V2JN-3GP

LDT_RST#_CPU 9

LDT_PW ROK

LDT_STP#_CPU 9

CPU_LDT_REQ#_CPU

for TR

12

C205

DY

1 2

R1314 0R2J-2-GP

DY

IF 0 ohm IS NOT GOOD ENOUGH, TRY 68.00082.491

R401

1 2

0R0603-PAD

Cloce To CPU

CPU_CLK3 CPU_CLK#3

For HDT DBG

CPU_VDD0_RUN_FB_H45 CPU_VDD0_RUN_FB_L45

CPU_VDD1_RUN_FB_H45 CPU_VDD1_RUN_FB_L45

C734 SC3900P50V2KX-2GPC734 SC3900P50V2KX-2GP C732 SC3900P50V2KX-2GPC732 SC3900P50V2KX-2GP

LDT_RST#_CPU

HDT_RST#

1 2

R74

R74 0R0402-PAD

0R0402-PAD

1D2V_S0

TP93TP93

TP104TP104

TP97TP97

TP94TP94

RN42

SRN300J-1-GP

-1_20091021

LDT_PW ROK_R

Q24

MMBT3904-4-GP

THERMTRIP#

CPU exceeds to 125

4

E

2ND = 84.03904.L06

2D5V_VDDA_S02D5V_S0

12

C745

C739

SC10U10V5ZY-1GP

DY

1 2 1 2

1 1

1

B

84.T3904.C11

R386 169R2F-GPR386 169R2F-GP

TPAD14-GP

TPAD14-GP TPAD14-GP

TPAD14-GP

1 2

R84 44D2R2F-GPR84 44D2R2F-GP

1 2

R83 44D2R2F-GPR83 44D2R2F-GP

R110 0R0402-PADR110 0R0402-PAD R108 0R0402-PADR108 0R0402-PAD

R104 0R0402-PADR104 0R0402-PAD R105 0R0402-PADR105 0R0402-PAD

1

CPU_TEST21 CPU_TEST20

678

123

4 5

LDT_PW ROK_R

C



12

C752

C227

SC3300P50V2KX-1GP

SC4D7U10V5ZY-3GP

DY

1 2

LDT_PW ROK LDT_STP#_CPU CPU_LDT_REQ#_CPU

TP186

TP186 TP185

TP185 TP87

TP87

CPU_VDD0_RUN_FB_H_R

1 2

CPU_VDD0_RUN_FB_L_R

1 2

CPU_VDD1_RUN_FB_H_R

1 2

CPU_VDD1_RUN_FB_L_R

1 2

CPU_DBRDY CPU_TMS CPU_TCK CPU_TRST# CPU_TDI

TP105TP105 TP103TP103

TP95TP95

TP187TP187

R77

1 2

0R0402-PAD

C723

SC1U10V3KX-3GP

1 2

DY

RSMRST# 35,36

LYAOUT:ROUTE VDDA TRACE APPROX. 50mils WIDE(USE 2X25 mil TRACES TO EXIT BALL FIELD) AND 500 mils LONG.

12

C264

SCD22U16V3ZY-GP

SC10U10V5ZY-1GP

DY

ACPU1D

F8

CLKCPU_IN

CLKCPU#_IN

CPU_SIC

1

CPU_SID

1

CPU_ALERT#

1

CPU_HTREF0 CPU_HTREF1

CPU_TEST23 CPU_TEST18

CPU_TEST19

CPU_TEST25_H

1

CPU_TEST25_L

1

CPU_TEST21 CPU_TEST20 CPU_TEST24 CPU_TEST22 CPU_TEST12

1

CPU_TEST27

1

CPU_TEST9

3

VDDA1

F9

VDDA2

A9

CLKIN_H

A8

CLKIN_L

B7

RESET_L

A7

PWROK

F10

LDTSTOP_L

C6

LDTREQ_L

AF4

SIC

AF5

SID

AE6

ALERT_L

R6

HT_REF0

P6

HT_REF1

F6

VDD0_FB_H

E6

VDD0_FB_L

Y6

VDD1_FB_H

AB6

VDD1_FB_L

G10

DBRDY

AA9

TMS

AC9

TCK

AD9

TRST_L

AF9

TDI

AD7

TEST23

H10

TEST18

G9

TEST19

E9

TEST25_H

E8

TEST25_L

AB8

TEST21

AF7

TEST20

AE7

TEST24

AE8

TEST22

AC8

TEST12

AF8

TEST27

C2

TEST9

AA6

TEST6

A3

RSVD1

A5

RSVD2

B3

RSVD3

B5

RSVD4

C1

RSVD5

SKT-CPU638P,DANUB

1 2

THERMTRIP_L

PROCHOT_L

MEMHOT_L

THERMDC THERMDA

VDDIO_FB_H

VDDIO_FB_L

VDDNB_FB_H

VDDNB_FB_L

DBREQ_L

TEST28_H

TEST28_L

TEST29_H

TEST29_L

R612

300R2J-4-GP

DY

KEY1 KEY2

SVC SVD

TDO

TEST17 TEST16 TEST15 TEST14

TEST7

TEST10

TEST8

RSVD10

RSVD9 RSVD8 RSVD7 RSVD6

1D8V_S0

1D8V_S3

12

R1205

1KR2J-1-GP

M11 W18

A6 A4

THERMTRIP#

AF6

PROCHOT#

AC7

CPU_MEMHOT#

AA8

internal pull high 300 ohm

W7 W8

1 2

DY

CPU_VDDIO_SUS_FB_H

W9

CPU_VDDIO_SUS_FB_L

Y9 H6

G6

CPU_DBREQ#

E10

CPU_TDO

AE9

CPU_TEST28_H

J7

CPU_TEST28_L

H8

CPU_TEST17

D7

CPU_TEST16

E7

CPU_TEST15

F7

CPU_TEST14

C7 C3

CPU_TEST10

K8 C4

CPU_TEST29H

C9

CPU_TEST29L

C8

H18 H19 AA7 D5 C5

CPU_TEST19CPU_TEST18 CPU_TEST22

R611

300R2J-4-GP

DY

1 2

12

R1204

1KR2J-1-GP

DY

H_THERMDC 35 H_THERMDA 35

C213SC3300P50V2KX-1GP

CPU_VDDNB_RUN_FB_H 45 CPU_VDDNB_RUN_FB_L 45

LAYOUT: Route FBCLKOUT_H/L differentially impedance 80

1 1

1 1 1 1

1 1

R613

300R2J-4-GP

DY

1 2

2

1D8V_S3

678

DY

4 5

CPU_DBREQ#

12

R1203

R1203 1KR2J-1-GP

1KR2J-1-GP

CPU_SVC 45 CPU_SVD 45

1

TP99TP99

1

TP100TP100

TP92TP92 TP98TP98

TP89TP89 TP90TP90 TP91TP91 TP88TP88

TP101TP101 TP102TP102

RN84

SRN300J-1-GP

1D2V_S0

123

DY

R610

300R2J-4-GP

1 2

HDT Connectors

1D8V_S3

JV50-TR8

Title

CPU_Control&Debug_(3/4)

Size Document Number Rev

A3

Date: Sheet of

JV50-TR8

temperature. 100 I=Active HTC O=FAN

R366

R366 300R2J-4-GP

300R2J-4-GP

R67

1 2

0R0402-PAD

CPU_DBREQ# CPU_DBRDY CPU_TCK CPU_TMS CPU_TDI CPU_TRST# CPU_TDO

HDT_RST#

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

PROCHOT#_SB 11

HDT1

1

DY

3 5 7

9 11 13 15 17 19 21 23

SMC-CONN26A-FP

6 63Monday, October 26, 2009

2 4

6 8 10 12 14 16 18 20 22 24 26



-1

5

ACPU1F

AA4

VSS1

AA11

VSS2

AA13

VSS3

AA15

VSS4

AA17

VSS5

AA19

D D

C C

B B

VSS6

AB2

VSS7

AB7

VSS8

AB9

VSS9

AB23

VSS10

AB25

VSS11

AC11

VSS12

AC13

VSS13

AC15

VSS14

AC17

VSS15

AC19

VSS16

AC21

VSS17

AD6

VSS18

AD8

VSS19

AD25

VSS20

AE11

VSS21

AE13

VSS22

AE15

VSS23

AE17

VSS24

AE19

VSS25

AE21

VSS26

AE23

VSS27

B4

VSS28

B6

VSS29

B8

VSS30

B9

VSS31

B11

VSS32

B13

VSS33

B15

VSS34

B17

VSS35

B19

VSS36

B21

VSS37

B23

VSS38

B25

VSS39

D6

VSS40

D8

VSS41

D9

VSS42

D11

VSS43

D13

VSS44

D15

VSS45

D17

VSS46

D19

VSS47

D21

VSS48

D23

VSS49

D25

VSS50

E4

VSS51

F2

VSS52

F11

VSS53

F13

VSS54

F15

VSS55

F17

VSS56

F19

VSS57

F21

VSS58

F23

VSS59

F25

VSS60

H7

VSS61

H9

VSS62

H21

VSS63

H23

VSS64

J4

VSS65

SKT-CPU638P,DANUB

VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98

VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129

J6 J8 J10 J12 J14 J16 J18 K2 K7 K9 K11 K13 K15 K17 L6 L8 L10 L12 L14 L16 L18 M7 M9 AC6 M17 N4 N8 N10 N16 N18 P2 P7 P9 P11 P17 R8 R10 R16 R18 T7 T9 T11 T13 T15 T17 U4 U6 U8 U10 U12 U14 U16 U18 V2 V7 V9 V11 V13 V15 V17 W6 Y21 Y23 N6

add 0.1U

VCC_CORE_S0_0

Bottom Side Decoupling Bottom Side Decoupling

C239

SC10U6D3V5KX-1GP

C316

1D8V_S3

C281

12

VDDNB

SC10U6D3V5KX-1GP

C295

C286

12

DY

SC10U6D3V5KX-1GP

3A for VDDNB

C324

12

SC10U6D3V5KX-1GP

3A for VDDIO

Bottom Side Decoupling

C392

C398

12

DY

SC10U6D3V5KX-1GP

SCD22U6D3V2KX-1GP

SC10U6D3V5KX-1GP

C381

12

DY

C808

C206

12

SC10U6D3V5KX-1GP

SCD22U6D3V2KX-1GP

C356

12

DY

4

36A for VDD0&VDD1

ACPU1E

G4

VDD0_1

H2

VDD0_2

J9

VDD0_3

J11

VDD0_4

J13

C244

C315

12

DY

12

SCD01U50V2KX-1GP

SC180P50V2JN-1GP

C349

C372

12

DY

SC180P50V2JN-1GP

VDD0_5

J15

VDD0_6

K6

VDD0_7

K10

VDD0_8

K12

VDD0_9

K14

VDD0_10

L4

VDD0_11

L7

VDD0_12

L9

VDD0_13

L11

VDD0_14

L13

VDD0_15

L15

VDD0_16

M2

VDD0_17

M6

VDD0_18

M8

VDD0_19

M10

VDD0_20

N7

VDD0_21

N9

VDD0_22

N11

VDD0_23

K16

VDDNB_1

M16

VDDNB_2

P16

VDDNB_3

T16

VDDNB_4

V16

VDDNB_5

H25

VDDIO1

J17

VDDIO2

K18

VDDIO3

K21

VDDIO4

K23

VDDIO5

K25

VDDIO6

L17

VDDIO7

M18

VDDIO8

M21

VDDIO9

M23

VDDIO10

M25

VDDIO11

N17

VDDIO12

SKT-CPU638P,DANUB

VDD1_1 VDD1_2 VDD1_3 VDD1_4 VDD1_5 VDD1_6 VDD1_7 VDD1_8

VDD1_9 VDD1_10 VDD1_11 VDD1_12 VDD1_13 VDD1_14 VDD1_15 VDD1_16 VDD1_17 VDD1_18 VDD1_19 VDD1_20 VDD1_21 VDD1_22 VDD1_23 VDD1_24 VDD1_25 VDD1_26

VDDIO27 VDDIO26 VDDIO25 VDDIO24 VDDIO23 VDDIO22 VDDIO21 VDDIO20 VDDIO19 VDDIO18 VDDIO17 VDDIO16 VDDIO15 VDDIO14 VDDIO13

P8 P10 R4 R7 R9 R11 T2 T6 T8 T10 T12 T14 U7 U9 U11 U13 U15 V6 V8 V10 V12 V14 W4 Y2 AC4 AD2

Y25 V25 V23 V21 V18 U17 T25 T23 T21 T18 R17 P25 P23 P21 P18

3

VCC_CORE_S0_1

C154

C308

C193

12

SC180P50V2JN-1GP

C308

12

SCD01U50V2KX-1GP

SCD22U6D3V2KX-1GP

C253

C280

12

DY

SC10U6D3V5KX-1GP

Place near to CPU

C385

C351

12

SC180P50V2JN-1GP

C385

C362

12

DY

SCD01U50V2KX-1GP

C375

C379

12

SCD22U6D3V2KX-1GP

C312

C293

12

DY

SC10U6D3V5KX-1GP

3

A for VDDIO

1D8V_S3

C365

C358

C361

C347

C363

12

DY

SCD22U6D3V2KX-1GP

12

DY

SCD22U6D3V2KX-1GP

-1

C363

12

DY

SC4D7U6D3V3MX-2GP

SC4D7U6D3V3KX-GP

2

C378

12

DY

SC4D7U6D3V3KX-GP

1

A A

5

4

3

2

JV50-TR8

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Date: Sheet

CPU_Power_(4/4)

Taipei Hsien 221, Taiwan, R.O.C.

JV50-TR8

of

7 63Monday, October 05, 2009

1

-1

5

HT_CPU_NB_CAD_H04 HT_CPU_NB_CAD_L04 HT_CPU_NB_CAD_H14 HT_CPU_NB_CAD_L14 HT_CPU_NB_CAD_H24 HT_CPU_NB_CAD_L24 HT_CPU_NB_CAD_H34 HT_CPU_NB_CAD_L34 HT_CPU_NB_CAD_H44 HT_CPU_NB_CAD_L44 HT_CPU_NB_CAD_H54

D D

C C

PEG_RXN[15..0]55 PEG_RXP[15..0]55

B B

MINICARD1 MINICARD2 NEW CARD

A A

A-LINK

5

HT_CPU_NB_CAD_L54 HT_CPU_NB_CAD_H64 HT_CPU_NB_CAD_L64 HT_CPU_NB_CAD_H74 HT_CPU_NB_CAD_L74

HT_CPU_NB_CAD_H84 HT_CPU_NB_CAD_L84 HT_CPU_NB_CAD_H94 HT_CPU_NB_CAD_L94 HT_CPU_NB_CAD_H104 HT_CPU_NB_CAD_L104 HT_CPU_NB_CAD_H114 HT_CPU_NB_CAD_L114 HT_CPU_NB_CAD_H124 HT_CPU_NB_CAD_L124 HT_CPU_NB_CAD_H134 HT_CPU_NB_CAD_L134 HT_CPU_NB_CAD_H144 HT_CPU_NB_CAD_L144 HT_CPU_NB_CAD_H154 HT_CPU_NB_CAD_L154

HT_CPU_NB_CLK_H04 HT_CPU_NB_CLK_L04 HT_CPU_NB_CLK_H14 HT_CPU_NB_CLK_L14

HT_CPU_NB_CTL_H04 HT_CPU_NB_CTL_L04 HT_CPU_NB_CTL_H14 HT_CPU_NB_CTL_L14

1 2

Place < 100mils from pin C23 and A24 Place < 100mils from pin B25 and B24

LAN

TPAD14-GP

TPAD14-GP TPAD14-GP

TPAD14-GP

ALINK_NBRX_SBTX_P011 ALINK_NBRX_SBTX_N011 ALINK_NBRX_SBTX_P111 ALINK_NBRX_SBTX_N111 ALINK_NBRX_SBTX_P211 ALINK_NBRX_SBTX_N211 ALINK_NBRX_SBTX_P311 ALINK_NBRX_SBTX_N311

TP21

TP21 TP20

TP20

R344

R344 301R2F-GP

301R2F-GP

PCIE_RXP126 PCIE_RXN126 PCIE_RXP233 PCIE_RXN233 PCIE_RXP333 PCIE_RXN333 PCIE_RXP534 PCIE_RXN534

PEG_RXP0 PEG_RXN0 PEG_RXP1 PEG_RXN1 PEG_RXP2 PEG_RXN2 PEG_RXP3 PEG_RXN3 PEG_RXP4 PEG_RXN4 PEG_RXP5 PEG_RXN5 PEG_RXP6 PEG_RXN6 PEG_RXP7 PEG_RXN7 PEG_RXP8 PEG_RXN8 PEG_RXP9 PEG_RXN9 PEG_RXP10 PEG_RXN10 PEG_RXP11 PEG_RXN11 PEG_RXP12 PEG_RXN12 PEG_RXP13 PEG_RXN13 PEG_RXP14 PEG_RXN14 PEG_RXP15 PEG_RXN15

4

ANB1A

Y25

HT_RXCAD0P

Y24

HT_RXCAD0N

V22

HT_RXCAD1P

V23

HT_RXCAD1N

V25

HT_RXCAD2P

V24

HT_RXCAD2N

U24

HT_RXCAD3P

U25

HT_RXCAD3N

T25

HT_RXCAD4P

T24

HT_RXCAD4N

P22

HT_RXCAD5P

P23

HT_RXCAD5N

P25

HT_RXCAD6P

P24

HT_RXCAD6N

N24

HT_RXCAD7P

N25

HT_RXCAD7N

AC24

HT_RXCAD8P

AC25

HT_RXCAD8N

AB25

HT_RXCAD9P

AB24

HT_RXCAD9N

AA24

HT_RXCAD10P

AA25

HT_RXCAD10N

Y22

HT_RXCAD11P

Y23

HT_RXCAD11N

W21

HT_RXCAD12P

W20

HT_RXCAD12N

V21

HT_RXCAD13P

V20

HT_RXCAD13N

U20

HT_RXCAD14P

U21

HT_RXCAD14N

U19

HT_RXCAD15P

U18

HT_RXCAD15N

T22

HT_RXCLK0P

T23

HT_RXCLK0N

AB23

HT_RXCLK1P

AA22

HT_RXCLK1N

M22

HT_RXCTL0P

M23

HT_RXCTL0N

R21

HT_RXCTL1P

R20

HT_RXCALP HT_TXCALP HT_RXCALN

GPP_RX5P GPP_RX5N

HT_RXCTL1N

C23

HT_RXCALP

A24

HT_RXCALN

RS780M-GP-U2

ANB1B

D4

GFX_RX0P

C4

GFX_RX0N

A3

GFX_RX1P

B3

GFX_RX1N

C2

GFX_RX2P

C1

GFX_RX2N

E5

GFX_RX3P

F5

GFX_RX3N

G5

GFX_RX4P

G6

GFX_RX4N

H5

GFX_RX5P

H6

GFX_RX5N

J6

GFX_RX6P

J5

GFX_RX6N

J7

GFX_RX7P

J8

GFX_RX7N

L5

GFX_RX8P

L6

GFX_RX8N

M8

GFX_RX9P

L8

GFX_RX9N

P7

GFX_RX10P

M7

GFX_RX10N

P5

GFX_RX11P

M5

GFX_RX11N

R8

GFX_RX12P

P8

GFX_RX12N

R6

GFX_RX13P

R5

GFX_RX13N

P4

GFX_RX14P

P3

GFX_RX14N

T4

GFX_RX15P

T3

GFX_RX15N

AE3

GPP_RX0P

AD4

GPP_RX0N

AE2

GPP_RX1P

AD3

GPP_RX1N

AD1

GPP_RX2P

AD2

GPP_RX2N

V5

GPP_RX3P

W6

GPP_RX3N

U5

GPP_RX4P

U6

GPP_RX4N

U8

GPP_RX5P

U7

GPP_RX5N

AA8

SB_RX0P

Y8

SB_RX0N

AA7

SB_RX1P

Y7

SB_RX1N

AA5

SB_RX2P

AA6

SB_RX2N

W5

SB_RX3P

Y5

SB_RX3N

RS780M-GP-U2

4

PART 1 OF 6

PART 2 OF 6

PCIE I/F GPP

PCIE I/F SB

HYPER TRANSPORT CPU I/F

PCIE I/F GFX

HT_TXCAD0P HT_TXCAD0N HT_TXCAD1P HT_TXCAD1N HT_TXCAD2P HT_TXCAD2N HT_TXCAD3P HT_TXCAD3N HT_TXCAD4P HT_TXCAD4N HT_TXCAD5P HT_TXCAD5N HT_TXCAD6P HT_TXCAD6N HT_TXCAD7P HT_TXCAD7N

HT_TXCAD8P HT_TXCAD8N HT_TXCAD9P

HT_TXCAD9N HT_TXCAD10P HT_TXCAD10N HT_TXCAD11P HT_TXCAD11N HT_TXCAD12P HT_TXCAD12N HT_TXCAD13P HT_TXCAD13N HT_TXCAD14P HT_TXCAD14N HT_TXCAD15P HT_TXCAD15N

HT_TXCLK0P

HT_TXCLK0N

HT_TXCLK1P

HT_TXCLK1N

HT_TXCTL0P HT_TXCTL0N HT_TXCTL1P HT_TXCTL1N

HT_TXCALP

HT_TXCALN

GFX_TX10P GFX_TX10N GFX_TX11P GFX_TX11N GFX_TX12P GFX_TX12N GFX_TX13P GFX_TX13N GFX_TX14P GFX_TX14N GFX_TX15P GFX_TX15N

GPP_TX0N GPP_TX1N GPP_TX2N GPP_TX3N GPP_TX4N GPP_TX5N

PCE_CALRP

PCE_CALRN

GFX_TX0P GFX_TX0N GFX_TX1P GFX_TX1N GFX_TX2P GFX_TX2N GFX_TX3P GFX_TX3N GFX_TX4P GFX_TX4N GFX_TX5P GFX_TX5N GFX_TX6P GFX_TX6N GFX_TX7P GFX_TX7N GFX_TX8P GFX_TX8N GFX_TX9P GFX_TX9N

GPP_TX0P GPP_TX1P GPP_TX2P GPP_TX3P GPP_TX4P GPP_TX5P

SB_TX0P

SB_TX0N

SB_TX1P

SB_TX1N

SB_TX2P

SB_TX2N

SB_TX3P

SB_TX3N

D24 D25 E24 E25 F24 F25 F23 F22 H23 H22 J25 J24 K24 K25 K23 K22

F21 G21 G20 H21 J20 J21 J18 K17 L19 J19 M19 L18 M21 P21 P18 M18

H24 H25 L21 L20

M24 M25 P19 R18

B24 B25

A5 B5 A4 B4 C3 B2 D1 D2 E2 E1 F4 F3 F1 F2 H4 H3 H1 H2 J2 J1 K4 K3 K1 K2 M4 M3 M1 M2 N2 N1 P1 P2

AC1 AC2 AB4 AB3 AA2 AA1 Y1 Y2 Y4 Y3 V1 V2

AD7 AE7 AE6 AD6 AB6 AC6 AD5 AE5

AC8 AB8

3

HT_TXCALN

GTXP0 GTXN0 GTXP1 GTXN1 GTXP2 GTXN2 GTXP3 GTXN3 GTXP4 GTXN4 GTXP5 GTXN5 GTXP6 GTXN6 GTXP7 GTXN7 GTXP8

DIS

GTXN8

DIS

GTXP9

DIS

GTXN9

DIS

GTXP10

DIS

GTXN10

DIS

GTXP11

DIS

GTXN11

DIS

GTXP12

DIS

GTXN12

DIS

GTXP13

DIS

GTXN13

DIS

GTXP14

DIS

GTXN14

DIS

GTXP15

DIS

GTXN15

DIS

TXP0 TXN0 TXP1 TXN1 TXP3 TXN3 TXP5 TXN5

GPP_TX5P GPP_TX5N

ALINK_NBTX_SBRX_P0 ALINK_NBTX_SBRX_N0 ALINK_NBTX_SBRX_P1 ALINK_NBTX_SBRX_N1 ALINK_NBTX_SBRX_P2 ALINK_NBTX_SBRX_N2 ALINK_NBTX_SBRX_P3 ALINK_NBTX_SBRX_N3

PCE_PCAL PCE_NCAL

Place < 100mils from pin AC8 and AB8

3

HT_NB_CPU_CAD_H0 4 HT_NB_CPU_CAD_L0 4 HT_NB_CPU_CAD_H1 4 HT_NB_CPU_CAD_L1 4 HT_NB_CPU_CAD_H2 4 HT_NB_CPU_CAD_L2 4 HT_NB_CPU_CAD_H3 4 HT_NB_CPU_CAD_L3 4 HT_NB_CPU_CAD_H4 4 HT_NB_CPU_CAD_L4 4 HT_NB_CPU_CAD_H5 4 HT_NB_CPU_CAD_L5 4 HT_NB_CPU_CAD_H6 4 HT_NB_CPU_CAD_L6 4 HT_NB_CPU_CAD_H7 4 HT_NB_CPU_CAD_L7 4

HT_NB_CPU_CAD_H8 4 HT_NB_CPU_CAD_L8 4 HT_NB_CPU_CAD_H9 4 HT_NB_CPU_CAD_L9 4 HT_NB_CPU_CAD_H10 4 HT_NB_CPU_CAD_L10 4 HT_NB_CPU_CAD_H11 4 HT_NB_CPU_CAD_L11 4 HT_NB_CPU_CAD_H12 4 HT_NB_CPU_CAD_L12 4 HT_NB_CPU_CAD_H13 4 HT_NB_CPU_CAD_L13 4 HT_NB_CPU_CAD_H14 4 HT_NB_CPU_CAD_L14 4 HT_NB_CPU_CAD_H15 4 HT_NB_CPU_CAD_L15 4

HT_NB_CPU_CLK_H0 4 HT_NB_CPU_CLK_L0 4 HT_NB_CPU_CLK_H1 4 HT_NB_CPU_CLK_L1 4

HT_NB_CPU_CTL_H0 4 HT_NB_CPU_CTL_L0 4 HT_NB_CPU_CTL_H1 4 HT_NB_CPU_CTL_L1 4

1 2

C617 SCD1U16V2KX-3GP

1 2

DIS

DIS DIS

DIS

C616 SCD1U16V2KX-3GP

1 2

C592 SCD1U16V2KX-3GP

1 2

C593 SCD1U16V2KX-3GP

1 2

C614 SCD1U16V2KX-3GP

1 2

C615 SCD1U16V2KX-3GP

1 2

C591 SCD1U16V2KX-3GP

1 2

C590 SCD1U16V2KX-3GP

1 2

C613 SCD1U16V2KX-3GP

1 2

C612 SCD1U16V2KX-3GP

1 2

C589 SCD1U16V2KX-3GP

1 2

C588 SCD1U16V2KX-3GP

1 2

C611 SCD1U16V2KX-3GP

1 2

C610 SCD1U16V2KX-3GP

1 2

C587 SCD1U16V2KX-3GP

1 2

C586 SCD1U16V2KX-3GP

1 2

C609 SCD1U16V2KX-3GP

1 2

C608 SCD1U16V2KX-3GP

1 2

C585 SCD1U16V2KX-3GP

1 2

C584 SCD1U16V2KX-3GP

1 2

C607 SCD1U16V2KX-3GP

1 2

C606 SCD1U16V2KX-3GP

1 2

C583 SCD1U16V2KX-3GP

1 2

C582 SCD1U16V2KX-3GP

1 2

C605 SCD1U16V2KX-3GP

1 2

C604 SCD1U16V2KX-3GP

1 2

C581 SCD1U16V2KX-3GP

1 2

C580 SCD1U16V2KX-3GP

1 2

C602 SCD1U16V2KX-3GP

1 2

C603 SCD1U16V2KX-3GP

1 2

C579 SCD1U16V2KX-3GP

1 2

C578 SCD1U16V2KX-3GP

1 2

C621 SCD1U16V2KX-3GPC621 SCD1U16V2KX-3GP

1 2

C622 SCD1U16V2KX-3GPC622 SCD1U16V2KX-3GP

1 2

C597 SCD1U16V2KX-3GPC597 SCD1U16V2KX-3GP

1 2

C596 SCD1U16V2KX-3GPC596 SCD1U16V2KX-3GP

1 2

C599 SCD1U16V2KX-3GPC599 SCD1U16V2KX-3GP

1 2

C598 SCD1U16V2KX-3GPC598 SCD1U16V2KX-3GP

1 2

C600 SCD1U16V2KX-3GPC600 SCD1U16V2KX-3GP

1 2

C601 SCD1U16V2KX-3GPC601 SCD1U16V2KX-3GP

1 2

C642 SCD1U16V2KX-3GPC642 SCD1U16V2KX-3GP

1 2

C640 SCD1U16V2KX-3GPC640 SCD1U16V2KX-3GP

1 2

C632 SCD1U16V2KX-3GPC632 SCD1U16V2KX-3GP

1 2

C637 SCD1U16V2KX-3GPC637 SCD1U16V2KX-3GP

1 2

C627 SCD1U16V2KX-3GPC627 SCD1U16V2KX-3GP

1 2

C629 SCD1U16V2KX-3GPC629 SCD1U16V2KX-3GP

1 2

C624 SCD1U16V2KX-3GPC624 SCD1U16V2KX-3GP

1 2

C625 SCD1U16V2KX-3GPC625 SCD1U16V2KX-3GP

1 2

R315 1K27R2F-L-GPR315 1K27R2F-L-GP

1 2

R16 2KR2F-3-GPR16 2KR2F-3-GP

Placement: close RS780

R343

R343 301R2F-GP

301R2F-GP

Placement: close RS780

PEG_TXP0 PEG_TXN0 PEG_TXP1 PEG_TXN1 PEG_TXP2 PEG_TXN2 PEG_TXP3 PEG_TXN3 PEG_TXP4 PEG_TXN4 PEG_TXP5 PEG_TXN5 PEG_TXP6 PEG_TXN6 PEG_TXP7 PEG_TXN7 PEG_TXP8 PEG_TXN8 PEG_TXP9 PEG_TXN9 PEG_TXP10 PEG_TXN10 PEG_TXP11 PEG_TXN11 PEG_TXP12 PEG_TXN12 PEG_TXP13 PEG_TXN13 PEG_TXP14 PEG_TXN14 PEG_TXP15 PEG_TXN15

TP16 TPAD14-GPTP16 TPAD14-GP TP17 TPAD14-GPTP17 TPAD14-GP

1D1V_S0

for TR

PCIE_TXP1 26

PCIE_TXN1 26

PCIE_TXP2 33

PCIE_TXN2 33

PCIE_TXP3 33

PCIE_TXN3 33

PCIE_TXP5 34

PCIE_TXN5 34

ALINK_NBTX_C_SBRX_P0 11 ALINK_NBTX_C_SBRX_N0 11 ALINK_NBTX_C_SBRX_P1 11 ALINK_NBTX_C_SBRX_N1 11 ALINK_NBTX_C_SBRX_P2 11 ALINK_NBTX_C_SBRX_N2 11 ALINK_NBTX_C_SBRX_P3 11 ALINK_NBTX_C_SBRX_N3 11

2

PEG_TXP[15..0] 55 PEG_TXN[15..0] 55

1

RS780M Display Port Support(muxed on GFX)

DP0

GFX_TX0,TX1,TX2,TX3,AUX0,HPD0 GFX_TX4,TX5,TX6,TX7,AUX1,HPD1DP1

GTXP0 GTXN0 GTXP1 GTXN1 GTXP2 GTXN2 GTXP3 GTXN3

UMA

UMA UMA

UMA

C30 SCD1U16V2KX-3GP

1 2

C29 SCD1U16V2KX-3GP

1 2

C27 SCD1U16V2KX-3GP

1 2

C26 SCD1U16V2KX-3GP

1 2

C25 SCD1U16V2KX-3GP

1 2

C22 SCD1U16V2KX-3GP

1 2

C21 SCD1U16V2KX-3GP

1 2

C19 SCD1U16V2KX-3GP

1 2

LAN MINICARD1

MINICARD2 NEW CARD

JV50-TR8

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

ATi-RS880M_HT LINK&PCIe(1/3)

Size Document Number Rev

A3

Date: Sheet of

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

JV50-TR8

1

HDMI_DATA2+ 21 HDMI_DATA2- 21 HDMI_DATA1+ 21 HDMI_DATA1- 21 HDMI_DATA0+ 21 HDMI_DATA0- 21 HDMI_CLK+ 21 HDMI_CLK- 21

8 63Monday, October 26, 2009

-1

5

1 : Bypass the loading of EEPROM straps and use Hardware Default Values

R21 0R2J-2-GP

1 2

DY

LDT_RST#_CPU6

D D

PLT_RST1#

Close to NB ball

C C

LDT_STP#_CPU6

ALLOW_LDTSTOP6

R69 BOM Option

2ND = 77.C1071.081

1ST 68.00217.711

2ND = 68.00119.111

1D8V_S0

B B

1D8V_S0

2ND = 68.00119.111

L5

1 2

220ohm 200mA

SBK160808T-221Y-N-GP

SC1U10V2KX-1GP

L1

1 2

220ohm 200mA

SBK160808T-221Y-N-GP

SC1U10V2KX-1GP

1ST 68.00217.711

2ND = 68.00119.111

R17

1 2

-1

GMCH_BLUE

12

R36

150R2F-1-GP

-1

R14

1 2

0R0402-PAD

0R0402-PAD R24

R24

1 2

0R2J-2-GP

for TR

80.10715.L04

VDDA18HTPLL

C86

VDDA18PCIEPLL

C41

DY

0R0402-PAD

GMCH_GREEN

12

R37

150R2F-1-GP

DY

12

DY

12

DY

SYSREST#

12

C37

C37 SC220P50V2KX-3GP

SC220P50V2KX-3GP

GMCH_RED

12

R38

140R2F-GP

NB_LDT_STOP#

NB_ALLOW_LDTSTOP

1D8V_S0

220ohm 200mA

12

TC1

12

C97

C97 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

C42

C42 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

ST100U6D3VBML1GP

2ND = 68.00119.111

1ST 68.00217.711

1D8V_S0

TC2

ST100U6D3VBM-5GP

DY

1D8V_S0

for TR

12

R609

R609 1KR2F-3-GP

1KR2F-3-GP

CRT

L4

1 2

SBK160808T-221Y-N-GP

SC47U6D3V5MX-1-GP

SB

1D1V_S0

L33

1 2

SBK160808T-221Y-N-GP

220ohm 200mA

SC1U10V2KX-1GP

12

C82

ENABLE External CLK GEN

UMA-->L4-->2R 0603 C82-->47U/6.3V DIS-->L4-->Bead C82-->DY

GPIO MODE STRP_DATA 0 1 VCC_NB

4

1ST 68.00217.711

2ND = 68.00119.111

1ST 68.00217.711

2ND = 68.00119.111

1 2

R43

SBK160808T-221Y-N-GP

12

220ohm 200mA

GMCH_RED20

GMCH_GREEN20

GMCH_BLUE20

1ST 68.00217.711

2ND = 68.00119.111

12

C644

12

C78

SC1U10V2KX-1GP

DY

CRT

1D1V_S0

SB

CLK_DDC_EDID19

DAT_DDC_EDID19

*

1.0V1.1V

3D3V_S0

L3

1 2

SBK160808T-221Y-N-GP

SC1U10V2KX-1GP

1D8V_S0

1 2

0R0603-PAD

SC1U10V2KX-1GP

C80

SC1U10V2KX-1GP

GMCH_DDCCLK20

GMCH_DDCDATA20

1D1V_S0_PLLVDD

12

C643

C643 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

DY

12

C77

C77 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

RN11

1 2 3

SRN1KJ-7-GP

GMCH_HDMI_CLK21

GMCH_HDMI_DATA21

220ohm 200mA

12

C71

R41

12

C88

12

C99

C99 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

GMCH_HSYNC20 GMCH_VSYNC20

NB_PWRGD12,42

NB_ALLOW_LDTSTOP11

4

CLK_NB_GFX3 CLK_NB_GFX#3

TPAD14-GP

TPAD14-GP TPAD14-GP

TPAD14-GP

TPAD14-GP TPAD14-GP

TPAD14-GP

3D3V_S0_AVDD

12

C70

C70 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

DY

1D8V_S0_AVDDDI

12

C89

C89 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

CLK_NBHT_CLK3 CLK_NBHT_CLK#3

CLK_NB_14M3

TP180

TP180 TP181

TP181

TP188

TP188 TP239

TP239

1D8V_S0_AVDDQ

DAC_RSET

R33

1 2

715R2F-GP

1D8V_S0_PLVDD18

VDDA18HTPLL

VDDA18PCIEPLL

SYSREST#

NB_LDT_STOP#

NB_ALLOW_LDTSTOP

NB_REFCLK_N

CLK_NB_GFX CLK_NB_GFX#

CLK_NBGPP_CLK CLK_NBGPP_CLK#

CLK_NB_GPPSB3 CLK_NB_GPPSB#3

DDC_DATA0/AUX0N

DDC_CLK0/AUX0P GMCH_HDMI_CLK GMCH_HDMI_DATA

STRP_DATA

RS780_AUX_CAL

12

R294

R294 150R2F-1-GP

150R2F-1-GP

3

ANB1C

F12

AVDD1

E12

AVDD2

F14

AVDDDI

G15

AVSSDI

H15

AVDDQ

H14

AVSSQ

E17

C_Pr

F17

Y

F15

COMP_Pb

G18

RED

G17

REDb

E18

GREEN

F18

GREENb

E19

BLUE

F19

BLUEb

A11

DAC_HSYNC

B11

DAC_VSYNC

F8

DAC_SCL

E8

DAC_SDA

G14

DAC_RSET

A12

PLLVDD

D14

PLLVDD18

B12

PLLVSS

H17

VDDA18HTPLL

D7

VDDA18PCIEPLL1

E7

VDDA18PCIEPLL2

D8

SYSRESET#

A10

POWERGOOD

C10

LDTSTOP#

C12

ALLOW_LDTSTOP

C25

HT_REFCLKP

C24

HT_REFCLKN

E11

REFCLK_P/OSCIN

F11

REFCLK_N

T2

GFX_REFCLKP

T1

GFX_REFCLKN

U1

GPP_REFCLKP

U2

GPP_REFCLKN

V4

GPPSB_REFCLKP

V3

GPPSB_REFCLKN

B9

I2C_CLK

A9

I2C_DATA

B8

DDC_CLK0/AUX0P

A8

DDC_DATA0/AUX0N

B7

DDC_CLK1/AUX1P

A7

DDC_DATA1/AUX1N

B10

STRP_DATA

G11

RESERVED

C8

AUX_CAL

RS780M-GP-U2

R563

3K3R3J-L-GP

3D3V_S0

12

DDC_DATA0/AUX0N DDC_CLK0/AUX0P

R562

R562 3K3R3J-L-GP

3K3R3J-L-GP

GMCH_VSYNC

GMCH_HSYNC

PART 3 OF 6

CRT/TVOUT

PM

CLOCKs PLL PWR

MIS.

LVTM

2

1

STRAP_DEBUG_BUS_GPIO_ENABLEb

Enables the Test Debug Bus using GPIO.(PIN: RS780M--> VSYNC#) 1 :Disable 0 : Enable

*

R

S780: Enables Side port memory ( RS780 use HSYNC#)

1 :Disable 0 : Enable

*

SUS_STAT#

Selects Loading of STRAPS From EEPROM

*

0 : I2C Master can load strap values from EEPROM if connected, or use default values if not connected

TXOUT_L0P TXOUT_L0N TXOUT_L1P TXOUT_L1N TXOUT_L2P TXOUT_L2N TXOUT_L3P TXOUT_L3N

TXOUT_U0P TXOUT_U0N TXOUT_U1P TXOUT_U1N TXOUT_U2P TXOUT_U2N TXOUT_U3P TXOUT_U3N

TXCLK_LP TXCLK_LN TXCLK_UP

TXCLK_UN

VDDLTP18 VSSLTP18

VDDLT18_1 VDDLT18_2 VDDLT33_1 VDDLT33_2

VSSLT1 VSSLT2 VSSLT3 VSSLT4 VSSLT5 VSSLT6 VSSLT7

LVDS_DIGON

LVDS_BLON

LVDS_ENA_BL

TMDS_HPD

HPD

SUS_STAT#

THERMALDIODE_P THERMALDIODE_N

TESTMODE

A22 B22 A21 B21 B20 A20 A19 B19

B18 A18 A17 B17 D20 D21 D18 D19

B16 A16 D16 D17

1D8V_S0_VDDLP18

A13 B13

A15 B15 A14 B14

C14 D15 C16 C18 C20 E20 C22

E9

GMCH_BL_ON

F7

LVDS_ENA_BL

G12

D9 D10

D12 AE8

AD8

TESTMODE_NB

D13

GMCH_TXAOUT0+ 19 GMCH_TXAOUT0- 19 GMCH_TXAOUT1+ 19 GMCH_TXAOUT1- 19 GMCH_TXAOUT2+ 19 GMCH_TXAOUT2- 19

GMCH_TXBOUT0+ 19 GMCH_TXBOUT0- 19 GMCH_TXBOUT1+ 19 GMCH_TXBOUT1- 19 GMCH_TXBOUT2+ 19 GMCH_TXBOUT2- 19

GMCH_TXACLK+ 19

GMCH_TXACLK- 19

GMCH_TXBCLK+ 19

GMCH_TXBCLK- 19

C649

SC1U10V2KX-1GP

1D8V_S0_VDDLT18

SC4D7U6D3V3MX-2GP

-1

NB_DVI_HPD SUS_STAT#

R29 10KR2J-3-GPR29 10KR2J-3-GP

RS780_DXP3_1 RS780_DXN3_1

12

DY

12

C652

RN10

2 3 1

SRN4K7J-8-GP

R31

1 2

4K7R2J-2-GP

HDMI_DETECT# 21

TP24 TPAD14-GPTP24 TPAD14-GP

R347

R347 1K8R2F-GP

1K8R2F-GP

1 2

SBK160808T-221Y-N-GP

12

C648

C648 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

1 2

PBY201209T-221Y-N-GP

12

C653

DY

SCD1U10V2KX-4GP

4

12

TP23 TPAD14-GPTP23 TPAD14-GP TP22 TPAD14-GPTP22 TPAD14-GP

1D8V_S0

L34

L35

GMCH_LCDVDD_ON 19

GMCH_BL_ON 36

TP26 TPAD14-GPTP26 TPAD14-GP

UMA

3D3V_S0

1ST 68.00217.711

2ND = 68.00119.111

68.00206.121

2ND = 68.00216.161

3D3V_S0

12

R19

A A

DY

R19 2K2R2J-2-GP

2K2R2J-2-GP

STRP_DATA

BLON_IN36,56

BRIGHTNESS_AMD19,56

for TR

5

4

3

1 2

R576 0R2J-2-GP

UMA

1 2

R578 0R2J-2-GP

UMA

LVDS_ENA_BL

GMCH_BL_ON

JV50-TR8

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

ATi-RS880M_LVDS&CRT_(2/3)

Size Document Number Rev

A3

Date: Sheet of

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

JV50-TR8

-1

9 63Monday, October 26, 2009

1

-1

5

1D1V_S0

L36

1 2

PBY201209T-221Y-N-GP

220 ohm @ 100MHz,2A

D D

220 ohm @ 100MHz,2A

C C

220 ohm @ 100MHz,2A

2ND = 68.00216.161

68.00206.121

2ND = 68.00216.161

1D1V_S0

L40

1 2

PBY201209T-221Y-N-GP

68.00206.121

2ND = 68.00216.161

1D2V_S0

L38

1 2

PBY201209T-221Y-N-GP

68.00206.121

2ND = 68.00216.161

1D8V_S0

L2

1 2

PBY201209T-221Y-N-GP

68.00206.121

-1

C673

12

80mil Width

12

C63

SC4D7U6D3V3KX-GP

DY

0.6A per ANT Rev1.1, Page3

C655

12

SC4D7U6D3V3MX-2GP

12

DY

SCD1U10V2KX-4GP

12

DY

+1.1V_RUN_VDDHT

C659

C91

C655

0.45A per ANT Rev1.1, Page3

SC4D7U6D3V3MX-2GP

C111

12

C62

SC4D7U6D3V3MX-2GP

SCD1U10V2KX-4GP

+1.1V_RUN_VDDHTRX

C674

SCD1U10V2KX-4GP

12

+1.2V_RUN_VDDHTTX

C104

12

SCD1U10V2KX-4GP

DY

+1.8V_RUN_VDDA18PCIE

12

C57

C53

SCD1U10V2KX-4GP

DY

C677

12

SC4D7U6D3V3MX-2GP

12

C106

12

DY

C95

12

C94

SCD1U10V2KX-4GP

12

C102

SCD1U10V2KX-4GP

12

SCD1U10V2KX-4GP

DY

C101

12

SCD1U10V2KX-4GP

DY

12

C61

C47

SCD1U10V2KX-4GP

DY

-1

1D8V_S0

12

C59

SC1U10V2KX-1GP

1 2

0R0603-PAD

R320

+1.8V_RUN_VDD18_MEM

12

C651

SC1U10V2KX-1GP

M16 R16

H18 G19

D22

AE25 AD24 AC23 AB22 AA21

W19

U17 R17 M17

M10

R10 AA9

AB9 AD9 AE9 U10

AE11 AD11

J17 K16 L16

P16 T16

F20 E21

B23 A23

Y20 V18 T17 P17

J10 P10 K10

L10

T10

W9

H9

Y9

F9

G9

4

ANB1E

VDDHT_1 VDDHT_2 VDDHT_3 VDDHT_4 VDDHT_5 VDDHT_6 VDDHT_7

VDDHTRX_1 VDDHTRX_2 VDDHTRX_3 VDDHTRX_4 VDDHTRX_5 VDDHTRX_6 VDDHTRX_7

VDDHTTX_1 VDDHTTX_2 VDDHTTX_3 VDDHTTX_4 VDDHTTX_5 VDDHTTX_6 VDDHTTX_7 VDDHTTX_8 VDDHTTX_9 VDDHTTX_10 VDDHTTX_11 VDDHTTX_12 VDDHTTX_13

VDDA18PCIE_1 VDDA18PCIE_2 VDDA18PCIE_3 VDDA18PCIE_4 VDDA18PCIE_5 VDDA18PCIE_6 VDDA18PCIE_7 VDDA18PCIE_8 VDDA18PCIE_9 VDDA18PCIE_10 VDDA18PCIE_11 VDDA18PCIE_12 VDDA18PCIE_13 VDDA18PCIE_14 VDDA18PCIE_15

VDD18_1 VDD18_2 VDD18_MEM1 VDD18_MEM2

RS780M-GP-U2

PART 5/6

POWER

VDDPCIE_1 VDDPCIE_2 VDDPCIE_3 VDDPCIE_4 VDDPCIE_5 VDDPCIE_6 VDDPCIE_7 VDDPCIE_8

VDDPCIE_9 VDDPCIE_10 VDDPCIE_11 VDDPCIE_12 VDDPCIE_13 VDDPCIE_14 VDDPCIE_15 VDDPCIE_16 VDDPCIE_17

VDDC_1 VDDC_2 VDDC_3 VDDC_4 VDDC_5 VDDC_6 VDDC_7 VDDC_8

VDDC_9 VDDC_10 VDDC_11 VDDC_12 VDDC_13 VDDC_14 VDDC_15 VDDC_16 VDDC_17 VDDC_18 VDDC_19 VDDC_20 VDDC_21 VDDC_22

VDD_MEM1 VDD_MEM2 VDD_MEM3 VDD_MEM4 VDD_MEM5 VDD_MEM6

VDD33_1 VDD33_2

A6 B6 C6 D6 E6 F6 G7 H8 J9 K9 M9 L9 P9 R9 T9 V9 U9

K12 J14 U16 J11 K15 M12 L14 L11 M13 M15 N12 N14 P11 P13 P14 R12 R15 T11 T15 U12 T14 J16

AE10 AA11 Y11 AD10 AB10 AC10

H11

+3.3V_RUN_VDD33

H12

C66

SCD1U10V2KX-4GP

C66

3

300mil Width

12

C83

DY

1103

10A per ANT Rev1.1, Page3

12

C49

C55

SCD1U10V2KX-4GP

C55

SCD1U10V2KX-4GP

DY

Per check list (Rev 0.02)

S780M: 1V ~ 1.1V, check PWR team

R

12

C52

DY

VDD_MEM

12

DY

12

C36

SCD1U10V2KX-4GP

1 2

0R0603-PAD

R316

12

C65

12

C90

C74

SCD1U10V2KX-4GP

DY

R30

1 2

0R0603-PAD

SCD1U10V2KX-4GP

1D1V_S0

SC1U10V2KX-1GP

12

C60

DY

3D3V_S0

12

C68

2

ANB1F

A25

VSSAHT1

D23 E22 G22 G24

12

SC1U10V2KX-1GP

C40

C40 SC4D7U6D3V3MX-2GP

SC4D7U6D3V3MX-2GP

-1

+NB_VCORE

1D1V_S0

12

C79

SCD1U10V2KX-4GP

DY

12

C46

12

C85

C76

SC10U6D3V3MX-GP

SCD1U10V2KX-4GP

SC10U6D3V3MX-GP

G25 H19

M20 N22 P20 R19 R22 R24 R25 H20 U22

V19 W22 W24 W25

Y21

AD25

M14

N13

P12

P15

R11

R14

T12

U14

U11

U15

V12 W11 W15

AC12 AA14

Y18

AB11 AB15 AB17 AB19 AE20 AB21

K11

J22 L17 L22 L24 L25

L12

RS780M-GP-U2

VSSAHT2 VSSAHT3 VSSAHT4 VSSAHT5 VSSAHT6 VSSAHT7 VSSAHT8 VSSAHT9 VSSAHT10 VSSAHT11 VSSAHT12 VSSAHT13 VSSAHT14 VSSAHT15 VSSAHT16 VSSAHT17 VSSAHT18 VSSAHT19 VSSAHT20 VSSAHT21 VSSAHT22 VSSAHT23 VSSAHT24 VSSAHT25 VSSAHT26 VSSAHT27

VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34

PART 6/6

GROUND

1

VSSAPCIE1 VSSAPCIE2 VSSAPCIE3 VSSAPCIE4 VSSAPCIE5 VSSAPCIE6 VSSAPCIE7 VSSAPCIE8

VSSAPCIE9 VSSAPCIE10 VSSAPCIE11 VSSAPCIE12 VSSAPCIE13 VSSAPCIE14 VSSAPCIE15 VSSAPCIE16 VSSAPCIE17 VSSAPCIE18 VSSAPCIE19 VSSAPCIE20 VSSAPCIE21 VSSAPCIE22 VSSAPCIE23 VSSAPCIE24 VSSAPCIE25 VSSAPCIE26 VSSAPCIE27 VSSAPCIE28 VSSAPCIE29 VSSAPCIE30 VSSAPCIE31 VSSAPCIE32 VSSAPCIE33 VSSAPCIE34 VSSAPCIE35 VSSAPCIE36 VSSAPCIE37 VSSAPCIE38 VSSAPCIE39 VSSAPCIE40

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9

VSS10

A2 B1 D3 D5 E4 G1 G2 G4 H7 J4 R7 L1 L2 L4 L7 M6 N4 P6 R1 R2 R4 V7 U4 V8 V6 W1 W2 W4 W7 W8 Y6 AA4 AB5 AB1 AB7 AC3 AC4 AE1 AE4 AB2

AE14 D11 G8 E14 E15 J15 J12 K14 M11 L15

B B

A A

5

AB12 AE16

AE15 AA12 AB16 AB14 AD14 AD13 AD15 AC16 AE13 AC14

AD16 AE17 AD17

W12

AD18 AB13 AB18

W14

AE12 AD12

V11

Y14

Y12

V14 V15

ANB1D

MEM_A0 MEM_A1 MEM_A2 MEM_A3 MEM_A4 MEM_A5 MEM_A6 MEM_A7 MEM_A8 MEM_A9 MEM_A10 MEM_A11 MEM_A12 MEM_A13

MEM_BA0 MEM_BA1 MEM_BA2

MEM_RAS# MEM_CAS# MEM_WE# MEM_CS# MEM_CKE MEM_ODT

MEM_CKP MEM_CKN

MEM_COMPP MEM_COMPN

RS780M-GP-U2

PAR 4 OF 6

MEM_DQ0/DVO_VSYNC MEM_DQ1/DVO_HSYNC

MEM_DQ2/DVO_DE MEM_DQ3/DVO_D0

MEM_DQ4 MEM_DQ5/DVO_D1 MEM_DQ6/DVO_D2 MEM_DQ7/DVO_D4 MEM_DQ8/DVO_D3 MEM_DQ9/DVO_D5

MEM_DQ10/DVO_D6 MEM_DQ11/DVO_D7

MEM_DQ12

MEM_DQ13/DVO_D9 MEM_DQ14/DVO_D10 MEM_DQ15/DVO_D11

MEM_DQS0P/DVO_IDCKP MEM_DQS0N/DVO_IDCKN

MEM_DQS1P

MEM_DQS1N

MEM_DM0

MEM_DM1/DVO_D8

SBD_MEM/DVO_I/F

4

IOPLLVDD18

IOPLLVDD

IOPLLVSS

MEM_VREF

AA18 AA20 AA19 Y19 V17 AA17 AA15 Y15 AC20 AD19 AE22 AC18 AB20 AD22 AC22 AD21

Y17 W18 AD20 AE21

W17 AE19

AE23 AE24

AD23 AE18

MEM_COMP_P and MEM_COMP_N trace width >=10mils and 10mils spacing from other Signals in X,Y,Z directions

1D8V_S0

R339

1 2

0R0402-PAD

+1.8V_IOPLLVDD18

+1.1V_IOPLLVDD

1 2

0R0402-PAD

R341

1D1V_S0

3

JV50-TR8

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

ATi-RS880M_Side Port&PWR&GND(3/3)

Size Document Number Rev

A3

Date: Sheet of

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

JV50-TR8

-1

10 63Monday, October 05, 2009

1

-1

5

R146

R146 33R2J-2-GP

33R2J-2-GP

PLT_RST1#6,9,26,33,36,55

ALINK_NBRX_SBTX_P08 ALINK_NBRX_SBTX_N08 ALINK_NBRX_SBTX_P18 ALINK_NBRX_SBTX_N18 ALINK_NBRX_SBTX_P28 ALINK_NBRX_SBTX_N28 ALINK_NBRX_SBTX_P38

D D

1D2V_S0 +1.2V_RUN_PCIE_PVDD PCIE_VDDR

L24

1 2

PBY201209T-221Y-N-GP

220 ohm 2A

68.00206.121

2ND = 68.00216.161

C C

PLT_RST1#6,9,26,33,36,55

ALINK_NBRX_SBTX_N38

>15mil Width

12

C810

C811

SC1U10V2KX-1GP

3D3V_S5

147

1 2

73.07408.L16

2ND = 73.07408.L15

2ND = 73.07408.L15 3RD = 73.07408.02B

3RD = 73.07408.02B

43 mA

U16A

3

TSLVC08APW-1-GP

1 2

C774 SCD1U16V2KX-3GPC774 SCD1U16V2KX-3GP

1 2

C777 SCD1U16V2KX-3GPC777 SCD1U16V2KX-3GP

1 2

C779 SCD1U16V2KX-3GPC779 SCD1U16V2KX-3GP

1 2

C787 SCD1U16V2KX-3GPC787 SCD1U16V2KX-3GP

1 2

C794 SCD1U16V2KX-3GPC794 SCD1U16V2KX-3GP

1 2

C791 SCD1U16V2KX-3GPC791 SCD1U16V2KX-3GP

1 2

C802 SCD1U16V2KX-3GPC802 SCD1U16V2KX-3GP

1 2

C801 SCD1U16V2KX-3GPC801 SCD1U16V2KX-3GP

1 2

ALINK_NBTX_C_SBRX_P08 ALINK_NBTX_C_SBRX_N08 ALINK_NBTX_C_SBRX_P18 ALINK_NBTX_C_SBRX_N18 ALINK_NBTX_C_SBRX_P28 ALINK_NBTX_C_SBRX_N28 ALINK_NBTX_C_SBRX_P38 ALINK_NBTX_C_SBRX_N38

R143 562R2F-GPR143 562R2F-GP

1 2

R147 2K05R2F-GPR147 2K05R2F-GP

1 2

Place R <100mils form pins T25,T24

PLT_RST1#_B 32,33,34,37

for TR

For SB710

1 2

DY

R162 10MR2J-L-GP

C424

B B

82.30001.691

2ND = 82.30001.A81

12

SC18P50V2JN-1-GP

X4X-32D768KHZ-38GPU

2 3

12

C433 SC18P50V2JN-1-GPC433 SC18P50V2JN-1-GP

4

12

1

SB

A A

R164

R164 10MR2J-L-GP

10MR2J-L-GP

32K_X2

CLK_SB_14M3

4

ASB1A

NB_RST#

ALINK_NBRX_C_SBTX_P0 ALINK_NBRX_C_SBTX_N0 ALINK_NBRX_C_SBTX_P1 ALINK_NBRX_C_SBTX_N1 ALINK_NBRX_C_SBTX_P2 ALINK_NBRX_C_SBTX_N2 ALINK_NBRX_C_SBTX_P3 ALINK_NBRX_C_SBTX_N3

PCIE_CALRP

PCIE_CALRN

CLK_PCIE_SB3 CLK_PCIE_SB#3

CLK_SB_14M_1

R440

1 2

0R0402-PAD

TP209

TPAD14-GP

-1

NB_ALLOW_LDTSTOP9 RTC_CLK 15,35

TPAD14-GP

TP210

TPAD14-GP

PROCHOT#_SB6

CPU_PW RGD6,52

CPU_LDT_STOP#6 CPU_LDT_RST#6,52

N2

A_RST#

V23

PCIE_TX0P

V22

PCIE_TX0N

V24

PCIE_TX1P

V25

PCIE_TX1N

U25

PCIE_TX2P

U24

PCIE_TX2N

T23

PCIE_TX3P

T22

PCIE_TX3N

U22

PCIE_RX0P

U21

PCIE_RX0N

U19

PCIE_RX1P

V19

PCIE_RX1N

R20

PCIE_RX2P

R21

PCIE_RX2N

R18

PCIE_RX3P

R17

PCIE_RX3N

T25

PCIE_CALRP

T24

PCIE_CALRN

P24

PCIE_PVDD

P25

PCIE_PVSS

N25

PCIE_RCLKP/NB_LNK_CLKP

N24

PCIE_RCLKN/NB_LNK_CLKN

K23

NB_DISP_CLKP

K22

NB_DISP_CLKN

M24

NB_HT_CLKP

M25

NB_HT_CLKN

P17

CPU_HT_CLKP

M18

CPU_HT_CLKN

M23

SLT_GFX_CLKP

M22

SLT_GFX_CLKN

J19

GPP_CLK0P

J18

GPP_CLK0N

L20

GPP_CLK1P

L19

GPP_CLK1N

M19

GPP_CLK2P

M20

GPP_CLK2N

N22

GPP_CLK3P

P22

GPP_CLK3N

L18

25M_48M_66M_OSC

J21

25M_X1

J20

25M_X2

A3

X1

B3

X2

F23

ALLOW_LDTSTP

F24

PROCHOT#

F22

LDT_PG

G25

LDT_STP#

G24

LDT_RST#

SB700-1-GP-U1

Part 1 of 5

RTC XTAL

CPU

SB700

PCI EXPRESS INTERFACE

LPC

RTC

3

PCICLK0 PCICLK1 PCICLK2 PCICLK3 PCICLK4

PCICLK5/GPIO41

PCI CLKS

PCIRST#

FRAME#

DEVSEL#

PCI INTERFACE

REQ3#/GPIO70 REQ4#/GPIO71

GNT3#/GPIO72 GNT4#/GPIO73

CLKRUN#

INTE#/GPIO33

CLOCK GENERATOR

INTF#/GPIO34 INTG#/GPIO35 INTH#/GPIO36

LPCCLK0 LPCCLK1

LFRAME#

LDRQ1#/GNT5#/GPIO68

BMREQ#/REQ5#/GPIO65

RTCCLK

INTRUDER_ALERT#

AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8

AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31

CBE0# CBE1# CBE2# CBE3#

IRDY#

TRDY#

PAR

STOP# PERR# SERR# REQ0# REQ1# REQ2#

GNT0# GNT1# GNT2#

LOCK#

LAD0 LAD1 LAD2 LAD3

LDRQ0#

SERIRQ

VBAT

PCI_CLK0_R

P4

PCI_CLK1_R

P3

PCI_CLK2_R

P1

PCI_CLK3_R

P2

PCI_CLK4_R

T4

PCI_CLK5_R

T3

PCIRST#_SB

N1

U2 P7 V4 T1 V3 U1 V1 V2 T2 W1 T9 R6 R7 R5 U8 U5 Y7 W8 V9 Y8 AA8 Y4 Y3 Y2 AA2 AB4 AA1 AB3 AB2 AC1 AC2 AD1 W2 U7 AA7 Y1 AA6 W5 AA5 Y5 U6 W6 W4 V7

PCI_REQ#0

AC3

PCI_REQ#1

AD4

PCI_REQ#2

AB7

PCI_REQ#3

AE6

PCI_REQ#4

AB6

PCI_GNT#0

AD2

PCI_GNT#1

AE4

PCI_GNT#2

AD5

PE_GPIO1

AC6

PCI_GNT#4

AE5 AD6 V5

AD3 AC4 AE2 AE3

G22 E22 H24 H23 J25 J24 H25 H22 AB8 AD7 V15

C3

INTRUDER#

C2

RTC_AUX_S5_R

B2

PCI_LOCK#32K_X1

INT_PIRQE# INT_PIRQF# INT_PIRQG# PE_GPIO

LPCCLK0_R LPCCLK1_R

LDRQ0# LDRQ1# PCI_REQ#5

12

C407

R144 0R0402-PADR144 0R0402-PAD R141 0R0402-PADR141 0R0402-PAD R137 0R0402-PADR137 0R0402-PAD R138 0R0402-PADR138 0R0402-PAD

PCI_AD23 15 PCI_AD24 15 PCI_AD25 15 PCI_AD26 15 PCI_AD27 15 PCI_AD28 15 PCI_AD29 15 PCI_AD30 15

TP213 TPAD14-GPTP213 TPAD14-GP TP193 TPAD14-GPTP193 TPAD14-GP

INT_SERIRQ 36

12

C408

SC1U10V2KX-1GP

TP204 TPAD14-GPTP204 TPAD14-GP TP203 TPAD14-GPTP203 TPAD14-GP

1 2 1 2 1 2 1 2

TP138 TPAD14-GPTP138 TPAD14-GP

TP124 TPAD14-GPTP124 TPAD14-GP TP119 TPAD14-GPTP119 TPAD14-GP TP198 TPAD14-GPTP198 TPAD14-GP TP115 TPAD14-GPTP115 TPAD14-GP TP197 TPAD14-GPTP197 TPAD14-GP TP117 TPAD14-GPTP117 TPAD14-GP TP121 TPAD14-GPTP121 TPAD14-GP TP118 TPAD14-GPTP118 TPAD14-GP

TP120 TPAD14-GPTP120 TPAD14-GP TP201 TPAD14-GPTP201 TPAD14-GP TP116 TPAD14-GPTP116 TPAD14-GP

TP191 TPAD14-GPTP191 TPAD14-GP TP123 TPAD14-GPTP123 TPAD14-GP

RN51

1 2 3

TP148

1 2

SCD1U16V2ZY-2GP

RN51

4

LPC_LAD0 36,37 LPC_LAD1 36,37 LPC_LAD2 36,37 LPC_LAD3 36,37

LPC_LFRAME# 36,37

PCI_REQ#5 12

TPAD14-GP

R158

510R2J-1-GP

2

SRN22-3-GP

RTC_AUX_S5

TP262 TPAD14-GPTP262 TPAD14-GP

TP263 TPAD14-GPTP263 TPAD14-GP

EC48

1 2

DY

EC47

1 2

DY

PCI_CLK2 15 PCI_CLK3 15

CLK_PCI4 15

EC40 SC22P50V2JN-4GPDYEC40 SC22P50V2JN-4GP

12

DY

CLK_PCI_LOM 15

12

DY

EC41 SC22P50V2JN-4GPDYEC41 SC22P50V2JN-4GP

EC42 SC22P50V2JN-4GPDYEC42 SC22P50V2JN-4GP

EC39 SC22P50V2JN-4GPDYEC39 SC22P50V2JN-4GP

12

DY

090917-remove Muxless circuit

R126

R126 10KR2J-3-GP

10KR2J-3-GP

LPC_LAD[0..3]

1

2 NP1 NP2

BAT-CON2-1-GP-U

PM_CLKRUN# 36

ARTC1

PWR GND NP1 NP2

62.70001.011

PCLK_FW H 15,37

PCLK_KBC 15,36

SC22P50V2JN-4GP

SC22P50V2JN-4GP SC22P50V2JN-4GP

SC22P50V2JN-4GP

12

C409

DY

JV50-TR8

12

DY

SCD1U16V2ZY-2GP

1

LPC_LAD[0..3] 36,37

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

ATi-SB710_PCIE&PCI_(1/5)

ize Document Number Rev

Size Document Number Rev

S

A3

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

JV50-TR8

-1

11 63Monday, October 26, 2009

1

-1

5

4

3

2

1

NB_PWRGD_R

NB_PWRGD9,42

1D8V_S0

1 2

R419 300R2J-4-GPR419 300R2J-4-GP

3D3V_S0

D D

1 2

DY

R411 10KR2J-3-GP

3D3V_S5

1 2

DY

R445 2K2R2F-GP

1 2

DY

R443 2K2R2F-GP

1 2

DY

R442 2K2R2F-GP

1 2

DY

R154 10KR2J-3-GP

1 2

DY

R444 10KR2J-3-GP

1 2

DY

R441 10KR2J-3-GP

RN97

SRN10KJ-6-GP

3D3V_S5 3D3V_S0

1 2 3 45

R570

ACZ_SDATAOUT_MDC31

R571

R571 R572

R572

8 7

C C

B B

6

NEWCARD /GLAN

SRN4K7J-10-GP

SMB_CLK26,33,34 SMB_DATA26,33,34

A A

SMBC0_SB3,16,17 SMBD0_SB3,16,17

SC100P50V2JN-3GP

5

12

R422 0R2J-2-GP

DY

NB_PWRGD

FP_ID

SB_TEST2 SB_TEST1 SB_TEST0

ICH_PME# PCIE_WAKE# SMB_ALERT#

PM_SLP_S5#

ECSCI#_1 ECSWI#

PM_SLP_S3#

1 2 1 2

ACZ_BITCLK28

ACZ_SDATAIN028 ACZ_SDATAIN131

ACZ_SYNC28,31 ACZ_RST#28,31

RN53

RSMRST#_KBC_SB

10KR2J-3-GP

10KR2J-3-GP 10KR2J-3-GP

10KR2J-3-GP

PCI_REQ#5

10KR2J-3-GP

3D3V_S03D3V_S5

678

4 5

12

1 2

ACZ_BTCLK_MDC31

ACZ_SDATAOUT28

C859

SB

ECSMI#_KBC

R439

R448

10KR2J-3-GP

DY

1 2

123

C857

C857 SC100P50V2JN-3GP

SC100P50V2JN-3GP

3D3V_S0

PCI_REQ#5 11

Close to SB710

EC45

EC44

SC12P50V2JN-3GP

1 2

DY

R410

R410 1KR2F-3-GP

1KR2F-3-GP

1 2

SB

R172

1 2

R173 33R2J-2-GPR173 33R2J-2-GP

SRN33J-5-GP-U

EC80

EC43

SC12P50V2JN-3GP

1 2

DY

KA20GATE36 KBRCIN#36 ECSCI#_136

RSMRST#_KBC_SB42

GPIO0/HDMI

for TR

RN49

SRN33J-5-GP-U

1 2 3

33R2J-2-GP

RN96

1 2 3

EC82

SC12P50V2JN-3GP

1 2

DY

PCIE_WAKE#26,34

4

TPAD14-GP

TPAD14-GP TPAD14-GP

TPAD14-GP

TPAD14-GP TPAD14-GP

TPAD14-GP

ACZ_SPKR28

TPAD14-GP

TPAD14-GP TPAD14-GP

TPAD14-GP

4

3D3V_S0

PM_SLP_S3#34,35,36,42,44,49,53,54 PM_SLP_S5#34,36,48 PM_PWRBTN#36,52

SB_PWRGD42

TPAD14-GP

EC_TMR36

FP_ID38

TPAD14-GP

TPAD14-GP TPAD14-GP

TPAD14-GP

TPAD14-GP TPAD14-GP

TPAD14-GP

4

R151

10KR2J-3-GP

DY

1 2

R152

1 2

DY

10KR2J-3-GP

TP208

ECSMI#_KBC

TP141

TP141 TP139

TP139

TP190

TP190 TP194

TP194 TP192

TP192

TP196

TP196 TP199

TP199 TP149

TP149 TP200

TP200 TP218

TP218

ECSWI#36

USB_OC#425

CPPE#34

TP212TP212 TP214TP214 TP216TP216

TP221TP221 TP147TP147 TP145TP145 TP222TP222

TP143TP143 TP142TP142 TP211TP211

PM_SUS_STAT# SB_TEST2 SB_TEST1 SB_TEST0

GEVENT5# SYS_RST#

EC_TMR SMB_ALERT# NB_PWRGD_R

RSMRST#_KBC_SB

DDC1_SCL

DDC1_SDA

GEVENT7#

TP151

TP220

TP220 TP150

TP150

USB_OC#025

ACZ_BIT_CLK

ACZ_SDATAOUT_R

TP206

TP206 TP205

TP205

ACZ_SYNC_R

TP207TP207

ACZ_RST#_R 15

TO STRAPS

1 1 1

1 1 1 1

ICH_PME#

1

RI#

1

S2#

1

FP_ID GPIO6 GPIO4

GPIO39

SMBC0_SB

SMBD0_SB SMB_CLK SMB_DATA

SATA_DET#

GPIO5

USB_OC#5 USB_OC#4

USB_OC#2 USB_OC#1

ACZ_SDIN2 ACZ_SDIN3

ACZ_RST#_R

1

IMC_GPIO0 IMC_GPIO1 IMC_GPIO2 IDE_RST#

IMC_GPIO4 IMC_GPIO5 IMC_GPIO6 IMC_GPIO7

GPM8#

ASB1D

E1

PCI_PME#/GEVENT4#

E2

RI#/EXTEVNT0#

H7

SLP_S2/GPM9#

F5

SLP_S3#

G1

SLP_S5#

H2

PWR_BTN#

H1

PWR_GOOD

K3

SUS_STAT#

H5

TEST2

H4

TEST1

H3

TEST0

Y15

GA20IN/GEVENT0#

W15

KBRST#/GEVENT1#

K4

LPC_PME#/GEVENT3#

K24

LPC_SMI#/EXTEVNT1#

F1

S3_STATE/GEVENT5#

J2

SYS_RESET#/GPM7#

H6

WAKE#/GEVENT8#

F2

BLINK/GPM6#

J6

SMBALERT#/THRMTRIP#/GEVENT2#

W14

NB_PWRGD

D3

RSMRST#

AE18

SATA_IS0#/GPIO10

AD18

CLK_REQ3#/SATA_IS1#/GPIO6

AA19

SMARTVOLT/SATA_IS2#/GPIO4

W17

CLK_REQ0#/SATA_IS3#/GPIO0

V17

CLK_REQ1#/SATA_IS4#/FANOUT3/GPIO39

W20

CLK_REQ2#/SATA_IS5#/FANIN3/GPIO40

W21

SPKR/GPIO2

AA18

SCL0/GPOC0#

W18

SDA0/GPOC1#

K1

SCL1/GPOC2#

K2

SDA1/GPOC3#

AA20

DDC1_SCL/GPIO9

Y18

DDC1_SDA/GPIO8

C1

LLB#/GPIO66

Y19

SHUTDOWN#/GPIO5

G5

DDR3_RST#/GEVENT7#

B9

USB_OC6#/IR_TX1/GEVENT6#

B8

USB_OC5#/IR_TX0/GPM5#

A8

USB_OC4#/IR_RX0/GPM4#

A9

USB_OC3#/IR_RX1/GPM3#

E5

USB_OC2#/GPM2#

F8

USB_OC1#/GPM1#

E4

USB_OC0#/GPM0#

M1

AZ_BITCLK

M2

AZ_SDOUT

J7

AZ_SDIN0/GPIO42

J8

AZ_SDIN1/GPIO43

L8

AZ_SDIN2/GPIO44

M3

AZ_SDIN3/GPIO46

L6

AZ_SYNC

M4

AZ_RST#

L5

AZ_DOCK_RST#/GPM8#

H19

IMC_GPIO0

H20

IMC_GPIO1

H21

SPI_CS2#/IMC_GPIO2

F25

IDE_RST#/F_RST#/IMC_GPO3

D22

IMC_GPIO4

E24

IMC_GPIO5

E25

IMC_GPIO6

D23

IMC_GPIO7

SB700-1-GP-U1

3

Part 4 of 5

SB700

USBCLK/14M_25M_48M_OSC

ACPI / WAKE UP EVENTS

USB OC

HD AUDIO

INTEGRATED uC

Part 4 of 5

USB_RCOMP

USB_FSD13P

USB MISC

USB_FSD13N USB_FSD12P

USB_FSD12N

USB_HSD11P

USB 1.1

USB_HSD11N

USB_HSD10P

USB_HSD10N

USB_HSD9P USB_HSD9N

USB_HSD8P USB_HSD8N

USB_HSD7P USB_HSD7N

USB_HSD6P USB_HSD6N

USB_HSD5P USB_HSD5N

USB_HSD4P

USB 2.0

USB_HSD4N USB_HSD3P

GPIO

USB_HSD3N USB_HSD2P

USB_HSD2N USB_HSD1P

USB_HSD1N USB_HSD0P

USB_HSD0N

IMC_GPIO8 IMC_GPIO9

IMC_PWM0/IMC_GPIO10

SCL2/IMC_GPIO11

SDA2/IMC_GPIO12

SCL3_LV/IMC_GPIO13

SDA3_LV/IMC_GPIO14

IMC_PWM1/IMC_GPIO15

IMC_PWM2/IMC_GPO16 IMC_PWM3/IMC_GPO17

IMC_GPIO18 IMC_GPIO19 IMC_GPIO20 IMC_GPIO21 IMC_GPIO22 IMC_GPIO23 IMC_GPIO24 IMC_GPIO25

IMC_GPIO26 IMC_GPIO27 IMC_GPIO28 IMC_GPIO29 IMC_GPIO30 IMC_GPIO31 IMC_GPIO32 IMC_GPIO33 IMC_GPIO34 IMC_GPIO35 IMC_GPIO36 IMC_GPIO37 IMC_GPIO38 IMC_GPIO39 IMC_GPIO40 IMC_GPIO41

C8 G8

E6 E7

F7 E8

H11 J10

E11 F11

A11 B11

C10 D10

G11 H12

E12 E14

C12 D12

B12 A12

G12 G14

H14 H15

A13 B13

B14 A14

A18 B18 F21 D21 F19 E20 E21 E19 D19 E18

G20 G21 D25 D24 C25 C24 B25 C23

B24 B23 A23 C22 A22 B22 B21 A21 D20 C20 A20 B20 B19 A19 D18 C18

CLK48_USB

USB_PCOMP

1 2

R167

R167 11K8R2F-GP

11K8R2F-GP

1%

Place R near pin14. Route it with 10mils Trace width and 25mils spacing to any signals in X, Y, Z directions.

USBPP10 32 USBPN10 32

USBPP8 19 USBPN8 19

USBPP4 33 USBPN4 33

USBPP3 25 USBPN3 25

USBPP1 25 USBPN1 25

USBPP2 25 USBPN2 25

USBPP5 24 USBPN5 24

R161

R161 10KR2J-3-GP

10KR2J-3-GP

Place these close SB700

1 2

DY

CLK48_USB_R2

Pair

11 CardReader 10 9 8 7 6 5

USBPP6 38 USBPN6 38

USBPP9 34 USBPN9 34

USBPP7 33 USBPN7 33

USBPP0 25 USBPN0 25

SB_GPO16 15 SB_GPO17 15

4 3 2 NEW1 1

Strap Pin / define to use LPC or SPI ROM

JV50-TR8

Title

ATi-SB710_USB&GPIO_(2/5)

ize Document Number Rev

Size Document Number Rev

S

A3

Date: Sheet of

2

Date: Sheet of

CLK48_USB 3

1 2

C432

SC10P50V2JN-4GP

USB

Device

WEBCAM

MINIC2 USB4 USB3 USB2 Bluetooth NC Fringer print

MINIC1 USB10

JV50-TR8

DY

OCP1#

OCP0#

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

12 63Wednesday, November 11, 2009

1

-1

5

PLACE SATA AC DECOUPLING CAPS CLOSE TO SB710

C370 SCD01U50V2KX-1GPC370 SCD01U50V2KX-1GP

D D

SATA HDD

SATA ODD

C C

SATA_TXP022 SATA_TXN022

SATA_RXN022 SATA_RXP022

SATA_TXP123 SATA_TXN123

SATA_RXN123 SATA_RXP123

1ST 82.30020.851

2ND = 82.30020.791

SB

B B

1 2

C371 SCD01U50V2KX-1GPC371 SCD01U50V2KX-1GP

1 2

C687 SCD01U50V2KX-1GPC687 SCD01U50V2KX-1GP

1 2

C686 SCD01U50V2KX-1GPC686 SCD01U50V2KX-1GP

1 2

C369 SCD01U50V2KX-1GPC369 SCD01U50V2KX-1GP

1 2

C368 SCD01U50V2KX-1GPC368 SCD01U50V2KX-1GP

1 2

C449 SCD01U50V2KX-1GPC449 SCD01U50V2KX-1GP

1 2

C446 SCD01U50V2KX-1GPC446 SCD01U50V2KX-1GP

1 2

C373

C373 SC15P50V2JN-2-GP

SC15P50V2JN-2-GP

12

X3XTAL-25MHZ-120-GP-U

12

C367

C367 SC15P50V2JN-2-GP

SC15P50V2JN-2-GP

3D3V_S0

Very Close to SB710

12

R127

R127 10MR2J-L-GP

10MR2J-L-GP

SATA_X2_R

R426

1 2

0R0603-PAD

R428

1 2

0R0603-PAD

3D3V_S0

1 2

R128 300R2J-4-GPR128 300R2J-4-GP

PLLVDD_SATA1D2V_S0

XTLVDD_SATA

R573 10KR2J-3-GPR573 10KR2J-3-GP R574 10KR2J-3-GPR574 10KR2J-3-GP R575 10KR2J-3-GPR575 10KR2J-3-GP

1KR2F-3-GP

1 2

MEDIA_LED#39

15mil Width

>

12

C784

C784 SC1U10V2KX-1GP

SC1U10V2KX-1GP

>15mil Width

12

C778

C778 SC1U10V2KX-1GP

SC1U10V2KX-1GP

1 2 1 2 1 2

4

R434

SATA_TXP0_CSATA_TXP0_C SATA_TXN0_C

SATA_RXN0_C SATA_RXP0_C

SATA_TXP1_C SATA_TXN1_C

SATA_RXN1_C SATA_RXP1_CSATA_RXP1_C

SATA_CAL SATA_X1

93 mA

12

C785

SCD1U10V2KX-4GP

DY

AB10 AC10

AE10 AD10

AD11 AE11

AB12 AC12

AE12 AD12

AD13 AE13

AB14 AC14

AE14 AD14

AD15 AE15

AB16 AC16

AE16 AD16

SATA_X2

AA12

AA11

MEDIA_LED# PSW_CLR# ALERT#

ASB1B

AD9

SATA_TX0P

AE9

SATA_TX0N SATA_RX0N

SATA_RX0P SATA_TX1P

SATA_TX1N SATA_RX1N

SATA_RX1P SATA_TX2P

SATA_TX2N SATA_RX2N

SATA_RX2P SATA_TX3P

SATA_TX3N SATA_RX3N

SATA_RX3P SATA_TX4P

SATA_TX4N SATA_RX4N

SATA_RX4P SATA_TX5P

SATA_TX5N SATA_RX5N

SATA_RX5P

V12

SATA_CAL

Y12

SATA_X1 SATA_X2

W11

SATA_ACT#/GPIO67

PLLVDD_SATA

W12

XTLVDD_SATA

SB700-1-GP-U1

SB700

Part 2 of 5

SATA PWR SERIAL ATA

3

IDE_D0/GPIO15 IDE_D1/GPIO16 IDE_D2/GPIO17 IDE_D3/GPIO18 IDE_D4/GPIO19 IDE_D5/GPIO20 IDE_D6/GPIO21 IDE_D7/GPIO22 IDE_D8/GPIO23 IDE_D9/GPIO24

ATA 66/100/133

IDE_D10/GPIO25 IDE_D11/GPIO26 IDE_D12/GPIO27 IDE_D13/GPIO28 IDE_D14/GPIO29 IDE_D15/GPIO30

SPI_DI/GPIO12

SPI_DO/GPIO11

SPI_CLK/GPIO47

SPI_HOLD#/GPIO31

SPI_CS#/GPIO32

LAN_RST#/GPIO13

ROM_RST#/GPIO14

SPI ROM

FANOUT0/GPIO3 FANOUT1/GPIO48 FANOUT2/GPIO49

FANIN0/GPIO50 FANIN1/GPIO51 FANIN2/GPIO52

TEMP_COMM TEMPIN0/GPIO61 TEMPIN1/GPIO62 TEMPIN2/GPIO63

TEMPIN3/TALERT#/GPIO64

VIN0/GPIO53 VIN1/GPIO54 VIN2/GPIO55

HW MONITOR

VIN3/GPIO56 VIN4/GPIO57 VIN5/GPIO58 VIN6/GPIO59 VIN7/GPIO60

IDE_IORDY

IDE_IRQ

IDE_A0 IDE_A1 IDE_A2

IDE_DACK#

IDE_DRQ

IDE_IOR#

IDE_IOW#

IDE_CS1# IDE_CS3#

AVDD AVSS

AA24 AA25 Y22 AB23 Y23 AB24 AD25 AC25 AC24 Y25 Y24

AD24 AD23 AE22 AC22 AD21 AE20 AB20 AD19 AE19 AC20 AD20 AE21 AB22 AD22 AE23 AC23

G6 D2 D1 F4 F3

LAN_RST#

U15

ROM_RST#

J1 M8

M5 M7

P5 P8 R8

C6 B6 A6 A5 B5

PSW_CLR#

A4 B4 C4 D4 D5 D6 A7 B7

>15mil Width

F6 G7

CLK_ID_0 CLK_ID_1

SB_SPI_MISO SPI_MOSI_R ICH_SPICLK

SB_SPI_HOLD ICH_SPICS0#

AVDD_HW M

C418

12

SCD1U10V2KX-4GP

2

TP217 TPAD14-GPTP217 TPAD14-GP TP146 TPAD14-GPTP146 TPAD14-GP TP144 TPAD14-GPTP144 TPAD14-GP TP215 TPAD14-GPTP215 TPAD14-GP TP219 TPAD14-GPTP219 TPAD14-GP

TP202 TPAD14-GPTP202 TPAD14-GP TP140 TPAD14-GPTP140 TPAD14-GP

ALERT# 35

3D3V_S5

R163

1 2

0R0603-PAD

12

C423

SC2D2U6D3V3KX-GP

DY

Layout connect to Cap then GND

CLK_ID_1 CLK_ID_0

Dummy CKG select

3D3V_S0

12

R407

R407 10KR2J-3-GP

10KR2J-3-GP

RTM

12

R416

R416 10KR2J-3-GP

10KR2J-3-GP

ICS+SEG

PSW_CLR#

GAP-OPEN

G106

12

R412

R412 10KR2J-3-GP

10KR2J-3-GP

SEG

R413

R413 10KR2J-3-GP

10KR2J-3-GP

ICS+RTM

21

1

CLK_ID (1,0) ICS: 0,0 SEG: 0,1 RTM: 1,0

A A

5

4

3

2

JV50-TR8

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

ATi-SB710_SATA-IDE_(3/5)

ize Document Number Rev

Size Document Number Rev

S

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

JV50-TR8

13 63Monday, October 26, 2009

1

-1

5

3D3V_S0

12

C435

D D

2ND = 68.00216.161

C C

PBY201209T-221Y-N-GP

12

EC81

DY

C781

SC4D7U6D3V3KX-GP

SC10U6D3V3MX-GP

1D2V_S0

PBY201209T-221Y-N-GP

220 ohm 2A

68.00206.121

DY

L25

1 2

DY

-1

L23

1 2

SCD1U16V2ZY-2GP

68.00206.121

2ND = 68.00216.161

C799

C800

SC1U10V2KX-1GP

>100mil Width

12

C394

SC4D7U6D3V3MX-2GP

>50mil Width

12

C354

SC10U6D3V3MX-GP

DY

SCD1U10V2KX-4GP

C809

C366

SC1U10V2KX-1GP

SC10U6D3V3MX-GP

12

C807

12

DY

C786

SCD1U10V2KX-4GP

C389

SC1U10V2KX-1GP

12

C773

PCIE_VDDR

12

SC1U10V2KX-1GP

AVDD_SATA1D2V_S0

C770

12

SCD1U10V2KX-4GP

C395

SCD1U10V2KX-4GP

Use Plane Shape for +3.3V_AVDD_USB

3D3V_S5

L27

68.00206.121

2ND = 68.00216.161

B B

L27

1 2

PBY201209T-221Y-N-GP

12

C428

C429

SC10U6D3V3MX-GP

DY

AVDD_USB

12

C416

SC1U10V2KX-1GP

12

C415

658 mA

>50mil Width

12

SC1U10V2KX-1GP

C420

SCD1U10V2KX-4GP

131 mA

>50mil Width

71 mA

600 mA

12

C396

SCD1U10V2KX-4GP

DY

567 mA

C772

SCD1U10V2KX-4GP

12

DY

12

C421

SCD1U10V2KX-4GP

DY

4

T15

U16 U17

W7

AA4 AB5

AB21

Y20 AA21 AA22 AE25

P18

P19

P20

P21

R22

R24

R25

AA14 AB18 AA15 AA17 AC18 AD17 AE17

A16

B16

C16

D16

D17

E17

F15 F17

F18 G15 G17 G18

L9

M9

U9

V8 Y6

ASB1C

VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 VDDQ_10 VDDQ_11 VDDQ_12

VDD33_18_1 VDD33_18_2 VDD33_18_3 VDD33_18_4

PCIE_VDDR_1 PCIE_VDDR_2 PCIE_VDDR_3 PCIE_VDDR_4 PCIE_VDDR_5 PCIE_VDDR_6 PCIE_VDDR_7

AVDD_SATA_1 AVDD_SATA_4 AVDD_SATA_2 AVDD_SATA_3 AVDD_SATA_5 AVDD_SATA_6 AVDD_SATA_7

AVDDTX_0 AVDDTX_1 AVDDTX_2 AVDDTX_3 AVDDTX_4 AVDDTX_5 AVDDRX_0 AVDDRX_1 AVDDRX_2 AVDDRX_3 AVDDRX_4 AVDDRX_5

SB700-1-GP-U1

SB700

Part 3 of 5

PCI/GPIO I/O

IDE/FLSH I/O

POWER

A-LINK I/O

3.3V_S5 I/OCORE S5

SATA I/O

USB_PHY_1.2V_1 USB_PHY_1.2V_2

PLL CLKGEN I/O

USB I/O

VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8

CORE S0

VDD_9

CKVDD_1.2V_1 CKVDD_1.2V_2 CKVDD_1.2V_3 CKVDD_1.2V_4

S5_3.3V_1 S5_3.3V_2 S5_3.3V_3 S5_3.3V_4 S5_3.3V_5 S5_3.3V_6 S5_3.3V_7

S5_1.2V_1 S5_1.2V_2

V5_VREF AVDDCK_3.3V AVDDCK_1.2V

AVDDC

L15 M12 M14 N13 P12 P14 R11 R15 T16

L21 L22 L24 L25

32 mA

A17 A24 B17 J4 J5 L1 L2

113 mA

G2 G4

197 mA

A10 B10

AE7 J16 K17 E9

17mA

510 mA

12

V5_VREF AVDDCK_3D3V AVDDK_1D2V

3D3V_AVDDC

12

C437

SCD1U10V2KX-4GP

DY

3

>100mil Width

12

C806

SC1U10V2KX-1GP

DY

12

C403

DY

>20mil Width

12

DY

>30mil Width

12

C427

SC1U10V2KX-1GP

DY

1 2

12

C436

SC1U10V2KX-1GP

1D2V_S0

12

C815

C805

SC2D2U6D3V3KX-GP

C404

PBY201209T-221Y-N-GP

SCD1U10V2KX-4GP

SC1U10V2KX-1GP

12

C400

SC2D2U6D3V3KX-GP

DY

3D3V_S5

12

C414

SC1U10V2KX-1GP

SCD1U10V2KX-4GP

12

C422

C431

SC1U10V2KX-1GP

DY

3D3V_S5

L28

68.00206.121

2ND = 68.00216.161

>15mil Width

DY

12

DY

SCD1U10V2KX-4GP

12

C814

C402

SC2D2U6D3V3KX-GP

12

C419

1D2V_S5

DY

12

C386

SCD1U10V2KX-4GP

DY

CKVDD

12

C401

DY

12

SCD1U10V2KX-4GP

12

C417

SCD1U10V2KX-4GP

>10mil Width

C769

SCD1U10V2KX-4GP

SC10U6D3V3MX-GP

R148

1 2

0R0402-PAD

SC2D2U6D3V3KX-GP

C405

SC4D7U6D3V3MX-2GP

12

C434

SC10U6D3V3MX-GP

12

C766

SC1U10V2KX-1GP

DY

1D2V_S0

-1

12

1KR2J-1-GP

K A

2ND = 83.R0304.A8F

2

5V_S0

R406

12

3D3V_S0

D26

RB751V-40-2-GP

83.R2004.B8F

AA9

AB9 AB11 AB13 AB15 AB17

AC8

AD8

AE8

M16

M17

M21

T10 U10 U11 U12

V14

Y11 Y14

A15 B15 C14

D11 D13 D14 D15 E15 F12 F14

H17

K10 K12 K14 K15

H18

K25

P16

V11 W9

Y17

J11 J12 J14 J15

J17 J22

Y9

D8 D9

G9

H9

J9

F9

ASB1E

SB700

AVSS_SATA_1 AVSS_SATA_2 AVSS_SATA_3 AVSS_SATA_4 AVSS_SATA_5 AVSS_SATA_6 AVSS_SATA_7 AVSS_SATA_8 AVSS_SATA_9 AVSS_SATA_10 AVSS_SATA_11 AVSS_SATA_12 AVSS_SATA_13 AVSS_SATA_14 AVSS_SATA_15 AVSS_SATA_16 AVSS_SATA_17 AVSS_SATA_18 AVSS_SATA_19 AVSS_SATA_20

AVSS_USB_1 AVSS_USB_2 AVSS_USB_3 AVSS_USB_4 AVSS_USB_5 AVSS_USB_6 AVSS_USB_7 AVSS_USB_8 AVSS_USB_9 AVSS_USB_10 AVSS_USB_11 AVSS_USB_12 AVSS_USB_13 AVSS_USB_14 AVSS_USB_15 AVSS_USB_16 AVSS_USB_17 AVSS_USB_18 AVSS_USB_19 AVSS_USB_20 AVSS_USB_21 AVSS_USB_22 AVSS_USB_23 AVSS_USB_24

PCIE_CK_VSS_1 PCIE_CK_VSS_2 PCIE_CK_VSS_3 PCIE_CK_VSS_4 PCIE_CK_VSS_5 PCIE_CK_VSS_6 PCIE_CK_VSS_7 PCIE_CK_VSS_8

AVSSC

SB700-1-GP-U1

Part 5 of 5

GROUND

1

VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8

VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50

PCIE_CK_VSS_9 PCIE_CK_VSS_10 PCIE_CK_VSS_11 PCIE_CK_VSS_12 PCIE_CK_VSS_13 PCIE_CK_VSS_14 PCIE_CK_VSS_15 PCIE_CK_VSS_16 PCIE_CK_VSS_17 PCIE_CK_VSS_18 PCIE_CK_VSS_19 PCIE_CK_VSS_20 PCIE_CK_VSS_21

AVSSCK

A2 A25 B1 D7 F20 G19 H8 K9 K11 K16 L4 L7 L10 L11 L12 L14 L16 M6 M10 M11 M13 M15 N4 N12 N14 P6 P9 P10 P11 P13 P15 R1 R2 R4 R9 R10 R12 R14 T11 T12 T14 U4 U14 V6 Y21 AB1 AB19 AB25 AE1 AE24

P23 R16 R19 T17 U18 U20 V18 V20 V21 W19 W22 W24 W25

L17

47 mA

AVDDCK_3D3V

C425

SCD1U10V2KX-4GP

62 mA

AVDDK_1D2V

C816

SCD1U10V2KX-4GP

A A

5

4

SCD1U10V2KX-4GP

C816

DY

3

>15mil Width

12

SC1U10V2KX-1GP

12

SC1U10V2KX-1GP

12

C426

DY

>15mil Width

12

C817

L26

0R0603-PAD

L52

1 2

0R0603-PAD

3D3V_S0

12

1D2V_S0

JV50-TR8

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

ATi-SB710_POWER&GND_(4/5)

Size Document Number Rev

A3

Date: Sheet of

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

JV50-TR8

-1

14 63Monday, October 05, 2009

1

-1

5

4

3

2

1

REQUIRED STRAPS

D D

R145

12

DY

10KR2J-3-GP

C C

1

23

RN46

SRN10KJ-5-GP

4

3D3V_S0 3D3V_S5

R140

R136

R142

DY

R136

R135

DY

12

10KR2J-3-GP

R139

12

10KR2J-3-GP

12

10KR2J-3-GP

DY

R153

12

10KR2J-3-GP

12

10KR2J-3-GP

REQUIRED SYSTEM STRAPS

R160

12

DY

10KR2J-3-GP

R159

DY

12

10KR2J-3-GP

1

4

23

RN50

RN50 SRN10KJ-5-GP

SRN10KJ-5-GP

R155

DY

R171

R430

12

10KR2J-3-GP

12

10KR2J-3-GP

R430

R429

DY

R171

DY

12

2K2R2F-GP

1

4

23

RN52

SRN2K2J-1-GP

12

DY

R166

R166 2K2R2F-GP

2K2R2F-GP

PCI_CLK2 11

PCI_CLK3 11

CLK_PCI4 11

CLK_PCI_LOM 11

PCLK_FW H 11,37 PCLK_KBC 11,36

RTC_CLK 11,35

ACZ_RST#_R 12

SB_GPO17 12

SB_GPO16 12

DEBUG STRAPS

TPAD14-GP

TPAD14-GP TPAD14-GP

TPAD14-GP

TP137

TP137 TP136

TP136 TP195

TP195 TP135

TP135 TP134

TP134 TP133

TP133 TP130

TP130 TP129

TP129

PCI_AD23 11 PCI_AD24 11 PCI_AD25 11 PCI_AD26 11 PCI_AD27 11 PCI_AD28 11 PCI_AD29 11 PCI_AD30 11

12

10KR2J-3-GP

12

10KR2J-3-GP

B B

PULL HIGH

PULL LOW

A A

PCI_CLK2

WatchDOG

NB_PWRGD)

( ENABLED

WatchDog (NB_PWRGD) DISABLED

DEFAULT

5

PCI_CLK3

USE DEBUG STRAPS

IGNORE DEBUG STRAPS

DEFAULT

CLK_PCI_LOM CLK_PCI4

RESERVED

PCLK_FWH

IMC ENABLED

IMC DISABLED

DEFAULT

CLKGEN ENABLED

Use Internal)

(

CLKGEN DISABLED

(Use External)

DEFAULT

RTCCLKPCLK_KBC

INTERNAL RTC

DEFAULT

EXT. RTC

(PD on X1, apply 32KHz to RTC_CLK)

AZ_RST#

ENABLE PCI ROM BOOT

DISABLE PCI ROM BOOT

DEFAULT

SB_GPO17 , SB_GPO16

ROM TYPE: H, H = Reserved

H, L = SPI ROM

L, H = LPC ROM

L, L = FWH ROM

NOTE: SB700 HAS INTERNAL 15K PULL UP RESISTOR FOR RTCCLK

4

DEFAULT

Note: SB700 has 15K internal PU FOR PCI_AD[30:23]

3

PCI_AD28

USE

PULL

LONG

HIGH

RESET

(DEFAULT) (DEFAULT)(DEFAULT)(DEFAULT)(DEFAULT)(DEFAULT)

USE

PULL

SHORT

LOW

RESET

USE PCI PLL

BYPASS PCI PLL

PCI_AD26PCI_AD27

USE ACPI BCLK

BYPASS ACPI BCLK

2

PCI_AD25 PCI_AD23

USE IDE PLL

BYPASS IDE PLL

JV50-TR8

Title

ize Document Number Rev

Size Document Number Rev

S

A3

Date: Sheet of

PCI_AD24

USE DEFAULT PCIE STRAPS

USE EEPROM PCIE STRAPS

ATi-SB710_STRAPPING_(5/5)

JV50-TR8

Reserved

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

PCI_AD30 PCI_AD29

Reserved

-1

15 63Monday, October 26, 2009

1

-1

5

D D

C C

B B

A A

5

VREF_DDR_MEM

SC2D2U6D3V3KX-GP

4

MEM_MA_ADD05,18 MEM_MA_ADD15,18 MEM_MA_ADD25,18 MEM_MA_ADD35,18 MEM_MA_ADD45,18 MEM_MA_ADD55,18 MEM_MA_ADD65,18 MEM_MA_ADD75,18 MEM_MA_ADD85,18 MEM_MA_ADD95,18 MEM_MA_ADD105,18 MEM_MA_ADD115,18 MEM_MA_ADD125,18 MEM_MA_ADD135,18 MEM_MA_ADD145,18 MEM_MA_ADD155,18

MEM_MA_BANK25,18 MEM_MA_BANK05,18 MEM_MA_BANK15,18

MEM_MA_DATA05 MEM_MA_DATA15 MEM_MA_DATA25 MEM_MA_DATA35 MEM_MA_DATA45 MEM_MA_DATA55 MEM_MA_DATA65 MEM_MA_DATA75 MEM_MA_DATA85 MEM_MA_DATA95 MEM_MA_DATA105 MEM_MA_DATA115 MEM_MA_DATA125 MEM_MA_DATA135 MEM_MA_DATA145 MEM_MA_DATA155 MEM_MA_DATA165 MEM_MA_DATA175 MEM_MA_DATA185 MEM_MA_DATA195 MEM_MA_DATA205 MEM_MA_DATA215 MEM_MA_DATA225 MEM_MA_DATA235 MEM_MA_DATA245 MEM_MA_DATA255 MEM_MA_DATA265 MEM_MA_DATA275 MEM_MA_DATA285 MEM_MA_DATA295 MEM_MA_DATA305 MEM_MA_DATA315 MEM_MA_DATA325 MEM_MA_DATA335 MEM_MA_DATA345 MEM_MA_DATA355 MEM_MA_DATA365 MEM_MA_DATA375 MEM_MA_DATA385 MEM_MA_DATA395 MEM_MA_DATA405 MEM_MA_DATA415 MEM_MA_DATA425 MEM_MA_DATA435 MEM_MA_DATA445 MEM_MA_DATA455 MEM_MA_DATA465 MEM_MA_DATA475 MEM_MA_DATA485 MEM_MA_DATA495 MEM_MA_DATA505 MEM_MA_DATA515 MEM_MA_DATA525 MEM_MA_DATA535 MEM_MA_DATA545 MEM_MA_DATA555 MEM_MA_DATA565 MEM_MA_DATA575 MEM_MA_DATA585 MEM_MA_DATA595 MEM_MA_DATA605 MEM_MA_DATA615 MEM_MA_DATA625 MEM_MA_DATA635

MEM_MA_DQS0_N5 MEM_MA_DQS1_N5 MEM_MA_DQS2_N5 MEM_MA_DQS3_N5 MEM_MA_DQS4_N5 MEM_MA_DQS5_N5 MEM_MA_DQS6_N5 MEM_MA_DQS7_N5

MEM_MA_DQS0_P5 MEM_MA_DQS1_P5 MEM_MA_DQS2_P5 MEM_MA_DQS3_P5 MEM_MA_DQS4_P5 MEM_MA_DQS5_P5 MEM_MA_DQS6_P5 MEM_MA_DQS7_P5

MEM_MA0_ODT05,18 MEM_MA0_ODT15,18

12

C845

Place C2.2uF and 0.1uF < 500mils from DDR connector

12

SCD1U10V2KX-4GP

C847

4

ADIMM2

102

A0

101

A1

100

A2

99

A3

98

A4

97

A5

94

A6

92

A7

93

A8

91

A9

105

A10/AP

90

A11

89

A12

116

A13

86

A14

84

A15

85

A16/BA2

107

BA0

106

BA1

5

DQ0

7

DQ1

17

DQ2

19

DQ3

4

DQ4

6

DQ5

14

DQ6

16

DQ7

23

DQ8

25

DQ9

35

DQ10

37

DQ11

20

DQ12

22

DQ13

36

DQ14

38

DQ15

43

DQ16

45

DQ17

55

DQ18

57

DQ19

44

DQ20

46

DQ21

56

DQ22

58

DQ23

61

DQ24

63

DQ25

73

DQ26

75

DQ27

62

DQ28

64

DQ29

74

DQ30

76

DQ31

123

DQ32

125

DQ33

135

DQ34

137

DQ35

124

DQ36

126

DQ37

134

DQ38

136

DQ39

141

DQ40

143

DQ41

151

DQ42

153

DQ43

140

DQ44

142

DQ45

152

DQ46

154

DQ47

157

DQ48

159

DQ49

173

DQ50

175

DQ51

158

DQ52

160

DQ53

174

DQ54

176

DQ55

179

DQ56

181

DQ57

189

DQ58

191

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

11

DQS0#

29

DQS1#

49

DQS2#

68

DQS3#

129

DQS4#

146

DQS5#

167

DQS6#

186

DQS7#

13

DQS0

31

DQS1

51

DQS2

70

DQS3

131

DQS4

148

DQS5

169

DQS6

188

DQS7

114

OTD0

119

OTD1

1

VREF

2

VSS

202

GND

MH1

SKT-SODIMM20020U4GP

62.10017.661

2ND = 62.10017.A41

3RD = 62.10017.G81

NORMAL TYPE

RAS#

WE#

CAS# CS0#

CS1# CKE0

CKE1

CK0#

CK1#

DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7

SDA

VDDSPD

NC#50 NC#69 NC#83

NC#120

NC#163/TEST

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

GND MH2

CK0

CK1

SCL

SA0 SA1

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

3

108 109 113

110 115

79 80

30 32

164 166

10 26 52 67 130 147 170 185

195 197

199 198

200 50

(A0)

69 83 120 163

1D8V_S3

81 82 87 88 95 96 103 104 111 112 117 118

3 8 9 12 15 18 21 24 27 28 33 34 39 40 41 42 47 48 53 54 59 60 65 66 71 72 77 78 121 122 127 128 132 133 138 139 144 145 149 150 155 156 161 162 165 168 171 172 177 178 183 184 187 190 193 196

201 MH2

3

MEM_MA_RAS# 5,18 MEM_MA_WE# 5,18 MEM_MA_CAS# 5,18

MEM_MA0_CS#0 5,18 MEM_MA0_CS#1 5,18

MEM_MA_CKE0 5,18 MEM_MA_CKE1 5,18

MEM_MA_CLK0_P 5 MEM_MA_CLK0_N 5

MEM_MA_CLK1_P 5 MEM_MA_CLK1_N 5

MEM_MA_DM0 5 MEM_MA_DM1 5 MEM_MA_DM2 5 MEM_MA_DM3 5 MEM_MA_DM4 5 MEM_MA_DM5 5 MEM_MA_DM6 5 MEM_MA_DM7 5

SMBD0_SB 3,12,17

SMBC0_SB 3,12,17

SC2D2U6D3V3KX-GP

PLACE CLOSE TO PROCESSOR WITHIN 1.5 INCH

3D3V_S0

C458

DY

MEM_MA_CLK0_P

12

C338

C338 SC1D5P50V2CN-1GP

SC1D5P50V2CN-1GP

MEM_MA_CLK0_N MEM_MA_CLK1_P

12

C331

SC1D5P50V2CN-1GP

MEM_MA_CLK1_N

12

DDR_VREF

1D8V_S3

RN100

1 2 3

SRN1KJ-7-GP

LAYOUT: Locate close to DIMM

VREF_DDR_MEM

12

C844

4

SCD1U10V2KX-4GP

2

C456

C456 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

DY

12

C834

SCD1U10V2KX-4GP

LOW 5.2 mm

2

12

C832

C832 SC1KP50V2KX-1GP

SC1KP50V2KX-1GP

1

JV50-TR8

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

ize Document Number Rev

Size Document Number Rev

S

Custom

Date: Sheet of

DDR_SO-DIMM SKT_1

Taipei Hsien 221, Taiwan, R.O.C.

JV50-TR8

1

16 63Monday, October 26, 2009

-1

5

MEM_MB_ADD05,18 MEM_MB_ADD15,18 MEM_MB_ADD25,18 MEM_MB_ADD35,18 MEM_MB_ADD45,18 MEM_MB_ADD55,18 MEM_MB_ADD65,18 MEM_MB_ADD75,18 MEM_MB_ADD85,18

MEM_MB_ADD95,18 MEM_MB_ADD105,18 MEM_MB_ADD115,18

D D

C C

B B

A A

5

VREF_DDR_MEM

SC2D2U6D3V3KX-GP

MEM_MB_ADD125,18 MEM_MB_ADD135,18 MEM_MB_ADD145,18 MEM_MB_ADD155,18

MEM_MB_BANK25,18 MEM_MB_BANK05,18 MEM_MB_BANK15,18

MEM_MB_DATA05 MEM_MB_DATA15 MEM_MB_DATA25 MEM_MB_DATA35 MEM_MB_DATA45 SMBD0_SB 3,12,16 MEM_MB_DATA55 MEM_MB_DATA65 MEM_MB_DATA75 MEM_MB_DATA85

MEM_MB_DATA95 MEM_MB_DATA105 MEM_MB_DATA115 MEM_MB_DATA125 MEM_MB_DATA135 MEM_MB_DATA145 MEM_MB_DATA155 MEM_MB_DATA165 MEM_MB_DATA175 MEM_MB_DATA185 MEM_MB_DATA195 MEM_MB_DATA205 MEM_MB_DATA215 MEM_MB_DATA225 MEM_MB_DATA235 MEM_MB_DATA245 MEM_MB_DATA255 MEM_MB_DATA265 MEM_MB_DATA275 MEM_MB_DATA285 MEM_MB_DATA295 MEM_MB_DATA305 MEM_MB_DATA315 MEM_MB_DATA325 MEM_MB_DATA335 MEM_MB_DATA345 MEM_MB_DATA355 MEM_MB_DATA365 MEM_MB_DATA375 MEM_MB_DATA385 MEM_MB_DATA395 MEM_MB_DATA405 MEM_MB_DATA415 MEM_MB_DATA425 MEM_MB_DATA435 MEM_MB_DATA445 MEM_MB_DATA455 MEM_MB_DATA465 MEM_MB_DATA475 MEM_MB_DATA485 MEM_MB_DATA495 MEM_MB_DATA505 MEM_MB_DATA515 MEM_MB_DATA525 MEM_MB_DATA535 MEM_MB_DATA545 MEM_MB_DATA555 MEM_MB_DATA565 MEM_MB_DATA575 MEM_MB_DATA585 MEM_MB_DATA595 MEM_MB_DATA605 MEM_MB_DATA615 MEM_MB_DATA625 MEM_MB_DATA635

MEM_MB_DQS0_N5 MEM_MB_DQS1_N5 MEM_MB_DQS2_N5 MEM_MB_DQS3_N5 MEM_MB_DQS4_N5 MEM_MB_DQS5_N5 MEM_MB_DQS6_N5 MEM_MB_DQS7_N5

MEM_MB_DQS0_P5 MEM_MB_DQS1_P5 MEM_MB_DQS2_P5 MEM_MB_DQS3_P5 MEM_MB_DQS4_P5 MEM_MB_DQS5_P5 MEM_MB_DQS6_P5 MEM_MB_DQS7_P5

MEM_MB0_ODT05,18 MEM_MB0_ODT15,18

C854

4

SCD1U10V2KX-4GP

12

C855

Place C2.2uF and 0.1uF < 500mils from DDR connector

4

ADIMM1

102

A0

101

A1

100

A2

99

A3

98

A4

97

A5

94

A6

92

A7

93

A8

91

A9

105

A10/AP

90

A11

89

A12

116

A13

86

A14

84

A15

85

A16/BA2

107

BA0

106

BA1

5

DQ0

7

DQ1

17

DQ2

19

DQ3

4

DQ4

6

DQ5

14

DQ6

16

DQ7

23

DQ8

25

DQ9

35

DQ10

37

DQ11

20

DQ12

22

DQ13

36

DQ14

38

DQ15

43

DQ16

45

DQ17

55

DQ18

57

DQ19

44

DQ20

46

DQ21

56

DQ22

58

DQ23

61

DQ24

63

DQ25

73

DQ26

75

DQ27

62

DQ28

64

DQ29

74

DQ30

76

DQ31

123

DQ32

125

DQ33

135

DQ34

137

DQ35

124

DQ36

126

DQ37

134

DQ38

136

DQ39

141

DQ40

143

DQ41

151

DQ42

153

DQ43

140

DQ44

142

DQ45

152

DQ46

154

DQ47

157

DQ48

159

DQ49

173

DQ50

175

DQ51

158

DQ52

160

DQ53

174

DQ54

176

DQ55

179

DQ56

181

DQ57

189

DQ58

191

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

11

DQS0#

29

DQS1#

49

DQS2#

68

DQS3#

129

DQS4#

146

DQS5#

167

DQS6#

186

DQS7#

13

DQS0

31

DQS1

51

DQS2

70

DQS3

131

DQS4

148

DQS5

169

DQS6

188

DQS7

114

OTD0

119

OTD1

1

VREF

2

VSS

202

GND

MH1

DDR2-200P-22-GP-U3

62.10017.A61

2ND = 62.10017.A51

HI 9.2mm

108

RAS#

109

WE#

113

CAS#

110

CS0#

115

CS1#

79

CKE0

80

CKE1

30

CK0

32

CK0#

164

CK1

166

CK1#

10

DM0

26

DM1

52

DM2

67

DM3

130

DM4

147

DM5

170

DM6

185

DM7

195

SDA

197

SCL

199

VDDSPD

198

SA0

200

SA1

50

NC#50

69

NC#69

83

NC#83

120

NC#120

NC#163/TEST

163

81

VDD

82

VDD

87

VDD

88

VDD

95

VDD

96

VDD

103

VDD

104

VDD

111

VDD

112

VDD

117

VDD

118

VDD

3

VSS

8

VSS

9

VSS

12

VSS

15

VSS

18

VSS

21

VSS

24

VSS

27

VSS

28

VSS

33

VSS

34

VSS

39

VSS

40

VSS

41

VSS

42

VSS

47

VSS

48

VSS

53

VSS

54

VSS

59

VSS

60

VSS

65

VSS

66

VSS

71

VSS

72

VSS

77

VSS

78

VSS

121

VSS

122

VSS

127

VSS

128

VSS

132

VSS

133

VSS

138

VSS

139

VSS

144

VSS

145

VSS

149

VSS

150

VSS

155

VSS

156

NORMAL TYPE

VSS

161

VSS

162

VSS

165

VSS

168

VSS

171

VSS

172

VSS

177

VSS

178

VSS

183

VSS

184

VSS

187

VSS

190

VSS

193

VSS

196

VSS

201

GND

MH2

3RD = 62.10017.G71

3

DIMM2_SA1

R203 10KR2J-3-GPR203 10KR2J-3-GP

1D8V_S3

3

MEM_MB_RAS# 5,18 MEM_MB_WE# 5,18 MEM_MB_CAS# 5,18

MEM_MB0_CS#0 5,18 MEM_MB0_CS#1 5,18

MEM_MB_CKE0 5,18 MEM_MB_CKE1 5,18

MEM_MB_CLK0_P 5 MEM_MB_CLK0_N 5

MEM_MB_CLK1_P 5 MEM_MB_CLK1_N 5

MEM_MB_DM0 5 MEM_MB_DM1 5 MEM_MB_DM2 5 MEM_MB_DM3 5 MEM_MB_DM4 5 MEM_MB_DM5 5 MEM_MB_DM6 5 MEM_MB_DM7 5

SMBC0_SB 3,12,16

1 2

C507

SC2D2U6D3V3KX-GP

(A2)

PLACE CLOSE TO PROCESSOR WITHIN 1.5 INCH

MEM_MB_CLK0_P

12

C348

C348 SC1D5P50V2CN-1GP

SC1D5P50V2CN-1GP

MEM_MB_CLK0_N MEM_MB_CLK1_P

12

C340

C340 SC1D5P50V2CN-1GP

SC1D5P50V2CN-1GP

MEM_MB_CLK1_N

1ST change to 62.10017.E21

3D3V_S0

12

DY

2

12

C499

C499 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

DY

2

1

JV50-TR8

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

ize Document Number Rev

Size Document Number Rev

S

Custom

Date: Sheet of

DDR_SO-DIMM SKT_2

Taipei Hsien 221, Taiwan, R.O.C.

JV50-TR8

17 63Monday, October 26, 2009

1

-1

5

4

3

2

1

Decoupling Capacitor

0D9V_S3

12

C450

SCD1U16V2ZY-2GP

DY

D D

PARALLEL TERMINATION

DY

Put decap near power(0.9V) and pull-up resistor

C451

12

SCD1U16V2ZY-2GP

C452

C470

SCD1U16V2ZY-2GP

12

C468

SCD1U16V2ZY-2GP

DY

C469

12

C498

SCD1U16V2ZY-2GP

12

C496

12

C515

SC1KP50V2KX-1GP

DY

C497

SC1KP50V2KX-1GP

DY

12

C514

SC1KP50V2KX-1GP

C516

DY

12

C513

SC10P50V2JN-4GP

Put decap near power(0.9V) and pull-up resistor

0D9V_S30D9V_S3

RN55

RN63

1

8

2

7

3

6

4 5

SRN47J-4-GP

RN66

1

8

2

7

3

6

4 5

SRN47J-4-GP

RN68

1

8

2

7

3

6

4 5

SRN47J-4-GP

C C

B B

SRN47J-4-GP

RN61

1 2 3 4 5

SRN47J-4-GP

RN62

1 2 3 4 5

SRN47J-4-GP

RN67

1 2 3 4 5

SRN47J-4-GP

RN69

1 2 3 4 5

SRN47J-4-GP

8 7 6

MEM_MA0_ODT1 5,16 MEM_MA0_CS#1 5,16 MEM_MA_WE# 5,16 MEM_MA_CAS# 5,16

MEM_MA_ADD8 5,16 MEM_MA_ADD5 5,16 MEM_MA_CKE1 5,16

MEM_MA_ADD15 5,16

MEM_MA_ADD4 5,16 MEM_MA_ADD2 5,16

MEM_MA_BANK1 5,16

MEM_MA_ADD0 5,16

MEM_MA_ADD12 5,16

MEM_MA_ADD9 5,16

MEM_MA_BANK2 5,16

MEM_MA_CKE0 5,16

MEM_MA_BANK0 5,16

MEM_MA_ADD10 5,16 MEM_MA_ADD3 5,16 MEM_MA_ADD1 5,16

MEM_MA_ADD14 5,16 MEM_MA_ADD7 5,16

MEM_MA_ADD11 5,16 MEM_MA_ADD6 5,16

MEM_MA0_CS#0 5,16 MEM_MA_RAS# 5,16

MEM_MA0_ODT0 5,16

MEM_MA_ADD13 5,16

RN55

1 2 3 4 5

SRN47J-4-GP

RN58

1 2 3 4 5

SRN47J-4-GP

RN59

1 2 3 4 5

SRN47J-4-GP

RN54

1 2 3 4 5

SRN47J-4-GP

RN60

1 2 3 4 5

SRN47J-4-GP

RN56

1 2 3 4 5

SRN47J-4-GP

SRN47J-4-GP RN57

RN57

1 2 3 4 5

SRN47J-4-GP

8 7 6

MEM_MB_ADD4 5,17 MEM_MB_ADD11 5,17 MEM_MB_ADD5 5,17 MEM_MB_ADD8 5,17

MEM_MB_ADD6 5,17 MEM_MB_ADD2 5,17 MEM_MB_ADD0 5,17 MEM_MB_BANK1 5,17

MEM_MB_RAS# 5,17 MEM_MB0_CS#0 5,17 MEM_MB0_ODT0 5,17 MEM_MB_ADD13 5,17

MEM_MB_ADD9 5,17 MEM_MB_ADD12 5,17 MEM_MB_BANK2 5,17 MEM_MB_CKE0 5,17

MEM_MB_CKE1 5,17 MEM_MB_ADD15 5,17 MEM_MB_ADD14 5,17 MEM_MB_ADD7 5,17

MEM_MB_BANK0 5,17 MEM_MB_ADD10 5,17 MEM_MB_ADD1 5,17 MEM_MB_ADD3 5,17

MEM_MB0_CS#1 5,17 MEM_MB0_ODT1 5,17 MEM_MB_CAS# 5,17 MEM_MB_WE# 5,17

Place these Caps near DM1

1D8V_S3

12

Place these Caps near DM2

12

Place these Caps near PARALLEL TERMINATION

0D9V_S3

12

C523

SCD1U16V2ZY-2GP

DY

C482

C840

12

SC2D2U6D3V3KX-GP

1D8V_S3

SC2D2U6D3V3KX-GP

C524

SCD1U16V2ZY-2GP

C480

SC2D2U6D3V3KX-GP

12

C481

SC2D2U6D3V3KX-GP

DY

12

C525

12

C838

SC2D2U6D3V3KX-GP

12

C487

SC2D2U6D3V3KX-GP

12

C526

SCD1U16V2ZY-2GP

DY

12

C841

C886

SC2D2U6D3V3KX-GP

SCD1U16V2ZY-2GP

DY

12

SCD1U16V2ZY-2GP

C839

C885

SCD01U50V2KX-1GP

SC2D2U6D3V3KX-GP

12

C527

C490

SCD1U16V2ZY-2GP

DY

12

SCD1U16V2ZY-2GP

DY

C884

C887

C484

SCD1U16V2ZY-2GP

12

SCD01U50V2KX-1GP

DY

12

C491

SCD1U16V2ZY-2GP

Layout Note: Place one cap close to every 2 pullup resistors terminated to 0D9V_S3

12

C483

C888

SC180P50V2JN-1GP

Layout Note: Place one cap close to every 2 pullup resistors terminated to 0D9V_S3

1D8V_S3

C488

SCD1U16V2ZY-2GP

12

C479

SCD1U16V2ZY-2GP

12

SCD1U16V2ZY-2GP

DY

Do not share the Term resistor between the DDR addess and Control Signals.

12

DY

A A

5

4

3

C478

C440

SCD1U16V2ZY-2GP

DY

12

C441

C442

SCD1U16V2ZY-2GP

DY

C444

12

C443

SCD1U16V2ZY-2GP

DY

2

12

C477

SCD1U16V2ZY-2GP

12

C489

C475

SCD1U16V2ZY-2GP

DY

SCD1U16V2ZY-2GP

DY

JV50-TR8

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

DDR_DAMPING & TERMINATION

ize Document Number Rev

Size Document Number Rev

S

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

JV50-TR8

18 63Monday, October 26, 2009

1

-1

5

LCD/INVERTER/CCD CONN

-

1

LCD1

41

D D

C C

B B

-1

USBPP812 USBPN812

3D3V_S0

DCBATOUT

2ND = 69.50007.A41

F1

1 2

POLYSW-1D1A24V-GP

69.50007.A31

LCD_CB_SEL36

1 2

R253 0R0402-PADR253 0R0402-PAD

1 2

R254 0R0402-PADR254 0R0402-PAD

DBC_EN36

LCD_EDID_CLK_1 LCD_EDID_DAT_1

BRIGHTNESS_CN BLON_OUT_1

DCBATOUT_LCD1

12

C5

SC10U35V0ZY-GPC5SC10U35V0ZY-GP

USBPP8_R USBPN8_R CCD_PW R

40 39

38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 42

2ND = 20.F1557.040

for TR

GMCH_LCDVDD_ON9

LCDVDD_ON56

A A

5

1 2

3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

ACES-CONN40C-4-GP

20.F1296.040

UMA

1 2

R2 0R2J-2-GP

1 2

R25 0R2J-2-GP

DIS

100KR2J-1-GP

R1

DY

12

LCDVDD

DY

4

12

C1

C1 SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

LCD_TXBCLK+ LCD_TXBCLKLCD_TXBOUT2+ LCD_TXBOUT2LCD_TXBOUT1+ LCD_TXBOUT1LCD_TXBOUT0+ LCD_TXBOUT0LCD_TXACLK+ LCD_TXACLKLCD_TXAOUT2+ LCD_TXAOUT2LCD_TXAOUT1+ LCD_TXAOUT1LCD_TXAOUT0+ LCD_TXAOUT0-

SB

CCD_PW R

12

C555

-1

LCDVDD

Layout 40 mil

12

C6

SCD1U16V2ZY-2GP

4

USBPN8_R USBPP8_R

12

SC4D7U6D3V5KX-3GP

DY

LCDVDD_ON_1

C2

SC4D7U6D3V5KX-3GPC2SC4D7U6D3V5KX-3GP

-1

DY

EC56

1 2

SC22P50V2JN-4GP

EC57

1 2

SC22P50V2JN-4GP

DY

C554

C554 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

U1

1

EN

2

GND OUT3IN#4

G5285T11U-GP

74.05285.07F

F2

1 2

FUSE-1D1A6V-4GP-U

69.50007.691

2ND = 69.50007.771

3D3V_S0

5

IN#5

4

3

for TR

LVDS_TXACLK-56 LVDS_TXACLK+56 LVDS_TXAOUT2-56 LVDS_TXAOUT2+56

LVDS_TXAOUT0-56 LVDS_TXAOUT0+56 LVDS_TXAOUT1-56 LVDS_TXAOUT1+56

LVDS_TXBCLK-56 LVDS_TXBCLK+56 LVDS_TXBOUT2-56 LVDS_TXBOUT2+56

LVDS_TXBOUT0-56 LVDS_TXBOUT0+56 LVDS_TXBOUT1-56 LVDS_TXBOUT1+56

LVDS_TXACLKLVDS_TXACLK+ LVDS_TXAOUT2LVDS_TXAOUT2+

LVDS_TXAOUT0LVDS_TXAOUT0+ LVDS_TXAOUT1LVDS_TXAOUT1+

LVDS_TXBCLKLVDS_TXBCLK+ LVDS_TXBOUT2LVDS_TXBOUT2+

LVDS_TXBOUT0LVDS_TXBOUT0+ LVDS_TXBOUT1LVDS_TXBOUT1+

2

1 2 3 4 5

SRN0J-7-GP

DIS

1 2 3 4 5

SRN0J-7-GP

DIS

1 2 3 4 5

SRN0J-7-GP

DIS

1 2 3 4 5

SRN0J-7-GP

DIS

RN23

RN22

RN25

RN24

LCD_TXACLK-

8

LCD_TXACLK+

7

LCD_TXAOUT2-

6

LCD_TXAOUT2+

LCD_TXAOUT0-

8

LCD_TXAOUT0+

7

LCD_TXAOUT1-

6

LCD_TXAOUT1+

LCD_TXBCLK-

8

LCD_TXBCLK+

7

LCD_TXBOUT2-

6

LCD_TXBOUT2+

LCD_TXBOUT0-

8

LCD_TXBOUT0+

7

LCD_TXBOUT1-

6

LCD_TXBOUT1+

1

Inverter Pin

Symbol

1

Vin

2

Vin Brightness

3 4

BLON GND

5 6

GND

CCD Pin Pin

Symbol CCD_PWR

1

USB-

RN17

8 7 6

RN16

8 7

LCD_TXAOUT0+

6

RN19

8 7 6

RN18

8 7 6

12

SRN4K7J-8-GP

DIS

RN14

1 2 3

SRN0J-10-GP-U

RN13

2 3 1

UMA

for TR

LCD_TXAOUT2+ LCD_TXAOUT2LCD_TXACLK+ LCD_TXACLK-

LCD_TXAOUT1+ LCD_TXAOUT1-

LCD_TXAOUT0-

LCD_TXBOUT2+ LCD_TXBOUT2LCD_TXBCLK+ LCD_TXBCLK-

LCD_TXBOUT1+ LCD_TXBOUT1LCD_TXBOUT0+ LCD_TXBOUT0-

BRIGHTNESS_AMD 9,56

BRIGHTNESS 36 BLON_OUT 36

R3

R3 10KR2J-3-GP

10KR2J-3-GP

3D3V_M92

4

RN111

DY

1

4

SRN0J-10-GP-U

JV50-TR8

Title

Size Document Number Rev

A3

Date: Sheet of

3D3V_S0

4

RN2

RN2 SRN4K7J-8-GP

SRN4K7J-8-GP

2 3

1

2 3

12

C856

SC220P50V2KX-3GP

LCD CONN

JV50-TR8

LCD_EDID_CLK_1 LCD_EDID_DAT_1

12

C701

SC220P50V2KX-3GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

3D3V_S0

PESD5V0S1BB-GP-U

-1

GMCH_TXAOUT2+9 GMCH_TXAOUT2-9 GMCH_TXACLK+9 GMCH_TXACLK-9

GMCH_TXAOUT1+9 GMCH_TXAOUT1-9 GMCH_TXAOUT0+9 GMCH_TXAOUT0-9

GMCH_TXBOUT2+9 GMCH_TXBOUT2-9 GMCH_TXBCLK+9 GMCH_TXBCLK-9

GMCH_TXBOUT1+9 GMCH_TXBOUT1-9 GMCH_TXBOUT0+9 GMCH_TXBOUT0-9

BRIGHTNESS_CN BLON_OUT_1

D35

DY

1 2

GMCH_TXAOUT2+ GMCH_TXAOUT2GMCH_TXACLK+ GMCH_TXACLK-

GMCH_TXAOUT1+ GMCH_TXAOUT1GMCH_TXAOUT0+ GMCH_TXAOUT0-

GMCH_TXBOUT2+ GMCH_TXBOUT2GMCH_TXBCLK+ GMCH_TXBCLK-

GMCH_TXBOUT1+ GMCH_TXBOUT1GMCH_TXBOUT0+ GMCH_TXBOUT0-

12

C4

SC100P50V2JN-3GP

DY

UMA

1 2

R508 33R2J-2-GPR508 33R2J-2-GP

1 2

R588 33R2J-2-GP

1 2

R589 33R2J-2-GPR589 33R2J-2-GP

12

C3

SC100P50V2JN-3GP

DY

1 2 3 4 5

SRN0J-7-GP

1 2 3 4 5

SRN0J-7-GP

1 2 3 4 5

SRN0J-7-GP

1 2 3 4 5

SRN0J-7-GP

DY

Close to connector LCD1

LCD_EDID_CLK56

12

C7

SC4D7U6D3V5KX-3GPC7SC4D7U6D3V5KX-3GP

-1

3

LCD_EDID_DAT56

CLK_DDC_EDID9 DAT_DDC_EDID9

2

USB+

3 42GND 5

GND

19 63Monday, October 26, 2009

1

-1

5

UMA

RN21

SRN0J-7-GP

for TR

DIS

RN114

SRN0J-7-GP

1 2 3 45

CRT_R_1

CRT_G_1

CRT_B_1

1 2 3 45

R489

150R2F-1-GP

Change

12

150R2F-1-GP

12

R488

12

R490

150R2F-1-GP

8

GMCH_BLUE9

GMCH_GREEN9

GMCH_RED9

D D

CRT_RED56

CRT_GREEN56

CRT_BLUE56

7 6

8 7 6

for TR

R489 PU & TR-DIS-->150R TR-UMA & TR-MUX-->140R

Layout Note:

C C

Place these resistors close to the CRT-out connector

Layout Note: * Must be a ground return path between this ground and the ground on the VGA connector. Pi-filter & 150 Ohm pull-down resistors should be as close as to CRT CONN. RGB will hit 75 Ohm first, pi-filter, then CRT CONN.

CRT I/F & CONNECTOR

B B

5V_CRT_S0

C722

SCD01U16V2KX-3GP

CRT_VSYNC1

12

A A

C150

SC15P50V2JN-2-GP

CRT_HSYNC1

12

C161

SC15P50V2JN-2-GP

CLK_DDC1_5

12

C142

DY

SC100P50V2JN-3GP

DAT_DDC1_5

12

C148

C148 SC100P50V2JN-3GP

SC100P50V2JN-3GP

DY

CRT_DEC#36

-1

UMA-->C150, C161 DY for flicker

5

CRT_R CRT_G CRT_B

CRT_IN#_R

4

2ND = 68.00119.081

12

EC32

DY

R64

12

470R2J-2-GP

C129

SC100P50V2JN-3GP

4

Ferrite bead impedance: 10 ohm@100MHz

68.00230.021

12

EC30

SC3P50V2CN-1-GP

DY

CRT1

6 1

7 2 8 3 9 4

10

5

D-SUB-15-37-GP

20.20378.015

2ND = 20.20813.015

CRT_IN#_R

12

DY

L18

1 2

FCB1608CF-GP

FCB1608CF-GP L16

L16

1 2

FCB1608CF-GP

FCB1608CF-GP L15

L15

1 2

12

EC27

FCB1608CF-GP

SC3P50V2CN-1-GP

DY

17

11 12 13 14 15

16

1 2

MLVG04023R0QV05-GP

CRT_R

1 2

CRT_G

1 2

CRT_B

1 2

DAT_DDC1_5 CRT_HSYNC1 CRT_VSYNC1 CLK_DDC1_5

SB

EC24

EC31

MLVG04023R0QV05-GP

EC29

MLVG04023R0QV05-GP

EC28

MLVG04023R0QV05-GP

DY

12

DY

C215

SC15P50V2JN-2-GP

3

CRT_R

CRT_G

SRN2K2J-1-GP

C203

SC15P50V2JN-2-GP

12

CRT_B

C176

SC15P50V2JN-2-GP

CRT_HSYNC56,59 CRT_VSYNC56,59

GMCH_VSYNC9 GMCH_HSYNC9

12

DIS

UMA

SRN0J-10-GP-U

RN34

2 3 1

SRN0J-10-GP-U

RN31

1 2 3

SRN2K2J-1-GP

4

2

3D3V_S0

4

RN37

1

4

Hsync & Vsync level shift

5V_S0

DY

14

2 3

HSYNC_1

VSYNC_1

14

4

5 6

7

73.74125.L13

2ND = 73.74125.L12

1

2 3

TSAHCT125PW-GP

U46B

TSAHCT125PW-GP

73.74125.L13

7

2ND = 73.74125.L12

CRT_VSYNC1_1

12

C700

C700 SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

U46A

CRT_HSYNC1_1

1

For System CRT

RN36

RN36 SRN22-3-GP

SRN22-3-GP

1 2 3

CRT

UMA-->33R for flicker

4

CRT_HSYNC1 CRT_VSYNC1

SB

for TR

DDC_CLK & DATA level shift

5V_CRT_S0

12

F3

FUSE-1D1A6V-4GP-U

69.50007.691

2ND = 69.50007.771

3D3V_M92

RN112

SRN2K2J-1-GP

DY

DIS

RN33

UMA

2 3 1

SRN0J-10-GP-U

RN20

2 3 1

SRN0J-10-GP-U

4

CRT_DDCDATA56 CRT_DDCCLK56

GMCH_DDCCLK9 GMCH_DDCDATA9

4

1

2 3

CLK_DDC1_5_Q

3D3V_S0

4

1

2 3

RN26

RN26 SRN2K2J-1-GP

SRN2K2J-1-GP

DAT_DDC1_5_Q

for TR

3

2

2ND = 69.50007.771

U69

5 6

2N7002KDW-GP

84.2N702.A3F

2ND = 84.DM601.03F

2009/04/28 For 2KV ESD protect

JV50-TR8

Title

ize Document Number Rev

Size Document Number Rev

S

Date: Sheet of

F3

5V_CRT_DDC

DAT_DDC1

34 2 1

CRT Connector

JV50-TR8

5V_S0

1

2

3

83.00016.F11

2ND = 83.00016.B11

3D3V_S0

D25

D25 BAS16PT-GP

BAS16PT-GP

500mA

678

RN35

SRN10KJ-6-GP

123

4 5

CRT_IN#_R

DAT_DDC1_5

R49

1 2

0R0402-PAD

-1

CLK_DDC1_5CLK_DDC1

R50

1 2

0R0402-PAD

-1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

20 63Monday, October 26, 2009

1

-1