Wistron DQDN15 AMD QUEEN M12 Schematic

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	DQDN15 AMD QUEEN M12
D	Muxless /UMA Schematics Document

	AMD LIANO APU FS1
	AMD GPU Seymour XT
C	FCH HUDSON M3
	PCB 10246-1
	2011-05-28
	REV : A00
B
	DY :None Installed
	UMA_PX:UMA and Muxless platform installed
	DIS_PX:DIS and Muxless platform installed
	PX:Muxless platform installed
	FCH_UMA_PX:UMA_PX CRT FCH output
	Whistler: For 8 X Vram
	DN15: For DN15
		DQ15 AMD DIS SAMSUNG TI
A
				Wistron Corporation
				21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
				Taipei Hsien 221, Taiwan, R.O.C.
		Title		Cover Page
		Size		Document Number		Rev
		Custom		DQDN15 AMD QUEEN M12		X00
		Date:	Friday, May 27, 2011		Sheet 1 of	104

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Project code

: 91.4IE01.001

CHARGER

BQ24745

40

Part Number

: 48.4IE04.0SA DQDN15 QUEEN AMD M12 UMA/Muxless DIS 15'

INPUTS

OUTPUTS

VRAM

AD+

28,29

PCB P/N

: 10246-SB

BT+

DCBATOUT

64Mx16bx4 (512MB)

SYSTEM DC/DC

D

Revision

: SB

90, 91

DDRIII

DIMM1

TPS51123

41

DDRIII 1333

AMD

INPUTS

OUTPUTS30

800/1066/1333

AMD Graphic

14

Liano APU

Muxless (Share PCIe x 8)

3D3V_AUX_S5

DDRIII

DIMM2

PCIeX16

Seymour-XT

DCBATOUT

5V_AUX_S5

DDRIII 1333

(FS1 socket)

83, 84, 85, 86, 87

5V_S5

800/1066/1333

UMA HDMI(Share PCIe x 4)

15

722-Pin uFCPGA722

3D3V_S5

27

DP0

HDMI 51

APU Core/NB Power

TRAVIS

LAN Controller

Reserve for HDMI v1.4

ISL6267HRTZ-T

42, 43

RJ45

PCIe

ANX3110

31

Realtek RTL8105E

PCIeX1

INPUTS

OUTPUTS

CONN

4, 5, 6, 7, 8

DP1

LCD

USB3.0 x2

Connector

USB3.0 X 2

9

49

INPUTS

OUTPUTS

DCBATOUT

APU_VDD

PCIe & USB2.0

UMI Link 4X4

APU_VDDNB

WLAN

For FCH CRT Input

DDRIII SUS

USB3.0 & 2.0 x2

Reserve GPU CRT for VRAM verification

TPS51116RGER

44

C

I/OBoard

FCH

DCBATOUT

1D5V_S3

USB3.0

USB 3.0 (4parts)

Integrated Display DAC

BoardCRT Connector

CRT

DDRIII VTT

Azalia

USB2.0

Redriver x2

USB2.0 X 3

HUDSON-M3

TPS51116RGER

44

MIC IN

USB2.0 X1

INPUTS

OUTPUTS

Integrated Display DAC

DCBATOUT

0D75V_S0

HP1

APU VDDR/VDDP

CODEC & OP AMP

AZALIA

USB 2.0 (10 parts)

RT8209

46

82

IDT 92HD87

USB 1.1 (2 parts)

INPUTS

OUTPUTS

82

29

SATA (6 parts)

DCBATOUT

1D2V_S0

INT RTC

CardReader

AMD FCH CORE Power

SD/SDIO/MMC

INT CLK GEN

USB2.0 X4

Realtek

RT8209

46

2CH SPEAKER

MS/MS Pro/xD

HW MONITOR

RTS5138

32

INPUTS

OUTPUTS33

58

ACPI 1.1

LPC Bus

DCBATOUT

1D1V_S5

75

DN15 Vostro

PCIe & USB2.0

Camera Conn

AMD GPU CORE

Express Card

RT8208B

92

(LVDS & Camera Conn.)

26

B

DN15 Vostro

64

49

INPUTS

OUTPUTS

USB2.0 X 1

17, 18, 19, 20, 21, 22

DCBATOUT VGA_CORE_PWR

Fingerprinter

PCB LAYER

Bluetooth

L1: Top

USB3.0/2.0

SATA

SATA

SATA

63

L2: VCC

Touch Panel

L5: GND

L3: Signal

L4: Signal

63

L6: Bottom

eSATA

USB3.0

HDD

ODD

KBC

Cbmbo

SPI

NUVOTON

57

56

56

NPCE795P

27

A

Flash ROM

Touch

Int.

Thermal

FAN

PAD

KB

ENE P2800

G991P11U

DQ15 AMD DIS SAMSUNG TI

2MB

60

69

69

28

28

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

25

28

Title

Block Diagram

25

Size

Document Number

Rev

Custom

QUEEN AMD Muxless/UMA

X00

Date:

Thursday, May 26, 2011

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Strapping

No Fusion Config, Strap Not needed, but reserve

REQUIRED SYSTEM STRAPS

EC_PWM2

PCI_CLK1

RTC_CLK

CLK_PCI_LPC

PCI_CLK4

LPC_CLK0

LPC_CLK1

PCH GPO199

PULL

Allow

S5_PLUS Mode

USE

non_Fusion

ENABLE EC

CLKGEN

LPC ROM

ENABLED

HIGH

PCIE GEN2

DISABLE

DEBUG STRAPS

CLOCK mode

(Use Internal)

DEFAULT

DEFAULT

DEFAULT

PULL

SPI ROM

Force

S5_PLUS Mode

IGNORE

Fusion

DISABLE EC

CLKGEN

C

LOW

PCIE GEN1

ENABLE

DEBUG STRAPS

CLOCK mode

DISABLED

C

DEFAULT

DEFAULT

DEFAULT

DEFAULT

(Use External)

USB Table

PCIe Routing

USB

APU

Pair

Device

0

USB Debug Port / CRT USB 2.0

LANE0

LAN

1

Mini Card (WLAN)

LANE1

WWAN

2

Fingerprint

LANE2

3

WWAN

WLAN

B

4

Bluetooth

LANE3

CardReader

B

5

Touch Panel

6

eSATA/USB Charger

7

CCD Camera

FCH

8

New Card

LANE0

9

CardReader

LANE1

Express Card

10

USB 3.0 port 1

11

USB 3.0 port 2

LANE2

12

USB 3.0 port 3

13

USB 3.0 port 4

LANE3

A

DQ15 AMD DIS SAMSUNG TI

A

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title

Table of Content

Size

Document Number

Rev

A3

QUEEN AMD Muxless/UMA

X00

Date:

Thursday, May 26, 2011

Sheet 3

of

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LAN		82	PCIE_RXP0
		82	PCIE_RXN0
WWAN		82	PCIE_RXP2
WLAN
		82	PCIE_RXN2

17 UMI_FCH_APU_RX0P

17 UMI_FCH_APU_RX0N

17 UMI_FCH_APU_RX1P

17 UMI_FCH_APU_RX1N

17 UMI_FCH_APU_RX2P

17 UMI_FCH_APU_RX2N

17 UMI_FCH_APU_RX3P

17UMI_FCH_APU_RX3N 1D2V_S0 1 R402

			APU1F			6 OF 6
		AA8		PCI EXPRESS
			P_GFX_RXP0			P_GFX_TXP0
		AA9			SAINE
			P_GFX_RXN0			P_GFX_TXN0
		W8
		Y7	P_GFX_RXP1			P_GFX_TXP1
		Y8
			P_GFX_RXN1			P_GFX_TXN1
		W5
			P_GFX_RXP2			P_GFX_TXP2
		W6
			P_GFX_RXN2			P_GFX_TXN2
			P_GFX_RXP3			P_GFX_TXP3
		W9
			P_GFX_RXN3			P_GFX_TXN3
		V7
			P_GFX_RXP4			P_GFX_TXP4
		V8
		U5	P_GFX_RXN4			P_GFX_TXN4
			P_GFX_RXP5			P_GFX_TXP5
		U6
			P_GFX_RXN5			P_GFX_TXN5
		U8
		U9	P_GFX_RXP6		GRAPHICS	P_GFX_TXP6
			P_GFX_RXN6			P_GFX_TXN6
	PEG_RXP8	R5
		T7	P_GFX_RXP7			P_GFX_TXP7
		T8
			P_GFX_RXN7			P_GFX_TXN7
	PEG_RXN8	R6	P_GFX_RXP8			P_GFX_TXP8
			P_GFX_RXN8			P_GFX_TXN8
	PEG_RXP9	R8
			P_GFX_RXP9			P_GFX_TXP9
	PEG_RXN9	R9
	PEG_RXP10	P7	P_GFX_RXN9			P_GFX_TXN9
			P_GFX_RXP10			P_GFX_TXP10
	PEG_RXN10	P8
			P_GFX_RXN10			P_GFX_TXN10
	PEG_RXP11	N5
	PEG_RXN11	N6	P_GFX_RXP11			P_GFX_TXP11
			P_GFX_RXN11			P_GFX_TXN11
	PEG_RXP12	N8
			P_GFX_RXP12			P_GFX_TXP12
	PEG_RXN12	N9
			P_GFX_RXN12			P_GFX_TXN12
	PEG_RXP13	M7
	PEG_RXN13	M8	P_GFX_RXP13			P_GFX_TXP13
			P_GFX_RXN13			P_GFX_TXN13
	PEG_RXP14	L5
			P_GFX_RXP14			P_GFX_TXP14
	PEG_RXN14	L6
	PEG_RXP15	L8	P_GFX_RXN14			P_GFX_TXN14
			P_GFX_RXP15			P_GFX_TXP15
	PEG_RXN15	L9
			P_GFX_RXN15			P_GFX_TXN15
		AC5
			P_GPP_RXP0			P_GPP_TXP0
		AC6
			P_GPP_RXN0			P_GPP_TXN0
		AC8
			P_GPP_RXP1			P_GPP_TXP1
		AC9
		AB7	P_GPP_RXN1		GPP	P_GPP_TXN1
			P_GPP_RXP2			P_GPP_TXP2
		AB8
		AA5	P_GPP_RXN2			P_GPP_TXN2
		AA6	P_GPP_RXP3			P_GPP_TXP3
			P_GPP_RXN3			P_GPP_TXN3
		AF8
			P_UMI_RXP0			P_UMI_TXP0
		AF7
		AE6	P_UMI_RXN0			P_UMI_TXN0
			P_UMI_RXP1			P_UMI_TXP1
		AE5
			P_UMI_RXN1			P_UMI_TXN1
		AE9
		AE8	P_UMI_RXP2		LINK-	P_UMI_TXP2
			P_UMI_RXN2			P_UMI_TXN2
		AD8	P_UMI_RXP3		UMI	P_UMI_TXP3
		AD7
2196R2F-GP P_ZVDDP		K5	P_UMI_RXN3			P_UMI_TXN3
			P_ZVDDP			P_ZVSS

SAINE

AA2
AA3
Y2
Y1
Y4
Y5
W2
W3
V2
V1
V4
V5
U2
U3
T2
T1
T4	GTXP8		DIS_PX	C417	1		2	SCD1U16V2KX-3GP	PEG_TXP8
T5	GTXN8		DIS_PX	C418	1		2	SCD1U16V2KX-3GP	PEG_TXN8
R2	GTXP9		DIS_PX	C419	1		2	SCD1U16V2KX-3GP	PEG_TXP9
R3	GTXN9		DIS_PX	C420	1		2	SCD1U16V2KX-3GP	PEG_TXN9
P2	GTXP10		DIS_PX	C421	1		2	SCD1U16V2KX-3GP	PEG_TXP10
P1	GTXN10		DIS_PX	C422	1		2	SCD1U16V2KX-3GP	PEG_TXN10
P4	GTXP11		DIS_PX	C423	1		2	SCD1U16V2KX-3GP	PEG_TXP11
P5	GTXN11		DIS_PX	C424	1		2	SCD1U16V2KX-3GP	PEG_TXN11
N2	GTXP12		DIS_PX	C425	1		2	SCD1U16V2KX-3GP	PEG_TXP12
N3	GTXN12		DIS_PX	C426	1		2	SCD1U16V2KX-3GP	PEG_TXN12
M2	GTXP13		DIS_PX	C427	1		2	SCD1U16V2KX-3GP	PEG_TXP13
M1	GTXN13		DIS_PX	C428	1		2	SCD1U16V2KX-3GP	PEG_TXN13
M4	GTXP14		DIS_PX	C429	1		2	SCD1U16V2KX-3GP	PEG_TXP14
M5	GTXN14		DIS_PX	C430	1		2	SCD1U16V2KX-3GP	PEG_TXN14
L2	GTXP15		DIS_PX	C431	1		2	SCD1U16V2KX-3GP	PEG_TXP15
L3	GTXN15		DIS_PX	C432	1		2	SCD1U16V2KX-3GP	PEG_TXN15
AD4	PCIE_TXP0_C			C441	1			SCD1U16V2KX-3GP
							2
AD5	PCIE_TXN0_C			C442	1		2	SCD1U16V2KX-3GP
AC2
AC3	PCIE_TXP2_C
AB2				C457	1		2	SCD1U16V2KX-3GP
AB1	PCIE_TXN2_C			C460	1		2	SCD1U16V2KX-3GP
AB4
AB5
AF1	UMI_TX0P_C			C445	1			SCD1U16V2KX-3GP
							2
AF2	UMI_TX0N_C			C446	1		2	SCD1U16V2KX-3GP
AF5	UMI_TX1P_C			C447	1		2	SCD1U16V2KX-3GP
AF4	UMI_TX1N_C			C448	1		2	SCD1U16V2KX-3GP
AE3	UMI_TX2P_C			C449	1		2	SCD1U16V2KX-3GP
AE2	UMI_TX2N_C			C450	1		2	SCD1U16V2KX-3GP
AD1	UMI_TX3P_C			C451	1		2	SCD1U16V2KX-3GP
AD2	UMI_TX3N_C			C452	1		2	SCD1U16V2KX-3GP
K4	P_ZVSS
		1	R401
			196R2F-GP

APU_HDMI_DATA2 51

APU_HDMI_DATA2# 51

APU_HDMI_DATA1 51

APU_HDMI_DATA1# 51

APU_HDMI_DATA0 51

APU_HDMI_DATA0# 51

APU_HDMI_CLK 51

APU_HDMI_CLK# 51

PEG_TXP[8..15]

PEG_TXP[8..15] 83

PEG_TXN[8..15]

PEG_TXN[8..15] 83

		PEG_RXP[8..15]
						PEG_RXP[8..15] 83
		PEG_RXN[8..15]
PCIE_TXP0	82					PEG_RXN[8..15] 83
					LAN
PCIE_TXN0	82
PCIE_TXP2	82				WWAN
					WLAN
PCIE_TXN2	82

UMI_APU_FCH_TX0P 17

UMI_APU_FCH_TX0N 17

UMI_APU_FCH_TX1P 17

UMI_APU_FCH_TX1N 17

UMI_APU_FCH_TX2P 17

UMI_APU_FCH_TX2N 17

UMI_APU_FCH_TX3P 17

UMI_APU_FCH_TX3N 17

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DQ15 AMD DIS SAMSUNG TI

A

		Wistron Corporation
		21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
		Taipei Hsien 221, Taiwan, R.O.C.
Title
		APU_PCIE(1/5)
Size	Document Number				Rev
A3		QUEEN AMD Muxless/UMA			X00
Date:	Thursday, May 26, 2011		Sheet 4	of	104

5

4

3

2

1

5

4

3

2

1

APU1A

1 OF 6

MEMORY CHANNEL

APU1B

2 OF 6

14 M_A_A0

U20

A

E13

M_A_DQ0

14

MEMORY CHANNEL B

MA_ADD0

MA_DATA0

R20

J13

T27

A14

14 M_A_A1

MA_ADD1

MA_DATA1

M_A_DQ1

14

15 M_B_A0

MB_ADD0

MB_DATA0

M_B_DQ0

15

R21

H15

P24

B14

14 M_A_A2

MA_ADD2

MA_DATA2

M_A_DQ2

14

15 M_B_A1

MB_ADD1

SAINE

MB_DATA1

M_B_DQ1

15

D

P22

SAINE

J15

P25

D16

D

14 M_A_A3

MA_ADD3

MA_DATA3

M_A_DQ3

14

15 M_B_A2

MB_ADD2

MB_DATA2

M_B_DQ2

15

P21

H13

N27

E16

14 M_A_A4

MA_ADD4

MA_DATA4

M_A_DQ4

14

15 M_B_A3

MB_ADD3

MB_DATA3

M_B_DQ3

15

N24

F13

N26

B13

14 M_A_A5

MA_ADD5

MA_DATA5

M_A_DQ5

14

15 M_B_A4

MB_ADD4

MB_DATA4

M_B_DQ4

15

N23

F15

M28

C13

14 M_A_A6

MA_ADD6

MA_DATA6

M_A_DQ6

14

15 M_B_A5

MB_ADD5

MB_DATA5

M_B_DQ5

15

N20

E15

M27

B16

14 M_A_A7

MA_ADD7

MA_DATA7

M_A_DQ7

14

15 M_B_A6

MB_ADD6

MB_DATA6

M_B_DQ6

15

N21

M24

A16

14 M_A_A8

MA_ADD8

15 M_B_A7

MB_ADD7

MB_DATA7

M_B_DQ7

15

M21

H17

M25

14 M_A_A9

MA_ADD9

MA_DATA8

M_A_DQ8

14

15 M_B_A8

MB_ADD8

U23

F17

L26

C17

14 M_A_A10

MA_ADD10

MA_DATA9

M_A_DQ9

14

15 M_B_A9

MB_ADD9

MB_DATA8

M_B_DQ8

15

M22

E19

U26

B18

14 M_A_A11

MA_ADD11

MA_DATA10

M_A_DQ10

14

15 M_B_A10

MB_ADD10

MB_DATA9

M_B_DQ9

15

L24

J19

L27

B20

14 M_A_A12

MA_ADD12

MA_DATA11

M_A_DQ11

14

15 M_B_A11

MB_ADD11

MB_DATA10

M_B_DQ10

15

AA25

G16

K27

A20

14 M_A_A13

MA_ADD13

MA_DATA12

M_A_DQ12

14

15 M_B_A12

MB_ADD12

MB_DATA11

M_B_DQ11

15

L21

H16

W26

E17

14 M_A_A14

MA_ADD14

MA_DATA13

M_A_DQ13

14

15 M_B_A13

MB_ADD13

MB_DATA12

M_B_DQ12

15

L20

H19

K25

B17

14

M_A_A15

MA_ADD15

MA_DATA14

M_A_DQ14

14

15 M_B_A14

MB_ADD14

MB_DATA13

M_B_DQ13

15

F19

K24

B19

MA_DATA15

M_A_DQ15

14

15 M_B_A15

MB_ADD15

MB_DATA14

M_B_DQ14

15

U24

C19

14 M_A_BS0

MA_BANK0

MB_DATA15

M_B_DQ15

15

U21

H20

U27

14 M_A_BS1

MA_BANK1

MA_DATA16

M_A_DQ16

14

15 M_B_BS0

MB_BANK0

L23

F21

T28

C21

14

M_A_BS2

MA_BANK2

MA_DATA17

M_A_DQ17

14

15 M_B_BS1

MB_BANK1

MB_DATA16

M_B_DQ16

15

J23

K28

B22

MA_DATA18

M_A_DQ18

14

15 M_B_BS2

MB_BANK2

MB_DATA17

M_B_DQ17

15

E14

H23

C23

14

M_A_DM0

MA_DM0

MA_DATA19

M_A_DQ19 14

MB_DATA18

M_B_DQ18

15

J17

G20

D14

A24

14

M_A_DM1

MA_DM1

MA_DATA20

M_A_DQ20

14

15 M_B_DM0

MB_DM0

MB_DATA19

M_B_DQ19

15

E21

E20

A18

D20

14

M_A_DM2

MA_DM2

MA_DATA21

M_A_DQ21

14

15 M_B_DM1

MB_DM1

MB_DATA20

M_B_DQ20

15

F25

G22

A22

B21

14

M_A_DM3

MA_DM3

MA_DATA22

M_A_DQ22

14

15 M_B_DM2

MB_DM2

MB_DATA21

M_B_DQ21

15

AD27

H22

C25

E23

14

M_A_DM4

MA_DM4

MA_DATA23

M_A_DQ23

14

15 M_B_DM3

MB_DM3

MB_DATA22

M_B_DQ22

15

AC23

AF25

B23

14

M_A_DM5

MA_DM5

15 M_B_DM4

MB_DM4

MB_DATA23

M_B_DQ23

15

AD19

G24

AG22

14

M_A_DM6

MA_DM6

MA_DATA24

M_A_DQ24

14

15 M_B_DM5

MB_DM5

AC15

E25

AH18

E24

14

M_A_DM7

MA_DM7

MA_DATA25

M_A_DQ25

14

15 M_B_DM6

MB_DM6

MB_DATA24

M_B_DQ24

15

G27

AD14

B25

MA_DATA26

M_A_DQ26

14

15 M_B_DM7

MB_DM7

MB_DATA25

M_B_DQ25

15

G14

G26

B27

14

M_A_DQS0

MA_DQS_H0

MA_DATA27

M_A_DQ27 14

MB_DATA26

M_B_DQ26

15

H14

F23

C15

D28

C

14

M_A_DQS#0

MA_DQS_L0

MA_DATA28

M_A_DQ28

14

15 M_B_DQS0

MB_DQS_H0

MB_DATA27

M_B_DQ27

15

C

G18

H24

B15

B24

14

M_A_DQS1

MA_DQS_H1

MA_DATA29

M_A_DQ29

14

15 M_B_DQS#0

MB_DQS_L0

MB_DATA28

M_B_DQ28

15

H18

E28

E18

D24

14

M_A_DQS#1

MA_DQS_L1

MA_DATA30

M_A_DQ30

14

15 M_B_DQS1

MB_DQS_H1

MB_DATA29

M_B_DQ29

15

J21

F27

D18

D26

14

M_A_DQS2

MA_DQS_H2

MA_DATA31

M_A_DQ31

14

15 M_B_DQS#1

MB_DQS_L1

MB_DATA30

M_B_DQ30

15

H21

E22

C27

14

M_A_DQS#2

MA_DQS_L2

15 M_B_DQS2

MB_DQS_H2

MB_DATA31

M_B_DQ31

15

E27

AB28

D22

14

M_A_DQS3

MA_DQS_H3

MA_DATA32

M_A_DQ32

14

15 M_B_DQS#2

MB_DQS_L2

E26

AC27

B26

AG26

14

M_A_DQS#3

MA_DQS_L3

MA_DATA33

M_A_DQ33

14

15 M_B_DQS3

MB_DQS_H3

MB_DATA32

M_B_DQ32

15

AE26

AD25

A26

AH26

14

M_A_DQS4

MA_DQS_H4

MA_DATA34

M_A_DQ34

14

15 M_B_DQS#3

MB_DQS_L3

MB_DATA33

M_B_DQ33

15

AD26

AA24

AG24

AF23

14

M_A_DQS#4

MA_DQS_L4

MA_DATA35

M_A_DQ35

14

15 M_B_DQS4

MB_DQS_H4

MB_DATA34

M_B_DQ34

15

AB22

AE28

AG25

AG23

14

M_A_DQS5

MA_DQS_H5

MA_DATA36

M_A_DQ36

14

15 M_B_DQS#4

MB_DQS_L4

MB_DATA35

M_B_DQ35

15

AA22

AD28

AG21

AG27

14

M_A_DQS#5

MA_DQS_L5

MA_DATA37

M_A_DQ37

14

15 M_B_DQS5

MB_DQS_H5

MB_DATA36

M_B_DQ36

15

AB18

AB26

AF21

AF27

14

M_A_DQS6

MA_DQS_H6

MA_DATA38

M_A_DQ38

14

15 M_B_DQS#5

MB_DQS_L5

MB_DATA37

M_B_DQ37

15

AA18

AC25

AG17

AH24

14

M_A_DQS#6

MA_DQS_L6

MA_DATA39

M_A_DQ39

14

15 M_B_DQS6

MB_DQS_H6

MB_DATA38

M_B_DQ38

15

AA14

AG18

AE24

14

M_A_DQS7

MA_DQS_H7

15 M_B_DQS#6

MB_DQS_L6

MB_DATA39

M_B_DQ39

15

AA15

Y23

AH14

14

M_A_DQS#7

MA_DQS_L7

MA_DATA40

M_A_DQ40

14

15 M_B_DQS7

MB_DQS_H7

AA23

AG14

AE22

MA_DATA41

M_A_DQ41

14

15 M_B_DQS#7

MB_DQS_L7

MB_DATA40

M_B_DQ40

15

T21

Y21

AH22

14

M_A_DIM0_CLK_DDR0

MA_CLK_H0

MA_DATA42

M_A_DQ42 14

MB_DATA41

M_B_DQ41

15

T22

AA20

R26

AE20

14

M_A_DIM0_CLK_DDR#0

MA_CLK_L0

MA_DATA43

M_A_DQ43

14

15 M_B_DIM0_CLK_DDR0

MB_CLK_H0

MB_DATA42

M_B_DQ42

15

R23

AB24

R27

AH20

14

M_A_DIM0_CLK_DDR1

MA_CLK_H1

MA_DATA44

M_A_DQ44

14

15 M_B_DIM0_CLK_DDR#0

MB_CLK_L0

MB_DATA43

M_B_DQ43

15

R24

AD24

P27

AD23

14

M_A_DIM0_CLK_DDR#1

MA_CLK_L1

MA_DATA45

M_A_DQ45

14

15 M_B_DIM0_CLK_DDR1

MB_CLK_H1

MB_DATA44

M_B_DQ44

15

AA21

P28

AD22

MA_DATA46

M_A_DQ46

14

15 M_B_DIM0_CLK_DDR#1

MB_CLK_L1

MB_DATA45

M_B_DQ45

15

14

M_A_DIM0_CKE0

H28

AC21

AD21

MA_CKE0

MA_DATA47

M_A_DQ47 14

MB_DATA46

M_B_DQ46

15

H27

J26

AD20

14

M_A_DIM0_CKE1

MA_CKE1

15 M_B_DIM0_CKE0

MB_CKE0

MB_DATA47

M_B_DQ47

15

AA19

J27

MA_DATA48

M_A_DQ48

14

15 M_B_DIM0_CKE1

MB_CKE1

Y25

AC19

AF19

14

M_A_DIM0_ODT0

MA_ODT0

MA_DATA49

M_A_DQ49 14

MB_DATA48

M_B_DQ48

15

AA27

AC17

W27

AE18

14

M_A_DIM0_ODT1

MA_ODT1

MA_DATA50

M_A_DQ50

14

15 M_B_DIM0_ODT0

MB_ODT0

MB_DATA49

M_B_DQ49

15

AA17

Y28

AE16

MA_DATA51

M_A_DQ51

14

15 M_B_DIM0_ODT1

MB_ODT1

MB_DATA50

M_B_DQ50

15

V22

AB20

AH16

14

M_A_DIM0_CS#0

MA_CS#0

MA_DATA52

M_A_DQ52 14

MB_DATA51

M_B_DQ51

15

AA26

Y19

V25

AG20

14

M_A_DIM0_CS#1

MA_CS#1

MA_DATA53

M_A_DQ53

14

15 M_B_DIM0_CS#0

MB_CS#0

MB_DATA52

M_B_DQ52

15

AD18

Y27

AG19

B

MA_DATA54

M_A_DQ54

14

15 M_B_DIM0_CS#1

MB_CS#1

MB_DATA53

M_B_DQ53

15

B

V21

AD17

AF17

14

M_A_RAS#

MA_RAS#

MA_DATA55

M_A_DQ55 14

MB_DATA54

M_B_DQ54

15

W24

V24

AD16

14

M_A_CAS#

MA_CAS#

15 M_B_RAS#

MB_RAS#

MB_DATA55

M_B_DQ55

15

W23

AA16

V27

14

M_A_W E#

MA_WE#

MA_DATA56

M_A_DQ56

14

15 M_B_CAS#

MB_CAS#

Y15

V28

AG15

MA_DATA57

M_A_DQ57

14

15 M_B_W E#

MB_WE#

MB_DATA56

M_B_DQ56

15

H25

AA13

AD15

14

M_A_RST#

M_A_EVENT#

MA_RESET#

MA_DATA58

M_A_DQ58 14

MB_DATA57

M_B_DQ57

15

T24

AC13

J25

AG13

MA_EVENT#

MA_DATA59

M_A_DQ59

14

15 M_B_RST#

MB_RESET#

MB_DATA58

M_B_DQ58

15

Y17

M_B_EVENT#

T25

AD13

M_VREF_DQ_APU

MA_DATA60

M_A_DQ60

14

MB_EVENT#

MB_DATA59

M_B_DQ59

15

W20

AB16

AG16

M_VREF

MA_DATA61

M_A_DQ61

14

MB_DATA60

M_B_DQ60

15

AB14

AF15

MA_DATA62

M_A_DQ62

14

MB_DATA61

M_B_DQ61

15

1D5V_S3

1 R501

2

M_ZVDDIO

W21

Y13

AE14

M_ZVDDIO

MA_DATA63

M_A_DQ63

14

MB_DATA62

M_B_DQ62

15

39R2F-GP

AF13

MB_DATA63

M_B_DQ63

15

SAINE

SAINE

APU_VREF_DQ

DDR_VREF_S3

1D5V_S3

1

R502 2

M_VREF_DQ_APU

Do Not Stuff 1

C501

1

C502

RN501

M_A_EVENT#

4

1

SCD1U10V2KX-5GP

SC1KP50V2KX-1GP

3

2

M_B_EVENT#

2

2

SRN1KJ-7-GP

DQ15 AMD DIS SAMSUNG TI

A

A

LAYOUT: place them close to APU

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

1207: Change To 4 Pin Array Resistor

Taipei Hsien 221, Taiwan, R.O.C.

AMD Confirm: PU Needed even if not used

Title

Size

Document Number

APU_DDR(2/5)

Rev

A3

QUEEN AMD Muxless/UMA

X00

Date:

Thursday, May 26, 2011

Sheet

5

of

104

5

4

3

2

1

D

C

B

A

5

4

3

2

1

RN610

SVC

SVD

Boot Voltage

Boot Voltage

DP_AUX0N

4

1

DP_AUX0P

3

2

(VCC/GND)

(open)

0112: Change To 2 Single 1.8K 0402 for

0

0

1.1

1.1

layout routing.

SRN1K8J-GP

0

1

1.0

1.2

DP_AUX1N

4

RN611

1

1

0

0.9

1.1

DP_AUX1P

3

2

1

1

0.8

0.9

APU1C

3 OF 6

1008: De-Pop R602, Follow Checklist

SRN1K8J-GP

ANALOG/DISPLAY/MISC

9 LVDS_L0P_TRAVIS

UMA_PX C602 1

2

SCD1U16V2KX-3GP

DP0_TX0P

F2

DP0_TXP0

DP0_AUXP

D4

DP_AUX0P UMA_PX

C603

1

2

SCD1U16V2KX-3GP

LVDS_CHP_TRAVIS 9

LVDS

Travis LVDS Panel

9 LVDS_L0N_TRAVIS

UMA_PX C606 1

2

SCD1U16V2KX-3GP

DP0_TX0N

F1

DP0_TXN0

SAINE

DP0_AUXN

D5

DP_AUX0N

UMA_PX

C601

1

2

SCD1U16V2KX-3GP

LVDS_CHN_TRAVIS

9

APU_TEST25_H_BYPASSCLK_H

1

R611

2

510R2J-1-GP

1

DP0_TX2P

D2

J5

9 LVDS_L1P_TRAVIS

UMA_PX C607 1

2

SCD1U16V2KX-3GP

DP0_TX1P

E3

DP0_TXP1

DP1_AUXP

E5

DP_AUX1P

SCD1U16V2KX-3GP

2

1 C626 FCH_UMA_PX

DP1_AUXP_R

19

VGA

M_TEST

1

R608

2

39R2F-GP

9 LVDS_L1N_TRAVIS

UMA_PX C604 1

2

SCD1U16V2KX-3GP

DP0_TX1N

E2

DP0_TXN1

DP1_AUXN

E6

DP_AUX1N

SCD1U16V2KX-3GP

2

1

C627

FCH_UMA_PX

DP1_AUXN_R

19

APU_TEST9_ANALOGIN

R602

Do Not Stuff

2

1DY

Do Not Stuff

TP602

1

DP0_TX2N

D1

DP0_TXP2

DP2_AUXP

J6

PCH_HDMI_CLK_R 51

HDMI

APU_TEST18_PLLTEST1

1

R605

2

1KR2J-1-GP

Do Not Stuff

TP603

DP0_TXN2

DP2_AUXN

PCH_HDMI_DATA_R

51

1

DP0_TX3P

C2

0

H4

Do Not Stuff

TP604

1

DP0_TX3N

C3

DP0_TXP3

PORT

DP3_AUXP

H5

Do Not Stuff

TP605

DP0_TXN3

DP3_AUXN

19 DP1_TX0P_R

FCH_UMA_PX C618 1

2

SCD1U16V2KX-3GP

DP1_TX0P

K2

DP1_TXP0

DISPLAY

MISC.

DP4_AUXP

G5

APU_TEST21_SCANEN

3

RN612

2

FCH_UMA_PX

C619

1

2

SCD1U16V2KX-3GP

DP1_TX0N

K1

G6

APU_TEST24_SCANCLK1

4

1

19 DP1_TX0N_R

DP1_TXN0

PORT

DP4_AUXN

19

DP1_TX1P_R

FCH_UMA_PX

C620

1

2

SCD1U16V2KX-3GP

DP1_TX1P

J3

DP1_TXP1

DP5_AUXP

F4

DP Input To FCH

19 DP1_TX1N_R

FCH_UMA_PX C621 1

2

SCD1U16V2KX-3GP

DP1_TX1N

J2

DP1_TXN1

DISPLAY

DP5_AUXN

F5

SRN1KJ-7-GP

19

DP1_TX2P_R

FCH_UMA_PX

C622

1

2

SCD1U16V2KX-3GP

DP1_TX2P

H2

DP1_TXP2

DP0_HPD

D7

DP0_HPD

19

DP1_TX2N_R

FCH_UMA_PX

C623

1

2

SCD1U16V2KX-3GP

DP1_TX2N

H1

DP1_TXN2

DP1_HPD

E7

DP1_HPD

RN609

1

DP2_HPD

J7

DP2_HPD

51

0109: EMI Reserve, Place Near R631

19 DP1_TX3N_R

FCH_UMA_PX

C625

1

2

SCD1U16V2KX-3GP

DP1_TX3N

G3

DP1_TXN3

PORT

G7

APU_TEST22_SCANSHIFTEN

7

2

DP4_HPD

19 DP1_TX3P_R

FCH_UMA_PX

C624

1

2

SCD1U16V2KX-3GP

DP1_TX3P

G2

DP1_TXP3

DISPLAY

DP3_HPD

H7

APU_TEST19_PLLTEST0

8

1

17

APU_CLKP

CLKIN_H

DP5_HPD

F7

APU_TEST20_SCANCLK2

6

3

AH7

APU_TEST12_SCANSHIFTEND

5

4

17

APU_CLKN

AH6

CLKIN_L

CLK

DP_BLON

C6

APU_RST_L_BUF

C5

FCH_UMA_PX

SRN1KJ-4-GP

AH4

DP_DIGON

2

Do Not Stuff

APU_BLPWM

3D3V_S0

17

DISP_CLKP

DISP_CLKIN_H

DP_VARY_BL

C7

APU_BLPWM_R

1 R621

2

17

DISP_CLKN

AH3

DISP_CLKIN_L

D8

DP_AUX_ZVSS 1 R623

2 150R2F-1-GP

DY

DP_AUX_ZVSS

R671

EC601

B8

LVDS_CHN_TRAVIS

1

2

42 APU_SVC_R

SVC

1D2V_S0

1

42

APU_SVD_R

RN606

Do Not Stuff

A8

SVD

TEST6

AA10

APU_TEST9_ANALOGIN

Do Not Stuff

DY

Stuff

1

APU_SIC

AH11

SER.

G10

R672

APU_TEST25_L_BYPASSCLK_L

1

R613

2

510R2J-1-GP

4

TEST9

H10

DY

Not

18

SCLK3

2

DY

3

APU_SID

AG11

SIC

TEST10

H12

APU_TEST12_SCANSHIFTEND

LVDS_CHP_TRAVIS

Do Not Stuff1

2

18

SDATA3

SID

TEST12

1D5V_S0

1

R631

2 Do Not Stuff

D9

APU_TEST14_BP0

TP611 Do Not Stuff

Do

71

APU_RST_L_BUF

DY

1

R629

2

Do Not Stuff

APU_RST#_R

AF10

TEST14

E9

APU_TEST15_BP1

17

APU_RST#

RESET#

TEST15

TP610 Do Not Stuff

H_CPUPWRGD

1

R630

2

Do Not Stuff

APU_PWRGD_R

AE10

G9

APU_TEST16_BP2

ALLOW_STOP

1

R614

2

Do Not Stuff

17,36,71

H_CPUPWRGD

PWROK

CTRL

TEST16

H9

APU_TEST17_BP3

TP612 Do Not Stuff

DY

1D5V_S3

TEST17

TP613 Do Not Stuff

17

APU_PROCHOT#_VDDIO

1

R632DY2 Do Not Stuff

APU_THERMTRIP#_VDDIO

AD10

PROCHOT#

TEST18

H11

APU_TEST18_PLLTEST1

APU_TEST18_PLLTEST1 71

1

R643

2

1KR2J-1-GP

27,40

H_PROCHOT#

AG12

THERMTRIP#

TEST19

G11

APU_TEST19_PLLTEST0

APU_TEST19_PLLTEST0 71

APU_ALERT#

AH12

F12

APU_TEST20_SCANCLK2

ALERT#

TEST20

E11

APU_TEST21_SCANEN

1D5V_S0

TEST21

0111: Dummy APU-> FCH Prochot function

71

APU_TDI

APU_TDI

C12

TDI

TEST

D11

APU_TEST22_SCANSHIFTEN

SRN300J-3-GP

APU_TDO

TEST22

3D3V_AUX_S5

71

APU_TDO

A12

TDO

TEST23

F10

4

1

APU_RST#

APU_TCK

A11

G12

APU_TEST24_SCANCLK1

71

APU_TCK

TCK

JTAG

TEST24

3

2

H_CPUPWRGD

APU_TMS

D12

AH10

APU_TEST25_H_BYPASSCLK_H

FS1R1

1

R615

2

Do Not Stuff

71

APU_TMS

APU_TRST#

B12

TMS

TEST25_H

AH9

APU_TEST25_L_BYPASSCLK_L

DY

RN603

71

APU_TRST#

TRST#

TEST25_L

APU_DBRDY

B11

K7

1D5V_S3

71

APU_DBRDY

APU_DBREQ#

C11

DBRDY

TEST28_H

K8

1D5V_S3

71

APU_DBREQ#

DBREQ#

TEST28_L

RN608

TEST30_H

AA12

ANATSTIN_H

TP601 Do Not Stuff

4

1

E8

RSVD#E8

TEST30_L

AB12

ANATSTIN_L

TP617 Do Not Stuff

1

3

DY

2

K21

K22

M_TEST

[AMD FAE Frank]: This is electrical key.

RSVD#K21

TEST31

R612

AC11

RSVD#AC11

RSVD

TEST32_H

AB11 ANATSTOUT_H

TP618 Do Not Stuff

Do not allow power to turn on if this pin is still "L."

Do Not Stuff

42

APU_VDDNB_RUN_FB_L

1

R648

2

Do Not Stuff

AA11

ANATSTOUT_L

300R2J-4-GP

TEST32_L

D10

TEST35

TP619 Do Not Stuff

FS1 package is open pin, in the furtur, FS1r2 will have this pin tied to VSS.

1

R649

2

Do Not Stuff

APU_RUN_FB_L

B9

TEST35

If the wrong processor is plugged the socket, this is more of a problem on desktop platforms

2

1D5V_S0

42 APU_VDD_RUN_FB_L

1

VSS_SENSE

Y11

FS1R1

Do Not Stuff

TP620

APU_VDDP_FB_H

C8

VDDP_SENSE

FS1R1

FS1R1

36

(CPUs changing)

TEST35

RN605

42 APU_VDDNB_RUN_FB_H

Do Not Stuff

TP622

A9

VDDIO_SENSE

SENSE

DMAACTIVE#

AB10

ALLOW_STOP

17

1

4

1

APU_SVD_R

1

APU_VDDIO_SUS_FB_H

B10

VDDNB_SENSE

3

DY

2

APU_SVC_R

42 APU_VDD_RUN_FB_H

APU_VDDR_FB_H

C9

VDD_SENSE

THERMDA

AE12

DY R617

Do Not Stuff

Do Not Stuff

TP623

1

A10

VDDR_SENSE

THERMDC

AD12

PU for internal

Do Not Stuff

1D5V_S3

PD for customer

SAINE

2

RN607

4

1

3

2

SRN1K8J-GP

1D5V_S3

3D3V_S0

19 DP_HPD1_R

1 R637

2 Do Not Stuff

DP_HPD1_C

1

FCH_UMA_PX

1

R653

1D5V_S3

3D3V_S5

1D5V_S3

R635

10KR2J-3-GP

10KR2J-3-GP

C

84.T3904.C11

R651

210KR2J-3-GP

PCH_TEMP_ALERT#

1

2

DP_HPD1_C

R639

2150KR2J-L1-GP

DP_HPD1_C_B

Q604

2ND = 84.03904.P11

1

2

R636

1

B

3rd = 84.03904.L06

PROCHOT#APU VDDIO Q

1

MMBT3904-4-GP

THERMTRIP#APU VDDIO Q

DY Do Not Stuff

R644

2 1 E

SRN1KJ-4-GP

1

10KR2J-3-GP

ALERT#APU Q

2

DP1_HPD

S3 Power

2

DY Do Not Stuff

1D5V_S3

RN601

3D3V_S5

R640

8

1

APU_ALERT#

1008: FCH No Internal PU, POP R638

10KR2J-3-GP

7

2 APU_THERMTRIP#_VDDIO

6

3

APU_SIC

5

4

APU_SID

R638

B

2

APU_ALERT#

APU_PROCHOT#_VDDIO

1D5V_S3

APU_THERMTRIP#_VDDIO

E

DYC

PCH_TEMP_ALERT#

19,27

C

E

APU_PROCHOT#_VDDIO_R

42

1D5V_S3

E

C

H_THERMTRIP#

18,36,85

Q603

Q602

RN604

Q601

Do Not Stuff

MMBT3904-4-GP

8

1

APU_TRST#

MMBT3904-4-GP

Do Not Stuff

84.T3904.C11

7

2

APU_TCK

84.T3904.C11

2ND = 84.03904.P11

2ND = 84.03904.P11

1207 Modify: Add Level Shift, Page

C

84.T3904.C11

6

3

APU_TMS

2ND = 84.03904.P11

3rd = 84.03904.L06

3rd = 84.03904.L06

42 Regulator Has 3D3V_S0 Pull High

2ND = 84.03904.P11

5

4

APU_TDI

3rd = 84.03904.L06

9

DP_HPD0_C

1

R641

150KR2J-L1-GP

DP_HPD0_C_B

B

Q605

3rd = 84.03904.L06

2

SRN1KJ-4-GP

1

MMBT3904-4-GP

CPU exceeds to 125

E

R646

SICAPU

SIDAPU

2

100KR2J-1-GP

1

DP0_HPD

1

R634

2300R2J-4-GP

APU_DBREQ#

R642

10KR2J-3-GP

1D5V_S3

1

1

1D5V_S0

2

0714: Move From Page 9

R616

1KR2J-1-GP APU_PROCHOT#_VDDIO

C628

C629

1

2

2

Do Not Stuff

2

Do Not Stuff

1

1D5V_S3

DY R667

3D3V_S0_TRAVIS

1008: Change R616 From 300 Ohm To 1K, AMD Checklist Update

DY

DY

Do Not Stuff

2

2

R656

1

CPUPWRGDH B

3D3V_S0

2K2R2J-2-GP

R657

0105: APU SMBUS Timing Issue, Change From BJT To Mos

UMA_PX

4K7R2J-2-GP

1

1

2ND = 84.03904.P11

Do Not Stuff

1

2

1

2 1

BLPWMAPUQ

3D3V_S5

3D3V_S5

R668

Do Not Stuff

DY

1D5V_S3

Q606

R650

1D5V_S3

Q607

R652

DY

B

DQ15 AMD DIS SAMSUNG TI

H_CPUPWRGD

BSS138-8-GP

10KR2J-3-GP

BSS138-8-GP

10KR2J-3-GP

2

3

H_CPUPWRGD_E

42

84.00138.H31

84.00138.H31

Q611

APU_BLPWM

Wistron Corporation

G

2

G

2

Do Not Stuff

E

C

APU_BLPWM_TRAVIS

9

Q608

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

D

D

Taipei Hsien 221, Taiwan, R.O.C.

SML1_CLK

27,85

SML1_DATA

27,85

1

R633

2

Do Not Stuff

1

MMBT3904-4-GP

APU_SIC

S

APU_SID

S

1011: Reserve Level Shift.

R655

84.T3904.C11

Title

APU_COntrol&Debug(3/5)

101227

DY

Do Not Stuff

2ND = 84.03904.P11

		2	3rd = 84.03904.L06	Size	Document Number				Rev
				Custom		QUEEN AMD Muxless/UMA			X00
				Date:	Thursday, May 26, 2011		Sheet 6	of	104
5	4	3	2				1

D

C

B

A

D

C

B

A

5

APU_VDD

	1	C708	1	C707	1		C706	1	C705	1	C704	1	C703	1	C702	1	C701
		SC10U6D3V5KX1GP-		SC10U6D3V5KX1GP-			StuffNotDo		SC10U6D3V5KX1GP-		SCD22U10V2KX1GP-		SCD01U16V2KX3GP-		SCD01U16V2KX3GP-			StuffNotDo
	2		2		2			2		2		2		2
						DY										DY
																2

APU_VDDNB

2 1

C719

2 1

C718

1

C717

1

C716

1

C715

1D5V_S3

-SC22U6D3V5MX

-SC22U6D3V5MX

DY

StuffNot Do

DY

StuffNot Do

DY

StuffNot Do

2

2

2

2GP

2GP

1

C730

2 1

C729

2 1

C728

2 1

C727

1

C726

2 1

C725

1

C724

2

Stuff Not Do

1GP-SCD22U10V2KX

1GP-SCD22U10V2KX

1GP-SCD22U10V2KX

Stuff Not Do

GP-SC4D7U6D3V3KX

2

Stuff Not Do

DY

DY

DY

2

1D2V_S0

1D2V_S0

0.75A for VDDA(35W/45W) 2D5V_S0

1

C740

1

C739

1

C738

2

GP-SC4D7U6D3V3KX

2

1GP-SCD22U10V2KX

2

1GP-SC3300P50V2KX

5

4

APU1D

C1 VDD

D3 VDD

D6 VDD

E1 VDD

F3 VDD

F6 VDD

F8 VDD

G1 VDD

H3 VDD

H6 VDD

H8 VDD

J1 VDD

K3 VDD

K6 VDD

L1 VDD

L11 VDD

L19 VDD

M3 VDD

M6 VDD

M10 VDD

M18 VDD

N1 VDD

N11 VDD

N19 VDD

P3 VDD

P6 VDD

P10 VDD

P18 VDD

R1 VDD

R11 VDD

R19 VDD

T3 VDD

J9 VDDNB

J10 VDDNB

J11 VDDNB

J12 VDDNB

J14 VDDNB

J16 VDDNB

K9 VDDNB

K10 VDDNB

G28 VDDIO

H26 VDDIO

J28 VDDIO

K20 VDDIO

K23 VDDIO

K26 VDDIO

L22 VDDIO

L25 VDDIO

L28 VDDIO

M20 VDDIO

M23 VDDIO

M26 VDDIO

N22 VDDIO

N25 VDDIO

N28 VDDIO

P20 VDDIO

P23 VDDIO

P26 VDDIO

AG2 VDDP_A

AG3 VDDP_A

AG4 VDDP_A

AG5 VDDP_A

AG6 VDDR

AG7 VDDR

AG8 VDDR

AG9 VDDR

AE11	VDDA
AF11	VDDA
	SAINE

4

SAINE

4 OF 6

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDDNB VDDNB VDDNB VDDNB VDDNB VDDNB VDDNB VDDNB

VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO

VDDP_B VDDP_B VDDP_B VDDP_B

VDDR

VDDR

VDDR

VDDR

T6

T10

T18

U1

U11

U19

V3

V6

V10

V18

W1

W11

W13

W15

W17

W19

Y3

Y6

Y10

Y12

Y14

Y16

Y18

Y20

AA1

AB3

AB6

AC1

AD3

AD6

AE1

K11

K12

K13

K14

K16

K17

K18

L18

R22

R25

R28

T20

T23

T26

U22

U25

U28

V20

V23

V26

W22

W25

W28

Y24

Y26

AA28

A3

A4

B3

B4

A5

A6

B5

B6

3

2

1

APU_VDD

2 1

C714

2 1

C713

2 1

C712

2 1

C711

2 1

C710

1

C709

SC10U6D3V5KX

SC10U6D3V5KX

SC10U6D3V5KX

SCD22U10V2KX

SCD01U16V2KX

DY

StuffNot Do

2

1GP-

1GP-

1GP-

1GP-

3GP-

VDD:

36A for VDD(35W CPU)

45A for VDD(45W CPU)

10uF X7

0.22uF X2

10nF X3

D

180pF Cap for EMI requirment

2 1	C723
		SC22U6D3V5MX
		2GP-
1		C737
		Do
DY		Not
2		Stuff
2 1		C751
		SC10U6D3V5KX
		1GP-

2 1	C722
	SC22U6D3V5MX
	2GP-
2 1	C736
	SCD22U10V2KX
	1GP-
2 1	C750
	SC10U6D3V5KX
	1GP-

	APU_VDDNB
2 1	C721	1	C720
	SCD22U10V2KX	2	StuffNot Do
		DY
	1GP-
2 1	C735	2 1	C734
	SCD22U10V2KX		SCD22U10V2KX
	1GP-		1GP-
2 1	C749	2 1	C748
	SC10U6D3V5KX		SCD22U10V2KX
	1GP-		1GP-

VDDNB:

18A for VDDNB(35W CPU)

22A for VDDNB(45W CPU)

10UF X4

0.22UF X2

10nF X4

180pF Cap for EMI requirment

					1D5V_S3
1	C733		1	C732		2 1	C731
		StuffNot Do	2		StuffNot Do			SC4D7U6D3V3KX
DY			DY
2
								GP-
					1D2V_S0
2 1	C747		1	C746		1	C745
		SCD22U10V2KX	DY		StuffNot Do	DY		StuffNot Do
			2			2
		1GP-

VDDIO:

4A for VDDIO(35W CPU)

4.6A for VDDIO(45W CPU)

10uF X2

0.22uF X6

4.7uF X4

180pF Cap for EMI requirment

VDDP:

3.5A for VDDP(35W/45W)

10uF X3

0.22uF X4

180pF Cap for EMI requirment

0111: Change C744, C743 From 22uF to 0.22 uF

1D5V_S3

21	C744	21	C743	1
	SCD22U10V2KX		SCD22U10V2KX		C742
					Do Not Stuff
				2
				DY
	1GP-		1GP-

Decoupling between processor and DIMMs across VDDIO and VSS Split

1D2V_S0

C

1		C741
		Do Not Stuff

DY2

B

2 1

C767

C766

C765

2 1

C764

1

C763

1

C762

1

C761

1

C760

2 1

C759

2 1

C758

2 1

C757

C756

2 1

C755

C754

2 1

C753

C752

1GP-SCD22U10V2KX 21

1GP-SCD22U10V2KX 21

1GP-SCD22U10V2KX

1GP-SCD22U10V2KX

DY

StuffNot Do

DY

StuffNot Do

DY

StuffNot Do

DY

StuffNot Do

GP-SC4D7U6D3V3KX

GP-SC4D7U6D3V3KX

GP-SC4D7U6D3V3KX

2 1

GP-SC4D7U6D3V3KX

1GP-SC1KP50V2KX 21

1GP-SC1KP50V2KX

1GP-SC1KP50V2KX 21

1GP-SC1KP50V2KX

2

2

2

2

VDDR:

3A for VDDR(35W)

3.5A for VDDR(45W)

DQ15 AMD DIS SAMSUNG TI

A

4.7uF X4

Wistron Corporation

0.22uF X4

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

1nF X4

Taipei Hsien 221, Taiwan, R.O.C.

180pF Cap for EMI requirment

Title

APU_Power(4/5)

Size

Document Number

Rev

Custom

QUEEN AMD Muxless/UMA

X00

Date:

Thursday, May 26, 2011

Sheet

7

of

104

3

2

1

5

4

3

2

1

D

		A7
		A13
		A15
		A17
		A19
		A21
		A23
		A25
		B7
		C4
		C10
		C14
		C16
		C18
		C20
		C22
		C24
		C26
		C28
		D13
		D15
		D17
		D19
		D21
		D23
	C	D25
		D27
		E4
		E10
		E12
		F9
		F11
		F14
		F16
		F18
		F20
		F22
		F24
		F26
		F28
		G4
		G8
		G13
		G15
		G17
		G19
		G21
		G23
		G25
		J4
		J8
		J18
		J20
	B	J22
		J24
		K19
		L4
		L7
		L10
		M9
		M11
		M19
		N4
		N7
		N10
		N18
		P9
		P11
		P19
		R4
		R7
		R10
		R18
		T9
	A

APU1E

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

SAINE

SAINE

5 OF 6

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

T11

T19

U4

U7

U10

U18

V9

V11

V19

W4

W7

W10

W12

W14

W16

W18

Y9

Y22

AA4

AA7

AB9

AB13

AB15

AB17

AB19

AB21

AB23

AB25

AB27

AC4

AC7

AC10

AC12

AC14

AC16

AC18

AC20

AC22

AC24

AC26

AC28

AD9

AD11

AE4

AE7

AE13

AE15

AE17

AE19

AE21

AE23

AE25

AE27

AF3

AF6

AF9

AF12

AF14

AF16

AF18

AF20

AF22

AF24

AF26

AF28

AG10

AH5

AH8

AH13

AH15

AH17

AH19

AH21

AH23

AH25

DQ15 AMD DIS SAMSUNG TI

		Wistron Corporation
		21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
		Taipei Hsien 221, Taiwan, R.O.C.
Title
		APU_VSS(5/5)
Size	Document Number				Rev
A3		QUEEN AMD Muxless/UMA			X00
Date:	Thursday, May 26, 2011		Sheet 8	of	104

D

C

B

A

5

4

3

2

1

D

C

B

A

5

4

3

2

1

1207: Use PLT_RST# to replace 3D3V_S0_TRAVIS for APU_PCIE_RST#_R.

UMA_PX

1

R901

2

Do

Not Stuff

APU_PCIE_RST#_R

17,71,82,83 PLT_RST#

R923

1

3D3V_S0_TRAVIS

2

1

UMA_PX

DY

C902

Do Not Stuff

2

SCD1U10V2KX-5GP

0628: Change Tolerence to 5 %

TRAVIS Rev 1.01 sugget to stuff 1M-ohm

SCD1U10V2KX-5GP

3D3V_S0_TRAVIS

1	U902
	R902
UMA_PX	1MR2J-L2-GP
2

DVDD33

53 DVDD33

13 DVDD33

1

2

C905

POR#

34

POR#

UMA_PX

APU_PCIE_RST#_R

12

RESET#

1231: New Spec Changed Pin 30 To IN and Connect P,

17

TRAVIS_REFCLKN

31

OSC_IN

From Vendor Feedback. Mail Confirm

17

TRAVIS_REFCLKP

30

OSC_OUT

Do Not Stuff TP902

1

DAC_TDO

54

TDO

Do Not Stuff TP904

1

DAC_TDI

55

TDI

Do Not Stuff TP903

1

DAC_TMS

57

TMS

Do Not Stuff TP901

1

DAC_TCK

56

TCK

0105: Vendor Suggestion To Add Pair of Cap In Near Travis Also

48

6 APU_BLPWM_TRAVIS

CPU_VARY_BL

UMA_PX

6

LVDS_CHN_TRAVIS

C921

1

2SCD1U16V2KX-3GP

LVDS_CHN_TRAVIS_C

60

AUX_CH_N

6

LVDS_CHP_TRAVIS

C932

1

2SCD1U16V2KX-3GP

LVDS_CHP_TRAVIS_C

61

AUX_CH_P

UMA_PX

3

6

LVDS_L0P_TRAVIS

DPRX_L0_P

4

6

LVDS_L0N_TRAVIS

6

DPRX_L0_N

6

LVDS_L1P_TRAVIS

DPRX_L1_P

6 LVDS_L1N_TRAVIS

7

DPRX_L1_N

6 DP_HPD0_C

UMA_PX 1R905

2LVDS_HPD_TRAVIS

58

DPRX_HPD

Do Not Stuff

0112: Vendor Suggestion To Add PU For AUXP, PL for AUXN

GND

ANX3110-GP

65

3D3V_S0

UMA_PX C920

1

2

LVDS_CHP_TRAVIS

1 R903

2

Do Not Stuff

SCD1U10V2KX-5GP

DY

UMA_PX

1

2

R914

Do Not Stuff

1231: Change To 10K PU

LVDS_CHN_TRAVIS

1 R906

2

DYDo Not Stuff

GND_TRVS

3D3V_S0_TRAVIS

1 R927

2 ANX3100_CLK_SEL

UMA_PX 10KR2J-3-GP

DVDD12 AVDD33											AVDD12
																				GND_TRVS
9		32	46	59		8	25	33	39	63		1			2		5	62
DVDD12		DVDD12 DVDD12 DVDD12				AVDD33 AVDD33 AVDD33 AVDD33 AVDD33							AVDD12			AVSS AVSS AVSS
																			LVDS_U3_P			45
																						44
																			LVDS_U3_N			43	if use single channel,
																		LVDS_CLKU_P
																						42
																		LVDS_CLKU_N
																						41	have to use L Group
																			LVDS_U2_N			40
																			LVDS_U2_P
																			LVDS_U1_P			38
																						37
																			LVDS_U1_N			36
																			LVDS_U0_P			35
																			LVDS_U0_N			29	No Need
																			LVDS_L3_P
																						28
																			LVDS_L3_N			27										LVDSA_CLK	49
																		LVDS_CLKL_P
																						26
																		LVDS_CLKL_N				24										LVDSA_CLK#		49
																			LVDS_L2_P			23										LVDSA_DATA2		49
																			LVDS_L2_N													LVDSA_DATA2#		49
																						22
			UMA_PX																LVDS_l1_P			20										LVDSA_DATA1		49
																			LVDS_l1_N
																						21										LVDSA_DATA1#		49
																			LVDS_L0_P													LVDSA_DATA0		49
																						19
																			LVDS_L0_N					UMA_PX								LVDSA_DATA0#		49
																			DDC_DATA			50	LVDS_DDC_DATA_X	1R907			2	Do Not Stuff				LVDS_DDC_DATA_R 49
							SDACFG SCLCFG				SELCLK ENTEST BIASR											49	LVDS_DDC_CLK_X	1R908			2	Do Not Stuff
0GPIO		1GPIO 2GPIO																		DIGON												LVDS_VDD_EN 49
																				DDC_CLK		47		UMA_PX								LVDS_DDC_CLK_R 49
																				VARY_BL												L_BKLT_CTRL		49
																						15
																				BL_EN		14										L_BKLT_EN	27
16		17	18			52		51			10		11		64
2											ANX3100CLK SEL		DAC TST EN		R BIAS
			R915
			10KR2J-3-GP
1			UMA_PX
									R917			2
						Do Not Stuff						DY					1231:Reserve 10K, Vendor Suggest											L_BKLT_EN
												1																	1
																															R926
																													2		100KR2J-1-GP
											R904
															1				1
													-L-12KR2F							C912
																			2
																				SC100P50V2JN-3GP
									UMA_PX									UMA		_PX
													GP		2

Vendor Confirm: C912 100p

1D2V_TRAVIS

	R922	UMA_PX
		1	2
	Do Not Stuff
2
DY	C906
1	Do Not Stuff

DVDD12

				400mA
1	1		1	1		2		1	C911	1
C907	C908	C909		C903	C910		C904		UMA3GP-SCD01U16V2KX 2
DoNot Stuff 2	UMASCD1U10V2KX-5GP 2	_PX	2	UMASCD1U10V2KX-5GP 2	_PXSC2D2U10V3KX-1GP	UMA1		_PXStuffNotDo			_PX
		Stuff						2
		NotDo
DY
			DY					DY

1D2V_TRAVIS

AVDD12

	220 ohm 3A
	L901
	1	2UMA_PX
	HCB2012KF-221T30-GP
	68.00216.161
	2ND = 68.00206.121
2DY
	C901
1	Do Not Stuff

3D3V_S0_TRAVIS

	400mA
1	1	2	1	C919	1
C915	C916	C917	C918	3GP-SCD01U16V2KX
DoNot Stuff 2	DoNot Stuff 2	SC2D2U10V3KX-1GP 1	DYStuffNotDo		2
			2
DY	DY	UMA_PX		UMA_PX
		AVDD33

	220 ohm 3A								0512 David
		L903						150mA
	UMA_PX
	1		2
	HCB2012KF-221T30-GP
	68.00216.161
	2ND = 68.00206.121
2				1	C924	1	1	2	1	C928	1
	C922		C923			C925		C926	C927	UMA3GP-SCD01U16V2KX _PX
DY1	Do Not Stuff		SCD1U10V2KX-5GP	2	DYDoNotStuff		DoNotStuff 2DY	UMASC2D2U10V3KX-1GP _PX 3GP-SCD01U16V2KX 2
						2		1			2
			UMA_PX						UMA_PX
3D3V_S0_TRAVIS					DVDD33
	R921	UMA_PX		150mA
		1	2
		Do Not Stuff
2				1		2
	C929		C930		C931
	Do Not Stuff			2		UMA1	_PX
DY			UMA5GP _PX
1			SCD1U10V2KX-		SC2D2U10V3KX1GP-

D

C

B

0504 -Sabine David

Annie and Rosa team soluton co-layout

0321

0321

MOS spec VGS:20V

1

2

For ANX3100 ALSO

Rosa:RUN_Enable 15V

R924

Do Not Stuff

R925

Do Not Stuff

2

Annie:RUN Enable 9V

U901

1D2V_TRAVIS

Do Not Stuff

1D2V_S0

U905

3D3V_S0

0714: Add to Avoid System Run Power Being Pull Low

3D3V_S0_TRAVIS

Do Not Stuff

15V_S5

S

D

S

D

G

DY

DY

1

Do Not Stuff

G

R919

Do Not Stuff

Do Not Stuff

TRAVIS_1D2V

R916

TRAVIS_3D3V

DY

DY

MOS spec VGS:20V

2

Q903_D

2

1

Rosa:RUN_Enable 15V

1

Do Not Stuff

Annie:RUN Enable 9V

DY

C936

1

R918

2

1

2

Do Not Stuff

DY

Do Not Stuff

DY

C933

A

Do Not Stuff

2

1

Q903

DY

C935

Do Not Stuff

2

18

TRAVIS_EN#

G

DY

DQ15 AMD DIS SAMSUNG TI

D

Wistron Corporation

1

S

R920

Do Not Stuff

Reserved for tuning sequence of 3.3V and 1.2V

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Do Not Stuff

Taipei Hsien 221, Taiwan, R.O.C.

DY

Do Not Stuff

Title

2

TRAVIS ANX3100

2ND = 84.2N702.031

Size

Document Number

Rev

A2

QUEEN AMD Muxless/UMAX00

Date:

Friday, May 27, 2011

Sheet

9

of

104

5

4

3

2

1

5

4

3

2

1

D

D

C

C

B

B

A

A

DQ15 AMD DIS SAMSUNG TI

		Wistron Corporation
		21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
		Taipei Hsien 221, Taiwan, R.O.C.
Title		Reserved
Size	Document Number			Rev
A2		QUEEN AMD Muxless/UMA		X00
Date:	Thursday, May 26, 2011	Sheet 10	of	104

5

4

3

2

1

5

4

3

2

1

D

C

B

A

DQ15 AMD DIS SAMSUNG TI

		Wistron Corporation
		21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
		Taipei Hsien 221, Taiwan, R.O.C.
Title
		Reserved
Size	Document Number				Rev
A3		QUEEN AMD Muxless/UMA			X00
Date:	Thursday, May 26, 2011		Sheet 11	of	104

D

C

B

A

5

4

3

2

1

5

4

3

2

1

D

C

B

A

DQ15 AMD DIS SAMSUNG TI

		Wistron Corporation
		21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
		Taipei Hsien 221, Taiwan, R.O.C.
Title
		Reserved
Size	Document Number				Rev
A3		QUEEN AMD Muxless/UMA			X00
Date:	Thursday, May 26, 2011		Sheet 12	of	104

D

C

B

A

5

4

3

2

1

5

4

3

2

1

D

C

B

A

DQ15 AMD DIS SAMSUNG TI

		Wistron Corporation
		21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
		Taipei Hsien 221, Taiwan, R.O.C.
Title
		Reserved
Size	Document Number				Rev
A3		QUEEN AMD Muxless/UMA			X00
Date:	Thursday, May 26, 2011		Sheet 13	of	104

D

C

B

A

5

4

3

2

1

D

C

B

A

5							4						3															2														1
SSID = MEMORY
											DM1												0117: Brazo S3 Issue, Sabine Reserve Only
								5	M_A_A0	98	A0	NP1	NP1																	M_A_DIM0_CKE0
								5	M_A_A1	97	A1	NP2	NP2																	M_A_DIM0_CKE1
										96
								5	M_A_A2	95	A2		110		M_A_RAS#	5																											D
								5	M_A_A3		A3	RAS#
								5	M_A_A4	92	A4	W E#	113		M_A_WE#	5
								5	M_A_A5	91	A5	CAS#	115		M_A_CAS#	5						1			1
										90
								5	M_A_A6		A6
								5	M_A_A7	86	A7	CS0#	114		M_A_DIM0_CS#0		5						R1403			R1404
										89			121										Do Not Stuff			Do Not Stuff
								5	M_A_A8	85	A8	CS1#			M_A_DIM0_CS#1		5							DY		DY
								5	M_A_A9		A9
								5	M_A_A10	107	A10/AP	CKE0	73		M_A_DIM0_CKE0		5					2			2
										84			74
								5	M_A_A11		A11	CKE1			M_A_DIM0_CKE1		5
								5	M_A_A12	83	A12
								5	M_A_A13	119	A13	CK0	101		M_A_DIM0_CLK_DDR0			5
										80			103
								5	M_A_A14		A14	CK0#			M_A_DIM0_CLK_DDR#0			5
								5	M_A_A15	78	A15
								5	M_A_BS2	79	A16/BA2	CK1	102		M_A_DIM0_CLK_DDR1			5
													104
												CK1#			M_A_DIM0_CLK_DDR#1			5
								5 M_A_BS0		109	BA0
										108			11
								5	M_A_BS1		BA1	DM0	28		M_A_DM0	5
												DM1			M_A_DM1	5
								5	M_A_DQ0	5	DQ0	DM2	46		M_A_DM2 5
										7			63					Intel HR DM tied to GND
								5	M_A_DQ1		DQ1	DM3			M_A_DM3	5
								5	M_A_DQ2	15	DQ2	DM4	136		M_A_DM4	5		AMD still following previous design
										17			153
								5	M_A_DQ3	4	DQ3	DM5	170		M_A_DM5	5
								5	M_A_DQ4		DQ4	DM6			M_A_DM6 5
								5	M_A_DQ5	6	DQ5	DM7	187		M_A_DM7	5																1213 Modify: Remove Dimm Thermal Function
								5	M_A_DQ6	16	DQ6
								5	M_A_DQ7	18	DQ7	SDA	200		PCH_SMBDATA		15,79,82
								5	M_A_DQ8	21	DQ8	SCL	202		PCH_SMBCLK		15,79,82
										23
								5	M_A_DQ9	33	DQ9		198					3D3V_S0
								5	M_A_DQ10		DQ10	EVENT#
								5	M_A_DQ11	35	DQ11
										22			199
								5	M_A_DQ12	24	DQ12	VDDSPD
DDR_VREF_S3								5	M_A_DQ13		DQ13
								5	M_A_DQ14	34	DQ14	SA0	197	SA0_DIM0	1				1
										36			201	SA1_DIM0		C1401				C1402
								5	M_A_DQ15		DQ15	SA1
								5	M_A_DQ16	39	DQ16					SCD1U10V2KX-5GP			DYDo Not Stuff
								5	M_A_DQ17	41	DQ17	NC#1	77		2				2
1		1		1				5	M_A_DQ18	51	DQ18	NC#2	122		1D5V_S3
	C1411		C1412		C1413			5	M_A_DQ19	53	DQ19	NC#/TEST	125
	SCD1U10V2KX-5GP	DYDo Not Stuff			SCD1U10V2KX-5GP					40
								5	M_A_DQ20		DQ20		75																								RN1401
2		2		2				5	M_A_DQ21	42	DQ21	VDD1				SA0_DIM0																PCH_SMBDATA
								5	M_A_DQ22	50	DQ22	VDD2	76																								2			3	SMB_DATA	18,75
										52			81																			PCH_SMBCLK					1			4			C
								5	M_A_DQ23	57	DQ23	VDD3	82			SA1_DIM0																									SMB_CLK	18,75
								5	M_A_DQ24		DQ24	VDD4
								5	M_A_DQ25	59	DQ25	VDD5	87																								SRN0J-6-GP
										67			88
0D75V_S0								5	M_A_DQ26	69	DQ26	VDD6	93					1				1																DY2
								5	M_A_DQ27		DQ27	VDD7
										56			94						R1401					R1402								PCH_SMBDATA					C1423 1			Do Not Stuff
								5	M_A_DQ28	58	DQ28	VDD8	99						Do Not Stuff					Do Not Stuff								PCH_SMBCLK					C1424 1		2	Do Not Stuff
								5	M_A_DQ29		DQ29	VDD9
1								5	M_A_DQ30	68	DQ30	VDD10	100																									DY
	C1418									70			105					2				2
DYDo Not Stuff								5	M_A_DQ31	129	DQ31	VDD11	106
								5	M_A_DQ32		DQ32	VDD12
2								5	M_A_DQ33	131	DQ33	VDD13	111
										141			112
								5	M_A_DQ34	143	DQ34	VDD14	117
								5	M_A_DQ35		DQ35	VDD15
								5	M_A_DQ36	130	DQ36	VDD16	118
										132			123
								5	M_A_DQ37	140	DQ37	VDD17	124
								5	M_A_DQ38		DQ38	VDD18
								5	M_A_DQ39	142	DQ39
										147			2
								5	M_A_DQ40		DQ40	VSS
0D75V_S0								5	M_A_DQ41	149	DQ41	VSS	3
								5	M_A_DQ42	157	DQ42	VSS	8
										159			9
								5	M_A_DQ43		DQ43	VSS
								5	M_A_DQ44	146	DQ44	VSS	13
										148			14
								5	M_A_DQ45	158	DQ45	VSS	19
								5	M_A_DQ46		DQ46	VSS
								5	M_A_DQ47	160	DQ47	VSS	20
										163			25
1	C1419	1	C1420	1	C1421	1	C1422	5	M_A_DQ48	165	DQ48	VSS	26
								5	M_A_DQ49		DQ49	VSS
	SC1U6D3V2KX-GP	DYDo Not Stuff			SC1U6D3V2KX-GP	DYDo Not Stuff		5	M_A_DQ50	175	DQ50	VSS	31
2		2		2		2		5	M_A_DQ51	177	DQ51	VSS	32
								5	M_A_DQ52	164	DQ52	VSS	37
								5	M_A_DQ53	166	DQ53	VSS	38
	Place these caps close to VTT1 and VTT2.									174			43
								5	M_A_DQ54		DQ54	VSS
								5	M_A_DQ55	176	DQ55	VSS	44
										181			48
								5	M_A_DQ56	183	DQ56	VSS	49
								5	M_A_DQ57		DQ57	VSS
								5	M_A_DQ58	191	DQ58	VSS	54
										193			55
								5	M_A_DQ59	180	DQ59	VSS	60
								5	M_A_DQ60		DQ60	VSS
								5	M_A_DQ61	182	DQ61	VSS	61
										192			65
								5	M_A_DQ62	194	DQ62	VSS	66
								5	M_A_DQ63		DQ63	VSS
												VSS	71																														B
								5	M_A_DQS#0	10	DQS0#		72					SODIMM A DECOUPLING Layout Note: Place these Caps near SO-DIMMA.
												VSS
								5	M_A_DQS#1	27	DQS1#	VSS	127
								5	M_A_DQS#2	45	DQS2#	VSS	128					1D5V_S3
										62			133
								5	M_A_DQS#3		DQS3#	VSS
								5	M_A_DQS#4	135	DQS4#	VSS	134								0112: Change TC1401 330uF 6m To 220uF 15 m "DY" same as DV14 Brazo
								5	M_A_DQS#5	152	DQS5#	VSS	138
								5	M_A_DQS#6	169	DQS6#	VSS	139
								5	M_A_DQS#7	186	DQS7#	VSS	144
													145								TC1401
										12		VSS	150
								5	M_A_DQS0		DQS0	VSS								1	Do Not Stuff		1		2 1		1		2 1		1			1		1		1
								5 M_A_DIM0_ODT0		29	ODT0	VSS	151											StuffNot Do		1GP-SC10U6D3V5KX		StuffNot Do		1GP-SC10U6D3V5KX			Stuff		StuffNot Do		StuffNot Do			StuffNot Do
								5	M_A_DQS1	47	DQS1	VSS	155																				Do
								5	M_A_DQS2	64	DQS2	VSS	156							DY2			DY2			DY2					DY2		NotDY2			DY2		DY2
								5	M_A_DQS3	137	DQS3	VSS	161
								5	M_A_DQS4	154	DQS4	VSS	162
								5	M_A_DQS5	171	DQS5	VSS	167
								5	M_A_DQS6	188	DQS6	VSS	168
								5	M_A_DQS7		DQS7	VSS	172
												VSS
										116			173
								5	M_A_DIM0_ODT1	120	ODT1	VSS	178
													179
												VSS
									DDR_VREF_S3	126	VREF_CA	VSS	184					1		1			1		1
										1			185						C1414		C1415			C1416		C1417
							M_A_RST#				VREF_DQ	VSS	189					2	5GP-SCD1U10V2KX	2	5GP-SCD1U10V2KX		2	5GP-SCD1U10V2KX	2	5GP-SCD1U10V2KX
					Intel HR channel A & B RST tied toghter			5	M_A_RST#	30		VSS	190
											RESET#	VSS
					AMD have to separate channel A & B							VSS	195
												VSS	196
									0D75V_S0	203	VTT1	VSS	205
										204			206
											VTT2	VSS
					1	C1425					DDR3-204P-43-GP
					DYDo Not Stuff							H =4mm
					2
										0914: DIMM1 Change To 62.10017.N71

0628: Reserve Cap						A
	DQ15 AMD DIS SAMSUNG TI
			Wistron Corporation
			21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
			Taipei Hsien 221, Taiwan, R.O.C.
	Title
		DDR3-SODIMM1
	Size	Document Number			Rev
		QUEEN AMD Muxless/UMA			X00
	Date:	Thursday, May 26, 2011	Sheet 14	of	104

5

4

3

2

1

D

C

B

A

5

4

3

2

1

SSID = MEMORY

SO-DIMMB is placed farther from the Processor than SO-DIMMA

										5	M_B_A0
										5	M_B_A1
										5	M_B_A2
										5	M_B_A3
										5	M_B_A4
										5	M_B_A5
										5	M_B_A6
										5	M_B_A7
										5	M_B_A8
										5	M_B_A9
										5	M_B_A10
										5	M_B_A11
										5	M_B_A12
										5	M_B_A13
										5	M_B_A14
										5	M_B_A15
										5 M_B_BS2
										5 M_B_BS0
										5 M_B_BS1
										5	M_B_DQ0
										5	M_B_DQ1
										5	M_B_DQ2
										5	M_B_DQ3
										5	M_B_DQ4
										5	M_B_DQ5
										5	M_B_DQ6
										5	M_B_DQ7
										5	M_B_DQ8
										5	M_B_DQ9
										5	M_B_DQ10
										5	M_B_DQ11
										5	M_B_DQ12
										5	M_B_DQ13
										5	M_B_DQ14
										5	M_B_DQ15
										5	M_B_DQ16
										5	M_B_DQ17
										5	M_B_DQ18
										5	M_B_DQ19
										5	M_B_DQ20
										5	M_B_DQ21
										5	M_B_DQ22
										5	M_B_DQ23
										5	M_B_DQ24
										5	M_B_DQ25
										5	M_B_DQ26
										5	M_B_DQ27
										5	M_B_DQ28
										5	M_B_DQ29
										5	M_B_DQ30
										5	M_B_DQ31
										5	M_B_DQ32
										5	M_B_DQ33
										5	M_B_DQ34
DDR_VREF_S3										5	M_B_DQ35
										5	M_B_DQ36
										5	M_B_DQ37
										5	M_B_DQ38
1			1	C1516		1	C1517			5	M_B_DQ39
										5	M_B_DQ40
	C1515			Do Not Stuff			SCD1U10V2KX-5GP
	SCD1U10V2KX-5GP		DY							5	M_B_DQ41
2			2			2				5	M_B_DQ42
										5	M_B_DQ43
										5	M_B_DQ44
										5	M_B_DQ45
										5	M_B_DQ46
										5	M_B_DQ47
										5	M_B_DQ48
										5	M_B_DQ49
0D75V_S0										5	M_B_DQ50
										5	M_B_DQ51
										5	M_B_DQ52
										5	M_B_DQ53
										5	M_B_DQ54
1	C1518	1	C1519		1	C1520		1	C1521	5	M_B_DQ55
										5	M_B_DQ56
DYDo Not Stuff			SC1U6D3V2KX-GP DYDo Not Stuff						SC1U6D3V2KX-GP
										5	M_B_DQ57
2		2			2			2		5	M_B_DQ58
										5	M_B_DQ59
										5	M_B_DQ60
	Place these caps close to VTT1 and VTT2.									5	M_B_DQ61
										5	M_B_DQ62
										5	M_B_DQ63
										5	M_B_DQS#0
										5	M_B_DQS#1
										5	M_B_DQS#2
										5	M_B_DQS#3
										5	M_B_DQS#4
										5	M_B_DQS#5
										5	M_B_DQS#6
										5	M_B_DQS#7
										5	M_B_DQS0
										5	M_B_DQS1
										5	M_B_DQS2
										5	M_B_DQS3
										5	M_B_DQS4
										5	M_B_DQS5
										5	M_B_DQS6
										5	M_B_DQS7
										5 M_B_DIM0_ODT0
										5 M_B_DIM0_ODT1
											DDR_VREF_S3
						M_B_RST#			Intel HR channel A & B RST tied toghter 5		M_B_RST#
				1		C1522			AMD have to separate channel A & B
				DYDo Not Stuff							0D75V_S0
				2

0628: Reserve Cap

		DM2
	98	A0	NP1	NP1
	97	A1	NP2	NP2
	96
	95	A2		110
		A3	RAS#
	92	A4	W E#	113
	91			115
	90	A5	CAS#
		A6
	86	A7	CS0#	114
	89			121
	85	A8	CS1#
		A9
	107	A10/AP	CKE0	73
	84			74
		A11	CKE1
	83	A12
	119			101
	80	A13	CK0	103
		A14	CK0#
	78	A15
	79			102
		A16/BA2	CK1	104
			CK1#
	109	BA0
	108			11
		BA1	DM0	28
			DM1
	5	DQ0	DM2	46
	7			63
		DQ1	DM3
	15	DQ2	DM4	136
	17	DQ3	DM5	153
	4			170
		DQ4	DM6
	6	DQ5	DM7	187
	16
	18	DQ6		200
		DQ7	SDA
	21	DQ8	SCL	202
	23
	33	DQ9		198
		DQ10	EVENT#
	35	DQ11
	22			199
	24	DQ12	VDDSPD
		DQ13
	34	DQ14	SA0	197	SA0_DIM1
	36			201	SA1_DIM1
		DQ15	SA1
	39	DQ16
	41			77
	51	DQ17	NC#1	122
		DQ18	NC#2
	53	DQ19	NC#/TEST	125
	40
	42	DQ20		75
		DQ21	VDD1
	50	DQ22	VDD2	76
	52			81
	57	DQ23	VDD3	82
		DQ24	VDD4
	59	DQ25	VDD5	87
	67			88
		DQ26	VDD6
	69	DQ27	VDD7	93
	56	DQ28	VDD8	94
	58			99
		DQ29	VDD9
	68	DQ30	VDD10	100
	70			105
	129	DQ31	VDD11	106
		DQ32	VDD12
	131	DQ33	VDD13	111
	141			112
	143	DQ34	VDD14	117
		DQ35	VDD15
	130	DQ36	VDD16	118
	132			123
	140	DQ37	VDD17	124
		DQ38	VDD18
	142	DQ39
	147			2
		DQ40	VSS
	149	DQ41	VSS	3
	157			8
	159	DQ42	VSS	9
		DQ43	VSS
	146	DQ44	VSS	13
	148			14
	158	DQ45	VSS	19
		DQ46	VSS
	160	DQ47	VSS	20
	163			25
	165	DQ48	VSS	26
		DQ49	VSS
	175	DQ50	VSS	31
	177			32
		DQ51	VSS
	164	DQ52	VSS	37
	166	DQ53	VSS	38
	174			43
		DQ54	VSS
	176	DQ55	VSS	44
	181			48
	183	DQ56	VSS	49
		DQ57	VSS
	191	DQ58	VSS	54
	193			55
	180	DQ59	VSS	60
		DQ60	VSS
	182	DQ61	VSS	61
	192			65
	194	DQ62	VSS	66
		DQ63	VSS
			VSS	71
	10			72
		DQS0#	VSS
	27	DQS1#	VSS	127
	45			128
	62	DQS2#	VSS	133
		DQS3#	VSS
	135	DQS4#	VSS	134
	152			138
	169	DQS5#	VSS	139
		DQS6#	VSS
	186	DQS7#	VSS	144
				145
	12		VSS	150
		DQS0	VSS
	29	DQS1	VSS	151
	47			155
		DQS2	VSS
	64	DQS3	VSS	156
	137	DQS4	VSS	161
	154			162
		DQS5	VSS
	171	DQS6	VSS	167
	188			168
		DQS7	VSS	172
			VSS
	116	ODT0	VSS	173
	120			178
		ODT1	VSS	179
			VSS
	126	VREF_CA	VSS	184
	1			185
		VREF_DQ	VSS	189
			VSS
	30	RESET#	VSS	190
				195
			VSS
			VSS	196
	203			205
	204	VTT1	VSS	206
		VTT2	VSS
		DDR3-204P-44-GP
			H = 8mm

0914: DIMM2 Change To 62.10017.N91

5

4

3

D

			0117: Brazo S3 Issue, Sabine Reserve Only
				M_B_DIM0_CKE0
				M_B_DIM0_CKE1
		1		1
M_B_RAS#	5		R1503	R1504
M_B_WE#	5		Do Not Stuff	Do Not Stuff
M_B_CAS# 5			DY	DY
		2		2
M_B_DIM0_CS#0 5
M_B_DIM0_CS#1 5
M_B_DIM0_CKE0 5
M_B_DIM0_CKE1		5

M_B_DIM0_CLK_DDR0 5

M_B_DIM0_CLK_DDR#0 5

M_B_DIM0_CLK_DDR1 5

M_B_DIM0_CLK_DDR#1 5

	M_B_DM0 5
	M_B_DM1 5
	M_B_DM2 5
	M_B_DM3		5	Intel HR DM tied to GND
	M_B_DM4 5					3D3V_S0
				AMD still following previous design
	M_B_DM5 5
	M_B_DM6 5
	M_B_DM7		5			1
	PCH_SMBDATA			14,79,82		R1501
						10KR2J-3-GP
	PCH_SMBCLK			14,79,82
						C
				3D3V_S0		2
						SA0_DIM1
	1	C1501		1	C1502	SA1_DIM1
						1
		SCD1U10V2KX-5GP DYDo Not Stuff				R1502
	2			2
						Do Not Stuff
	1D5V_S3					2

Intel HR B channel address is 01

AMD B channel address is 10

SODIMM B DECOUPLING Layout Note: Place these Caps near SO-DIMMB.

1D5V_S3

1

C1503

1

C1504

2 1

C1505

2 1

C1506

2 1

C1507

1

C1508

2 1

C1509

1

C1510

Do

StuffNot Do

1GP-SC10U6D3V5KX

1GP-SC10U6D3V5KX

1GP-SC10U6D3V5KX

StuffNot Do

1GP-SC10U6D3V5KX

StuffNot Do

Stuff

Not

DY

DY

DY

DY

2

2

2

2

B

1

C1511

1

C1512

1

C1513

1

C1514

2

5GP-SCD1U10V2KX

2

5GP-SCD1U10V2KX

2

5GP-SCD1U10V2KX

2

5GP-SCD1U10V2KX

A

DQ15 AMD DIS SAMSUNG TI

		Wistron Corporation
		21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
		Taipei Hsien 221, Taiwan, R.O.C.
Title
	DDR3-SODIMM2
Size	Document Number		Rev
	QUEEN AMD Muxless/UMA		X00
Date:	Thursday, May 26, 2011	Sheet 15 of	104

2

1

5

4

3

2

1

D

C

B

A

DQ15 AMD DIS SAMSUNG TI

			Wistron Corporation
			21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
			Taipei Hsien 221, Taiwan, R.O.C.
	Title
			Reserved
	Size	Document Number				Rev
	A3	QUEEN AMD Muxless/UMA				X00
	Date:	Thursday, May 26, 2011		Sheet 16	of	104

D

C

B

A

5

4

3

2

1

5

4

3

2

1

D

C

B

A

1

C1716

FCH1E

SC150P50V2KX-GP

PCIE_RST#_C

AE2

2

R1717

33R2J-2-GP

PCIE_RST#

27,36 A_RST#

1

2

A_RST#_R

AD5

A_RST#

C1707

1

2

SCD1U16V2KX-3GP

A_RX0P_C

AE30

4

UMI_FCH_APU_RX0P

UMI_TX0P

C1708

1

2

SCD1U16V2KX-3GP

A_RX0N_C

AE32

4

UMI_FCH_APU_RX0N

UMI_TX0N

C1709

1

2

SCD1U16V2KX-3GP

A_RX1P_C

AD33

4

UMI_FCH_APU_RX1P

UMI_TX1P

C1710

1

2

SCD1U16V2KX-3GP

A_RX1N_C

AD31

4

UMI_FCH_APU_RX1N

UMI_TX1N

C1711

1

2

SCD1U16V2KX-3GP

A_RX2P_C

AD28

4

UMI_FCH_APU_RX2P

UMI_TX2P

C1712

1

2

SCD1U16V2KX-3GP

A_RX2N_C

AD29

4

UMI_FCH_APU_RX2N

UMI_TX2N

C1713

1

2

SCD1U16V2KX-3GP

A_RX3P_C

AC30

4

UMI_FCH_APU_RX3P

UMI_TX3P

C1714

1

2

SCD1U16V2KX-3GP

A_RX3N_C

AC32

4

UMI_FCH_APU_RX3N

UMI_TX3N

AB33

4

UMI_APU_FCH_TX0P

UMI_RX0P

AB31

4

UMI_APU_FCH_TX0N

UMI_RX0N

AB28

4

UMI_APU_FCH_TX1P

UMI_RX1P

AB29

4

UMI_APU_FCH_TX1N

Y33

UMI_RX1N

4

UMI_APU_FCH_TX2P

UMI_RX2P

Y31

4

UMI_APU_FCH_TX2N

UMI_RX2N

Y28

4

UMI_APU_FCH_TX3P

Y29

UMI_RX3P

4

UMI_APU_FCH_TX3N

1

R1708

2

590R2F-GP

APU_PCIE_CALRP

AF29

UMI_RX3N

PCIE_CALRP

1D1V_PCIE_S0

1

R1709

2

2KR2F-3-GP

APU_PCIE_CALRN

AF31

INTERFACES

V33

PCIE_CALRN

GPP_TX0N

C1719 1

DN152 Do Not Stuff

V31

GPP_TX0P

75

PCIE_TXP5

PCIE_TXP5_C

W30

GPP_TX1P

EXPRESS

75

PCIE_TXN5

C1720 1

DN152 Do Not Stuff

PCIE_TXN5_C

W32

GPP_TX2P

AB26

AB27

GPP_TX2N

PCI

AA24

AA23

GPP_TX3P

1214: Add DN15 Express Card

AA27

GPP_TX3N

GPP_RX0P

AA26

75

PCIE_RXP5

W27

GPP_RX0N

GPP_RX1P

V27

75

PCIE_RXN5

GPP_RX1N

V26

W26

GPP_RX2P

GPP_RX2N

W24

GPP_RX3P

W23

1D1V_CKVDD_S0

1

R1710

2

2KR2F-3-GP

CLK_CALRN

F27

GPP_RX3N

CLK_CALRN

Ext. Clock_Gen

G30

PCIE_RCLKP

G28

Do Not Stuff

R1718

PCIE_RCLKN

6

DISP_CLKP

1

2

FCHDISP_CLKP_R

R26

DISP_CLKP

Do Not Stuff

1

R1719

2

FCHDISP_CLKN_R

T26

6

DISP_CLKN

DISP_CLKN

9

TRAVIS_REFCLKP

Do Not Stuff

1

R1720

2

FCHTRVS_CLKP_R

H33

DISP2_CLKP

Do Not Stuff

1

R1721

2

FCHTRVS_CLKN_R

H31

9

TRAVIS_REFCLKN

DISP2_CLKN

6

APU_CLKP

Do Not Stuff

1

R1736

2

FCHAPU_CLKP_R

T24

APU_CLKP

Do Not Stuff

1

R1737

2

FCHAPU_CLKN_R

T23

6

APU_CLKN

APU_CLKN

83 CLK_PCIE_VGA

Do Not Stuff

1

R1738

2

FCHGFX_CLKP_R

J30

SLT_GFX_CLKP

Do Not Stuff

1

R1739

2

FCHGFX_CLKN_R

K29

83

CLK_PCIE_VGA#

SLT_GFX_CLKN

Do Not Stuff

R1744

DN15

NEW_CLK_R

New Card

75

CLK_PCIE_NEW

1

DN15

2

H27

GPP_CLK0P

75 CLK_PCIE_NEW#

Do Not Stuff

R1745

1

2

NEW_CLK#_R

H28

GPP_CLK0N

WLAN

82 CLK_PCIE_WLAN

Do Not Stuff

1

R1740

2

CLK_MINI1_R

J27

GPP_CLK1P

Do Not Stuff

1

R1741

2

CLK_MINI1#_R

K26

82

CLK_PCIE_WLAN#

GPP_CLK1N

WWAN

F33

GPP_CLK2P

F31

82 CLK_PCIE_LAN

Do Not Stuff

1

R1742

2

LAN_CLK_R

E33

GPP_CLK2N

LAN

GPP_CLK3P

Do Not Stuff

1

R1743

2

LAN_CLK#_R

E31

82 CLK_PCIE_LAN#

GPP_CLK3N

GPP CLK port

Device

CLKREQ#

M23

GPP_CLK4P

M24

0

New Card

0

GPP_CLK4N

1

WLAN

1

M27

GPP_CLK5P

2

WWAN

2

M26

3

LAN

3

GPP_CLK5N

4

X

N25

GPP_CLK6P

5

X

N26

GPP_CLK6N

6

X

7

X

R23

GPP_CLK7P

8

X

R24

GPP_CLK7N

If LAN support Wake on S5,

N27

GPP_CLK8P

do not use clock from FCH,

R27

Use 48Mhz CLK For 5138

have to use X'tal

GPP_CLK8N

32 CLK_PCH_48M

1

R1711

222R2J-2-GP

48M_OSC

J26

14M_25M_48M_OSC

1

EC1701

25M_X1

DY

C31

25M_X1

2

Do Not Stuff

25M_X2

C33

25M_X2

0719: EMI Request

			C1704
25M_X1		X1701	1	2
			SC15P50V2JN-2-GP
	1	4
	2
R1701
1MR2J-1-GP	2	3		1122 Modify:
				Change X1701 to 82.30020.D41 from
	1	XTAL-25MHZ-155-GP	C1705	from Sourcer Dick updated.
25M_X2	82.30020.D41		1	2
			SC15P50V2JN-2-GP
5				4

Part 5 of 5

0628: Change R1712 & R1715 Short Pad

3D3V_S0

3D3V_S0

PCICLK0

AF3

PCI_CLK0_R

R1712

Do Not Stuff

TP59

Do Not Stuff

1

1

AF1

PCI_CLK1_R

1

2

PCICLK1/GPO36

PCI_CLK1

21

R1723

R1733

PCICLK2/GPO37

AF5

PCI_CLK2_R

TP60

Do Not Stuff

AG2

PCI_CLK3_R

1

R1714

2

22R2J-2-GP

Do Not Stuff

Do Not Stuff

PCICLK3/GPO38

CLK_PCI_LPC 21,71

AF6

PCI_CLK4_R

1

R1715

2

Do Not Stuff

DIS_UMA

DN15

CLKS

PCICLK4/14M_OSC/GPO39

PCI_CLK4

21

AB5

PCI_RST#

1

dGPU_PRSNT#

2

GSENSOR_DET

2

PCI

PCIRST#

TP1702

1

1

AD0/GPIO0

AJ3

R1722

R1735

AL5

0109: EMI Reserve, Place Near R1728

10KR2J-3-GP

Do Not Stuff

AD1/GPIO1

AD2/GPIO2

AG4

PX

DY

AL6

2

2

AD3/GPIO3

AH3

AD4/GPIO4

AJ5

DGPU_PWROK

AD5/GPIO5

AL1

AD6/GPIO6

AN5

GSENSOR_DET

For SW Jin define

For SW Jin define

AD7/GPIO7

2

AN6

dGPU_PRSNT#

AD8/GPIO8

EC1704

AJ1

AD9/GPIO9

AL8

1

AD10/GPIO10

AM7

DY

Stuff

AD11/GPIO11

AL3

AD12/GPIO12

AJ6

Not

CLK_PCI_LPC

AD13/GPIO13

AD14/GPIO14

AK7

Do

AN8

1

AD15/GPIO15

AG9

AD16/GPIO16

DY EC1702

AM11

AD17/GPIO17

AJ10

Do Not Stuff

AD18/GPIO18

2

AL12

AD19/GPIO19

AK11

AD20/GPIO20

AN12

Debug Strap

AD21/GPIO21

AG12

AD22/GPIO22

AE12

KBC

AD23/GPIO23

PCI_AD23

21

INTERFACE

AC12

0719: EMI Request

AD26/GPIO26

PCI_AD26

21

AD24/GPIO24

AE13

PCI_AD24

21

Folloiwng Intel HR netname

AD25/GPIO25

PCI_AD25

21

AF13

PCI

AD27/GPIO27

AH13

Do Not Stuff

R1728

PCI_AD27

21

1 R1716

33R2J-2-GP

AH14

PE_PWRGD

1

2

PCIE_RST#_C

2

AD28/GPIO28

DGPU_PWROK

86,92,93

PLT_RST#

9,71,82,83

AD15

BACO

AD29/GPIO29

AD30/GPIO30

AC15

1

C1715

AE16

AD31/GPIO31

AN3

SC150P50V2KX-GP

CBE0#

AJ8

2

CBE1#

0916: Add 1D5V_VGA_PWOK Connect To FCH,

AN10

CBE2#

AD12

AMD BACO Document Update

CBE3#

AG10

FRAME#

AK9

1207: Change DGPU_PWROK To 1D5V_VGA_PWOK

DEVSEL#

LDT_STP# connection is just for chipset automation purpose.

AL10

IRDY#

TRDY#

AF10

3D3V_S0

3D3V_S0

It is an automatic test for AMD validation team only

AE10

PAR

69

KB_LED_BL_DET

AH1

STOP#

1 R1702

2 Do Not Stuff

AM9

APU_STOP#

1D5V_S0

PERR#

AH8

0105: Follow DV GPIO

DY

SERR#

R1724

R1725

AG15

REQ0#

AG13

Do Not Stuff

Do Not Stuff

REQ1#/GPIO40

RTC_SENSE

60

AF15

DY

DY

REQ2#/CLK_REQ8#/GPIO41

AM17

KB_LED_BL_DET

69

Muxless support

REQ3#/CLK_REQ5#/GPIO42

2

2

GNT0#

AD16

AD13

PE_GPIO0: VGA_RESET

GNT1#/GPO44

PE_GPIO0

83

AD21

PE_GPIO1: VGA_PowerEnable

GNT2#/SD_LED/GPO45

PE_GPIO1

92,93

AK17

GNT3#/CLK_REQ7#/GPIO46

SATA_ODD_DA#

56

AD19

CLKRUN#

PM_CLKRUN#

27

AH9

LOCK#

PM_CLKRUN#:

No PU Res needed, integrated Resistor PU10K

INTE#

R1727

INTE#/GPIO32

AF18

1

2

HDD_FALL_INT1 79

0719: ADD, Confirm SW

AE18

Do Not Stuff

INTF#/GPIO33

AC16

DN15

INTG#/GPIO34

AD18

1019: Add KB_LED_BL_DET FCH GPIO.

INTH#/GPIO35

C1701 1

2 Do Not Stuff

LPCCLK0

B25

LPCCLK0_R

1

R1726

222R2J-2-GP

DY

LPC_CLK0

21,27

GENERATOR

D25

LPC

LAD2

A26

LPC_AD2_R

1

R1731

2

33R2J-2-GP

LPC_AD2

27,71

There is integrated pull-up.

LPCCLK1

D27

LPC_AD0_R

1

R1729

2

33R2J-2-GP

LPC_CLK1

21

LAD0

C28

LPC_AD1_R

1

R1730

2

33R2J-2-GP

LPC_AD0

27,71

LAD1

LPC_AD1

27,71

CLOCK

LAD3

A29

LPC_AD3_R

1

R1732

2

33R2J-2-GP

LPC_AD3

27,71

A31

LPC_FRAME#_R

1

R1734

2

33R2J-2-GP

LFRAME#

LPC_FRAME#

27,71

INT_SERIRQ 1 R1705

2 Do Not Stuff

B27

3D3V_S0

LDRQ0#

AE27

0304: Reserve 0 Ohm For EA Fail

DY

LDRQ1#/CLK_REQ6#/GPIO49

AE19

INT_SERIRQ

INT_SERIRQ

27

SERIRQ/GPIO48

G25

DMA_ACTIVE#

ALLOW_STOP

6

PROCHOT#

E28

APU_PROCHOT#_VDDIO 6

0906: Change X1702 From 82.3001.661 To 82.3001.A81

APU

E26

Base on Sourcer Suggestion

APU_PG

G26

APU_STOP#

H_CPUPWRGD

6,36,71

LDT_STP#

F26

APU_RST#

6

APU_RST#

32K_X1

1

2

C1702

32K_X1

G2

32K_X1

SC18P50V2JN-1-GP

32K_X2

G4

32K_X2

1

R1706

4

3

S5_CORE_EN

H7

1

2

Do Not Stuff

PCH_SUSCLK_KBC 27

R1703

PLUS

F1

20MR3-GP

X1702

RTCCLK

F3

INTRUDER_ALERT#

1

TP1701

RTC_CLK

21

INTRUDER_ALERT#

X-32D768KHZ-67-GP

E6

S5

VDDBT_RTC_G

2

C1706

RTC_AUX_S5

2

1

2

71.HUDM2.M01

1

SCD1U16V2KX-3GP

32K_X2

1

2

PCH_SUSCLK_KBC

C1703

SC18P50V2JN-1-GP

1

DQ15 AMD DIS SAMSUNG TI

DY

EC1703

2

Do Not Stuff

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

82.30020.851

Taipei Hsien 221, Taiwan, R.O.C.

Title

0719: EMI Request

Reserved

Size

Document Number

Rev

Custom

QUEEN AMD Muxless/UMA

X00

Date:

Friday, May 27, 2011

Sheet 17

of

104

3

2

1

D

C

B

A

5

4

3

2

1

D

C

B

A

0909: Modify

Pop R1843 For UMA Config	0109: EMI Reserve, Place Near R1810
Pop R1844 For Muxless Config	Remove PCIE2_RST, Did Not Use FCH GPP

3D3V_S5
2				FCH_PCIE_RST#
	R1843		2
	Do Not Stuff				EC1803
	UMA
21		CLKREQG#	1		Do Not Stuff
			DY
	R1844
	10KR2J-3-GP
1	DIS_PX

Confirm with SW, RSMRST# from KBC is push-pull. It can be drived high by SW.

1

R1825

2

100KR2J-1-GP RSMRST#_KBC

75 FCH_PCIE_RST#

27,36,44,46,75 PM_SLP_S3#

27,44,75 PM_SLP_S5#

27 PM_PWRBTN#

36 FCH_PWRGD

27	H_A20GATE
27	H_RCIN#
27	EC_SCI#
27	EC_SMI#

1213 Modify: Remove Dimm Thermal Function

1214 Add PCIE2_RST For EXPRESS CARD FCH GPP

				DN15
	R1810	1		Do Not Stuff2		FCH_PCIE_RST#_R
1	R1809	2		Do Not Stuff		PM_PWRBTN#_R
						FCH_TEST0
						FCH_TEST1
						FCH_TEST2
1	R1814	2		Do Not Stuff		EC_A20M#_R
						EC_KB_RST#_R
1	R1813	2		Do Not Stuff
						EC_SCI#
1	R1832	2		Do Not Stuff		EC_SMI#_R

1	C1802	RSMRST#_R		0716: From KBC	27	PCH_WAKE#
DY Do Not Stuff					6,36,85	H_THERMTRIP#
2							3D3V_S0
					27	RSMRST#_KBC
* Travis_EN#: Base on AMD suggestion, use the GPIO66 same the CRB first.					82 PCIE_CLK_LAN_REQ#
		If it work normally, ask BIOS to re-program to GPIO55 to double verify.
					75 CLK_PCIE_NEW_REQ#
						9	TRAVIS_EN#
						9	TRAVIS_EN#
3D3V_S5		0719: Change From 2.2K and POP				29	HDA_SPKR
					14,75		SMB_CLK
			RN1802		14,75		SMB_DATA
		4	1	SCLK1
		3	2	SDATA1
			SRN10KJ-5-GP	82	CLK_PCIE_WLAN_REQ#

1	R1815	2	10KR2J-3-GP			WD_PWRGD
1	R1821	2	Do Not Stuff			RSMRST#_R
				0719: ADD
1	R1829	2	Do	Not Stuff		PCIE_CLK_LAN_RQ1#_R
	DN15					CLK_PCIE_NEW_REQ#_R
1	R1846	2	Do Not Stuff
1	R1842	DY2	Do Not Stuff			FCH_GPIO55
1	R1841	2	Do Not Stuff
	R1840	DY	Do Not Stuff			HDA_SPKR_R
1		2
						SCLK1
						SDATA1
1	R1834	2	Do Not Stuff			CLK_PCIE_WLAN_REQ#_R

	RN1804			20	VGA_PD
1		8	FCH_TEST2
2		7	FCH_TEST1
3	DY	6	FCH_TEST0			0909: Un-Stuff (DY) For Leakage Issue, Follow DQ15 Intel
4		5	85	PEG_CLKREQ#		1	R1822	2 Do Not Stuff	CLKREQG#
	Do Not Stuff						DY

79

FFS_INT2_R

DN15

R1847

2

Do Not Stuff

FFS_INT2_X

27

EC_SWI#

EC_SWI#

1

R1845

2

Do Not Stuff

VGA_PD

82

USB_OC#5

DY

ODD_DA_Q

56

ODD_DA_Q

1

R1830

2

Do Not Stuff

SATA_ODD_PRSNT#_R

1

R1839

2

Do Not Stuff

PCH_WAKE#

56 SATA_ODD_PRSNT#

82

USB_OC#2

DY

57

USB_OC#1

1

R1824

2

Do Not Stuff

EC_SCI#

57

USB_OC#0

DY

EC1802

Do Not Stuff

1

DY2

1

R1833

2

Do Not Stuff

EC_SWI#

29 HDA_CODEC_BITCLK

1

R1803

2

33R2J-2-GP

HDA_BITCLK

DY

1

R1804

2

33R2J-2-GP

HDA_SDOUT

29 HDA_CODEC_SDOUT

29

HDA_SDIN0

HDA_SDIN0

1

R1835

2

Do Not Stuff

PM_PWRBTN#

3D3V_S0

DY

0721: Reserve PM_PWRBTN# If KBC Change To OD

R1805

33R2J-2-GP

HDA_SYNC

29

HDA_CODEC_SYNC

1

2

1

R1806

2

33R2J-2-GP

HDA_RST#

29

HDA_CODEC_RST#

1

EC1801

1

R1836

2

Do Not Stuff

EC_SMI#

DY Do Not Stuff

DY

2

1

R1837

2

Do Not Stuff

H_A20GATE

DY

1

R1838

2

Do Not Stuff

H_RCIN#

DY

There are integrated pull-up.

RN1801

1

4

SMB_CLK

2

3

SMB_DATA

SRN2K2J-1-GP

Modify Zero Power ODD circuit by

Annie team suggestion.

	RN1803
8		1	HDA_CODEC_RST#
7		2	HDA_CODEC_BITCLK
6	DY	3
5		4	HDA_SDIN0
	Do Not Stuff

Checklist suggestion: Don't stuff for default

0719: Modify

3D3V_S5

	RN1806
1	8	USB_OC#1
2	7	USB_OC#2
3	6	USB_OC#5
4	5	USB_OC#0

SRN100KJ-8-GP-U

Integrated PU is not supported when the pin is configured for USB over current function.

		FCH1A			Part 1 of 5
	AB6	PCIE_RST2#/PCI_PME#/GEVENT4#		USBCLK/14M_25M_48M_OSC
	R2	RI#/GEVENT22#
	W7	SPI_CS3#/GBE_STAT1/GEVENT21#		MISC	USB_RCOMP
	T3
	W2	SLP_S3#		USB
		SLP_S5#			USB_FSD1P/GPIO186
	J4
		PWR_BTN#			USB_FSD1N
	N7
		PWR_GOOD
	T9				USB_FSD0P/GPIO185
		TEST0		1.1	USB_FSD0N
	T10
		TEST1/TMS		USB
	V9
	AE22	TEST2			USB_HSD13P
		GA20IN/GEVENT0#		EVENTS	USB_HSD13N
	R9
	AG19	KBRST#/GEVENT1#
	C26	LPC_PME#/GEVENT3#		UP	USB_HSD12P
	U4	LPC_SMI#/GEVENT23#		WAKE/	USB_HSD12N
	T5	LPC_PD#/GEVENT5#
	K1	SYS_RESET#/GEVENT19#		ACPI	USB_HSD11P
		WAKE#/GEVENT8#			USB_HSD11N
	V7
		IR_RX1/GEVENT20#
	R10
		THRMTRIP#/SMBALERT#/GEVENT2#			USB_HSD10P
	AF19
		WD_PWRGD			USB_HSD10N
	U2	RSMRST#			USB_HSD9P
	AG24				USB_HSD9N
		CLK_REQ4#/SATA_IS0#/GPIO64
	AE24
		CLK_REQ3#/SATA_IS1#/GPIO63			USB_HSD8P
	AE26
		SMARTVOLT1/SATA_IS2#/GPIO50			USB_HSD8N
	AF22
		CLK_REQ0#/SATA_IS3#/GPIO60
	AH17
		SATA_IS4#/FANOUT3/GPIO55			USB_HSD7P
	AG18
		SATA_IS5#/FANIN3/GPIO59			USB_HSD7N
	AF24	SPKR/GPIO66
	AD26	SCL0/GPIO43			USB_HSD6P
	AD25	SDA0/GPIO47			USB_HSD6N
	T7
		SCL1/GPIO227		2.0
	R7
		SDA1/GPIO228			USB_HSD5P
	AG25			USB
		CLK_REQ2#/FANIN4/GPIO62			USB_HSD5N
	AG22
		CLK_REQ1#/FANOUT4/GPIO61		GPIO
	J2
	AG26	IR_LED#/LLB#/GPIO184			USB_HSD4P
		SMARTVOLT2/SHUTDOWN#/GPIO51			USB_HSD4N
	V8
		DDR3_RST#/GEVENT7#/VGA_PD
	W8
		GBE_LED0/GPIO183			USB_HSD3P
	Y6
		SPI_HOLD#/GBE_LED1/GEVENT9#			USB_HSD3N
	V10
		GBE_LED2/GEVENT10#
	AA8
		GBE_STAT0/GEVENT11#			USB_HSD2P
	AF25
		CLK_REQG#/GPIO65/OSCIN/IDLEEXIT#			USB_HSD2N
	M7				USB_HSD1P
		BLINK/USB_OC7#/GEVENT18#			USB_HSD1N
	R8	USB_OC6#/IR_TX1/GEVENT6#
	T1	USB_OC5#/IR_TX0/GEVENT17#			USB_HSD0P
	P6
		USB_OC4#/IR_RX0/GEVENT16#			USB_HSD0N
	F5
		USB_OC3#/AC_PRES/TDO/GEVENT15#
	P5
		USB_OC2#/TCK/GEVENT14#			USBSS_CALRP
	J7
		USB_OC1#/TDI/GEVENT13#			USBSS_CALRN
	T8	USB_OC0#/SPI_TPM_CS#/TRST#/GEVENT12#OC
				USB	USB_SS_TX3P
					USB_SS_TX3N
	AB3	AZ_BITCLK			USB_SS_RX3P
	AB1
		AZ_SDOUT			USB_SS_RX3N
	AA2	AZ_SDIN0/GPIO167
	Y5	AZ_SDIN1/GPIO168			USB_SS_TX2P
	Y3	AZ_SDIN2/GPIO169			USB_SS_TX2N
	Y1	AZ_SDIN3/GPIO170
	AE4		AUDIO
	AD6	AZ_SYNC			USB_SS_RX2P
		AZ_RST#	HD		USB_SS_RX2N
	K19				USB_SS_TX1P
		PS2_DAT/SDA4/GPIO187		3.0	USB_SS_TX1N
	J19
		PS2_CLK/CEC/SCL4/GPIO188		USB
	J21
		SPI_CS2#/GBE_STAT2/GPIO166			USB_SS_RX1P
					USB_SS_RX1N
	D21	PS2KB_DAT/GPIO189			USB_SS_TX0P
	C20
		PS2KB_CLK/GPIO190			USB_SS_TX0N
	D23
		PS2M_DAT/GPIO191
	C22
		PS2M_CLK/GPIO192			USB_SS_RX0P
					USB_SS_RX0N
	F21	KSO_0/GPIO209
	E20
		KSO_1/GPIO210			SCL2/GPIO193
	F20
		KSO_2/GPIO211			SDA2/GPIO194
	A22
		KSO_3/GPIO212			SCL3_LV/GPIO195
	E18
		KSO_4/GPIO213			SDA3_LV/GPIO196
	A20
		KSO_5/GPIO214		EC_PWM0/EC_TIMER0/GPIO197
	J18
		KSO_6/GPIO215		EC_PWM1/EC_TIMER1/GPIO198
	H18
		KSO_7/GPIO216	EC_PWM2/EC_TIMER2/WOL_EN/GPIO199
	G18
		KSO_8/GPIO217		EC_PWM3/EC_TIMER3/GPIO200
	B21
		KSO_9/GPIO218
	K18
		KSO_10/GPIO219	EMBEDDED CTRL		KSI_0/GPIO201
	D19
		KSO_11/GPIO220			KSI_1/GPIO202
	A18
		KSO_12/GPIO221			KSI_2/GPIO203
	C18
		KSO_13/GPIO222			KSI_3/GPIO204
	B19	KSO_14/XDB0/GPIO223			KSI_4/GPIO205
	B17	KSO_15/XDB1/GPIO224			KSI_5/GPIO206
	A24
		KSO_16/XDB2/GPIO225			KSI_6/GPIO207
	D17
		KSO_17/XDB3/GPIO226			KSI_7/GPIO208

71.HUDM2.M01

D

G8

B9

USB_RCOMP 1

R1819

2 11K8R2F-GP

H1

H3

H6

H5

H10

USB20_DP3

82

G10

USB20_DM3

82

K10

USB20_DP2

82

J12

USB20_DM2

82

G12

USB20_DP1

82

F12

USB20_DM1

82

K12

K13

B11

USB_PP9

32

D11

USB_PN9

32

E10

USB_PP8

75

F10

USB_PN8

75

1214: Add Express Card For DN15

C10

USB_PP7

49

A10

USB_PN7

49

H9

G9

A8

USB_PP5

49

C8

USB_PN5

49

C

F8

USB_PP4

63

E8

USB_PN4

63

C6

A6

C5

USB_PP2

64

A5

USB_PN2

64

1214: Add FP For DN15

C1

USB_PP1

82

C3

USB_PN1

82

E1

USB_PP0

57

E3

USB_PN0

57

C16

USBSS_CALRP

1 R1817 USB32 1KR2F-3-GP

A16

USBSS_CALRN

1

R1818

1KR2F-3-GP

1D1V_VDD_SSUSB_S5

USB32

A14

USB30_TXDP3_C

C1803 1USB32

SCD1U16V2KX-3GP

USB30_TXDP3

62

C14

USB30_TXDN3_C

C1804 1USB32

SCD1U16V2KX-3GP

USB30_TXDN3

62

C12

USB30_RXDP3

62

A12

USB30_RXDN3

62

D15

USB30_TXDP2_C

C1805 1USB32

SCD1U16V2KX-3GP

USB30_TXDP2

62

B15

USB30_TXDN2_C

C1806 1USB32

SCD1U16V2KX-3GP

USB30_TXDN2

62

E14

USB30_RXDP2

62

F14

USB30_RXDN2

62

F15

USB30_TXDP1_C

C1807 1USB32

SCD1U16V2KX-3GP

USB30_TXDP1

62

G15

USB30_TXDN1_C

C1808 1USB32

SCD1U16V2KX-3GP

USB30_TXDN1

62

H13

USB30_RXDP1

62

G13

USB30_RXDN1

62

J16

B

H16

J15

K15

H19

SCL2

G19

SDAT2

G22

SCLK3

SCLK3

6

G21

SDATA3

SDATA3

6

E22

H22

J22

EC_PWM2

21

H21

K21

K22

F22

KB_DET#

69

F24

E24

B23

C24

F18

0914: Remove DBC_EN & COLOR_ENGINE

0719: If not used SMBUS or GPIO, PD 10k.

		RN1807			SRN10KJ-5-GP
SCLK3	4	1	SCL2	3	2
SDATA3	3	2	SDAT2	4	1
		SRN10KJ-5-GP			RN1805

A

DQ15 AMD DIS SAMSUNG TI

		Wistron Corporation
		21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
		Taipei Hsien 221, Taiwan, R.O.C.
Title	HUDSON-M2(2/6)
Size	Document Number
					Rev
	QUEEN AMD Muxless/UMA				X00
Date:	Friday, May 27, 2011		Sheet 18	of	104

5

4

3

2

1

D

C

B

A

5

4

3

2

1

FCH1B

Part 2 of 5

0630: Place Cap Near Connecetor

56

SATA_TXP0

C1901 1

2SCD01U16V2KX-3GP SATA_TXP0_C

AK19

SATA_TX0P

SD_CLK/SCLK_2/GPIO73

AL14

56

SATA_TXN0

C1902 1

2SCD01U16V2KX-3GP SATA_TXN0_C

AM19

AN14

SATA_TX0N

SD_CMD/SLOAD_2/GPIO74

1st SATA HDD

AJ12

SD_CD#/GPIO75

56 SATA_RXN0_C

AL20

SATA_RX0N

SD_WP/GPIO76

AH12

56

SATA_RXP0_C

AN20

SATA_RX0P

SD_DATA0/SDATI_2/GPIO77

AK13

AM13

2SCD01U16V2KX-3GP SATA_TXP1_C

CARD

SD_DATA1/SDATO_2/GPIO78

56

SATA_TXP1

C1905 1

AN22

AH15

SATA_TX1P

SD_DATA2/GPIO79

D

C1906

1

SCD01U16V2KX-3GP SATA_TXN1_C

AL22

AJ14

SATA ODD

56

SATA_TXN1

2

SATA_TX1N

SD

SD_DATA3/GPIO80

56

SATA_RXN1_C

AH20

SATA_RX1N

GBE_COL

AC4

GBE_COL

GBE_CRS

56

SATA_RXP1_C

AJ20

SATA_RX1P

GBE_CRS

AD3

AD9

GBE_MDCK

57

SATA_TXP2

C1909

1

SCD01U16V2KX-3GP SATA_TXP2_C

AJ22

W10

GBE_MDIO

1

R1920

2

10KR2J-3-GP

2

SATA_TX2P

GBE_MDIO

3D3V_S5

57

SATA_TXN2

C1910 1

2SCD01U16V2KX-3GP SATA_TXN2_C

AH22

AB8

SATA_TX2N

GBE_RXCLK

AH7

GBE_RXD3

eSATA

57 SATA_RXN2_C

AM23

AF7

SATA_RX2N

GBE_RXD2

RN1903

57

SATA_RXP2_C

AK23

AE7

SATA_RX2P

GBE_RXD1

AD7

8

1

GBE_RXD0

AH24

AG8

7

2

SATA_TX3P

GBE_RXCTL/RXDV

AJ24

AD1

GBE_RXCLT

6

3

SATA_TX3N

GBE_RXERR

AB7

5

4

GBE_TXCLK

AN24

LAN

AF9

SATA_RX3N

GBE_TXD3

AL24

AG6

SRN10KJ-6-GP

SATA_RX3P

GBE

GBE_TXD2

AE8

GBE_TXD1

AL26

AD8

SATA_TX4P

GBE_TXD0

AN26

AB9

SATA_TX4N

GBE_TXCTL/TXEN

AC2

GBE_PHY_PD

AJ26

AA7

SATA_RX4N

GBE_PHY_RST#

GBE_PHY

AH26

W9

SATA_RX4P

GBE_PHY_INTR

AN29

SATA_TX5P

AL28

V6

SATA_TX5N

SPI_DI/GPIO164

V5

SPI_DO/GPIO163

AK27

SATA_RX5N

V3

0916: Remove SPI Signal Connect To FCH

ATA

SPI_CLK/GPIO162

AM27

SATA_RX5P

ROMSPI

SPI_CS1#/GPIO165

T6

SERIAL

V1

NC#AL29

ROM_RST#/SPI_WP#/GPIO161

AL29

AN31

NC#AN31

FCH_UMA_PX 1

R1904

2150R2F-1-GP

L30

CRT_RED

94

AL31

VGA_RED

FCH_UMA_PX 1

R1905

2150R2F-1-GP

C

NC#AL31

AL33

NC#AL33

VGA_GREEN

L32

FCH_UMA_PX 1

R1906

2150R2F-1-GP

CRT_GREEN

94

AH33

NC#AH33

VGA_BLUE

M29

CRT_BLUE

94

AH31

NC#AH31

AJ33

NC#AJ33

VGA_HSYNC/GPO68

M28

CRT_HSYNC

94

AJ31

N30

CRT_VSYNC

94

NC#AJ31

VGA_VSYNC/GPO69

DAC

VGA_DDC_SDA/GPO70

M33

CRT_DDC_DATA 94

N32

1

R1901

2

1KR2F-3-GP

SATA_CALP

AF28

VGA

VGA_DDC_SCL/GPO71

CRT_DDC_CLK

94

SATA_CALRP

1D1V_SATA_S0

1

R1902

2

1KR2F-3-GP

SATA_CALN

AF27

K31

HUDSON_DAC_RESET

1

R1907

2715R2F-GP

SATA_CALRN

VGA_DAC_RSET

FCH_UMA_PX

AUX_VGA_CH_P

V28

DP1_AUXP_R

6

68

SATA_LED#

AD22

V29

SATA_ACT#/GPIO67

AUX_VGA_CH_N

DP1_AUXN_R 6

AUXCAL

U28

AUXCAL

1

R1913

2100R2F-L1-GP-U

1D1V_VDDAN_ML_S0

AF21

SATA_X1

T31

ML_VGA_L0P

DP1_TX0P_R

6

[Checklist]:

T33

ML_VGA_L0N

DP1_TX0N_R

6

Integrated Clock Mode, left unconnected

ML_VGA_L1P

T29

DP1_TX1P_R

6

T28

ML_VGA_L1N

DP1_TX1N_R

6

R32

MAINLINK

ML_VGA_L2P

DP1_TX2P_R 6

AG21

R30

ML_VGA_L3P

DP1_TX3P_R

6

SATA_X2

ML_VGA_L2N

P29

DP1_TX2N_R

6

VGA

ML_VGA_L3N

P28

DP1_TX3N_R

6

1

R1908

2Do Not Stuff

3D3V_VDDAN_DAC_S0_R

support ODD Zero power

ML_VGA_HPD/GPIO229

C29

DY

DP_HPD1_R

6

AH16

FANOUT0/GPIO52

VIN0/GPIO175

N2

PSW _CLR#

56

SATA_ODD_PW RGT

AM15

M3

VRAM_SIZE1

FANOUT1/GPIO53

VIN1/GPIO176

B

Do Not Stuff TP1910

1

FCH_PROCHOT#_C

AJ16

L2

VRAM_SIZE2

FANOUT2/GPIO54

HW MONITOR

VIN2/SDATI_1/GPIO177

N4

MEM_1V5

[VRAM_SIZE1:VRAM_SIZE2]

AK15

VIN3/SDATO_1/GPIO178

FANIN0/GPIO56

VIN4/SLOAD_1/GPIO179

P1

MEM_1V35

LL=512M / HL=1G / LH=2G

AN16

P3

VIN_VDDIO

FANIN1/GPIO57

VIN5/SCLK_1/GPIO180

AL16

M1

VIN_VDDR

FANIN2/GPIO58

VIN6/GBE_STAT3/GPIO181

3D3V_S5

M5

GPIO182

VIN7/GBE_LED3/GPIO182

GPIO171

K6

TEMPIN0/GPIO171

FCH_USB3.0PORT_EN#

K5

AG16

TEMPIN1/GPIO172

NC#AG16

MB_THRMDA_FCH

K3

AH10

VDDIO

MEM_1V5

MEM_1V35

1

1

TEMPIN2/GPIO173

NC#AH10

6,27

PCH_TEMP_ALERT#

1

R1912

2

Do Not Stuff

APU_TALERT#

M6

TEMPIN3/TALERT#/GPIO174

NC#A28

A28

DY

G27

1.5V

H

Don't Care

NC#G27

NC#L4

L4

2G R2214

1G R2216

1.35V

L

H

Do Not Stuff

10KR2J-3-GP

2

2

VRAM_SIZE1

71.HUDM2.M01

VRAM_SIZE2

If not used HWM or GPIO, PD 10k.

1

1

R2215

R2217

RN1901

GPIO171

1G_512M 10KR2J-3-GP

Do Not Stuff

8

1

512M_2G

7

2

FCH_USB3.0PORT_EN#

2

2

6

3

GPIO182

5

4

VIN_VDDR

SRN10KJ-6-GP

For PX use only.

RN1902

8

1

VIN_VDDIO

7

2

MEM_1V35

6

3

MEM_1V5

A

5

4

PSW _CLR#

DQ15 AMD DIS SAMSUNG TI

SRN10KJ-6-GP

Wistron Corporation

1

R1914

2

10KR2J-3-GP

MB_THRMDA_FCH

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

1

R1915

2

10KR2J-3-GP

APU_TALERT#

Title

1213 Modify: Remove Dimm Thermal Function

Reserved

Pop R1914 If function Not used.

Size

Document Number

Rev

QUEEN AMD Muxless/UMA

X00

Date: Thursday, May 26, 2011

Sheet

19

of

104

5

4

3

2

1

D

C

B

A

5

4

3D3V_S0

3D3V_FCH_VDDIO_S0

FCH1C

Part 3 of 5

R2002

1

2

Do Not Stuff

102mA AB17

VDDIO_33_PCIGP

VDDCR_11

AB18

VDDIO_33_PCIGP

VDDCR_11

AE9

1

C2002

1

C2003

1

C2004

1

C2005

AD10

VDDIO_33_PCIGP

VDDCR_11

VDDIO_33_PCIGP

VDDCR_11

SC10U6D3V5KX-1GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

AG7

VDDIO_33_PCIGP

CORES0

VDDCR_11

2

2

2

2

AC13

PCI/GPIOI/O

VDDIO_33_PCIGP

VDDCR_11

AB14

AB12

VDDIO_33_PCIGP

VDDCR_11

AB13

VDDIO_33_PCIGP

VDDCR_11

1027 Modify: Change All 22uF To 10uF

AB16

VDDIO_33_PCIGP

VDDCR_11

VDDIO_33_PCIGP

3D3V_VPPL_SYS_S0

R2004

2Do Not Stuff VDDPL_33_DAC

50mA H24

VDDPL_33_SYS

VDDAN_11_CLK

3D3V_VDDPL_MLDAC_S0

1

20mA V22

VDDPL_33_DAC

VDDAN_11_CLK

1

R2005

Do Not Stuff VDDPL_33_ML

12mA U22

2

VDDPL_33_ML

VDDAN_11_CLK

3D3V_S0

220 ohm 300mA

3D3V_VDDAN_DAC_S0_R

30mA T22

VDDAN_33_DAC

VDDAN_11_CLK

L2003

3D3V_VDDPL_SSUSB_S5

11mA L18

VDDPL_33_SSUSB_S

VDDAN_11_CLK

1

2

VDDPL_3.3V_PCIE

3D3V_VDDPL_USB_S5

14mA

D7

VDDPL_33_USB_S

VDDAN_11_CLK

11mAAH29

VDDPL_33_PCIE

I/O

VDDAN_11_CLK

BLM15AG221SS1D-GP

12mAAG28

1

SC2D2U6D3V3KX-GP

1

SCD1U10V2KX-5GP

C2018 1

2

Do Not Stuff

VDDPL_33_SATA

CLKGEN

VDDAN_11_CLK

68.00084.E21

C2016

C2017

1D5V_S0

1

R2006

2

Do Not Stuff

LDO_CAP

DY

2

2

DY

M31

LDO_CAP

VDDAN_11_PCIE

1D1V_VDDAN_MLDAC_S0

1D1V_VDDAN_ML_S0

1D1V_VDDPL_DAC_S0

L2005

V21

VDDAN_11_PCIE

VDDPL_11_DAC

VDDAN_11_PCIE

220 ohm 300mA

1

2

1D1V_VDDAN_MLDAC

1

R2007

2

Do Not Stuff

7mA

3D3V_S0

PBY160808T-330Y-N-GP

1

R2008

2

Do Not Stuff

226mA

Y22

VDDAN_11_ML

VDDAN_11_PCIE

L2006

VDDAN_11_PCIE

1

1

1

V23

VDDAN_11_ML

VDDAN_11_PCIE

1

2

VDDPL_3.3V_SATA

C2026

C2027

C2028

V24

2 1

2 1

GP-SC4D7U6D3V3KX

2

2

5GP-SCD1U10V2KX

2

63mAAB11

VDDAN_11_ML

MAIN LINK

PCI EXPRESS

VDDAN_11_PCIE

VDDCR_11_GBE_S

VDDAN_11_SATA

BLM15AG221SS1D-GP

SCD1U10V2KX-5GP

V25

VDDAN_11_ML

VDDAN_11_PCIE

C2024

C2025

68.00084.E21

SC2D2U6D3V3KX-GP

SCD1U10V2KX-5GP

2mA AB10

VDDIO_33_GBE_S

VDDAN_11_SATA

VDDAN_11_SATA

VDDAN_11_SATA

VDDAN_11_SATA

AA11

VDDCR_11_GBE_S

ATA

VDDAN_11_SATA

145mAAA9

VDDIO_GBE_S

LAN

SERIAL

VDDAN_11_SATA

VDDAN_11_SATA

VDDAN_11_SATA

AA10

VDDIO_GBE_S

GBE

VDDAN_11_SATA

0120: Modify to 0402 0 Ohm

3D3V_S5

220 ohm 3A

3D3V_USB_S5

1

2

470mA G7

VDDAN_33_USB_S

VDDIO_33_S

L2008

Do Not Stuff

H8

VDDAN_33_USB_S

VDDIO_33_S

J8

1

C2037

1

C2038

1

C2039

1

C2040

1

C2041

K8

VDDAN_33_USB_S

VDDIO_33_S

VDDAN_33_USB_S

VDDIO_33_S

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SCD1U10V2KX-5GP

K9

VDDAN_33_USB_S

VDDIO_33_S

2

2

2

2

2

M9

M10

VDDAN_33_USB_S

I/O

VDDIO_33_S

N9

VDDAN_33_USB_S

S5

VDDIO_33_S

VDDAN_33_USB_S

VDDIO_33_S

M12

USB

3.3V

N10

VDDAN_33_USB_S

220 ohm 300mA

0120: Modify to 0402 0 Ohm

N12

VDDAN_33_USB_S

1D1V_S5

VDDAN_33_USB_S

VDDXL_33_S

M11

VDDAN_33_USB_S

1

L2010

2

Do Not Stuff

1D1V_S5 220 ohm 300mA

VDDAN_1.1V_USB

140mAU12

VDDAN_11_USB_S

VDDCR_11_S

1

C2044

1

C2045

U13

VDDAN_11_USB_S

VDDCR_11_S

SC2D2U6D3V3KX-GP

SCD1U10V2KX-5GP

1

L2011

2

Do Not Stuff

VDDCR_1.1V_USB

42mA T12

VDDCR_11_USB_S

VDDPL_11_SYS_S

2

2

C2046

C2047

C2048

T13

1D2V_S5

2 1

5GP-SCD1U10V2KX

2 1

5GP-SCD1U10V2KX

2 1

1GP-SC10U6D3V5KX

VDDCR_11_USB_S

1

R2020

2

Do Not Stuff

282mAP16

VDDAN_11_SSUSB_S

VDDAN_33_HW M_S

DY

M14

VDDAN_11_SSUSB_S

33 ohm 3A

N14

VDDIO_AZ_S

VDDAN_11_SSUSB_S

1D1V_S5

1D1V_VDD_SSUSB_S5

P13

VDDAN_11_SSUSB_S

P14

VDDAN_11_SSUSB_S

1

R2001

2

Do Not Stuff

VDDAN_1.1V_SSUSB_S

424mAN16

VDDCR_11_SSUSB_S

N17

VDDCR_11_SSUSB_S

SS

1

2

1

R2011

2

Do Not Stuff

VDDCR_11_SSUSB_S

P17

VDDCR_11_SSUSB_S

USB

L2001

Do Not Stuff

M17

VDDCR_11_SSUSB_S

USB3

1

C2053

C2054

C2055

C2056

2

1

1

1

1

1

2 1

2 1

1GP-SC10U6D3V5KX

GP-SC1U6D3V2KX

5GP-SCD1U10V2KX

5GP-SCD1U10V2KX

R2017

C2050

C2051

C2052

Do Not Stuff

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SC1U6D3V2KX-GP

USB3 USB3

Non USB3

USB3

USB3

USB3

USB3 USB3

POWER

2

2

2

2

2

71.HUDM2.M01

		3
T14	1007mA
T17
T20		1	C2006
U16
U18			SC1U6D3V2KX-GP
V14		2
V17
V20
Y17
H26	340mA
J25
K24		1	C2011
L22
M22			SC1U6D3V2KX-GP
N21		2
N22
P22
AB241088mA
Y21
AE25		1	C2019
AD24
AB23			SC1U6D3V2KX-GP
AA22		2
AF26
AG27
AA211337mA
Y20
AB21		1	C2029
AB22
AC22			SC1U6D3V2KX-GP
AC21		2
AA20
AA18
AB20
AC19
N18	60mA
L19		1	C2034
M18
V12		DYDo Not Stuff
V13		2
Y12
Y13
W 11
G24 5mA		VDDXL_3.3V
N20	190mA	VDDCR_1D1V
M20
J24	70mA	R2021 2 Do Not Stuff
	1
M8	12mA	DY
		3D3V_VDDAN_HWM_S5
AA4 26mA		VDDIO_AZ

	2					1
					1027 Modify: Errata Add	0111: Change R2019 From 100K to 0 Ohm
						5V_S0
	1207 Modify: Change From 0402 0 Ohm To 0603					2
						DY R2019
	1D1V_VDDCR_S0			1D1V_S0
							Do Not Stuff
	1		2			1
	R2003 Do Not Stuff

1	C2007	1		C2008			1	C2009		1	C2010
	SC1U6D3V2KX-GP			SC10U6D3V5KX-1GP				SCD1U10V2KX-5GP			SCD1U10V2KX-5GP
2		2					2			2
										1D1V_CKVDD_S0 33 ohm 3A
											1		2 VDDAN_11_CLK
											R2023 Do Not Stuff
1	C2012	1		C2013			1	C2014		1	C2015
	SCD1U10V2KX-5GP			SCD1U10V2KX-5GP				SC1U6D3V2KX-GP			SC10U6D3V5KX-1GP
2		2					2			2
										1D1V_PCIE_S0 33 ohm 3A				1D1V_S0
											1		2
											R2024 Do Not Stuff
1	C2021	1		C2022			1	C2020		1	C2023
	SCD1U10V2KX-5GP			SCD1U10V2KX-5GP				SC1U6D3V2KX-GP			SC10U6D3V5KX-1GP
2		2					2			2
										1D1V_SATA_S033 ohm 3A				1D1V_S0
											1		2
											R2025 Do Not Stuff
1	C2030	1		C2031			1	C2032		1	C2033
	SCD1U10V2KX-5GP			SCD1U10V2KX-5GP				SC1U6D3V2KX-GP			SC10U6D3V5KX-1GP
2		2					2			2
								1027 Modify: Change All 22uF To 10uF
	3D3V_S5
1	C2035		1	C2036
	SC2D2U6D3V3KX-GP			SC2D2U6D3V3KX-GP
2			2
										1D1V_S5		1	C2042	1
							1	R2010	2	Do Not Stuff		DYDo Not Stuff
				C2001		C2049						2		2
			2 1		2 1
1D1V_VPPL_SYS_S5				GP-SC1U6D3V2KX		GP-SC1U6D3V2KX				1D2V_S5
1D2V_VPPL_SYS_S5
							1	R2018	2	Do Not Stuff
								DY

VDDAN 11 CLK B
G	1D1V_S0

Do Not Stuff

VDDAN_11_CLK

D

DY

S

	Q2004			1
	Do Not Stuff								C2074
						DY		Do Not Stuff
				2
	1			2
R2029 Do Not Stuff

1207 Modify: Reserve R2029 DY Co-lay

1D2V_S5

1

3D3V_S5

R2027

U2001

Stuff

DY

1

C2077

1

5

IN

OUT

2

Do Not Stuff

2

2

GND

DY

DY

C2075

3

4

1D2V_SET

DY

SHDN#

SET

1 NotDo

2

Stuff

1

Do Not Stuff

Not

R2028

Do

Do Not Stuff

DY

Vout=1.0*(1+R1/R2)

2

3D3V_S5

L2009

1

2

BLM15AG221SS1D-GP

C2043

68.00084.E21

SC2D2U6D3V3KX-GP

220 ohm 300mA

If support USB 3.0 or LAN wake-up, pls tie to 3.3V_S5 otherwise, tie to 3.3V_S0

Confrim

Codec power use3.3V,VDDIO_AZ have to tied to 3.3V

Codec power use1.5V,VDDIO_AZ have to tied to 1.5V

If use 1.5V_S5 power,have to add LDO for it extra

220 ohm 300mA

3D3V_USB_S5	3D3V_VDDPL_USB_S5				3D3V_S5	VDDIO_AZ
	L2013
1	2				1 R2012	2 Do Not Stuff
BLM15AG221SS1D-GP
	1	C2060	1	C2061			1	C2059
68.00084.E21
		SC2D2U6D3V3KX-GP SCD1U10V2KX-5GP			Del reservaton 1D5V_S5			SC2D2U6D3V3KX-GP
	2		2				2

If support USB 3.0 wake-up, tie to 1.1V_S5 If no, tie to 1.1V_S0,

If no USB 3.0, tied to GND

18 VGA_PD

1
		R2015	1				C2073
		2K2R2J-2-GP					Do Not Stuff
			DY
2			2

0120: Modify to 0402 0 Ohm

220 ohm 300mA

3D3V_S0

3D3V_VDDPL_MLDAC_S0

3D3V_S0

3D3V_VPPL_SYS_S0

L2014

L2012

1

2

1

2

DoDYNot Stuff

BLM15AG221SS1D-GP

Do Not Stuff

1

C2062

1

C2063

220 ohm 300mA

1

C2057

1

C2058

3D3V_VDDAN_DAC_S0_R

68.00084.E21

SC2D2U6D3V3KX-GP

SCD1U10V2KX-5GP

SC2D2U6D3V3KX-GP

SCD1U10V2KX-5GP

2

2

2

2

1

R2013 2 Do Not Stuff

3D3V_S0

3D3V_VDDAN_DAC_S0_R

15V_S5

L2018

1

1

DY

2

1

Do Not Stuff

1

3D3V_VDDAN_DAC_S0

C2072

C2071

R2014

Q2002

Do Not Stuff

SC2D2U6D3V3KX-GP

SCD1U10V2KX-5GP

100KR2J-1-GP

2

2

D

S

2

DY

Do Not Stuff

L2019

1

2

VGA_PD_R

G

Do Not Stuff

o Not Stuff

DY

220 ohm 300mA

		1	C2070
	Q2001
		DY Do Not Stuff
G
		2
	D
S
	2N7002K-2-GP
	84.2N702.J31
	2ND = 84.2N702.031
			3D3V_S0

1D1V_S0

Q2003

D

G

Do Not Stuff

MOS spec VGS:20V

Rosa:RUN_Enable 15V

1D1V_VDDAN_MLDAC_S0

Annie:RUN Enable 9V

S

AO3404A-GP

84.03404.B31

1122 Modify:

Add G9091 LDO circuit for CRT DAC power to avoid monitor noise issue.

	5V_S5
	1
C2079
SC1U10V2KX-1GP	2

3D3V_VDDAN_HWM_S5

3D3V_S5

1D1V_S5

1D1V_VPPL_SYS_S5

3D3V_S5

USB3L2016

3D3V_VDDPL_SSUSB_S5

L2017

1

L2015

2

1

2

1

2

Do Not Stuff

BLM15AG221SS1D-GP

BLM15AG221SS1D-GP

1

220 ohm 300mA

1

C2065

1

C2064

220 ohm 300mA

1

C2068

1

C2069

220 ohm 300mA

1

C2066

1

C2067

R2016

SC2D2U6D3V3KX-GP

SCD1U10V2KX-5GP

68.00084.E21

SC2D2U6D3V3KX-GP

SCD1U10V2KX-5GP

68.00084.E21

SC2D2U6D3V3KX-GP

SCD1U10V2KX-5GP

Do Not Stuff

2

2

2

2

USB3

USB3

Non USB3

2

2

2

HW Montior Not implemented	If support USB 3.0 or LAN wake-up, tie to 1.1V_S5					If USB 3.0 wake-up is supported, tie to 3.3V_S5
or HW Montior balls not used GPIO	otherwise, tie to 1.1V_S0					If no, tie to 3.3V_S0,
=> Decoupled cap not used						If no USB 3.0, tie to GND
HW Montior Not implemented
or HW Montior balls used as GPIO
=> Bead not used	1D2V_S5			1D2V_VPPL_SYS_S5
			DY
			L2020
		1		2
			Do Not Stuff
			Do Not Stuff		1	C2078
						Do Not Stuff
					DY
					2

3.3V CRT LDO

Current Limit=360mA

3D3V_VDDAN_DAC_S0_R

U2002

1

VIN

VOUT

5

0111: Remove R2023

2

VGA_PD_G 1 R2022 2 Do Not Stuff U2002_EN 3

GND

4

1

EN

NC#4

1

C2081

G9091-330T11U-GP

C2080

Do Not Stuff

74.09091.J3F

DY

2

SC1U6D3V2KXGP-

2

2nd = 74.09198.G7F

20100621 V1.2

2

			R2026
			10KR2J-3-GP
		Q2005
			1
18	VGA_PD	G
		D	VGA_PD_G
		S
		2N7002K-2-GP
		84.2N702.J31

2ND = 84.2N702.031

DQ15 AMD DIS SAMSUNG TI

							Wistron Corporation
							21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
							Taipei Hsien 221, Taiwan, R.O.C.
				Title
						HUDSON-M2 Power(4/6)
				Size		Document Number			Rev
				Custom		QUEEN AMD Muxless/UMA			X00
				Date:	Thursday, May 26, 2011		Sheet 20	of	104
5	4	3	2				1

D

C

B

A

5

4

3

2

1

SSID = S.B
D
	REQUIRED STRAPS				CRB: PU to 3.3V_AUX_S5
					Checklist: PU to 3.3V_S5
					Confrim with AMD, follow CRB suggestion
	3D3V_S0		3D3V_S5				3D3V_AUX_S5	REQUIRED SYSTEM STRAPS
									EC_PWM2	PCI_CLK1	RTC_CLK
									PCH GPO199
	1	1	1	1	1		1	PULL	LPC ROM	Allow	S5_PLUS Mode
	R2102	R2101	R2103	R2104	R2105		R2107	HIGH		PCIE GEN2
											DISABLE
	10KR2J-3-GP DYDo Not Stuff		DYDo Not Stuff	DYDo Not Stuff	10KR2J-3-GP		10KR2J-3-GP
									DEFAULT	DEFAULT	DEFAULT
	2	2	2	2	2		2
17	PCI_CLK1							PULL	SPI ROM	Force	S5_PLUS Mode
17,71	CLK_PCI_LPC							LOW		PCIE GEN1	ENABLE
17	PCI_CLK4
C
17,27	LPC_CLK0
17	LPC_CLK1
18 EC_PW M2
17	RTC_CLK
	1	1	1	1	1	1
	R2113	R2114	R2115	R2116	R2117		R2118
	DY Do Not Stuff	10KR2J-3-GP	10KR2J-3-GP	10KR2J-3-GP DYDo Not Stuff DYDo Not Stuff
	2	2	2	2	2	2

D

						Use this pin to determine INT/EXT CLK
	CLK_PCI_LPC		PCI_CLK4		LPC_CLK0		LPC_CLK1
	USE		non_Fusion		ENABLE EC		CLKGEN
	DEBUG						ENABLED
	STRAPS		CLOCK mode				(Use Internal)
							DEFAULT
	IGNORE		Fusion		DISABLE EC		CLKGEN
	DEBUG		CLOCK mode				DISABLED
	STRAPS				DEFAULT		(Use External)
	DEFAULT		DEFAULT

C

No Fusion Config, Strap Not needed, but reserve

DEBUG STRAPS

B

B

R2108		R2109		R2110		R2111		R2112
1		1		1		1		1

DYDYDYDYDY

2	2	2	2	2
Do Not Stuff	Do Not Stuff	Do Not Stuff	Do Not Stuff	Do Not Stuff

A

PCI_AD23	17		PCI_AD27	PCI_AD26	PCI_AD25	PCI_AD24	PCI_AD23
PCI_AD24	17
PCI_AD25	17
PCI_AD26	17		USE PCI	Disable ILA	USE FC	USE DEFAULT
PCI_AD27	17	PULL					Disable PCI
			PLL	AUTORUN	PLL	PCIE STRAPS
		HIGH					MEM BOOT
			(DEFAULT)	(DEFAULT)	(DEFAULT)	(DEFAULT)	(DEFAULT)
		PULL	BYPASS	Enable ILA	BYPASS FC	USE EEPROM	Enable PCI
			PCI PLL	AUTORUN	PLL	PCIE STRAPS	MEM BOOT
		LOW

Note: FCH has 15K internal PU FOR PCI_AD[27:23]

DQ15 AMD DIS SAMSUNG TI

A

		Wistron Corporation
		21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
		Taipei Hsien 221, Taiwan, R.O.C.
Title	SB820M_STRAPPING_(5/5)
Size	Document Number			Rev
A3	QUEEN AMD Muxless/UMA			X00
Date:	Thursday, May 26, 2011		Sheet 21 of	104

5

4

3

2

1

5

4

3

2

1

	A3
	A33
	B7
	B13
	D9
	D13
	E5
D	E12

E16

E29

F7

F9

F11

F13

F16

F17

F19

F23

F25

F29

G6

G16

G32

H12

H15

H29

J6

J9

J10

J13

J28

J32

K7

K16

K27

K28

C	L6
	L12
	L13
	L15
	L16
	L21
	M13
	M16
	M21
	M25
	N6
	N11
	N13
	N23
	N24
	P12
	P18
	P20
	P21
	P31
	P33
	R4
	R11
	R25
	R28
	T11
	T16
	T18

B

N8

K25

H25

A

FCH1D
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS	GROUND
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSSAN_HWM

VSSXL

VSSPL_SYS

71.HUDM2.M01

Part 4 of 5

VSS T25

VSS T27

VSS U6

VSS U14

VSS U17

VSS U20

VSS U21

VSS U30

VSS U32

VSS V11

VSS V16

VSS V18

VSS W4

VSS W6

VSS W25

VSS W28

VSS Y14

VSS Y16

VSS Y18

VSS AA6

VSS AA12

VSS AA13

VSS AA14

VSS AA16

VSS AA17

VSS AA25

VSS AA28

VSS AA30

VSS AA32

VSS AB25

VSS AC6

VSS AC18

VSS AC28

VSS AD27

VSS AE6

VSS AE15

VSS AE21

VSS AE28

VSS AF8

VSS AF12

VSS AF16

VSS AF33

VSS AG30

VSS AG32

VSS AH5

VSS AH11

VSS AH18

VSS AH19

VSS AH21

VSS AH23

VSS AH25

VSS AH27

VSS AJ18

VSS AJ28

VSS AJ29

VSS AK21

VSS AK25

VSS AL18

VSS AM21

VSS AM25

VSS AN1

VSS AN18

VSS AN28

VSS AN33

VSSPL_DAC T21

VSSAN_DAC L28

VSSANQ_DAC K33

VSSIO_DAC N28

EFUSE R6

DQ15 AMD DIS SAMSUNG TI

		Wistron Corporation
		21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
		Taipei Hsien 221, Taiwan, R.O.C.
Title
		Reserved
Size	Document Number				Rev
A3		QUEEN AMD Muxless/UMA			X00
Date:	Thursday, May 26, 2011		Sheet 22	of	104

D

C

B

A

5

4

3

2

1

5

4

3

2

1

D

D

C

C

B

B

A	A
	DQ15 AMD DIS SAMSUNG TI

						Wistron Corporation
						21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
						Taipei Hsien 221, Taiwan, R.O.C.
				Title
						Reserved
				Size	Document Number				Rev
				A3		QUEEN AMD Muxless/UMA			X00
5	4	3	2	Date:	Thursday, May 26, 2011		Sheet1 23	of	104

5

4

3

2

1

D

C

B

A

DQ15 AMD DIS SAMSUNG TI

		Wistron Corporation
		21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
		Taipei Hsien 221, Taiwan, R.O.C.
Title
		Reserved
Size	Document Number				Rev
A3		QUEEN AMD Muxless/UMA			X00
Date:	Thursday, May 26, 2011		Sheet 24	of	104

D

C

B

A

5

4

3

2

1

5

4

3

2

1

D

D

C

C

B

B

A	A
	DQ15 AMD DIS SAMSUNG TI

						Wistron Corporation
						21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
						Taipei Hsien 221, Taiwan, R.O.C.
				Title
						Reserved
				Size	Document Number				Rev
				A3		QUEEN AMD Muxless/UMA			X00
5	4	3	2	Date:	Thursday, May 26, 2011		Sheet1 25	of	104

5

4

3

2

1

D

C

B

A

DQ15 AMD DIS SAMSUNG TI

		Wistron Corporation
		21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
		Taipei Hsien 221, Taiwan, R.O.C.
Title
		Reserved
Size	Document Number				Rev
A3		QUEEN AMD Muxless/UMA			X00
Date:	Thursday, May 26, 2011		Sheet 26	of	104

D

C

B

A

5

4

3

2

1

D

C

B

A

5

4

3

0107: Change R2724 & R2726 from 5 % To 1 & Resistor tolerence.

		3D3V_AUX_KBC
		1	R2724	PCB VERSION A/D(PIN98)	PULL-LOW RESISTOR	PULL-HIGH RESISTOR	VOLTAGE
			47KR2F-GP	SA	100.0K	10.0K	3.0V
				SB	100.0K	20.0K	2.75V
		2
PCB_VER_AD				SC	100.0K	33.0K	2.48V
	2	1		-1	100.0K	47.0K	2.24V
C2717	DY		R2726	Reserved	100.0K	64.9K	2.0V
Do Not Stuff	1		100KR2F-L1-GP
				Reserved	100.0K	76.8	1.87V
		2
SSID = KBC				Reserved	100.0K	100.0K	1.65V
		EC_AGND
0628 Modify:
Move R2771 to closed 3D3V_AUX_KBC power
rail base on layout placement.

2

0107: POP C2718, R2739, Change To Voltage Divider ** BOM Control For R2710 Value.

Default R2710 10K = DQ15_UMA

3D3V_AUX_KBC
1	R2710	1	R2740	1	R2741
	Do Not Stuff		20KR2F-L-GP		Do Not Stuff

MODELID MODELID MODELID

MODEL_ID_DET		2	2	2
		1
	2		R2739
C2718			100KR2F-L1-GP
SCD1U10V2KX-5GP	1

2

EC_AGND

0702 Modify:

Defualt un-stuff R2739(internal PL in KBC)

		1
0107: Update Model_ID_DET
Table,
DQ15_AMD_UMA
DQ15_AMD_DIS (PX)
DN15_AMD_DIS (PX)
MODEL_ID_DET(GPIO07)	PULL-LOW RESISTOR	PULL-HIGH RESISTOR	VOLTAGE
DQ15_UMA	100.0K	10.0K(64.10025.6DL)	3.0V
DQ15_ATI	100.0K	20.0K(64.20025.6DL)	2.75V
DQ15_NVIDIA	100.0K	33.0K	2.48V
DN15_UMA	100.0K	47.0K(64.47025.6DL)	2.24V
DN15_ATI	100.0K	64.9K(64.64925.6DL)	2.0V
Reserved	100.0K	76.8K	1.87V
Reserved	100.0K	100.0K	1.65V
DN13_UMA	100.0K	143.0K	1.358V
DN13_ATI	100.0K	174.0K	1.204V
DQ15_Ventura	100.0K	215.0K	1.048V

3D3V_AUX_KBC

1

R2702

2

VBAT

1

Do Not Stuff

R2771

2D2R3-1-U-GP

0716: Vendor Suggestion

2

3D3V_AUX_KBC_VCC

C2701

C2704

1C2705

C2706

C2707

C2708

C2709

C2710

2 1

1GP-SC2D2U10V3KX 21

5GP-SCD1U10V2KX

DY

Stuff Not Do

2 1

5GP-SCD1U10V2KX

2 1

5GP-SCD1U10V2KX 21

5GP-SCD1U10V2KX

2 1

SC2D2U10V3KX

2 1

5GP-SCD1U10V2KX

2

U2701A

19 46 76 88

115

EC_AGND1GP-

VCC VCC VCC VCC VCC

40

AD_IA

104

VREF

EC_AGND

C2714 1

DY2

Do Not Stuff

97

GPIO90/AD0

PCB_VER_AD

98

GPIO91/AD1

82

PSID_EC

99

GPIO92/AD2

28

CPU_THRM

100

GPIO93/AD3

28

FAN1_DAC

101

GPIO94/DA0

105

49

LCD_TST

MEDIA_BTN2#

106

GPIO95/DA1

GPIO96/DA2

0107: Modify:

Remove ESATA_PWR_EN# In GPIO2

79

GPIO2

Add GPIO04 To USB_IO_CRT_EN#

57 USBCHARGER_CB0

95

96

GPIO3

0702 Modify:

57,82 USB_IO_CRT_EN#

108

GPIO4

Rename EC_GPIO6 to PSL_IN2

28

SYS_THRM

PSL_IN2

93

GPIO5

GPIO6

MODEL_ID_DET

94

0629 Modify:

114

GPIO7

Rename TP_LOCK_LED#&BATT_WHITE_LED# 68

BATT_WHITE_LED#

ECSMI#_KBC

6

GPIO16

69

CAP_LED

109

GPIO24

14

GPIO30

36

S5_ENABLE

15

GPIO34

82

MEDIA_BTN3#

80

GPIO36

39

BAT_IN#

17

GPIO41

Rename PM_SLP_S4# To PM_SLP_S5#

70

LID_CLOSE#

20

GPIO42/TCK

18

RSMRST#_KBC

21

GPIO43/TMS

18,44,75

PM_SLP_S5#

EC_SPI_WP#

23

GPIO44/TDI

60

EC_SPI_WP#

GPIO46/TRST#

26

0702 Modify:

82

RCID

PSL_IN1

73

GPIO51

Rename EC_GPIO70 to PSL_IN1

PSL_OUT

74

GPIO70

GPIO71

Rename EC_GPIO71 to PSL_OUT

EC_GPIO72

75

82

WIFI_RF_EN

82

GPIO72

83

GPIO75

63,82

BLUETOOTH_EN

84

GPO76/SHBM

36,46

1D1V_S5_PWRGD

91

GPIO77

68

TP_LOCK_LED#

110

GPIO81

57

USB_PWR_EN#

112

GPO82/TEST#

85

THERMTRIP_VGA_GATE

107

GPO84/XORTR#

0719: ADD

36,46

1D2V_S0_PWRGD

GPIO97

0604 Modify:

RN2704 pull-Low 10K Resistor to DY

KBC_VCORF

44

VCORF

on BLUETOOTH_EN.

1

C2712

KBC GPIO7 change to DISCRETE#

SC1U25V3KX-1-GP

GND GND GND GND GND GND

2

0706 Modify:

KBC GPIO97 change to IMVP_PWRGD.

NPCE795PA0DX-GP-U

18

45

78

89

116

5

0109: EMI Reserve, Place Near R2768

1122 Modify:

RSMRST#_KBC

Change To X5R Cap

2

0719 Modify:

EC2702

Reserved 0.1uF on all of ADC input pins base on

1

Do Not Stuff

NUVOTON feedback list.(C2717~C2721)

DY

3D3V_S0

1	C2702	1			C2703
	SCD1U10V2KX-5GP		DY		Do Not Stuff
2		2

102	4	1 OF 2
AVCC	VDD					C2711 1DY			2Do Not Stuff
		LRESET#		7	PLT_RST#_EC		1	R2735		2
		LCLK	2						Do Not Stuff
		LFRAME#		3	LPC_AD3
		LAD3	1
		LAD2	128		LPC_AD2
		LAD1	127		LPC_AD1
		LAD0	126		LPC_AD0
		SERIRQ	125
			8
	GPIO11/CLKRUN#		9		PANEL_BLEN
		GPIO65/SMI#	29		ECSCI#_KBC
		ECSCI#/GPIO54	124
	GPIO10/LPCPD#		123		ECSWI#_KBC
	GPIO67/PWUREQ#		121
		GPIO85/GA20	122
		KBRST#/GPIO86
GPIO52/PSDAT3/RDY#			27		AD_IA_HW2
GPIO50/PSCLK3/TDO			25
		GPIO27/PSDAT2	11		MEDIA_BTN1#
		GPIO26/PSCLK2	10
			71
		GPIO35/PSDAT1	72
		GPIO37/PSCLK1	70
		GPIO17/SCL1
			69
		GPIO22/SDA1	67
		GPIO73/SCL2
		GPIO74/SDA2	68
		GPIO23/SCL3	119		EC_ENABLE#_1
		GPIO31/SDA3	120
			24		PROCHOT_EC
		GPIO47/SCL4
			28
		GPIO53/SDA4		90	EC_SPI_CS#_C		1	R2736		2	33R2J-2-GP
		F_CS0#
			92		EC_SPI_CLK_C		1	R2719		2	33R2J-2-GP
		F_SCK	86		EC_SPI_DI_C		1	R2737		2	Do Not Stuff
		F_SDI/F_SDIO1
	F_SDIO/F_SDIO0		87		EC_SPI_DO_C		1	R2722		2	33R2J-2-GP

A_RST#	17,36			<-- Rename Netname For AMD
LPC_CLK0	17,21			<-- Need To Align With Intel Netname?
LPC_FRAME#	17,71
LPC_AD3	17,71
LPC_AD2	17,71
LPC_AD1	17,71
LPC_AD0	17,71
INT_SERIRQ	17
PM_CLKRUN#	17
PCH_TEMP_ALERT#			6,19 0702 Modify:
H_A20GATE	18				Rename CHARGE_LED# to CHG_AMBER_LED#
					Rename DC_BATFULL# to BATT_WHITE_LED#.
H_RCIN#	18
BLON_OUT	49				0107 Modify: Add AD_IA_HW2 GPIO For Charger
AD_IA_HW2 40
PCH_WAKE#	18			<-- Use For Lan Wake Up, Need SW Confirm
TPDATA	69	0716: Rename, ADD PCH_WAKE# To FCH
				<-- TP
TPCLK	69
BAT_SCL	39,40			<-- BATTERY / CHARGER
BAT_SDA	39,40
SML1_CLK		6,85		<-- CPU -Temp
SML1_DATA		6,85
PM_LAN_ENABLE 82
LCD_TST_EN 49
SPI_CS0#_R 60
SPI_CLK_R 60					EC_SPI_DI_C
SPI_SO_R	60
SPI_SI_R	60			1

0706 Modify:

KBC GPIO13 change to MEDIA_LED1#. KBC GPIO66 change to MEDIA_LED2#. KBC GPIO33 change to MEDIA_LED3#.

28	FAN_TACH1
18	PM_PWRBTN#
75,82	PCIE_WAKE#
18,36,44,46,75 PM_SLP_S3#
68	CHG_AMBER_LED#
29	KBC_BEEP
82	MEDIA_LED1#
69 KB_BL_CTRL
40	AD_IA_HW
82	MEDIA_LED3#
82	MEDIA_LED2#
68	PWRLED#
0914: Modify GPIO Pin
Modify KBC GPIO45 From PWR_BTN_LED# To MEDIA_LED2#		ECRST#
0629 Modify:Modify KBC GPIO66 From MEDIA_LED2# To AD_IA_HW
Rename PWRLED#&PWR_BTN_LED#&CHARGE_LED#
82	E51_RxD
82	E51_TxD
29	AMP_MUTE#
17	PCH_SUSCLK_KBC

					Layout Note:			R2773
			AGND		Locate resistors R2719 and R2722 close to the KBC.			100KR2J-1-GP
					0106 Modify:	2
		103			Update U2701A, U2701B Symbol
						0604 Modify:
					Layout Note:	Add Pull down 100k ohm at F_SDI for Power consumption concern.
			AGND		Connect GND and AGND planes via either			1027 Modify:
					0R resistor or one point layout connection.			Change R2075 PU From 3D3V_AUX_S5
			EC_
								3D3V_AUX_KBC
1	R2711	2
Do Not Stuff						1

	0106 Modify:
	Update U2701A, U2701B Symbol
	U2701B	2 OF 2			KCOL[0..16]	69
31	GPIO56/TA1	KBSOUT0/JENK#	53	KCOL0
117	GPIO20/TA2	KBSOUT1/TCK	52	KCOL1
63	GPIO14/TB1	KBSOUT2/TMS	51	KCOL2
64	GPIO01/TB2	KBSOUT3/TDI	50	KCOL3
			49	KCOL4
32		KBSOUT4/JEN0#	48	KCOL5
118	GPIO15/A_PWM	KBSOUT5/TDO	47	KCOL6
62	GPIO21/B_PWM	KBSOUT6/RDY#	43	KCOL7
65	GPIO13/C_PWM	KBSOUT7	42	KCOL8
81	GPIO32/D_PWM	KBSOUT8	41	KCOL9
66	GPIO66/G_PWM	KBSOUT9/SDP_VIS#	40	KCOL10
	GPIO33/H_PWM	KBSOUT10/P80_CLK
22	GPIO45/E_PWM	KBSOUT11/P80_DAT	39	KCOL11
16	GPIO40/F_PWM	KBSOUT12/GPIO64	38	KCOL12
		KBSOUT13/GPIO63	37	KCOL13
		KBSOUT14/GPIO62	36	KCOL14
85	VCC_POR#	KBSOUT15/GPIO61/XOR_OUT	35	KCOL15
		GPIO60/KBSOUT16	34	KCOL16
		GPIO57/KBSOUT17	33	USB_DET#	0716: Rename
113	GPIO87/SIN_CR				KROW[0..7]	69
111			54	KROW0
	GPO83/SOUT_CR/TRIST#	KBSIN0	55	KROW1
30		KBSIN1	56	KROW2
77	GPIO55/CLKOUT	KBSIN2	57	KROW3
	GPIO00/EXTCLK	KBSIN3	58	KROW4
		KBSIN4
For Intel Only		KBSIN5	59	KROW5
13	PECI	KBSIN6	60	KROW6
12	VTT	KBSIN7	61	KROW7
	NPCE795PA0DX-GP-U
to 3D3V_AUX_KBC
ECRST#

	C2719	Do Not Stuff
CPU_THRM	2	DY1
	C2720	Do Not Stuff
USB_IO_CRT_EN# 2		DY1
	C2721	Do Not Stuff
SYS_THRM	2	DY1

EC_AGND

				R2761
9 L_BKLT_EN			1		2		PANEL_BLEN
				Do Not	Stuff

			0702 Modify:
			Rename EC_GPIO6 to PSL_IN2
				PSL_IN2
		D2702
		1		1 R2704	2	330KR2J-L1-GP		EC_GPIO72
68	KBC_PWRBTN#	3
		2		KBC_ON#
		BAT54CPT-GP
		83.R2003.E81
		2ND = 83.00054.Q81
				D2703
				2
				10mW		3	AC_IN#		40
		AC_IN#_KBC		1
				BAT54CPT-GP

83.R2003.E81

2ND = 83.00054.Q81

			3D3V_AUX_KBC
USB_DET#	1	R2772	2100KR2J-1-GP
MEDIA_BTN2#	1	R2774	2100KR2J-1-GP	KBC_ON#_R
PCIE_WAKE#	1	R2776	2100KR2J-1-GP
			3D3V_AUX_KBC

EC_AGND

EC_GPIO47 High Active

R2705

10KR2J-3-GP

Q2702

1

D2701

PROCHOT_EC

G

R2733

2

E

18

EC_SWI#

1

DY

D

H_PROCHOT#_EC

1

2

H_PROCHOT#

6,40

28,36

PURE_HW_SHUTDOWN#

B

3

ECSWI#_KBC

R2732

Do Not Stuff

2

100KR2J-1-GP

S

0621 Modify:

C

2

Removed R2723

Do Not Stuff

2N7002K-2-GP

Do Not Stuff

84.2N702.J31

2ND = 83.00016.F11

2ND = 84.2N702.031

D2704

18

EC_SCI#

1

DY

PSL Solution

10mW Solution

ECSCI#_KBC

3

2

RTC_AUX_S5

3D3V_AUX_KBC

Do Not Stuff

R2756

Do Not Stuff

1

2

EC_GPIO72

1

R2734

2 Do Not Stuff

EC_GPIO72

2ND = 83.00016.F11

Do Not Stuff

DY

VBACKUP

0714 Modify:

Un-stuff D2701,D2704 and Add R2758,R2759

ohm confirm with NUVOTON and SW.

1 R2768

2 Do Not Stuff

R2763

40 PWR_CHG_ACOK

PSL_IN1

AC_IN#_KBC

1

2

PSL_IN1

18

EC_SWI#

1

R2758 2ECSWI#_KBC

PSL

0702 Modify:

Do Not Stuff

Do Not Stuff

Rename EC_GPIO70 to PSL_IN1

10mW

PSL_IN1

1

R2759 2ECSCI#_KBC

18

EC_SCI#

Do Not Stuff

Q2704

1

R2767

Do Not Stuff

KBC_ON#_R

3D3V_AUX_KBC

G

DY2

0909 Modify:

Q2705

D

KBC_ON#

De-Pop C2713 &

PSL_OUT

G

10mW

Add C2722 Soft Start To Solve Leakage Issue.

EC_ENABLE#_1

S

0702 Modify:

D

Rename EC_GPIO71 to PSL_OUT

2N7002K-2-GP

3D3V_AUX_S5

3D3V_AUX_S5

S

84.2N702.J31

C2722

PSL

1

2

Do Not Stuff

2ND = 84.2N702.031

- S

RN2706

Do Not Stuff

KBC_ON#

1

R2766

2

KBC_ON#_R

SCD1U10V2KX 5GP

3

2

2ND = 84.2N702.031

Do Not Stuff

4

1

KBC_ON#_GATE

G

Q2703

PSL_OUT

G

DMP2130L-7-GP

10mW

SRN10KJ-5-GP

1

84.02130.031

D

2ND = 84.03413.A31

PSL_IN1

DY

D

1

C2713

2

RN2704

Do Not Stuff

3D3V_AUX_KBC

PSL

R2769

MEDIA_BTN3#

3

2

Do Not Stuff

MEDIA_BTN1#

4

1

2

0625 Modify:

SRN100KJ-6-GP

Change R2769 dummy column for PSL solution.

Do Not Stuff

G

R2757

0109: Follow Intel, Need Confirm DQ/DN Spec

S5_ENABLE

1

2

D

DQ15

0R2J-2-GP

DY

Do Not Stuff

S

1

MEDIA_BTN1#

Q2706

INSTANT_ON#

Do Not Stuff

Do Not Stuff

82

INSTANT_ON#

3

2ND = 84.2N702.031

DN15

2ND = 83.00054.Q81

0712 Modify:

2

KBC_ON#_R

Add D2706 connect to MEDIA

BUTTON Instant_on#.

D2706

0928 Modify:

0713 Modify:

Add Q2706 2N7002 to avoid leakage loop from

Add R2772,D2707 for USBCHARGER

BAT54CPT-GP

3D3V_S5 to 3D3V_AUX_KBC issue when 10mW

DETECT Function.

1

USB_DET#

latched fail timing.

57

USBDET_CON#

USBDET_CON#

3

83.R2003.E81

2ND = 83.00054.Q81

2

KBC_ON#_R

D2707

PWR_CHG_ACOK

0109: EMI Reserve, Place Near R2768

BAT54CPT-GP

2

1MEDIA_BTN2#

DY

EC2701

DATA_RECOVERY#3

1

Stuff

82

DATA_RECOVERY#

83.R2003.E81

2ND = 83.00054.Q81

2

KBC_ON#_R

Not

D2708

Do

5

4

3

	1	C2715					D2705
Q2701		Do Not Stuff	18	EC_SMI#		1			3		ECSMI#_KBC
	2
MMBT3906-4-GP DY
84.T3906.A11						2
2nd = 84.03906.F11							BAS16-6-GP
							83.00016.K11
							2ND = 83.00016.F11
			18	EC_SMI#			1 R2760 2ECSMI#_KBC
							DY			Do Not Stuff
			EC GPIO standard PH/PL							3D3V_AUX_KBC

		RN2701
BAT_SDA	3		2
BAT_SCL	4		1
		SRN4K7J-8-GP
		RN2703
BAT_IN#	3		2
AC_IN#_KBC	4		1
0630 Modify:		SRN100KJ-6-GP
Removed LID_CLOSE#
PH 10K on RN2705.
		RN2705
EC_ENABLE#_1	4		1
S5_ENABLE	3	DY	2
		Do Not Stuff

	0623 Modify:	0628 Modify:
	Change RN2702 to R2712 10K 0402	Stuff R2712 and Removed R2805.
	Resistor on FAN_TACH1.
					3D3V_S0
28 FAN_TACH1	FAN_TACH1	1	R2712	2	10KR2J-3-GP
	E51_RxD	1	R2708	2	Do Not Stuff
				DY
	BLUETOOTH_EN	1	R2709	2	Do Not Stuff
				DY
	0604 Modify:		0623 Modify:
	RN2704 pull-Low 10K Resistor to DY		Change RN2704 to R2708 10K 0402
	on BLUETOOTH_EN.		Resistor on BLUETOOTH_EN.

				3D3V_AUX_KBC
ECRST#	1	R2713	2	10KR2J-3-GP

0628 Modify:

Stuff R2712 and Removed R2805.

0716: Modify

0111: Pop D2705, DY R2760

DQ15 AMD DIS SAMSUNG TI

					Wistron Corporation
					21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
					Taipei Hsien 221, Taiwan, R.O.C.
		Title
				KBC Nuvoton NPCE795
		Size		Document Number			Rev
		Custom		QUEEN AMD Muxless/UMA			X00
		Date:	Thursday, May 26, 2011			Sheet 27 of	104
2				1

D

C

B

A

5	4		3			2
1122 Modify:	3D3V_S0
ADJ&ADJ_VGA power source change to 3D3V_DAC_S0				3D3V_S0		3D3V_S0
from 3D3V_S0 to solve T8 shut down issue.			RSET = 0.0012T 2 — 0.9308T + 96.147
1123 Modify:	2
Co-lay 3D3V_DAC_S0 & 3D3V_S0 In Case LDO is Not Used		R2811	T=87 ; RSET=24.25ohm
0112: Remove R2811 ADJ 3D3V_AUX_KBC Pull High			1			1
	DY Do Not Stuff				R2805		R2828
	1				Do Not Stuff	DYDo Not Stuff

3D3V_S0

D

1

DY

2

R2808

Do Not Stuff

C

1 R2813 2 Do Not Stuff	R2801	U2804	2	2
	Do Not Stuff

1

C2802

1

DY

2

G709_SET

1

SET

DY

VCC

5

G709_VCC

DY

87.1 Degree

2

GND

ADJ

THERM_SYS_SHDN#

1

2

G709_OUT#

3

HYST

4

G709_HYSY

1

2

R2820

OUT#

SCD1U10V2KX-5GP

1

Do Not Stuff

1

R2829

1C2805

Do Not Stuff

C2816

o Not Stuff

R2804

DY

Do Not Stuff

Do Not Stuff

DY

Hysterisis:

DY

DY

DY

10°C for HYST = V CC

Do Not Stuff

Do NotStuff

2

2

2

2°C for HYST = GND

Layout notice :

2

Both DXN and DXP routing 10 mil

trace width and 10 mil spacing.

1027 Modify: Add Extra T8 Incase P2800 Don't Work Properly

0105 Modify:

1122 Modify: Add R2829 0 Ohm To GND, DY R2828 Change Power

P2800_DXP

U2801

Change P2800 To EB0 Version

rail to 3D3V_S0, Change R2805 Power Rail From 3D3V_S0 To 3D3V_DAC_S0,

2ND = 84.03904.P11

Change R2801 Resistor Value From 18K to 24.3K.

1

0115: Use P2800EB0 As Pure Hardware Shutdown, DY R2820, Pop R2806

3

84.03904.L06

C2806

5

4

Q2801

VCC

TDR

SYS_THRM

27

1

2

SC470P50V3JN-2GP

C2807

6

3

PMBS3904-1-GP

2

SC2200P50V2KX-2GP

7

DXP

TDL

2

CPU_THRM

27

DXN

GND

2

P2800_DXN

THERM_SYS_SHDN#_OTZ8

OTZ

ADJ

1

ADJ

2.System Sensor, Put on palm rest

P2800EB0-GP

0117 Modify:

1.H/W T8 Shutdown

Vendor Suggest, But will reserve first only, Place Near KBC is OK

SYS_THRM

2

CPU_THRM

2

0906 X01 Modify:

R2812

R2814

Change U2801,U2803 to 74.02800.A71 from

470KR2J-2-GP

470KR2J-2-GP

3D3V_AUX_S5

74.02800.071 from vender updated parts.

Change R2803&R2817 to 107K from 499K,

1

1

3D3V_S0

R2804&R2818 to 226K from 102K base on

THERM_SYS_SHDN#_OTZ 1 R2806

2

Do Not Stuff

updated ADJ Table.

3

1

D2801

R2831

Do Not Stuff

100KR2J-1-GP

DY

Do Not Stuff

Q2805

2ND = 83.BAT54.D81

2

1

2

3rd = 83.BAT54.S81

S

THERM_SYS_SHDN#

27,36 PURE_HW_SHUTDOWN#

D

1

G

Q2805_G

1 R2810

2 Do Not Stuff

1

C2811

3D3V_S0

DY R2818

DY Do Not Stuff

2N7002K-2-GP

Do Not Stuff

2

84.2N702.J31

2

2ND = 84.2N702.031

1122 Modify: AddR2806

B	1213 Modify: Remove Dimm Thermal Function
	0107: Remove VGA P2800, SW Does Not Use

A

5

4

3

2

1

Fan controller P2793

U2802

R2802

1 DY

2 FON#

1

FON#

GND

8

Do Not Stuff

2

7

5V_S0

FAN_VCC

3

VIN

GND

6

27

FAN1_DAC

4

VO

GND

5

*Layout* 10 mil

VSET

GND

For linear FAN

G991P11U-GP

74.00991.031

2nd = 74.02793.A31

3rd = 74.05606.071

0819 X01 Modify:

0921:Modify

Re-assign FAN1 pin define from Niki suggestion.

Add AFTP, Follow DQ15 Intel

Pin1 : VCC;Pin2 : Ground;Pin3 : TACH

0823 X01 Modify:

Change U2802 Main source to 74.00991.031

2nd 74.02793.A31,3rd 74.05606.071

AFTP2801

1FAN_TACH1_C

0831 X01 Modify:

Change FAN1 to 20.F0772.003 from 20.F1639.004

AFTP2802

1FAN_VCC

base on ME Double updated.

5V_S0

1			1
	C2803			C2804
2		SC4D7U6D3V3KX-GP	2		SCD1U10V2KX-5GP

D

0906: Follow DQ15 Intel, Modify Fan1 Connector, Pin Define Changed 1122: Add 2nd 20.F1841.003 on FAN1 from ME updated connector list.

0105: Update DQ15 AMD Fan1 Connector To 4 Pin P/N 20.F1621.004, AMD Different To Intel

FAN2

6

4

27

FAN_TACH1

1 R2807

2

Do Not Stuff

FAN_TACH1_C

3

2

*Layout* 15 mil FAN_VCC

1

2

5

1

1

D2802 1

ACES-CON4-17-GP-U

C2808

C2809

DY C2810

20.F1621.004

EMI/ESD

StuffNotDo

DY2

2

-SC4D7U6D3V3KXGP

1

2

StuffNotDo

20.F1561.004

1

CH551H-30PT-GP

83.R5003.C8F

C

FAN_VCC

2ND = 83.R5003.H8H

3rd = 83.5R003.08F

EC2801

DY

Stuff2

NotDo

B

A

DQ15 AMD DIS SAMSUNG TI

		Wistron Corporation
		21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
		Taipei Hsien 221, Taiwan, R.O.C.
Title
	Thermal/Fan Controllor EMC2102
Size	Document Number			Rev
Custom	QUEEN AMD Muxless/UMA			X00
Date:	Friday, May 27, 2011	Sheet 28	of	104
		1

5

4

SSID = AUDIO

0913 X01 Modify:

Add R2920,R2921 and reserved EC2901,EC2902 on

AUD_DMIC_CLK &AUD_DMIC_IN0 for EMC suggestion.

0105 Modify:

EMI Request R2920, R2921 Place Near LCD1 Connector.

Move EC2901 EC2902 to P.49 and place after R2920, R2921

0105 Modify:

Vendor Suggest To Change R2920 To 33 Ohm

For EMI

AUD_DMIC_CLK

AUD_SPK_R+

AUD_SPK_R+ 58

5V_S0

+PVDD

AUD_DMIC_IN0

AUD_SPK_R-

AUD_SPK_L-

AUD_SPK_R-

58

+AVDD

1

1

AUD_SPK_L+

AUD_SPK_L58

AMP_MUTE#

+PVDD

AUD_SPK_L+

58

EC2901

EC2902

27 AMP_MUTE#

+AVDD

1

2

R2902 Do Not Stuff

C2909 SC1U10V2KX-1GP

0304 Modify:

2

2

SC22P50V2JN-4GP

AUD_DVDDCORE

41 40

39

38

37

36 35

34

33 32 31

1 2

C2905

SCD1U10V2KX-5GP

2 1

C2906

SC1U10V2KX-1GP

1 2

C2908 SCD1U10V2KX-5GP

2 1

2 1

C2910 SC10U6D3V5MX-3GP

SC22P50V2JN-4GP

Close to codec

AUD_AGND

EMI Suggest To Pop EC2901, EC2902 22P

U2901

AUD_AGND

1

AUD_AGND

to LVDS pin define.

2

C2901

PADTHERMAL EAPD PVDD

+RPORTD

RPORTD-

PVSS PORTDL- +LPORTD

PVDD AVDD2

5VVREG/+2

2

C2914

SC10U6D3V5MX-

3GP

0625 Modify:

PUMP_CAPP

CLOSE TO CODEC

AUD_DMIC_CLK&AUD_DMIC_IN0 connector

R2920

222R2J-2-GP AUD_DMIC_CLK_

R

1

DVDD_LV

CAP+

30

PUMP_CAPN

1

SC2D2U10V3KX-1GP

49 AUD_DMIC_CLK

1

2

DMIC_CLK/GPIO_1

CAP-

29

3D3V_S0

49 AUD_DMIC_IN0

1 R2921

222R2J-2-GP AUD_DMIC_IN0_R

3

DMIC_0/GPIO_2

V-

28

AUD_V_B

18 HDA_CODEC_SDOUT

HDA_CODEC_SDOUT

4

SDATA_OUT

AVSS2

27

HDA_CODEC_BITCLK

5

26

AUD_HP1_JACK_R

R2906

1

2

60D4R2F-GP

Close to codec

18 HDA_CODEC_BITCLK

1R2901

2HDA_CODEC_SDIN0

6

BITCLK

PORTB_R

25

AUD_HP1_JACK_L

R2905

1

2

60D4R2F-GP

AUD_HP1_JACK_R2 82

18

HDA_SDIN0

33R2J-2-GP

7

SDATA_IN

PORTB_L

24

AUD_HP1_JACK_L2 82

DVDD

AVSS2

AUD_AGND

18 HDA_CODEC_SYNC

HDA_CODEC_SYNC

8

SYNC

71.92H87.A03

PORTA_R

23

AUD_EXT_MIC_R

C2922

2

1

SC1U10V3KX-3GP

MIC_IN_R 82

18

HDA_CODEC_RST#

HDA_CODEC_RST#

9

RESET#

PORTA_L

22

AUD_EXT_MIC_L

C2921

2

1

SC1U10V3KX-3GP

MIC_IN_L

82

2 1

C2903 SC1U6D3V2KX-GP

1 2

C2904 SCD1U10V2KX-5GP

1 2

C2902

SCD1U10V2KX-5GP

AUD_PC_BEEP

10

PCBEEP

ASENSE BSENSE

LPORTF

RPORTF

LPORTC RPORTC VREFFILT

CAP2 VREFOUTA

AVDD1

21

+AVDD

VREFOUTC

Put C2921 and C2922 close to codec

0707 Modify:

updated U2901 part number from data base.

92HD87B1A5NDGXTBX8-GP

11

12

13

14

15

16

17

18

19

20

2010/06/30 Change to 92HD87 (71.92H87.A03)

3

2

1

ANNIE Audio solution

5V_S0

12

R2903 Do Not Stuff

12

R2904 Do Not Stuff

D

C

3D3V_S0

		1		R2908
				10KR2J-3-GP
		2					AMP_MUTE#
							AUD_VREFOUT_B
		1	1				HDA_CODEC_BITCLK
	C2923							C2907
					DY
SC1U10V2KX-1GP		2	2					Do Not Stuff
B
Azalia I/F EMI
	HDA_CODEC_SDOUT							1			R2912
								DY Do Not Stuff
								2	AZPCH
								_
								_	SDOUT1 CODEC_
								1			C2920
							DY
								2			Do Not Stuff
A

	AUD PC BEEP	AUD VREFFLT

						120KR2J-L-GP
						R2909
AUD_PC_BEEP	C2912	2	1	SCD1U10V2KX-5GP	SB_SPKR_R	1	2
AUD_PC_BEEP	C2913	2	1	SCD1U10V2KX-5GP	KBC_BEEP_R	1	2
Trace width>15 mils						470KR2J-2-GP
						R2910

	+AVDD
	1
		R2915
		2K49R2F-GP
AUD_SENSE_A	2
	1
		C2919
	2	SC1000P50V3JN-GP-U

AUD_AGND

	R2913
1	2	AUD_HP1_JD#	82
20KR2F-L-GP
	R2919
2	1	EXT_MIC_JD#	82

39K2R2F-L-GP

Close to Pin13

5

AUD_CAP2

AUD_VREFFLT

Remove Annie Audio

AUD_V_B

AUD_VREG

SC4D7U6D3V3KX-GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC1U6D3V2KX-GP

From SB

2 1

C2917

2 1

C2918

2 1

C2915

2 1

C2916

HDA_SPKR

18

KBC_BEEP

27

0707 Modify:

AUD_AGND

AUD_AGND

AUD_AGND

AUD_AGND

Change R2911,R2914,R2917 change

From EC

Close to codec

to 0ohm 0603 from short pad.

R2911

2

1 0R3J-0-U-GP

B

		R2914
	2	1 0R3J-0-U-GP
		R2917
	2	1 0R3J-0-U-GP
		AUD_AGND
	+AVDD
	1
	R2916
	2K49R2F-GP
	0715: Move To MB
AUD_SENSE_B	2
	1	MIC IN
	R2918
	20KR2F-L-GP
	2	AUD_VREFOUT_B

AUD_AGND

Close to Pin14

0109: EMI Reserve, Place Near R2918

2	AUD_SENSE_B
		EC2903
DY
1		Do Not Stuff
AUD_AGND

21

RN2901

SRN4K7J-8-GP

34

82 MIC_IN_L

82 MIC_IN_R

A

DQ15 AMD DIS SAMSUNG TI

			Wistron Corporation
			21F, 88, Sec.1, Hs in Tai Wu Rd., Hs ichih,
			Taipei Hs ien 221, Taiwan, R.O.C.
Title
		Audio Codec 92HD79B1
Size		Docum ent Num ber		Rev
Cus	tom	QUEEN AMD Muxless/UMA		X00
Date:	Thurs day, May 26, 2011		Sheet 29 of	104

4

3

2

1

5

4

3

2

1

AUDIO OP AMPLIFIER

D

C

B

A

DQ15 AMD DIS SAMSUNG TI

		Wistron Corporation
		21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
		Taipei Hsien 221, Taiwan, R.O.C.
Title
		AMP
Size	Document Number				Rev
A3		QUEEN AMD Muxless/UMA			X00
Date:	Thursday, May 26, 2011		Sheet 30	of	104

D

C

B

A

5

4

3

2

1