Wistron JE40-HR, Aspire 4750, Aspire 4750G, Aspire 4750Z, Aspire 4752 Schematic

5

4

3

2

1

JE40 HR

DIS/UMA/Muxless Schematics Document

D D

Sandy Bridge

Intel PCH

C C

DY :None Installed DIS:DIS installed DIS_Muxless :BOTH DIS or Muxless installed DIS_PX:BOTH DIS or PX installed

ANNIE: ONLY FOR ANNIE solution. PSL: KBC795 PSL circuit for 10mW solution installed. 10mW: External circuit for 10mW solution installed. 65W: for 65W adaptor installed. 90W: for 90W adaptor installed.

DIS_PX_Muxless:DIS or PX or Muxless installed. Muxless: Muxless installed.(PX4.0) PX:MUX installed.(PX3.0) PX_Muxless:BOTH PX or Muxless installed.

B B

UMA:UMA installed UMA_Muxless:BOTH UMA or Muxless installed UMA_PX_Muxless:UMA or PX or Muxless installed

HR UMA

A A

5

4

3

2

HR UMA

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Thursday, December 02, 2010

Date: Sheet of

Date: Sheet

Cover Page

JE40-HR

of

1 102

1

-1

5

##OnMainBoard

VRAM

D D

2GB/1GB/512MB

88,89,90,91

DDR3 800MHz

Nvidia N12P

83.84,85,86,87

Discreet/UMA/PX Co-lay

C C

HDMI

LCD

B B

HP1

MIC IN

A A

2CH SPEAKER

51

49

Left Side: USB x 1

Bluetooth

CAMERA

Internal Analog MIC

5

63

49

64

RGB CRT

CRT

LVDS(Dual Channel)

50

USB2.0 x 4

Azalia CODEC

ALC271X

4

3

JE40 HR Block Diagram (Discrete/UMA/co-lay)

Project code : 91.4IQ01.001 PCB P/N : 48.4IQ01.0SA Revision : 10267-1

DDRIII 1066/1333 Channel A

DDRIII 1066/1333 Channel B

PCIE x 1,USB x 1

USB 2.0 x 1

SATA x 2

LPC debug port

SMBus

3

Thermal

ENE P2800 ENE P2793

71

Fan

2869 2569

(Discrete only)

HDMI

Level shifter

AZALIA

29

4

PCIe x 16

FDIx4x2 (UMA only)

57

Intel CPU

Sandy Bridge FSB: 1066 MHz

4,5,6,7,8,9,10,11,12,13

DMIx4

Intel

PCH Cougar Point

14 USB 2.0/1.1 ports

ETHERNET (10/100/1000Mb)

High Definition Audio

SATA ports (6) PCIE ports (8)

LPC I/F ACPI 1.1

17,18,19,20,21,22,23,24,25,26

SPI

Flash ROM

4MB

Touch PAD

LPC Bus

60

KBC

NUVOTON

NPCE795P

27

Int. KB

DDRIII 1066/1333

PCIE x 1 USB x 2

PCIE x 1 USB x 1

PCIE x 1

2

Slot 0

Slot 1

14

15

USB3.0

uPD720200

Mini-Card

802.11a/b/g

1000 NIC

BCM57780A1

Mini-Card

WWAN

Right Side: USB x 1

SYSTEM DC/DC

APL5916KAI

INPUTS

1D05V_PWR

75

65

RJ45 CONN

31

SD/MMC+/MS/ MS Pro/xD

66 66

48

OUTPUTS

0D85V_S0

59

SIM

1

CPU DC/DC

NCP6131S52MNR

INPUTS

DCBATOUT

OUTPUTS

VCC_CORE

SYSTEM DC/DC

UP6128PQDD

INPUTS

DCBATOUT

OUTPUTS

1D05V_VTT

SYSTEM DC/DC

UP6183PQAG

INPUTS

DCBATOUT 5V_S5

OUTPUTS

5V_AUX_S5 3D3V_AUX_S5

3D3V_S5

SYSTEM DC/DC

UP6165BQKF

INPUTS

DCBATOUT

OUTPUTS

1D5V_S3 0D75V_S0 DDR_VREF_S3

SYSTEM DC/DC

NCP5911MNTBG

INPUTS

DCBATOUT

OUTPUTS

VCC_GFXCORE_PWR

VGA

RT8208BGQW

INPUTS

DCBATOUT

OUTPUTS

VGA_CORE

TI CHARGER

BQ24745RHDR

INPUTS

DCBATOUT

26

SYSTEM DC/DC

OUTPUTS

BT+

RT9025

INPUTS

3D3V_S0

OUTPUTS

1D8V_S0

SYSTEM DC/DC

RT9025-25PSP

INPUTS OUTPUTS

26

1D5V_S3 1V_VGA_S0 3D3V_S5

1D8V_VGA_S0

42~43

45

41

46

44

92

40

47

93

Switches

HDD

56

ODD

56

HR UMA

Title

Size Document Number Rev

28

2

Size Document Number Rev A3

A3

Thursday, December 02, 2010

Date: Sheet

Block Diagram

JE40-HR

INPUTS OUTPUTS

1D5V_S3

1D5V_VGA_S0 3D3V_VGA_S03D3V_S0

PCB LAYER

L1:Top L2:VCC L3:Signal

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

L4:Signal L5:GND L6:Bottom

of

2 102

-1

A

PCH Strapping

Name Schematics Notes

SPKR

INIT3_3V# GNT3#/GPIO55

4 4

GNT2#/GPIO53 GNT1#/GPIO51

SPI_MOSI

NV_ALE

NC_CLE

HAD_DOCK_EN# /GPIO[33]

3 3

HDA_SDO HDA_SYNC

GPIO15

GPIO8

2 2

GPIO27

Reboot option at power-up

Internal weak Pull-down.

Default Mode:

Connect to Vcc3_3 with 8.2-kȍ

No Reboot Mode with TCO Disabled:

- 10-kȍ weak pull-up resistor. Weak internal pull-up. Leave as "No Connect". GNT[3:0]# functionality is not available on Mobile.

Mobile: Used as GPIO only Pull-up resistors are not required on these signals. If pull-ups are used, they should be tied to the Vcc3_3power rail.

Enable Danbury:

Disable Danbury:

Enable Danbury:

Disable Danbury:

DMI termination voltage. Weak internal pull-up. Do not pull low. Low (0) - Flash Descriptor Security will be overridden. Also,

when this signals is sampled on the rising edge of PWROK then it will also disable Intel ME and its features. High (1) - Security measure defined in the Flash Descriptor will be enabled. Platform design should provide appropriate pull-up or pull-down depending on the desired settings. If a jumper option is used to tie this signal to GND as required by the functional strap, the signal should be pulled low through a weak pull-down in order to avoid asserting HDA_DOCK_EN# inadvertently. Note: CRB recommends 1-kohm pull-down for FD Override. There is an internal pull-up of 20 kohm for DA_DOCK_EN# which is only enabled at boot/reset for strapping functions.

Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#. Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#. Low (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with no

confidentiality High (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with confidentiality Note : This is an un-muxed signal. This signal has a weak internal pull-down of 20 kohm which is enabled when PWROK is low. Sampled at rising edge of RSMRST#. CRB has a 1-kohm pull-up on this signal to +3.3VA rail.

GPIO8 on PCH is the Integrated Clock Enable strap and is required to be pulled-down using a 1k +/- 5% resistor. When this signal is sampled high at the rising edge of RSMRST#, Integrated Clocking is enabled, When sampled low, Buffer Through Mode is enabled.

Default = Do not connect (floating)

High(1) = Enables the internal VccVRM to have a clean supply for analog rails. No need to use on-board filter circuit. Low (0) = Disables the VccVRM. Need to use on-board filter circuits for analog rails.

Huron River Schematic Checklist Rev.0_7

Connect to Vcc3_3 with 8.2-k? weak pull-up resistor.

Left floating, no pull-down required.

Connect to +NVRAM_VCCQ with 8.2-kohm weak pull-up resistor [CRB has it pulled up with 1-kohm no-stuff resistor]

Leave floating (internal pull-down)

B

C

Processor Strapping

Pin Name Strap Description Configuration (Default value for each bit is

CFG[2]

PCI-Express Static Lane Reversal

CFG[4]

CFG[6:5]

CFG[7]

POWER PLANE

5V_S0 3D3V_S0 1D8V_S0 1D5V_S0 1D05V_VTT 0D85V_S0 0D75V_S0 VCC_CORE VCC_GFXCORE 1D8V_VGA_S0 3D3V_VGA_S0 1V_VGA_S0

5V_USBX_S3 1D5V_S3 DDR_VREF_S3

BT+ DCBATOUT 5V_S5 5V_AUX_S5 3D3V_S5 3D3V_AUX_S5

3D3V_AUX_KBC

3D3V_AUX_S5

PCI-Express Port Bifurcation Straps

PEG DEFER TRAINING

VOLTAGE

5V

3.3V

1.8V

1.5V

1.05V

0.95 - 0.85V

0.75V

0.35V to 1.5V

0.4 to 1.25V

1.8V

3.3V 1V

5V

1.5V

0.75V

6V-14.1V 6V-14.1V 5V 5V

3.3V

3.3V3D3V_LAN_S5

3.3V

1 unless specified otherwise)

1:

Normal Operation. Lane Numbers Reversed 15 -> 0, 14 -> 1, ...

0:

Disabled - No Physical Display Port attached to

1:

Embedded DisplayPort. Enabled - An external Display Port device is

0:

connectd to the EMBEDDED display Port

11 : x16 - Device 1 functions 1 and 2 disabled 10 : x8, x8 - Device 1 function 1 enabled ; function 2 disabled 01 : Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00 : x8, x4, x4 - Device 1 functions 1 and 2 enabled

1:

PEG Train immediately following xxRESETB de assertion PEG Wait for BIOS for training

0:

Voltage Rails

ACTIVE IN

S0

S3

All S states

WOL_EN

DSW, Sx ON for supporting Deep Sleep states

G3, Sx

D

Huron River Schematic Checklist Rev.0_7

DESCRIPTION

CPU Core Rail Graphics Core Rail

AC Brick Mode only

Legacy WOL

Powered by Li Coin Cell in G3 and +V3ALW in Sx

Default Value

1

0

11

1

E

USB Table

Pair

PCIE Routing

0 1

LANE1 Mini Card2(WWAN) LANE2 LANE3 Card Reader LANE4

1 1

LANE5 LANE6 LANE7 LANE8 New Card

Mini Card1(WLAN)

Onboard LAN

USB3.0

Intel GBE LAN

Dock

SATA Table

SATA

Pair

0 1 2 3 4 5

Device

HDD1 HDD2

N/A N/A

ODD

ESATA

2 3 4 5 6 7 8 9 10 11 12 13

Device Touch Panel / 3G SIM USB Ext. port 1 (HS)

Fingerprint

BLUETOOTH Mini Card2 (WWAN) CARD READER X X

USB Ext. port 4 / E-SATA /USB CHARGER

USB Ext. port 2 EDP CAMERA Mini Card1 (WLAN) CAMERA

New Card

SMBus ADDRESSES

2

I C / SMBus Addresses

Device

EC SMBus 1 Battery CHARGER

EC SMBus 2 PCH eDP

PCH SMBus SO-DIMMA (SPD) SO-DIMMB (SPD) Digital Pot G-Sensor MINI

HURON RIVER ORB

Address Hex Bus Ref Des

BAT_SCL/BAT_SDA BAT_SCL/BAT_SDA BAT_SCL/BAT_SDA

SML1_CLK/SML1_DATA SML1_CLK/SML1_DATA SML1_CLK/SML1_DATA

PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK

HR UMA

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Thursday, December 02, 2010

Date: Sheet of

Date: Sheet

Table of Content

JE40-HR

3102

of

-1

A

SSID = CPU

5

D D

C C

B B

NOTE. Processor strap CFG[4] should be pulled low to enable Embedded DisplayPort.

Note: Intel DMI supports both Lane Reversal and polarity inversion but only at PCH side. This is enabled via a soft strap.

Note: Intel FDI supports both Lane Reversal and polarity inversion but only at PCH side. This is enabled via a soft strap.

Note: Lane reversal does not apply to FDI sideband signals.

1D05V_VTT

Signal Routing Guideline: EDP_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils. EDP_COMPIO keep W/S=4/15 mils and routing length less than 500 mils.

DMI_TXN[3:0]19

DMI_TXP[3:0]19

DMI_RXN[3:0]19

DMI_RXP[3:0]19

FDI_TXN[7:0]19

FDI_TXP[7:0]19

R402 24D9R2F-L-GPR402 24D9R2F-L-GP

1 2

R403 10KR2J-3-GPR403 10KR2J-3-GP

1 2

JE40 delete eDP function

4

CPU1A

CPU1A SANDY

SANDY

62.10055.421

62.10055.421 Change:62.10053.611

Change:62.10053.611 2nd = 62.10055.321

2nd = 62.10055.321 3rd = 62.10040.821

3rd = 62.10040.821

SANDY

DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3

DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3

DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3

DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3

FDI_TXN0 FDI_TXN1 FDI_TXN2 FDI_TXN3 FDI_TXN4 FDI_TXN5 FDI_TXN6 FDI_TXN7

FDI_TXP0 FDI_TXP1 FDI_TXP2 FDI_TXP3 FDI_TXP4 FDI_TXP5 FDI_TXP6 FDI_TXP7

FDI_FSYNC019 FDI_FSYNC119

FDI_INT19 FDI_LSYNC019

FDI_LSYNC119

DP_COMP eDP_HPD

B27 B25 A25 B24

B28 B26 A24 B23

G21 E22 F21 D21

G22 D22 F20 C21

A21 H19 E19 F18 B21 C20 D18 E17

A22 G19 E20 G18 B20 C19 D19 F17

H20

H17

A18 A17 B16

C15 D15

C17 F16 C16 G15

C18 E16 D16 F15

J18 J17

J19

DMI_RX#0 DMI_RX#1 DMI_RX#2 DMI_RX#3

DMI_RX0 DMI_RX1 DMI_RX2 DMI_RX3

DMI_TX#0 DMI_TX#1 DMI_TX#2 DMI_TX#3

DMI_TX0 DMI_TX1 DMI_TX2 DMI_TX3

FDI0_TX#0 FDI0_TX#1 FDI0_TX#2 FDI0_TX#3 FDI1_TX#0 FDI1_TX#1 FDI1_TX#2 FDI1_TX#3

FDI0_TX0 FDI0_TX1 FDI0_TX2 FDI0_TX3 FDI1_TX0 FDI1_TX1 FDI1_TX2 FDI1_TX3

FDI0_FSYNC FDI1_FSYNC

FDI_INT FDI0_LSYNC

FDI1_LSYNC

EDP_COMPIO EDP_ICOMPO EDP_HPD

EDP_AUX EDP_AUX#

EDP_TX0 EDP_TX1 EDP_TX2 EDP_TX3

EDP_TX#0 EDP_TX#1 EDP_TX#2 EDP_TX#3

SANDY

DMI

Intel(R) FDI

eDP

3

Signal Routing Guideline: PEG_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils. PEG_ICOMPI & PEG_RCOMPO keep W/S=4/15 mils and routing length less than 500 mils.

1 OF 9

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#0 PEG_RX#1 PEG_RX#2 PEG_RX#3 PEG_RX#4 PEG_RX#5 PEG_RX#6 PEG_RX#7 PEG_RX#8

PEG_RX#9 PEG_RX#10 PEG_RX#11 PEG_RX#12 PEG_RX#13 PEG_RX#14 PEG_RX#15

PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8

PEG_RX9 PEG_RX10 PEG_RX11 PEG_RX12 PEG_RX13 PEG_RX14 PEG_RX15

PEG_TX#0 PEG_TX#1 PEG_TX#2 PEG_TX#3 PEG_TX#4 PEG_TX#5 PEG_TX#6 PEG_TX#7 PEG_TX#8 PEG_TX#9

PEG_TX#10 PEG_TX#11

PCI EXPRESS* - GRAPHICS

PEG_TX#12 PEG_TX#13 PEG_TX#14 PEG_TX#15

PEG_TX0

PEG_TX1

PEG_TX2

PEG_TX3

PEG_TX4

PEG_TX5

PEG_TX6

PEG_TX7

PEG_TX8

PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15

J22 J21 H22

K33 M35 L34 J35 J32 H34 H31 G33 G30 F35 E34 E32 D33 D31 B33 C32

J33 L35 K34 H35 H32 G34 G31 F33 F30 E35 E33 F32 D34 E31 C33 B32

M29 M32 M31 L32 L29 K31 K28 J30 J28 H29 G27 E29 F27 D28 F26 E25

M28 M33 M30 L31 L28 K30 K27 J29 J27 H28 G28 E28 F28 D27 E26 D25

PEG_IRCOMP_R

PEG_RXN15 PEG_RXN14 PEG_RXN13 PEG_RXN12 PEG_RXN11 PEG_RXN10 PEG_RXN9 PEG_RXN8 PEG_RXN7 PEG_RXN6 PEG_RXN5 PEG_RXN4 PEG_RXN3 PEG_RXN2 PEG_RXN1 PEG_RXN0

PEG_RXP15 PEG_RXP14 PEG_RXP13 PEG_RXP12 PEG_RXP11 PEG_RXP10 PEG_RXP9 PEG_RXP8 PEG_RXP7 PEG_RXP6 PEG_RXP5 PEG_RXP4 PEG_RXP3 PEG_RXP2 PEG_RXP1 PEG_RXP0

PEG_C_TXN15 PEG_C_TXN14 PEG_C_TXN13 PEG_C_TXN12 PEG_C_TXN11 PEG_C_TXN10 PEG_C_TXN9 PEG_C_TXN8 PEG_C_TXN7 PEG_C_TXN6 PEG_C_TXN5 PEG_C_TXN4 PEG_C_TXN3 PEG_C_TXN2 PEG_C_TXN1 PEG_C_TXN0

PEG_C_TXP15 PEG_C_TXP14 PEG_C_TXP13 PEG_C_TXP12 PEG_C_TXP11 PEG_C_TXP10 PEG_C_TXP9 PEG_C_TXP8 PEG_C_TXP7 PEG_C_TXP6 PEG_C_TXP5 PEG_C_TXP4 PEG_C_TXP3 PEG_C_TXP2 PEG_C_TXP1 PEG_C_TXP0

R401

1 2

24D9R2F-L-GP

C401 Do Not Stuff

C401 Do Not Stuff C402 Do Not Stuff

C402 Do Not Stuff C403 Do Not Stuff

C403 Do Not Stuff C404 Do Not Stuff

C404 Do Not Stuff C405 Do Not Stuff

C405 Do Not Stuff C406 Do Not Stuff

C406 Do Not Stuff C407 Do Not Stuff

C407 Do Not Stuff C408 Do Not Stuff

C408 Do Not Stuff C409 Do Not Stuff

C409 Do Not Stuff C410 Do Not Stuff

C410 Do Not Stuff C411 Do Not Stuff

C411 Do Not Stuff C412 Do Not Stuff

C412 Do Not Stuff C413 Do Not Stuff

C413 Do Not Stuff C414 Do Not Stuff

C414 Do Not Stuff C415 Do Not Stuff

C415 Do Not Stuff C416 Do Not Stuff

C416 Do Not Stuff C417 Do Not Stuff

C417 Do Not Stuff C418 Do Not Stuff

C418 Do Not Stuff C419 Do Not Stuff

C419 Do Not Stuff C420 Do Not Stuff

C420 Do Not Stuff C421 Do Not Stuff

C421 Do Not Stuff C422 Do Not Stuff

C422 Do Not Stuff C423 Do Not Stuff

C423 Do Not Stuff C424 Do Not Stuff

C424 Do Not Stuff C425 Do Not Stuff

C425 Do Not Stuff C426 Do Not Stuff

C426 Do Not Stuff C427 Do Not Stuff

C427 Do Not Stuff C428 Do Not Stuff

C428 Do Not Stuff C429 Do Not Stuff

C429 Do Not Stuff C430 Do Not Stuff

C430 Do Not Stuff C431 Do Not Stuff

C431 Do Not Stuff C432 Do Not Stuff

C432 Do Not Stuff

1D05V_VTT

PEG_RXN[0..15] 83

PEG_RXP[0..15] 83

NOTE. If PEG is not implemented, the RX&TX pairs can be left as No Connect

PEG Static Lane Reversal

1 2

DIS_PX_Muxless

1 2

DIS_PX_Muxless

1 2

DIS_PX_Muxless

1 2

DIS_PX_Muxless

1 2

DIS_PX_Muxless

1 2

DIS_PX_Muxless

1 2

DIS_PX_Muxless

1 2

DIS_PX_Muxless

1 2

DIS_PX_Muxless

1 2

DIS_PX_Muxless

1 2

DIS_PX_Muxless

1 2

DIS_PX_Muxless

1 2

DIS_PX_Muxless

1 2

DIS_PX_Muxless

1 2

DIS_PX_Muxless

1 2

DIS_PX_Muxless

1 2

DIS_PX_Muxless

1 2

DIS_PX_Muxless

1 2

DIS_PX_Muxless

1 2

DIS_PX_Muxless

1 2

DIS_PX_Muxless

1 2

DIS_PX_Muxless

1 2

DIS_PX_Muxless

1 2

DIS_PX_Muxless

1 2

DIS_PX_Muxless

1 2

DIS_PX_Muxless

1 2

DIS_PX_Muxless

1 2

DIS_PX_Muxless

1 2

DIS_PX_Muxless

1 2

DIS_PX_Muxless

1 2

DIS_PX_Muxless

1 2

DIS_PX_Muxless

2

PEG_TXN15 PEG_TXN14 PEG_TXN13 PEG_TXN12 PEG_TXN11 PEG_TXN10 PEG_TXN9 PEG_TXN8 PEG_TXN7 PEG_TXN6 PEG_TXN5 PEG_TXN4 PEG_TXN3 PEG_TXN2 PEG_TXN1 PEG_TXN0

PEG_TXP15 PEG_TXP14 PEG_TXP13 PEG_TXP12 PEG_TXP11 PEG_TXP10 PEG_TXP9 PEG_TXP8 PEG_TXP7 PEG_TXP6 PEG_TXP5 PEG_TXP4 PEG_TXP3 PEG_TXP2 PEG_TXP1 PEG_TXP0

1

PEG_TXN[0..15] 83

PEG_TXP[0..15] 83

Stuff to disable internal graphics function for power saving.

FDI_LSYNC0 FDI_FSYNC0 FDI_FSYNC1 FDI_LSYNC1 FDI_INT

678

R404

R404 Do Not Stuff

Do Not Stuff

DIS

12

RN401

RN401 Do Not Stuff

Do Not Stuff

DIS

123

4 5

20100614 V1.1

NOTE: Select a Fast FET similar to 2N7002E whose rise/ fall time is less than 6 ns. If HPD on eDP interface is disabled, connect it to CPU VCCIO via a 10-kȍ pull-Up resistor on the motherboard.

HR UMA

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Thursday, December 02, 2010

Date: Sheet

CPU (PCIE/DMI/FDI)

JE40-HR

4102

of

A

-1

A

SSID = CPU

5

H_SNB_IVB#18

D D

1D05V_VTT

1 2

R501

R501 62R2J-GP

62R2J-GP

CRB : 47pf CEKLT:43pf

C C

B B

H_PROCHOT#

12

C502

C502 SC47P50V2JN-3GP

SC47P50V2JN-3GP

R513

3D3V_S0

8 7 6

1 2

56R2J-4-GP

BUF_CPU_RST#

H_THERMTRIP#22,36

H_PM_SYNC19

1 2

R505

BUF_CPU_RST#

H_PROCHOT#27,42

Connect EC to PROCHOT# through inverting OD buffer.

H_CPUPWRGD22,36,97

PM_DRAM_PWRGD19,37 VDDPWRGOOD37

RN503

RN503 SRN1K5J-1-GP

XDP_DBRESET#

PLT_RST#18,27,31,36,65,66,71,82,97

SRN1K5J-1-GP

1 2 3 4 5

5

4

JE40 modify

H_PECI22,27

H_PROCHOT#_R SM_RCOMP_0

R503

1 2

10KR2J-3-GP

DY

Do Not Stuff

CPU1B

CPU1B SANDY

SANDY

C26

SNB_IVB#

AN34

SKTOCC#

AL33

CATERR#

AN33

PECI

AL32

PROCHOT#

AN32

THERMTRIP#

AM34

PM_SYNC

AP33

UNCOREPWRGOOD

V8

SM_DRAMPWROK

AR33

RESET#

SANDY

MISCTHERMALPWR MANAGEMENT

CLOCKS

DDR3

JTAG & BPM

4

3

2 OF 9

BCLK

BCLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

SM_DRAMRST#

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

MISC

PRDY# PREQ#

TCK TMS

TRST#

TDO

DBR#

BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7

3

A28

CLK_EXP_P 20

A27

CLK_EXP_N 20

CLK_DP_P_R

A16

CLK_DP_N_R

A15

R8

AK1 A5 A4

AP29 AP27

AR26 AR27 AP30

AR28

TDI

AP26

AL35

AT28 AR29 AR30 AT30 AP32 AR31 AT31 AR32

1 2

SM_RCOMP_1 SM_RCOMP_2

Signal Routing Guideline: SM_RCOMP keep routing length less than 500 mils.

JE40 modify

XDP_TRST#

XDP_TDO

XDP_DBRESET#

JE40 modify

RN502

RN502 Do Not Stuff

Do Not Stuff

1

DIS

2 3

R502

4K99R2F-L-GP

R506 140R2F-GPR506 140R2F-GP

1 2

R507 25D5R2F-GPR507 25D5R2F-GP

1 2

R508 200R2F-L-GPR508 200R2F-L-GP

1 2

4

1D05V_VTT

SM_DRAMRST# 37

XDP_TDO XDP_TRST#

2

JE40 modify

RN501

RN501 SRN51J-GP

SRN51J-GP

2 3 1

2

1

Disabling Guidelines: If motherboard only supports external graphics: Connect DPLL_REF_SSCLK on Processor to GND through 1K +/- 5% resistor. Connect DPLL_REF_SSCLK# on Processor to VCCP through 1K +/- 5% resistorpower (~15 mW) may be wasted.

1D05V_VTT

4

HR UMA

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (THERMAL/CLOCK/PM )

Size Document Number Rev

Size Document Number Rev Custom

Custom

Thursday, December 02, 2010

Date: Sheet

JE40-HR

5102

1

-1

of

-1

A

5

4

3

2

1

SSID = CPU

4 OF 9

3 OF 9

CPU1C

SANDY

D D

C C

B B

M_A_DQ[63:0]14 M_B_DQ[63:0]15

M_A_BS014 M_A_BS114 M_A_BS214

M_A_CAS#14 M_A_RAS#14 M_A_WE#14

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

G10

N10

M10

AG6 AG5 AK6 AK5 AH5 AH6

AK8 AK9

AH8 AH9 AL9

AL8 AP11 AN11

AL12 AM12 AM11

AL11 AP12 AN12

AJ14 AH14

AL15 AK15

AL14 AK14

AJ15 AH15

AE10

AF10

AE8 AD9 AF9

C5

SA_DQ0

D5

SA_DQ1

D3

SA_DQ2

D2

SA_DQ3

D6

SA_DQ4

C6

SA_DQ5

C2

SA_DQ6

C3

SA_DQ7

F10

SA_DQ8

F8

SA_DQ9 SA_DQ10

G9

SA_DQ11

F9

SA_DQ12

F7

SA_DQ13

G8

SA_DQ14

G7

SA_DQ15

K4

SA_DQ16

K5

SA_DQ17

K1

SA_DQ18

J1

SA_DQ19

J5

SA_DQ20

J4

SA_DQ21

J2

SA_DQ22

K2

SA_DQ23

M8

SA_DQ24 SA_DQ25

N8

SA_DQ26

N7

SA_DQ27 SA_DQ28

M9

SA_DQ29

N9

SA_DQ30

M7

SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37

AJ5

SA_DQ38

AJ6

SA_DQ39

AJ8

SA_DQ40 SA_DQ41

AJ9

SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55

V6

SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

SA_BS0 SA_BS1 SA_BS2

SA_CAS# SA_RAS# SA_WE#

DDR SYSTEM MEMORY A

3 OF 9

SA_CLK0

SA_CLK#0

SA_CKE0

SA_CLK1

SA_CLK#1

SA_CKE1

SA_CLK2

SA_CLK#2

SA_CKE2

SA_CLK3

SA_CLK#3

SA_CKE3

SA_CS#0 SA_CS#1 SA_CS#2 SA_CS#3

SA_ODT0 SA_ODT1 SA_ODT2 SA_ODT3

SA_DQS#0 SA_DQS#1 SA_DQS#2 SA_DQS#3 SA_DQS#4 SA_DQS#5 SA_DQS#6 SA_DQS#7

SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8

SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15

AB6 AA6 V9

AA5 AB5 V10

AB4 AA4 W9

AB3 AA3 W10

AK3 AL3 AG1 AH1

AH3 AG3 AG2 AH2

C4 G6 J3 M6 AL6 AM8 AR12 AM15

D4 F6 K3 N6 AL5 AM9 AR11 AM14

AD10 W1 W2 W7 V3 V2 W3 W6 V1 W5 AD8 V4 W4 AF8 V5 V7

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_DIM0_CLK_DDR0 14 M_A_DIM0_CLK_DDR#0 14 M_A_DIM0_CKE0 14

M_A_DIM0_CLK_DDR1 14 M_A_DIM0_CLK_DDR#1 14 M_A_DIM0_CKE1 14

M_A_DIM0_CS#0 14 M_A_DIM0_CS#1 14

M_A_DIM0_ODT0 14 M_A_DIM0_ODT1 14

M_A_DQS#[7:0] 14

M_A_DQS[7:0] 14

M_A_A[15:0] 14

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

M_B_BS015 M_B_BS115 M_B_BS215

M_B_CAS#15 M_B_RAS#15 M_B_WE#15

D10

K10

AM5 AM6 AR3

AP3 AN3 AN2 AN1

AP2

AP5 AN9

AT5

AT6

AP6 AN8 AR6 AR5 AR9

AJ11

AT8

AT9

AH11

AR8

AJ12 AH12 AT11 AN14 AR14 AT14 AT12 AN15 AR15 AT15

AA9 AA7

AA10

AB8 AB9

CPU1D

SANDY

C9

SB_DQ0

A7

SB_DQ1 SB_DQ2

C8

SB_DQ3

A9

SB_DQ4

A8

SB_DQ5

D9

SB_DQ6

D8

SB_DQ7

G4

SB_DQ8

F4

SB_DQ9

F1

SB_DQ10

G1

SB_DQ11

G5

SB_DQ12

F5

SB_DQ13

F2

SB_DQ14

G2

SB_DQ15

J7

SB_DQ16

J8

SB_DQ17 SB_DQ18

K9

SB_DQ19

J9

SB_DQ20

J10

SB_DQ21

K8

SB_DQ22

K7

SB_DQ23

M5

SB_DQ24

N4

SB_DQ25

N2

SB_DQ26

N1

SB_DQ27

M4

SB_DQ28

N5

SB_DQ29

M2

SB_DQ30

M1

SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54

R6

SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

SB_BS0 SB_BS1 SB_BS2

SB_CAS# SB_RAS# SB_WE#

DDR SYSTEM MEMORY B

4 OF 9

SB_CLK0

SB_CLK#0

SB_CKE0

SB_CLK1

SB_CLK#1

SB_CKE1

SB_CLK2

SB_CLK#2

SB_CKE2

SB_CLK3

SB_CLK#3

SB_CKE3

SB_CS#0 SB_CS#1 SB_CS#2 SB_CS#3

SB_ODT0 SB_ODT1 SB_ODT2 SB_ODT3

SB_DQS#0 SB_DQS#1 SB_DQS#2 SB_DQS#3 SB_DQS#4 SB_DQS#5 SB_DQS#6 SB_DQS#7

SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7

SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8

SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15

AE2

M_B_DIM0_CLK_DDR0 15

AD2

M_B_DIM0_CLK_DDR#0 15

R9

M_B_DIM0_CKE0 15

AE1

M_B_DIM0_CLK_DDR1 15

AD1

M_B_DIM0_CLK_DDR#1 15

R10

M_B_DIM0_CKE1 15

AB2 AA2 T9

AA1 AB1 T10

AD3

M_B_DIM0_CS#0 15

AE3

M_B_DIM0_CS#1 15

AD6 AE6

AE4

M_B_DIM0_ODT0 15

AD4

M_B_DIM0_ODT1 15

AD5 AE5

M_B_DQS#0

D7

M_B_DQS#1

F3

M_B_DQS#2

K6

M_B_DQS#3

N3

M_B_DQS#4

AN5

M_B_DQS#5

AP9

M_B_DQS#6

AK12

M_B_DQS#7

AP15

M_B_DQS0

C7

M_B_DQS1

G3

M_B_DQS2

J6

M_B_DQS3

M3

M_B_DQS4

AN6

M_B_DQS5

AP8

M_B_DQS6

AK11

M_B_DQS7

AP14

M_B_A0

AA8

M_B_A1

T7

M_B_A2

R7

M_B_A3

T6

M_B_A4

T2

M_B_A5

T4

M_B_A6

T3

M_B_A7

R2

M_B_A8

T5

M_B_A9

R3

M_B_A10

AB7

M_B_A11

R1

M_B_A12

T1

M_B_A13

AB10

M_B_A14

R5

M_B_A15

R4

M_B_DQS#[7:0] 15

M_B_DQS[7:0] 15

M_B_A[15:0] 15

SANDY

A A

5

4

3

SANDY

HR UMA

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Thursday, December 02, 2010

Date: Sheet of

Date: Sheet

2

Date: Sheet

CPU (DDR)

JE40-HR

6 102

1

-1

of

-1

5

4

3

2

1

SSID = CPU

CFG2

12

R702

D D

DIS_PX_Muxless

PEG Static Lane Reversal

CFG2

1: Normal Operation; Lane # definition matches socket pin map definition

0:Lane Reversed

R702 Do Not Stuff

Do Not Stuff

AK28 AK29

AL26 AL27

AK26

AL29

AL30 AM31 AM32 AM30 AM28 AM26 AN28 AN31 AN26 AM27 AK31 AN29

AJ31 AH31

AJ33 AH33

AJ26

CPU1E

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17

RSVD#AJ31 RSVD#AH31 RSVD#AJ33 RSVD#AH33

RSVD#AJ26

SANDY

B4:VREF_DQ CHA

M_VREF_DQ_DIMM0_C

C C

B B

M_VREF_DQ_DIMM1_C

D1:VREF_DQ CHB

4

RN701

RN701 SRN1KJ-7-GP

SRN1KJ-7-GP

1

2 3

G25 G24

F25 F24 F23 D24

E23 D23 C30 A31 B30 B29 D30 B31 A30 C29

B18 A19

J20

J15

B4 D1

RSVD#B4 RSVD#D1

RSVD#F25 RSVD#F24 RSVD#F23 RSVD#D24 RSVD#G25 RSVD#G24 RSVD#E23 RSVD#D23 RSVD#C30 RSVD#A31 RSVD#B30 RSVD#B29 RSVD#D30 RSVD#B31 RSVD#A30 RSVD#C29

RSVD#J20 RSVD#B18 RSVD#A19

RSVD#J15

RESERVED

5 OF 9

RSVD#L7

RSVD#AG7

RSVD#AE7 RSVD#AK2

RSVD#W8

RSVD#AT26

RSVD#AM33

RSVD#AJ27

RSVD#T8

RSVD#J16 RSVD#H16 RSVD#G16

RSVD#AR35

RSVD#AT34 RSVD#AT33 RSVD#AP35 RSVD#AR34

RSVD#B34 RSVD#A33 RSVD#A34 RSVD#B35 RSVD#C35

RSVD#AJ32 RSVD#AK32

RSVD#AH27

RSVD#AN35

RSVD#AM35

RSVD#AT2 RSVD#AT1 RSVD#AR1

L7 AG7 AE7 AK2 W8

AT26 AM33 AJ27

T8 J16 H16 G16

AR35 AT34 AT33 AP35 AR34

B34 A33 A34 B35 C35

AJ32 AK32

AH27

AN35 AM35

AT2 AT1 AR1

SANDY

A A

5

4

3

2

HR UMA

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Thursday, December 02, 2010

Date: Sheet of

Date: Sheet

CPU (RESERVED)

JE40-HR

7 102

1

of

-1

5

SSID = CPU

PROCESSOR CORE POWER

VCC_CORE

D D

C C

B B

A A

12

C801

DY

12

C820

DY

12

VCC Output Decoupling Recommendation: 4 x 470 uF at Bottom Socket Edge 8 x 22 uF at Top Socket Cavity 8 x 22 uF at Top Socket Edge 8 x 22 uF at Bottom Socket Cavity

53A

12

C802

DY

Do Not Stuff

12

C819

DY

Do Not Stuff

12

C821

C816

Do Not Stuff

SC10U6D3V5KX-1GP

12

C836

C837

DY

SC10U6D3V5KX-1GP

5

12

C803

DY

Do Not Stuff

12

C818

DY

Do Not Stuff

12

C822

SC10U6D3V5KX-1GP

12

C835

SC10U6D3V5KX-1GP

12

C804

DY

Do Not Stuff

12

C817

DY

Do Not Stuff

12

C823

SC10U6D3V5KX-1GP

12

C834

SC10U6D3V5KX-1GP

12

C811

Do Not Stuff

12

C815

Do Not Stuff

12

C824

SC10U6D3V5KX-1GP

12

C833

DY

SC10U6D3V5KX-1GP

12

C825

SC10U6D3V5KX-1GP

12

C832

DY

Do Not Stuff

12

C826

SC10U6D3V5KX-1GP

12

C831

Do Not Stuff

12

C827

SC10U6D3V5KX-1GP

12

C828

SC10U6D3V5KX-1GP

4

VCC_CORE

AG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26

3

POWER

CPU1F

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

Y35

VCC

Y34

VCC

Y33

VCC

Y32

VCC

Y31

VCC

Y30

VCC

Y29

VCC

Y28

VCC

Y27

VCC

Y26

VCC

V35

VCC

V34

VCC

V33

VCC

V32

VCC

V31

VCC

V30

VCC

V29

VCC

V28

VCC

V27

VCC

V26

VCC

U35

VCC

U34

VCC

U33

VCC

U32

VCC

U31

VCC

U30

VCC

U29

VCC

U28

VCC

U27

VCC

U26

VCC

R35

VCC

R34

VCC

R33

VCC

R32

VCC

R31

VCC

R30

VCC

R29

VCC

R28

VCC

R27

VCC

R26

VCC

P35

VCC

P34

VCC

P33

VCC

P32

VCC

P31

VCC

P30

VCC

P29

VCC

P28

VCC

P27

VCC

P26

VCC

SANDY

POWER

SANDY

CORE SUPPLY

SENSE LINES SVID

6 OF 9

AH13

VCCIO

AH10

VCCIO

AG10

VCCIO

AC10

VCCIO

Y10

VCCIO

U10

VCCIO

P10

VCCIO

L10

VCCIO

J14

VCCIO

J13

VCCIO

J12

VCCIO

J11

VCCIO

H14

VCCIO

H12

VCCIO

H11

VCCIO

G14

VCCIO

G13

VCCIO

G12

VCCIO

F14

VCCIO

F13

VCCIO

F12

VCCIO

F11

VCCIO

E14

VCCIO

E12

VCCIO

E11

VCCIO

D14

VCCIO

D13

VCCIO

D12

VCCIO

D11

VCCIO

C14

VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO

VCCIO

VIDALERT#

VIDSCLK

VIDSOUT

C13 C12 C11 B14 B12 A14 A13 A12 A11

J23

H_CPU_SVIDALRT#

AJ29 AJ30 AJ28

AJ35 AJ34

B10 A10

PEG AND DDR

VCC_SENSE VSS_SENSE

VCCIO_SENSE VSSIO_SENSE

3

VCCIO Output Decoupling Recommendation: 2 x 330 uF (3 x 330 uF for 2012 capable designs) 5 x 22 uF & 5 x 0805 no-stuff at Bottom 7 x 22 uF & 2 x 0805 no-stuff at Top

12

C805

SC10U6D3V5KX-1GP

No-stuff sites outside the socket may be removed. No-stuff sites inside the socket cavity need to remain.

12

C812

SC10U6D3V5KX-1GP

For CRB VIDSOUT need to pull high 130 ohm closr to CPU and IMVP7 For CRB VIDALERT# need to pull high 75 ohm close to CPU

VCCIO_SENSE 45 VSSIO_SENSE 45

12

C806

SC10U6D3V5KX-1GP

12

C813

SC10U6D3V5KX-1GP

1 2

H_CPU_SVIDCLK 42

H_CPU_SVIDDAT 42

VCC_CORE

2

12

C829

SC10U6D3V5KX-1GP

12

C810

C809

SC10U6D3V5KX-1GP

12

C830

C842

DY

Do Not Stuff

SC10U6D3V5KX-1GP

VR_SVID_ALERT# 42

H_CPU_SVIDDAT

R801,R802 close to CPU

VCCSENSE 42 VSSSENSE 42

2

C807

SC10U6D3V5KX-1GP

C814

SC10U6D3V5KX-1GP

R803

R803 43R2J-GP

43R2J-GP

12

R801

R801 100R2F-L1-GP-U

100R2F-L1-GP-U

12

R802

R802 100R2F-L1-GP-U

100R2F-L1-GP-U

1

1D05V_VTT

12

C838

C839

SC10U6D3V5KX-1GP

1D05V_VTT

12

C844

C843

Do Not Stuff

SC10U6D3V5KX-1GP

R804 130R2F-1-GPR804 130R2F-1-GP

HR UMA

Title

Size Document Number Rev

Size Document Number Rev Custom

Custom

Thursday, December 02, 2010

Date: Sheet

Date: Sheet of

12

1 2

C841

C840

SC10U6D3V5KX-1GP

C845

SC10U6D3V5KX-1GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

CPU (VCC_CORE)

JE40-HR

1D05V_VTT

1

8 102

of

8 102

of

8 102

-1

5

VAXG Output Decoupling Recommendation:

SSID = CPU

VCC_GFXCORE

2 x 470 uF at Bottom Socket Edge 2 x 22 uF at Top Socket Cavity 4 x 22 uF at Top Socket Edge 2 x 22 uF at Bottom Socket Cavity 4 x 22 uF at Bottom Socket Edge

PROCESSOR VAXG: 24A

D D

C C

B B

VCC_GFXCORE

Disabling Guidelines for External Graphics Designs: Can connect to GND if motherboard only supports external graphics and if GFX VR is not stuffed. Can be left floating (Gfx VR keeps VAXG rail from floating) if the VR is stuffed

R903

R903 Do Not Stuff

Do Not Stuff

DIS

1 2

12

C901

DY

Do Not Stuff

UMA_PX_Muxless

12

C907

DY

Do Not Stuff

UMA_PX_Muxless

R904

R904 Do Not Stuff

Do Not Stuff

DIS

1 2

12

C902

C903

UMA_PX_Muxless

SC10U6D3V5KX-1GP

12

C918

C908

DY

Do Not Stuff

UMA_PX_Muxless

SC10U6D3V5KX-1GP

R905

R905 Do Not Stuff

Do Not Stuff

DIS

1 2

12

C904

UMA_PX_Muxless

SC10U6D3V5KX-1GP

12

C919

UMA_PX_Muxless

SC10U6D3V5KX-1GP

1 2

1D8V_S0

12

4

12

C905

C906

DY

Do Not Stuff

SC10U6D3V5KX-1GP

12

UMA_PX_Muxless

R901

R901 Do Not Stuff

Do Not Stuff

DIS

C921

C920

SC10U6D3V5KX-1GP

PROCESSOR VCCPLL: 1.2A

C922

SC1U10V2KX-1GP

AT24 AT23 AT21 AT20 AT18 AT17 AR24 AR23 AR21 AR20 AR18 AR17 AP24 AP23 AP21 AP20 AP18 AP17 AN24 AN23 AN21 AN20 AN18 AN17 AM24 AM23 AM21 AM20 AM18 AM17

AL24 AL23 AL21 AL20 AL18

AL17 AK24 AK23 AK21 AK20 AK18 AK17

AJ24

AJ23

AJ21

AJ20

AJ18

AJ17 AH24 AH23 AH21 AH20 AH18 AH17

3

2

1

R906,R907 close to CPU

VCC_GFXCORE

12

C914

Do Not Stuff

12

R906

R906 100R2F-L1-GP-U

100R2F-L1-GP-U

12

R907

R907 100R2F-L1-GP-U

100R2F-L1-GP-U

1D5V_S0

POWER

CPU1G

VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG

B6

VCCPLL

A6

VCCPLL

A2

VCCPLL

SANDY

POWER

SANDY

GRAPHICS

1.8V RAIL

SENSE

VREFMISC

DDR3 -1.5V RAILS

SA RAIL

7 OF 9

VAXG_SENSE

VSSAXG_SENSE

LINES

SM_VREF

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA

VCCSA_SENSE

FC_C22

VCCSA_VID1

AK35 AK34

Refer to the latest Huron River Mainstream PDG (Doc# 436735) for more details on S3 power reduction implementation.

VCC_AXG_SENSE 42 VSS_AXG_SENSE 42

+V_SM_VREF_CNT should have 10 mil trace width

AL1

AF7 AF4 AF1 AC7 AC4 AC1 Y7 Y4 Y1 U7 U4 U1 P7 P4 P1

Routing Guideline: Power from DDR_VREF_S3 and +V_SM_VREF_CNT should have 10 mils trace width.

+V_SM_VREF_CNT 37

PROCESSOR VDDQ: 10A

12

C909

C910

Do Not Stuff

C910

SC10U6D3V5KX-1GP

0D85V_S0

DY

12

C911

SC10U6D3V5KX-1GP

PROCESSOR VCCSA: 6A

VCCSA Output Decoupling Recommendation:

12

M27 M26 L26 J26 J25 J24 H26 H25

H23

C22 C24

VCCUSA_SENSE

H_FC_C22

DY

0D85V_S0

12

R902

R902 10R2J-2-GP

10R2J-2-GP

23

C915

C916

Do Not Stuff

1 x 330 uF 2 x 10 uF at Bottom Socket Cavity 1 x 10 uF at Bottom Socket Edge

SC10U6D3V5KX-1GP

R902 need be close to pin H23.

1

TP901 Do Not StuffTP901 Do Not Stuff

RN901

RN901 SRN1KJ-7-GP

SRN1KJ-7-GP

VCCSA_SEL 48

1

VCC_AXG_SENSE VSS_AXG_SENSE

12

C912

SC10U6D3V5KX-1GP

12

C913

DY

SC10U6D3V5KX-1GP

VDDQ Output Decoupling Recommendation: 1 x 330 uF 6 x 10 uF

4

VCCPLL Output Decoupling Recommendation: 1 x 330 uF 2 x 1 uF 1 x 10 uF

A A

5

4

3

2

HR UMA

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Thursday, December 02, 2010

Date: Sheet

CPU (VCC_GFXCORE)

JE40-HR

1

of

9 102

-1

5

4

3

2

1

SSID = CPU

8 OF 9

CPU1H

AT35

VSS

AT32

VSS

AT29

VSS

AT27

VSS

AT25

VSS

AT22

VSS

D D

C C

B B

AT19 AT16 AT13 AT10

AT7 AT4

AT3 AR25 AR22 AR19 AR16 AR13 AR10

AR7

AR4

AR2 AP34 AP31 AP28 AP25 AP22 AP19 AP16 AP13 AP10

AP7

AP4

AP1 AN30 AN27 AN25 AN22 AN19 AN16 AN13 AN10

AN7

AN4 AM29 AM25 AM22 AM19 AM16 AM13 AM10

AM7 AM4 AM3 AM2

AM1 AL34 AL31 AL28 AL25 AL22 AL19 AL16 AL13 AL10

AL7 AL4

AL2 AK33 AK30 AK27 AK25 AK22 AK19 AK16 AK13 AK10

AK7

AK4

AJ25

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SANDY

VSS

8 OF 9

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AJ22 AJ19 AJ16 AJ13 AJ10 AJ7 AJ4 AJ3 AJ2 AJ1 AH35 AH34 AH32 AH30 AH29 AH28 AH26 AH25 AH22 AH19 AH16 AH7 AH4 AG9 AG8 AG4 AF6 AF5 AF3 AF2 AE35 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE9 AD7 AC9 AC8 AC6 AC5 AC3 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 Y9 Y8 Y6 Y5 Y3 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 U9 U8 U6 U5 U3 U2

T35 T34 T33 T32 T31 T30 T29 T28 T27 T26

N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 M34

L33 L30 L27

K35 K32 K29 K26

J34

J31 H33 H30 H27 H24 H21 H18 H15 H13 H10

G35 G32 G29 G26 G23 G20 G17 G11 F34 F31 F29

CPU1I

SANDY

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

P9

VSS

P8

VSS

P6

VSS

P5

VSS

P3

VSS

P2

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

L9

VSS

L8

VSS

L6

VSS

L5

VSS

L4

VSS

L3

VSS

L2

VSS

L1

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

H9

VSS

H8

VSS

H7

VSS

H6

VSS

H5

VSS

H4

VSS

H3

VSS

H2

VSS

H1

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SANDY

VSS

9 OF 9

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

F22 F19 E30 E27 E24 E21 E18 E15 E13 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 D35 D32 D29 D26 D20 D17 C34 C31 C28 C27 C25 C23 C10 C1 B22 B19 B17 B15 B13 B11 B9 B8 B7 B5 B3 B2 A35 A32 A29 A26 A23 A20 A3

SANDY

A A

5

4

3

SANDY

HR UMA

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Thursday, December 02, 2010

Date: Sheet of

Date: Sheet

2

Date: Sheet

CPU (VSS)

JE40-HR

10 102

1

-1

of

-1

5

D D

C C

4

3

2

1

JE40 delete XDP function

B B

A A

5

4

3

2

HR UMA

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Thursday, December 02, 2010

Date: Sheet of

Date: Sheet

XDP

JE40-HR

11 102

1

of

-1

5

D D

C C

4

3

2

1

(Blanking)

B B

HR UMA

Wistron Corporation

A A

Title

Reserved

Size Document Number Rev

Size Document Number Rev A4

A4

Thursday, December 02, 2010

Date: Sheet

5

4

3

Date: Sheet

2

Reserved

JE40-HR

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

-1

12 102

of

1

-1

5

D D

C C

4

3

2

1

(Blanking)

B B

HR UMA

Wistron Corporation

A A

Title

Reserved

Size Document Number Rev

Size Document Number Rev A4

A4

Thursday, December 02, 2010

Date: Sheet

5

4

3

Date: Sheet

2

Reserved

JE40-HR

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

-1

13 102

of

1

-1

5

SSID = MEMORY

M_A_A[15:0] 6

D D

M_A_BS26 M_A_BS06

M_A_BS16

M_A_DQ[63:0]6

C C

B B

DDR_VREF_S3

12

-2

0D75V_S0

A A

12

C1413

C1411

12

C1413

SCD1U10V2KX-5GP

Place these caps close to VTT1 and VTT2.

12

C1419

C1421

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

SC1U6D3V2KX-GP

5

M_A_DQS#[7:0] 6 M_A_DQS[7:0] 6

M_A_DIM0_ODT06 M_A_DIM0_ODT16

DDR3_DRAMRST#15,37

DDR_VREF_S3

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

0D75V_S0

4

H =4mm

4

3

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12

119

A13

80

A14

78

A15

79

A16/BA2

109

BA0

108

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3#

135

DQS4#

152

DQS5#

169

DQS6#

186

DQS7#

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

116

ODT0

120

ODT1

126

VREF_CA

1

VREF_DQ

30

RESET#

203

VTT1

204

VTT2

NP1 NP2

RAS#

WE#

CAS# CS0#

CS1# CKE0

CKE1

CK0

CK0#

CK1

CK1#

DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7

SDA

SCL EVENT# VDDSPD

SA0

SA1

NC#1 NC#2

NC#/TEST

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8

VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

NP1 NP2

110 113 115

114 121

73 74

101 103

102 104

11 28 46 63 136 153 170 187

200 202

198 199 197

201 77

122 125

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 205 206

1D5V_S3

M_A_RAS# 6 M_A_WE# 6 M_A_CAS# 6

M_A_DIM0_CS#0 6 M_A_DIM0_CS#1 6

M_A_DIM0_CKE0 6 M_A_DIM0_CKE1 6

M_A_DIM0_CLK_DDR0 6 M_A_DIM0_CLK_DDR#0 6

M_A_DIM0_CLK_DDR1 6 M_A_DIM0_CLK_DDR#1 6

PCH_SMBDATA 15,20 PCH_SMBCLK 15,20

TS#_DIMM0_1 15

PART NUMBER Height

DM1

DM1 DDR3-204P-122-GP

DDR3-204P-122-GP

62.10017.Z51

62.10017.Z51 2nd = 62.10017.V51

2nd = 62.10017.V51 3rd = 62.10017.M51

3rd = 62.10017.M51 4th = 62.10017.X41

4th = 62.10017.X41

3

3D3V_S0

12

C1401

SCD1U10V2KX-5GP

Thermal EVENT

TS#_DIMM0_1

1D5V_S3

TYPE

2

R1403

1 2

10KR2J-3-GP

SODIMM A DECOUPLING

12

C1403

SC10U6D3V5KX-1GP

2

3D3V_S0

12

C1404

SC10U6D3V5KX-1GP

12

C1416

SCD1U10V2KX-5GP

1

Note: If SA0 DIM0 = 0, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA0 SO-DIMMA TS Address is 0x30

If SA0 DIM0 = 1, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA2 SO-DIMMA TS Address is 0x32

Layout Note: Place these Caps near SO-DIMMA.

SC56P50V2JN-2GP

12

C1406

C1407

SC10U6D3V5KX-1GP

HR UMA

Title

Size Document Number Rev

Size Document Number Rev Custom

Custom

Thursday, December 02, 2010

Date: Sheet

DY

C1405

12

C1417

Do Not Stuff

SCD1U10V2KX-5GP

12

C1408

3G_RF

DDR3-SODIMM1

JE40-HR

12

C1409

3G_RF

SCD1U50V3KX-GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

C1410

SCD1U50V3KX-GP

of

14 102

-1

5

SSID = MEMORY

M_B_A[15:0] 6

D D

M_B_BS26 M_B_BS06

M_B_BS16

M_B_DQ[63:0]6

C C

B B

DDR_VREF_S3

SCD1U10V2KX-5GP

C1515

Place these caps close to VTT1 and VTT2.

12

C1519

C1521

SC1U6D3V2KX-GP

12

C1517

M_B_DQS#[7:0] 6 M_B_DQS[7:0] 6

M_B_DIM0_ODT06 M_B_DIM0_ODT16

DDR3_DRAMRST#14,37

5

12

SCD1U10V2KX-5GP

-2

0D75V_S0

A A

12

4

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7

DDR_VREF_S3

0D75V_S0

4

H = 8mm

3

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12

119

A13

80

A14

78

A15

79

A16/BA2

109

BA0

108

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3#

135

DQS4#

152

DQS5#

169

DQS6#

186

DQS7#

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

116

ODT0

120

ODT1

126

VREF_CA

1

VREF_DQ

30

RESET#

203

VTT1

204

VTT2

NP1 NP2

RAS#

WE#

CAS#

CS0# CS1#

CKE0 CKE1

CK0

CK0#

CK1

CK1#

DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7

SDA SCL

EVENT#

VDDSPD

NC#1 NC#2

NC#/TEST

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8

VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

NP1 NP2

110 113 115

114 121

73 74

101 103

102 104

11 28 46 63 136 153 170 187

200 202

198 199 197

SA0

201

SA1

77 122 125

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 205 206

M_B_RAS# 6 M_B_WE# 6 M_B_CAS# 6

M_B_DIM0_CS#0 6 M_B_DIM0_CS#1 6

M_B_DIM0_CKE0 6 M_B_DIM0_CKE1 6

M_B_DIM0_CLK_DDR0 6 M_B_DIM0_CLK_DDR#0 6

M_B_DIM0_CLK_DDR1 6 M_B_DIM0_CLK_DDR#1 6

PCH_SMBDATA 14,20 PCH_SMBCLK 14,20

TS#_DIMM0_1 14

SA1_DIM1

1D5V_S3

3D3V_S0

12

R1501

R1501 10KR2J-3-GP

10KR2J-3-GP

DM2

DM2 DDR3-204P-126-GP

DDR3-204P-126-GP

62.10024.D41

2nd = 62.10017.R91

2nd = 62.10017.R91 3rd = 62.10017.V61

3rd = 62.10017.V61 4th = 62.10017.X51

4th = 62.10017.X51

3

C1501

SCD1U10V2KX-5GP

Layout Note: Place these Caps near SO-DIMMB.

2

1D5V_S3

SODIMM B DECOUPLING

C1503

SC5D6P50V2CN-1GP

12

3G_RF

2

1

Note: SO-DIMMB SPD Address is 0xA4 SO-DIMMB TS Address is 0x34

SO-DIMMB is placed farther from the Processor than SO-DIMMA

SCD1U50V3KX-GP

12

C1505

C1504

SC10U6D3V5KX-1GP

SC56P50V2JN-2GP

12

C1513

12

SCD1U10V2KX-5GP

HR UMA

Title

Size Document Number Rev

Size Document Number Rev Custom

Custom

Custom Date: Sheet

Date: Sheet

C1507

C1506

SC10U6D3V5KX-1GP

C1514

SCD1U10V2KX-5GP

Thursday, December 02, 2010

12

C1508

3G_RF

SCD1U50V3KX-GP

DDR3-SODIMM2

JE40-HR

12

C1509

3G_RF

SC10U6D3V5KX-1GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

C1510

of

15 102

-1

5

D D

4

3

2

1

C C

B B

A A

5

(Blanking)

4

HR UMA

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

DDR3-SODIMM2

Size Document Number Rev

Size Document Number Rev A4

A4

Thursday, December 02, 2010

Date: Sheet

3

Date: Sheet

2

DDR3-SODIMM2

JE40-HR

16 102

-1

of

1

-1

5

D D

4

3

2

1

3D3V_S0

RN1701

RN1701 SRN2K2J-1-GP

SRN2K2J-1-GP

2 3 1

UMA_Muxless

RN1702

RN1702 SRN100KJ-6-GP

SRN100KJ-6-GP

1 2 3

UMA_Muxless

C C

4

L_CTRL_DATA L_CTRL_CLK

L_BKLT_EN LVDS_VDD_EN

L_DDC_DATA(PAGE17): This signal is on the LVDS interface. This signal needs to be left NC if eDP is used for the local flat panel display

Place near PCH

2K37R2F-GP

UMA_Muxless

R1701

12

Impedance:90 ohm

L_BKLT_EN94

LVDS_VDD_EN94

L_BKLT_CTRL94

LVDS_DDC_CLK_R94

LVDS_DDC_DATA_R94

RN1704

RN1704 SRN0J-6-GP

SRN0J-6-GP

1 2 3

UMA_Muxless

LVDSA_CLK#94

LVDSA_CLK94

LVDSA_DATA0#94

LVDSA_DATA1#94

LVDSA_DATA2#94

LVDSA_DATA094

LVDSA_DATA194

LVDSA_DATA294

L_CTRL_CLK L_CTRL_DATA

LVDS_IBG

LVDS_VREFH

4

LVDS_VREFL

JE40 modify

JE40 delete LVDS B channel

Close to PCH side

CRT_BLUE CRT_GREEN

B B

CRT_RED

678

123

4 5

RN1705

RN1705 SRN150F-1-GP

SRN150F-1-GP

UMA_PX_Muxless

CRT_BLUE95 CRT_GREEN95 CRT_RED95

CRT_DDC_CLK95 CRT_DDC_DATA95

CRT_HSYNC95 CRT_VSYNC95

1KR2D-1-GP

R1702

DAC_IREF_R

12

PCH1D

J47

L_BKLTEN

M45

L_VDD_EN

P45

L_BKLTCTL

T40

L_DDC_CLK

K47

L_DDC_DATA

T45

L_CTRL_CLK

P39

L_CTRL_DATA

AF37

LVD_IBG

AF36

LVD_VBG

AE48

LVD_VREFH

AE47

LVD_VREFL

AK39

LVDSA_CLK#

AK40

LVDSA_CLK

AN48

LVDSA_DATA#0

AM47

LVDSA_DATA#1

AK47

LVDSA_DATA#2

AJ48

LVDSA_DATA#3

AN47

LVDSA_DATA0

AM49

LVDSA_DATA1

AK49

LVDSA_DATA2

AJ47

LVDSA_DATA3

AF40

LVDSB_CLK#

AF39

LVDSB_CLK

AH45

LVDSB_DATA#0

AH47

LVDSB_DATA#1

AF49

LVDSB_DATA#2

AF45

LVDSB_DATA#3

AH43

LVDSB_DATA0

AH49

LVDSB_DATA1

AF47

LVDSB_DATA2

AF43

LVDSB_DATA3

N48

CRT_BLUE

P49

CRT_GREEN

T49

CRT_RED

T39

CRT_DDC_CLK

M40

CRT_DDC_DATA

M47

CRT_HSYNC

M49

CRT_VSYNC

T43

DAC_IREF

T42

CRT_IRTN

COUGAR-GP-U2-NF

Cougar

Cougar Point

Point

LVDS

CRT

Digital Display Interface

4 OF 10

SDVO_TVCLKINN SDVO_TVCLKINP

SDVO_STALLN SDVO_STALLP

SDVO_INTN

SDVO_INTP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPB_AUXN DDPB_AUXP

DDPB_HPD

DDPB_0N

DDPB_0P

DDPB_1N

DDPB_1P

DDPB_2N

DDPB_2P

DDPB_3N

DDPB_3P

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN DDPC_AUXP

DDPC_HPD

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXN DDPD_AUXP

DDPD_HPD

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

AP43 AP45

AM42 AM40

AP39 AP40

P38 M39

AT49 AT47 AT40

AV42 AV40 AV45 AV46 AU48 AU47 AV47 AV49

P46 P42

AP47 AP49 AT38

AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49

M43 M36

AT45 AT43 BH41

BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42

UMA_Muxless

DDBP_DATA2# DDBP_DATA2 DDBP_DATA1# DDBP_DATA1 DDBP_DATA0# DDBP_DATA0 DDBP_CLK# DDBP_CLK

Impedance:90 ohm

3D3V_S0

4

RN1706

RN1706 SRN2K2J-1-GP

SRN2K2J-1-GP

1

2 3

PCH_HDMI_CLK 51 PCH_HDMI_DATA 51

C1701 SCD1U10V2KX-5GP

1 2

UMA_Muxless

UMA_Muxless UMA_Muxless

UMA_Muxless

C1702 SCD1U10V2KX-5GP

1 2

C1703 SCD1U10V2KX-5GP

1 2

C1704 SCD1U10V2KX-5GP

1 2

C1705 SCD1U10V2KX-5GP

1 2

C1706 SCD1U10V2KX-5GP

1 2

C1707 SCD1U10V2KX-5GP

1 2

C1708 SCD1U10V2KX-5GP

1 2

Close to PCH side

DDI Port B Detect:(SDVO_CTRL_ DATA) 1: Port B detected 0: Port B not detected

HDMI_PCH_DET 51 HDMI_DATA2_R# 51

HDMI_DATA2_R 51 HDMI_DATA1_R# 51 HDMI_DATA1_R 51 HDMI_DATA0_R# 51 HDMI_DATA0_R 51 HDMI_CLK_R# 51 HDMI_CLK_R 51

Impedance:100 ohm

A A

5

4

3

2

HR UMA

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Thursday, December 02, 2010

Date: Sheet

PCH (LVDS/CRT/DDI)

JE40-HR

1

of

17 102

-1

5

R

4

3

2

1

SSID = PCH

RN1801

RN1801 SRN8K2J-2-GP-U

D D

3D3V_S0

INT_PIRQH# INT_PIRQB# INT_PIRQF#

A16 swap override Strap/Top-Block Swap Override jumper

PCI_GNT#3 Low = A16 swap

C C

GNT1#/GPIO51 BOOT BIOS LocationSATA1GP/GPIO19

0 0 LPC 0 1 Reserved

B B

SRN8K2J-2-GP-U

1 2 3 4 5 6

override/Top-Block Swap Override enabled High = Default

10

INT_PIRQD#

9

INT_PIRQE#

8

INT_PIRQC#INT_PIRQA#

7

USB30_SMI#

BOOT BIOS Strap

11

SPI(Default)

3D3V_S0

RN1803

RN1803 SRN10KJ-5-GP

DGPU_HOLD_RST#83

1

DGPU_PWR_EN#93

1

R1813

R1813 Do Not Stuff

Do Not Stuff

1 2

SRN10KJ-5-GP

2 3 1

DGPU_PWM_SELECT#

4

INT_PIRQA# INT_PIRQB# INT_PIRQC# INT_PIRQD#

DGPU_SELECT#

INT_PIRQE# INT_PIRQF#

INT_PIRQH#

DGPU_HOLD_RST# DGPU_PWR_EN#

TP1806Do Not Stuff TP1806Do Not Stuff

Reserved01

TP1804Do Not Stuff TP1804Do Not Stuff

SATA_ODD_DA#56 USB30_SMI#82

JE40 modify 07/16

PLT_RST#5,27,31,36,65,66,71,82,97

R1804 22R2J-2-GPR1804 22R2J-2-GP

CLK_PCI_LPC71 CLK_PCI_FB20 CLK_PCI_KBC27

EC1803

Do Not Stuff

1 2

DY

1 2

R1805 22R2J-2-GPR1805 22R2J-2-GP

1 2

R1806 22R2J-2-GPR1806 22R2J-2-GP

1 2

EC1802

1 2

Do Not Stuff

DY

EC1801

Do Not Stuff

1 2

CLK_PCI_LPC_R CLK_PCI_FB_R CLK_PCI_KBC_R

PCH1E

BG26

BJ26

BH25

BJ16 BG16 AH38 AH37 AK43 AK45

C18 N30

H3

AH12

AM4 AM5

Y13 K24

L24 AB46 AB45

B21

M20 AY16 BG46

BE28 BC30 BE32

BJ32 BC28 BE30

BF32 BG32 AV26 BB26 AU28 AY30 AU26 AY26 AV28

AW30

K40 K38 H38

G38

C46 C44 E40

D47 E42 F46

G42 G40

C42 D44

K10

C6

H49 H43

J48 K42 H40

COUGAR-GP-U2-NF

Cougar

TP1

Point

TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP20

TP21 TP22 TP23 TP24

TP25 TP26 TP27 TP28 TP29 TP30 TP31 TP32 TP33 TP34 TP35 TP36 TP37 TP38 TP39 TP40

PIRQA# PIRQB# PIRQC# PIRQD#

REQ1#/GPIO50 REQ2#/GPIO52 REQ3#/GPIO54

GNT1#/GPIO51 GNT2#/GPIO53 GNT3#/GPIO55

PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5

PME# PLTRST#

CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4

RSVD

PCI

NVRAM

USB

5 OF 10

RSVD RSVD RSVD RSVD

RSVD RSVD

RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD

RSVD

DF_TVS

RSVD RSVD RSVD

RSVD RSVD

RSVD

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N

USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P

USBRBIAS#

USBRBIAS

OC0#/GPIO59 OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43

OC5#/GPIO9 OC6#/GPIO10 OC7#/GPIO14

AY7 AV7 AU3 BG4

AT10 BC8

AU2 AT4 AT3 AT1 AY3 AT5 AV3 AV1 BB1 BA3 BB5 BB3 BB7 BE8 BD4 BF6

AV5

NV_CLE

AY1 AV10 AT8 AY5

BA2 AT12

USB Ext. port 1 (HS)

BF3

External debug port use on Huron river platform

C24 A24 C25 B25 C26

JE40 delete FP function

A26 K28 H28 E28 D28 C28 A28 C29 B29 N28 M28 L30 K30 G30 E30 C30

JE40 delete eDP function

A30 L32 K32 G32 E32 C32

JE40 delete New Card function

A32

USB_RBIAS

C33

B33

A14 K20 B17 C16 L16 A16 D14 C14

DMI & FDI Termination Voltage

NV_CLE

Set to Vss when LOW Set to Vcc when HIGH

check R1808 R1809

CRB : 2.2K CEKLT: 1K

NV_CLE

USB_PN0 66 USB_PP0 66 USB_PN1 61 USB_PP1 61

USB_PN3 63 USB_PP3 63 USB_PN4 66 USB_PP4 66 USB_PN5 32 USB_PP5 32

USB_PN8 82 USB_PP8 82 USB_PN9 61 USB_PP9 61

USB_PN11 65 USB_PP11 65 USB_PN12 49 USB_PP12 49

3D3V_S5

1 2

R1820

R1820 10KR2J-3-GP

10KR2J-3-GP

SB add USB port 5

JE40 co-lay USB2.0

1 2

R1811

R1811 22D6R2F-L1-GP

22D6R2F-L1-GP

1 2

R1809

R1809 1KR2J-1-GP

1KR2J-1-GP

12

R1808

R1808 2K2R2J-2-GP

2K2R2J-2-GP

ଖ

H_SNB_IVB# 5

1D8V_S0

USB Table

Pair

0 1 2 3 4 5 6 7 8 9 10 11 12 13

Touch Panel / 3G SIM USB Ext. port 1 (HS)

Fingerprint

BLUETOOTH Mini Card2 (WWAN) CARD READER(DY) X X

USB Ext. port 4 / E-SATA /USB CHARGE

USB Ext. port 2 EDP CAMERA Mini Card1 (WLAN) CAMERA

New Card

Device

OC[3:0]# for Device 29 (Ports 0-7)

KBC CLK EMI

A A

5

4

OC[7:4]# for Device 26 (Ports 8-13)

3

HR UMA

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Thursday, December 02, 2010

Date: Sheet

2

Date: Sheet

PCH (PCI/USB/NVRAM)

JE40-HR

1

of

18 102

-1

5

4

3

2

1

SSID = PCH

D D

Signal Routing Guideline: DMI_ZCOMP keep W=4 mils and routing length less than 500 mils. DMI_IRCOMP keep W=4 mils and routing length less than 500 mils.

1D05V_VTT

R1901 49D9R2F-GPR1901 49D9R2F-GP R1902 750R2F-GPR1902 750R2F-GP

R1926

R1926 Do Not Stuff

Do Not Stuff

1 2

DY

C C

DY

1 2

R1904

R1904 100KR2J-1-GP

100KR2J-1-GP

S0_PWR_GOOD after PM_SLP_S3# delay 200 ms

B B

A A

SYS_PWROK PWROK

3D3V_S5

5

3D3V_S0

S0_PWR_GOOD27,42

RN1901

RN1901 SRN10KJ-6-GP

SRN10KJ-6-GP

8 7 6

R1921

R1921 10KR2J-3-GP

10KR2J-3-GP

R1908

R1908 100KR2J-1-GP

100KR2J-1-GP

DMI_RXN[3:0]4

DMI_RXP[3:0]4

DMI_TXN[3:0]4

DMI_TXP[3:0]4

DMI_RXN04 DMI_RXN14 DMI_RXN24 DMI_RXN34

DMI_RXP04 DMI_RXP14 DMI_RXP24 DMI_RXP34

DMI_TXN04 DMI_TXN14 DMI_TXN24 DMI_TXN34

DMI_TXP04 DMI_TXP14 DMI_TXP24 DMI_TXP34

R1924

R1924 Do Not Stuff

Do Not Stuff

PM_DRAM_PWRGD5,37

DMI_COMP_R RBIAS_CPY

SUS_PWR_ACK

SYS_RESET#

SYS_PWROK36

PWROK

12

JE40 modify

PCIE_WAKE# CRB : 1K

PM_RSMRST#

BATLOW#

PM_RI#

1 2 1 2

0628 Modify: Change R1904 to 100K 0402 from 10K and default stuff.

JE40 modify

1 2

R1905

R1905 10KR2J-3-GP

10KR2J-3-GP

SUS_PWR_ACK27

PM_PWRBTN#27,97

AC_PRESENT27

BATLOW#

1

PM_RI#

2

AC_PRESENT

3

SUS_PWR_ACK

45

PCIE_WAKE#

12

PCH1C

BC24

DMI0RXN

BE20

DMI1RXN

BG18

DMI2RXN

BG20

DMI3RXN

BE24

DMI0RXP

BC20

DMI1RXP

BJ18

DMI2RXP

BJ20

DMI3RXP

AW24

DMI0TXN

AW20

DMI1TXN

BB18

DMI2TXN

AV18

DMI3TXN

AY24

DMI0TXP

AY20

DMI1TXP

AY18

DMI2TXP

AU18

DMI3TXP

BJ24

DMI_ZCOMP

BG25

DMI_IRCOMP

BH21

DMI2RBIAS

C12

SUSACK#

K3

SYS_RESET#

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST#

K16

SUSWARN#/SUSPWRDNACK/GPIO30

E20

PWRBTN#

H20

ACPRESENT/GPIO31

E10

BATLOW#/GPIO72

A10

RI#

COUGAR-GP-U2-NF

CEKLT: 10K

PWRBTN# This signal has an internal pull-up resistor

12

PM_RSMRST#

PM_RSMRST# CRB : PL 10K ANNIE : PL 100K

4

Cougar

Cougar Point

Point

3 OF 10

BJ14

FDI_RXN0

AY14

FDI_RXN1

BE14

FDI_RXN2

BH13

FDI_RXN3

BC12

FDI_RXN4

BJ12

FDI_RXN5

BG10

FDI_RXN6

BG9

FDI_RXN7

BG14

FDI_RXP0

BB14

FDI_RXP1

BF14

FDI_RXP2

BG13

FDI_RXP3

BE12

FDI_RXP4

BG12

FDI_RXP5

BJ10

DMI

System Power Management

FDI_RXP6

FDI

FDI_RXP7

FDI_FSYNC0 FDI_FSYNC1 FDI_LSYNC0 FDI_LSYNC1

DSWVRMEN

CLKRUN#/GPIO32

SUS_STAT#/GPIO61

SUSCLK/GPIO62

SLP_S5#/GPIO63

SLP_SUS#

PMSYNCH

SLP_LAN#/GPIO29

3D3V_AUX_S5

R1916

R1916 10KR2J-3-GP

10KR2J-3-GP

1 2

3V_5V_POK_#

FDI_INT

DPWROK

WAKE#

SLP_S4#

SLP_S3#

SLP_A#

BH9

AW16 AV12 BC10 AV14 BB10

A18

E22

B9

N3

G8

N14

D10

H4

F4

G10

G16

AP14

K14

R1909

R1909 100KR2J-1-GP

100KR2J-1-GP

FDI_TXN0 4 FDI_TXN1 4 FDI_TXN2 4 FDI_TXN3 4 FDI_TXN4 4 FDI_TXN5 4 FDI_TXN6 4 FDI_TXN7 4

FDI_TXP0 4 FDI_TXP1 4 FDI_TXP2 4 FDI_TXP3 4 FDI_TXP4 4 FDI_TXP5 4 FDI_TXP6 4 FDI_TXP7 4

FDI_INT 4 FDI_FSYNC0 4 FDI_FSYNC1 4 FDI_LSYNC0 4 FDI_LSYNC1 4

DSWODVREN

PCH_DPWROK

PCIE_WAKE# 31,65,66,82

PM_CLKRUN# 27

PCH_SUSCLK_KBC 27

PM_SLP_S4# 27,46

PM_SLP_S3# 27,36,37,47,92

H_PM_SYNC 5

12

5 6

3

34 2 1

FDI_TXN[7:0] 4 FDI_TXP[7:0] 4

DY

PM_RSMRST#

Q1901

Q1901 2N7002KDW-GP

2N7002KDW-GP

84.2N702.A3F

2nd = 84.DM601.03F

R1910

R1910 Do Not Stuff

Do Not Stuff

1 2 1 2

R1911

R1911 Do Not Stuff

Do Not Stuff

JE40 modify 07/16

R1912

R1912 1KR2J-1-GP

1KR2J-1-GP

1 2

For platforms not supporting Deep S4/S5

1.VccSUS3_3 and VccDSW3_3 will rise at the same time (connected on board)

2.DPWROK and RSMRST# will rise at the same time (connected on board)

3.SLP_SUS# and SUSACK# are left as ‘no connect’

4.SUSWARN# used as SUSPWRDNACK/GPIO30

PM_RSMRST#

RTC_AUX_S5

SB modify

RSMRST#_KBC 27

3V_5V_POK 41

DSWODVREN - On Die DSW VR Enable

HIGH Enabled (DEFAULT)

LOW Disabled

R1917 330KR2J-L1-GPR1917 330KR2J-L1-GP

1 2

DSWODVREN

PM_CLKRUN#

2

R1918 Do Not Stuff

1 2

DY

R1919

R1919 8K2R2J-3-GP

8K2R2J-3-GP

1 2

HR UMA

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Thursday, December 02, 2010

Date: Sheet

RTC_AUX_S5

3D3V_S0

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

PCH (DM I/FDI/PM)

JE40-HR

1

of

19 102

-1

5

SSID = PCH

D D

C C

B B

A A

PCIE_RXN265

PCIE_RXP265 PCIE_TXN265 PCIE_TXP265

PCIE_RXN431

PCIE_RXP431 PCIE_TXN431 PCIE_TXP431

PCIE_RXN582

PCIE_RXP582 PCIE_TXN582 PCIE_TXP582

C2001 SCD1U10V2KX-5GPC2001 SCD1U10V2KX-5GP

1 2

C2002 SCD1U10V2KX-5GPC2002 SCD1U10V2KX-5GP

1 2

C2005 SCD1U10V2KX-5GPC2005 SCD1U10V2KX-5GP

1 2

C2006 SCD1U10V2KX-5GPC2006 SCD1U10V2KX-5GP

1 2

C2009 SCD1U10V2KX-5GPC2009 SCD1U10V2KX-5GP

1 2

C2010 SCD1U10V2KX-5GPC2010 SCD1U10V2KX-5GP

1 2

JE40 delete New Card function

WWAN CLK

RN2012

RN2012 SRN0J-6-GP

SRN0J-6-GP

WLAN CLK

LAN CLK

USB3.0 CLK

3D3V_S0

RN2018

RN2018 SRN10KJ-5-GP

SRN10KJ-5-GP

1 2 3

CLK_PCIE_WLAN#65 CLK_PCIE_WLAN65

CLK_PCIE_LAN#31 CLK_PCIE_LAN31

CLK_PCIE_USB3#82

CLK_PCIE_USB382

PCIE_CLK_RQ2#

4

CLK_PCIE_WLAN_REQ#

2 3 1

RN2014

RN2014 SRN0J-6-GP

SRN0J-6-GP

2 3 1

RN2013

RN2013 SRN0J-6-GP

SRN0J-6-GP

2 3 1

PCIECLKRQ1# and PCIECLKRQ2# Support S0 power only

5

PCIE_TXN2_C PCIE_TXP2_C

PCIE_TXN4_C PCIE_TXP4_C

PCIE_TXN5_C PCIE_TXP5_C

CLK_PCIE_WWAN_REQ#

CLK_PCH_SRC1_N CLK_PCH_SRC1_P

4

CLK_PCIE_WLAN_REQ#65

PCIE_CLK_RQ2#

CLK_PCH_SRC3_N CLK_PCH_SRC3_P

4

PCIE_CLK_LAN_RQ#31

CLK_PCH_SRC4_N CLK_PCH_SRC4_P

4

USB3_PEGB_CLKREQ#82

PCIE_CLK_REQ5#

PEG_B_CLKRQ#

PCIE_CLK_REQ6#

CLK_PCIE_NEW_REQ#

4

PCH1B

BG34

BJ34 AV32 AU32

BE34

BF34 BB32 AY32

BG36

BJ36 AV34 AU34

BF36 BE36 AY34 BB34

BG37 BH37 AY36 BB36

BJ38 BG38 AU36 AV36

BG40

BJ40 AY40 BB40

BE38 BC38

AW38

AY38

Y40 Y39

J2

AB49 AB47

M1

AA48 AA47

V10

Y37 Y36

A8

Y43 Y45

L12

V45 V46

L14

AB42 AB40

E6

V40 V42

T13 V38

V37 K12

AK14 AK13

COUGAR-GP-U2-NF

– Prioritize 27/14/24/48/25-MHz FLEX on FLEX1 and FLEX3 – Do not configure 27/14/24/48/25-MHz FLEX clock on FLEX0 and FLEX2 if more than 2 PCI clocks + PCI loopback are routed.

4

Cougar

PERN1 PERP1

Point

PETN1

W-WAN

PETP1 PERN2

PERP2

WLAN

PETN2 PETP2

PERN3 PERP3

Card Reader

PETN3 PETP3

PERN4 PERP4

LAN

PETN4 PETP4

PERN5 PERP5

USB3.0

PETN5 PETP5

PERN6 PERP6

Intel GBE LAN

PETN6 PETP6

PERN7 PERP7

Dock

PETN7 PETP7

PERN8

NEW CARD

PERP8 PETN8 PETP8

CLKOUT_PCIE0N CLKOUT_PCIE0P

PCIECLKRQ0#/GPIO73

CLKOUT_PCIE1N CLKOUT_PCIE1P

PCIECLKRQ1#/GPIO18

CLKOUT_PCIE2N CLKOUT_PCIE2P

PCIECLKRQ2#/GPIO20

CLKOUT_PCIE3N CLKOUT_PCIE3P

PCIECLKRQ3#/GPIO25

CLKOUT_PCIE4N CLKOUT_PCIE4P

PCIECLKRQ4#/GPIO26

CLKOUT_PCIE5N CLKOUT_PCIE5P

PCIECLKRQ5#/GPIO44

CLKOUT_PEG_B_N CLKOUT_PEG_B_P

PEG_B_CLKRQ#/GPIO56

CLKOUT_PCIE6N CLKOUT_PCIE6P

PCIECLKRQ6#/GPIO45 CLKOUT_PCIE7N

CLKOUT_PCIE7P PCIECLKRQ7#/GPIO46 CLKOUT_ITPXDP_N

CLKOUT_ITPXDP_P

PCI-E*

CLOCKS

SMBALERT#/GPIO11

SML0ALERT#/GPIO60

SMBUSController

SML1ALERT#/PCHHOT#/GPIO74

SML1CLK/GPIO58

SML1DATA/GPIO75

Link

PEG_A_CLKRQ#/GPIO47

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKOUT_DP_N CLKOUT_DP_P

CLKIN_DMI_N

CLKIN_DMI_P

CLKIN_GND1_N CLKIN_GND1_P

CLKIN_DOT_96N CLKIN_DOT_96P

CLKIN_SATA_N

CLKIN_SATA_P

CLKIN_PCILOOPBACK

XCLK_RCOMP

CLKOUTFLEX0/GPIO64 CLKOUTFLEX1/GPIO65 CLKOUTFLEX2/GPIO66 CLKOUTFLEX3/GPIO67

FLEX CLOCKS

2 OF 10

SMBCLK

SMBDATA

SML0CLK

SML0DATA

CL_CLK1

CL_DATA1

CL_RST1#

REFCLK14IN

XTAL25_IN

XTAL25_OUT

3

E12 H14 C9

A12 C8 G12

C13 E14 M16

M7

T11

P10

M10

AB37 AB38

AV22 AU22

AM12 AM13

BF18 BE18

BJ30 BG30

G24 E24

AK7 AK5

K45

H45

V47 V49

Y47

K43 F47 H47 K49

3

SMB_CLK SMB_DATA

SML0_CLK SML0_DATA

PCH_GPIO74

JE40 modify

JE40 delete XDP function

For DIS_PX mode or MXM mode.

PEG_CLKREQ#_R

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLK_EXP_N 5 CLK_EXP_P 5

CLK_BUF_EXP_N CLK_BUF_EXP_P

CLK_BUF_CPYCLK_N CLK_BUF_CPYCLK_P

CLK_BUF_DOT96_N CLK_BUF_DOT96_P

CLK_BUF_CKSSCD_N CLK_BUF_CKSSCD_P

CLK_BUF_REF14

XTAL25_IN XTAL25_OUT

XCLK_RCOMP

DGPU_PRSNT#

CLK_48_USB30

1 2

R2007

R2007 90D9R2F-1-GP

90D9R2F-1-GP

1 2

EC_SWI# 27

DRAMRST_CNTRL_PCH 37

SML1_CLK 27,86 SML1_DATA 27,86

R2003

1 2

Do Not Stuff

2 3 1

4

RN2016

RN2016 SRN0J-6-GP

SRN0J-6-GP

2 3 1

RN2008

RN2008 SRN10KJ-5-GP

SRN10KJ-5-GP

CLK_PCI_FB 18

1D05V_VTT

RTS

R2002

R2002 Do Not Stuff

Do Not Stuff

SB

PEG_CLKREQ#_R

PEG_CLKREQ# 83

CLK_PCIE_VGA# 83 CLK_PCIE_VGA 83

4

CLK_BUF_REF14 CLK_BUF_CKSSCD_P CLK_BUF_CKSSCD_N

48MHZ_OUT 32

2

3D3V_S0

12

R2004

R2004 10KR2J-3-GP

10KR2J-3-GP

12

R2005

R2005 Do Not Stuff

Do Not Stuff

DY

SMB_DATA

Q2001

Q2001 2N7002KDW-GP

2N7002KDW-GP

84.2N702.A3F

2nd = 84.DM601.03F

SMB_CLK

RN2009

RN2009 SRN10KJ-L3-GP

SRN10KJ-L3-GP

1 2 3 4 5 6

need very close to PCH

CLK_48_USB30

Do Not Stuff

12

RFC2001

SB

DY

2

1

3D3V_S0

RN2007

RN2007 SRN2K2J-1-GP

SRN2K2J-1-GP

1 2 3

6 5

4

1 2 34

SMB_CLK SMB_DATA

SML0_DATA SML0_CLK

SML1_CLK SML1_DATA

PCH_GPIO74 PCIE_CLK_REQ6#

DRAMRST_CNTRL_PCH

4

4 2 3

1 1

2 3

1 2

CRB : 1K CEKLT: 10K

PCH_SMBDATA 14,15

PCH_SMBCLK 14,15

R2008 and C2008 CO-LAY

SC12P50V2JN-3GP

XTAL25_IN

R2006

R2006 1M1R2J-GP

1M1R2J-GP

XTAL25_OUT

3D3V_S0 3D3V_S0

12

R2012

10KR2J-3-GP

UMA_Muxless

12

R2010

Do Not Stuff

DIS_PX

10 9 8 7

HR UMA

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet

Date: Sheet

1 2

12

R2013

10KR2J-3-GP

DIS_UMA

DGPU_PRSNT#

12

R2011

Do Not Stuff

PX_Muxless

3D3V_S5

CLK_BUF_EXP_P CLK_BUF_EXP_N CLK_BUF_DOT96_N CLK_BUF_DOT96_P

PCH (PCI-E/SMBUS/CLOCK/CL)

JE40-HR

Thursday, December 02, 2010

JE40-HR

SC12P50V2JN-3GP

X2001

X2001 XTAL-25MHZ-102-GP

XTAL-25MHZ-102-GP

82.30020.851

2nd = 82.30020.791

1 2

SC12P50V2JN-3GP

UMA_DISCRETE# UMA: 1 1 DIS :0 1 SG(PX) : 0 0 Optimus(Muxless) : 1 0

UMA_DIS# 22

RN2001

RN2001 SRN10KJ-6-GP

SRN10KJ-6-GP

1 2 3 4 5

RN2002

RN2002 SRN10KJ-6-GP

SRN10KJ-6-GP

1 2 3 4 5

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

RN2003

1

SRN2K2J-1-GP

23

RN2004

23

SRN2K2J-1-GP

1

RN2005

RN2005 SRN2K2J-1-GP

SRN2K2J-1-GP

4

RN2006

4

SRN10KJ-5-GP

R2009

R2009 1KR2J-1-GP

1KR2J-1-GP

C2008

12

C2007

PCIE_CLK_LAN_RQ#

8 7

CLK_PCIE_WWAN_REQ#

6

USB3_PEGB_CLKREQ#

PCIE_CLK_REQ5#

8

CLK_PCIE_NEW_REQ#

7

PEG_B_CLKRQ#

6

EC_SWI#

of

20 102

3D3V_S5

-1

5

4

3

2

1

SSID = PCH

RTC_X1

1 2

R2101 10MR2J-L-GPR2101 10MR2J-L-GP

X2101

X2101 X-32D768KHZ-34GPU

X-32D768KHZ-34GPU

82.30001.661

D D

12

SC5P50V2CN-2GP

C C

+3VS_+1.5VS_HDA_IO

B B

+3VS_+1.5VS_HDA_IO

This signal has a weak internal pull down. On Die PLL VR is supplied by 1.5V when sampled high, 1.8 V when sampled low. Needs to be pulled High for Huron River platform. co-operate with R2310

A A

82.30001.661

2nd = 82.30001.B21

1

C2101

2 3

HDA_CODEC_SYNC29 HDA_CODEC_SDOUT29

HDA_CODEC_RST#29 HDA_CODEC_BITCLK29

1 2

5V_S0

HDA_CODEC_SYNC

4

DY

R2102

R2102 Do Not Stuff

Do Not Stuff

R2103

R2103 1KR2J-1-GP

1KR2J-1-GP

G

S

RTC_X2

SB SEIKO suggest modify to 5P

12

EPSON suggest modifyg to 6P

C2102

C2102 SC5P50V2CN-2GP

SC5P50V2CN-2GP

-1M

R2122

R2122 33R2J-2-GP

33R2J-2-GP

DY

R2123

R2123 33R2J-2-GP

33R2J-2-GP

1 2 3

RN2102

RN2102 SRN33J-5-GP-U

SRN33J-5-GP-U

Flash Descriptor Security Overide

HDA_SDOUT

HDA_SPKR

HDA_SYNC

-1M

HDA_SYNC_R HDA_SYNC

D

Q2101

Q2101 Do Not Stuff

Do Not Stuff

2ND = 84.2N702.031

5

12 12

4

No Reboot Strap

PLL ODVR VOLTAGE

RTC_AUX_S5

HDA_SYNC HDA_SDOUT

HDA_RST# HDA_BITCLK

Low = Default High = Enable

Low = Default High = No Reboot

Low = 1.8V (Default) High = 1.5V

2 3 1

RN2104

RN2104 SRN20KJ-GP-U

SRN20KJ-GP-U

C2104

SC1U6D3V2KX-GP

4

12

C2103

C2103 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

21

12

G2101

G2101 Do Not Stuff

Do Not Stuff

RTC Reset

ME_UNLOCK27

DY

1 2

INTVRMEN- Integrated SUS

1.05V VRM Enable High - Enable internal VRs Low - Enable external VRs

RTC_AUX_S5

HDA_SPKR29

HDA_SDIN029

?????

?

R2107

1 2

1KR2J-1-GP

SPI_CLK_R27,60 SPI_CS0#_R27,60

SPI_SI_R27,60

SPI_SO_R27,60

EC2102

DY

-1M

Do Not Stuff

R2124

R2124 Do Not Stuff

Do Not Stuff

1 2

HDA_SYNC: This strap is sampled on rising edge of RSMRST# and is used to sample 1.5V VccVRM supply mode. 1K external pull-up resistor is required on this signal on the board. Signal may have leakage paths via powered off devices (Audio Codec) and hence contend with the external pull-up. A blocking FET is recommended in such a case to isolate HDA_SYNC from the Audio Codec device until after the Strap sampling is complete.

4

Do Not Stuff

RTC_X1 RTC_X2 RTC_RST#

12

R2108

R2108 33R2J-2-GP

33R2J-2-GP

R2109

R2109 33R2J-2-GP

33R2J-2-GP

Do Not Stuff

SRTC_RST# SM_INTRUDER# PCH_INTVRMEN

HDA_BITCLK HDA_SYNC

HDA_RST#

PCH_JTAG_TCK_BUF

PCH_SPI_CLK PCH_SPI_CS0#

PCH_SPI_SI

1M1R2J-GP

R2104

1 2

R2105

330KR2F-L-GP

R2121

R2121 4K7R2J-2-GP

4K7R2J-2-GP

1 2 1 2

1 2

R2110 33R2J-2-GPR2110 33R2J-2-GP

EC2103

1 2

HDA_SDOUT

JE40 modify

SPI_CS0#_RHDA_CODEC_BITCLK HDA_CODEC_SDOUT

EC2101

1 2

DY

Do Not Stuff

3

PCH1A

A20

RTCX1

C20

RTCX2

D20

RTCRST#

G22

SRTCRST#

K22

INTRUDER#

C17

INTVRMEN

N34

HDA_BCLK

L34

HDA_SYNC

T10

SPKR

K34

HDA_RST#

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

C36

HDA_DOCK_EN#/GPIO33

N32

HDA_DOCK_RST#/GPIO13

J3

JTAG_TCK

H7

JTAG_TMS

K5

JTAG_TDI

H1

JTAG_TDO

T3

SPI_CLK

Y14

SPI_CS0#

T1

SPI_CS1#

V4

SPI_MOSI

U3

SPI_MISO

COUGAR-GP-U2-NF

Cougar

Cougar Point

Point

RTCIHDA

JTAG

SPI

1 OF 10

FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3

LPC

FWH4/LFRAME#

LDRQ0#

LDRQ1#/GPIO23

SERIRQ

SATA0RXN SATA0RXP SATA0TXN

SATA0TXP

SATA1RXN SATA1RXP

SATA 6G

SATA1TXN

SATA1TXP

SATA2RXN SATA2RXP SATA2TXN

SATA2TXP

SATA3RXN SATA3RXP SATA3TXN

SATA3TXP

SATA4RXN SATA4RXP SATA4TXN

SATA

SATA4TXP

SATA5RXN SATA5RXP SATA5TXN

SATA5TXP

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATALED# SATA0GP/GPIO21 SATA1GP/GPIO19

C38 A38 B37 C37

D36 E36

K36 V5

AM3 AM1 AP7 AP5

AM10 AM8 AP11 AP10

AD7 AD5 AH5 AH4

AB8 AB10 AF3 AF1

Y7 Y5 AD3 AD1

Y3 Y1 AB3 AB1

Y11 Y10

AB12 AB13

AH1

P3 V14 P1

PSW_CLR#22

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

SATA_DET#0

2

LPC_FRAME# 27,71

INT_SERIRQ 27

SATA_RXN0 56 SATA_RXP0 56 SATA_TXN0 56 SATA_TXP0 56

SATA_RXN4 56 SATA_RXP4 56 SATA_TXN4 56 SATA_TXP4 56

SATA_COMP

SATA3_COMP

RBIAS_SATA3

SATA_LED# 68

SATA_LED# INT_SERIRQ SATA_DET#0

LPC_AD[0..3] 27,71

HDD1 HDD2

ODD

ESATA

1D05V_VTT

R2112 37D4R2F-GPR2112 37D4R2F-GP

1 2

R2113 49D9R2F-GPR2113 49D9R2F-GP

1 2

R2114 750R2F-GPR2114 750R2F-GP

1 2

RN2103

RN2103 SRN10KJ-6-GP

SRN10KJ-6-GP

1 2 3 4 5

HR UMA

Title

PCH (SPI/RTC/LPC/SATA/IHDA)

Size Document Number Rev

Size Document Number Rev A3

A3

Thursday, December 02, 2010

Date: Sheet of

Date: Sheet

1D05V_VTT

3D3V_S0

8 7 6

JE40-HR

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

of

21 102

1

-1

5

4

3

2

1

3D3V_S0

RN2203

RN2203 SRN10KJ-5-GP

SRN10KJ-5-GP

1 2 3

GPIO27 has a weak[20K] internal pull up. To enable on-die PLL Voltage regurator, should not place external pull down.

D D

3D3V_S0

4

R2220

1 2

10KR2J-3-GP

H_RCIN# H_A20GATE

FFS_INT2_R SATA_ODD_PRSNT#

Note: For PCH debug with XDP, need to NO STUFF R2218

3D3V_S0

INTERNAL GFX EXTERNAL GFX

R2205 DY 10K

R2206 100K DY

C C

B B

GFX_CRB_DET

12

R2206

R2206 100KR2J-1-GP

100KR2J-1-GP

EC_SMI# DGPU_HPD_INTR# EC_SCI#

MFG_MODE FP_DET# S_GPIO PCH_TEMP_ALERT#

USB3_PWR_ON PCH_GPIO12 PCH_GPIO24

PCH_GPIO15

RN2201

RN2201 SRN10KJ-6-GP

SRN10KJ-6-GP

1 2 3 4 5

RN2202

RN2202 SRN10KJ-6-GP

SRN10KJ-6-GP

1 2 3 4 5

RN2204

RN2204 SRN10KJ-6-GP

SRN10KJ-6-GP

8 7 6

R2201

1 2

1KR2J-1-GP

Pass Word Clear

3D3V_S0

8 7 6

3D3V_S5

1 2 3 45

PSW_CLR#21

JE40 delete FP function

VRAM Frequency Pull high: 800MHZ

3D3V_S0

Pull low :900MHZ

12

R2218

R2218 10KR2J-3-GP

10KR2J-3-GP

UMA_VRAM800MHZ

A A

UMA_VRAM800MHZ

PCH_GPIO22

12

R2219

R2219 10KR2J-3-GP

10KR2J-3-GP

VRAM900MHZ

5

2G

1G_512M

3D3V_S0

SSID = PCH

EC_SCI#27

SATA_ODD_PRSNT#56

R2202

R2202 10KR2J-3-GP

10KR2J-3-GP

1 2

DGPU_PWROK92,93

0806 delete TP2202, TP2203

JE40 delete G Sensor

PCH_TEMP_ALERT#27

VRAM SizeSB

12

R2214

Do Not Stuff

12

R2215

Do Not Stuff

4

Do Not Stuff

Do Not Stuff Do Not Stuff

Do Not Stuff

21

12

R2216

1G

VRAM_SIZE1 VRAM_SIZE2

12

R2217

512M_2G

TP2202

TP2202 TP2203

TP2203

G2201

G2201 Do Not Stuff

Do Not Stuff

TP2210Do Not Stuff TP2210Do Not Stuff

TP2206Do Not Stuff TP2206Do Not Stuff

TP2208Do Not Stuff TP2208Do Not Stuff

TP2207Do Not Stuff TP2207Do Not Stuff TP2209Do Not Stuff TP2209Do Not Stuff

S_GPIO EC_SMI# DGPU_HPD_INTR#

ICC_EN# PCH_GPIO12 PCH_GPIO15

PCH_GPIO22 PCH_GPIO24

1

PCH_GPIO27

1

PLL_ODVR_EN

FP_DET# DMI_OVRVLTG FDI_OVRVLTG MFG_MODE GFX_CRB_DET FFS_INT2_R

USB3_PWR_ON

1

PCH_NCTF_1

1

PCH_NCTF_3

1

PCH_NCTF_2

1

PCH_NCTF_4

1

6 OF 10

PCH1F

T7

BMBUSY#/GPIO0

A42

TACH1/GPIO1

H36

TACH2/GPIO6

E38

TACH3/GPIO7

C10

GPIO8

C4

LAN_PHY_PWR_CTRL/GPIO12

G2

GPIO15

U2

SATA4GP/GPIO16

D40

TACH0/GPIO17

T5

SCLOCK/GPIO22

E8

GPIO24/MEM_LED

E16

GPIO27

P8

GPIO28

K1

STP_PCI#/GPIO34

K4

GPIO35

V8

SATA2GP/GPIO36

M5

SATA3GP/GPIO37

N2

SLOAD/GPIO38

M3

SDATAOUT0/GPIO39

V13

SDATAOUT1/GPIO48

V3

SATA5GP/GPIO49

D6

GPIO57

A4

NCTF_VSS#A4

A44

NCTF_VSS#A44

A45

NCTF_VSS#A45

A46

NCTF_VSS#A46

A5

NCTF_VSS#A5

A6

NCTF_VSS#A6

B3

NCTF_VSS#B3

B47

NCTF_VSS#B47

BD1

NCTF_VSS#BD1

BD49

NCTF_VSS#BD49

BE1

NCTF_VSS#BE1

BE49

NCTF_VSS#BE49

BF1

NCTF_VSS#BF1

BF49

NCTF_VSS#BF49

COUGAR-GP-U2-NF

Cougar

Cougar Point

Point

GPIO

NCTF

NCTF TEST PIN:

D1,D49,E1,E49,F1,F49

A4,A44,A45,A46,A5,A6,B3,B47,BD1,BD49,BE1,BE49,BF1,BF49

BG2,BG48,BH3,BH47,BJ4,BJ44,BJ45,BJ46,BJ5,BJ6,C2,C48

6 OF 10

TACH4/GPIO68 TACH5/GPIO69 TACH6/GPIO70 TACH7/GPIO71

A20GATE

PECI

RCIN#

PROCPWRGD

THRMTRIP#

CPU/MISC

INIT3_3V#

TS_VSS1 TS_VSS2 TS_VSS3 TS_VSS4

NC_1

NCTF_VSS#BG2

NCTF_VSS#BG48

NCTF_VSS#BH3

NCTF_VSS#BH47

NCTF_VSS#BJ4 NCTF_VSS#BJ44 NCTF_VSS#BJ45 NCTF_VSS#BJ46

NCTF_VSS#BJ5

NCTF_VSS#BJ6

NCTF_VSS#C2

NCTF_VSS#C48

NCTF_VSS#D1

NCTF_VSS#D49

NCTF_VSS#E1

NCTF_VSS#E49

NCTF_VSS#F1

NCTF_VSS#F49

C40 B41 C41 A40

P4 AU16 P5 AY11 AY10 T14

AH8 AK11 AH10 AK10 P37

BG2 BG48 BH3 BH47 BJ4 BJ44 BJ45 BJ46 BJ5 BJ6 C2 C48 D1 D49 E1 E49 F1 F49

PLL ON DIE VR ENABLE

NOTE:This signal has a weak internal pull-up 20K ENABLED -- HIGH (R2212 UNSTUFFED) DEFAULT DISABLED -- LOW (R2212 STUFFED)

3

SB add Zero ODD function

SATA_ODD_PWRGT 56

H_A20GATE 27

H_RCIN# 27 H_CPUPWRGD 5,36,97

SB

ֆࣨ

UMA_DIS# 20

1 2

PCH_THERMTRIP_R

check different , check need modify or not

VRAM_SIZE1 VRAM_SIZE2

H_PECI_R

PCH_THERMTRIP_R

check intel , R2204

TS Signal Disable Guideline: TS_VSS1, TS_VSS2, TS_VSS3 and TS_VSS4 should not float on the motherboard. They should be tied to GND directly.

FDI_OVRVLTG

12

R2208

R2208 10KR2J-3-GP

10KR2J-3-GP

DMI_OVRVLTG

12

R2210

R2210 10KR2J-3-GP

10KR2J-3-GP

Integrated Clock Enable functionality is achieved via soft-strap. The default is integrated clock enable.

ICC_EN#

12

R2211

R2211 1KR2J-1-GP

1KR2J-1-GP

GPIO8 has a weak[20K] internal pull up.

Integrated Clock Enable functionality is achieved via soft-strap. The default is integrated clock enable.

PLL_ODVR_EN

12

R2212

R2212 Do Not Stuff

Do Not Stuff

DY

2

R2203

R2203 Do Not Stuff

Do Not Stuff

DY

H_PECI 5,27

1 2

R2204

R2204 54D9R2F-L1-GP

54D9R2F-L1-GP

RN2205

RN2205 Do Not Stuff

Do Not Stuff

1 2 3

DY

SB

4

1D05V_VTT

H_THERMTRIP# 5,36

FDI TERMINATION VOLTAGE OVERRIDE

GPIO37 (FDI_OVRVLTG)

LOW - Tx, Rx terminated to same voltage (DC Coupling Model DEFAULT)

DMI TERMINATION VOLTAGE OVERRIDE

GPIO36 (DMI_OVRVLTG)

LOW - Tx, Rx terminated to same voltage (DC Coupling Model DEFAULT)

Integrated Clock Chip Enable

ICC_EN#

HIGH (R2211 DY)- DISABLED [DEFAULT]

LOW (R2211)- ENABLED

HR UMA

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Thursday, December 02, 2010

Date: Sheet

PCH (GPIO/CPU)

JE40-HR

1

of

22 102

-1

5

SSID = PCH

6A

1D05V_VTT

1.3A

(1uFx3)

D D

(10uFx1_0603)

12

C2301

SC10U6D3V5KX-1GP

12

C2302

SC1U6D3V2KX-GP

12

C2303

SC1U6D3V2KX-GP

JE40 modify 07/16

1D05V_VTT

2.925A(Total current of VCCIO)

(1uF x4)

C C

0.266A (Totally VCC3_3 current)

(0.1uF x1)

0.159A(Totally current of VCCVRM)

B B

12

DY

C2306

Do Not Stuff

12

3D3V_S0

12

C2308

C2307

C2308

SC1U6D3V2KX-GP

12

SC1U6D3V2KX-GP

C2310

C2310 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

-2 modify power net name

0806 check VCCAFDIPLL

0.042A (Totally current of VCCDMI)

12

C2304

1D05V_VTT

JE40 modify

12

C2309

VCCVRM_S0

1D05V_VTT

JE40 modify

4

AA23 AC23 AD21 AD23

SC1U6D3V2KX-GP

AF21

AF23 AG21 AG23 AG24 AG26 AG27 AG29

AJ23

AJ26

AJ27

AJ29

AJ31

AN19

BJ22

AN16 AN17

SC1U6D3V2KX-GP

AN21 AN26 AN27 AP21 AP23 AP24 AP26 AT24

AN33 AN34

BH29

AP16

BG6

AP17

AU20

PCH1G

Cougar

VCCCORE

Point

VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE

VCCIO

VCCAPLLEXP

VCCIO VCCIO

VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO

VCCIO VCCIO

VCC3_3

VCCVRM

VCCAFDIPLL

VCCIO

VCCDMI

COUGAR-GP-U2-NF

POWER

VCC CORE

VCCIO

FDI

CRTLVDS

VCCTX_LVDS VCCTX_LVDS VCCTX_LVDS VCCTX_LVDS

DMI

NAND / SPI HVCMOS

7 OF 10

VCCADAC

VSSADAC

VCCALVDS

VSSALVDS

VCC3_3

VCCVRM

VCCDMI

VCCCLKDMI

VccDFTERM

VCCSPI

3

+VCCA_DAC_1_2

U48

U47

UMA_PX_Muxless

+3VS_VCCA_LVDS

AK36 AK37

AM37 AM38 AP36 AP37

V33

V34

AT16

AT20

AB36

AG16

AG17

AJ16

AJ17

SCD1U10V2KX-5GP

V1

1 2

DIS

3D3V_S0

12

C2319

C2319 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

C2326

12

C2323

C2323 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

(0.1uF/0.01uF x1) (10uF x1_0603)

12

C2313

SCD01U16V2KX-3GP

UMA_PX_Muxless

DIS

R2303

R2303 Do Not Stuff

Do Not Stuff

0.06A

R2309

R2309 Do Not Stuff

Do Not Stuff

1 2

12

C2320

C2320 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

12

UMA_PX_Muxless

JE40 modify

0.02A

+1.05VS_VCC_DMI_CCI

12

C2321

SC1U6D3V2KX-GP

DY

12

0.02A

C2325

Do Not Stuff

C2322

C2322 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

3D3V_S5

(1uFx1)

R2301

R2301 Do Not Stuff

Do Not Stuff

1 2

12

C2315

C2314

SCD1U10V2KX-5GP

Do Not Stuff

DY

0.001A

+1.8VS_VCCTX_LVDS

12

C2316

C2317

SCD01U16V2KX-3GP

UMA_PX_Muxless

C2318

SCD01U16V2KX-3GP

Do Not Stuff

DY

1 2

-2 modify power net name

VCCVRM_S0

1D05V_VTT

(1uF x1)

L2303

L2303 IND-10UH-218-GP

IND-10UH-218-GP

1 2

68.10050.10Y

2nd = 68.10090.10B

1D8V_S0

0.19A

JE40 modify

SB ֆࣨsuggest delete 3D3V_S0, R2313 SPI only support 3D3V_S5

2

DIS

R2315

R2315 Do Not Stuff

Do Not Stuff

R2304

R2304 0R3J-0-U-GP

0R3J-0-U-GP

UMA_PX_Muxless

R2305

R2305 0R5J-5-GP

0R5J-5-GP

1 2

UMA_PX_Muxless

SC1U10V3KX-3GP

1D05V_VTT

(1uFx1) (10uFx1)

3D3V_S0

3D3V_DAC_S0

3D3V_S0

12

1D8V_S0

(0.01uF x2) (22uF x1)

C2328

U2301 for ANNIE flicker issue R2312 for don't flicker solution

3.3V CRT LDO

U2301

U2301 G9091-330T11U-GP

5V_S0

12

C2311

UMA_PX_Muxless

G9091-330T11U-GP

74.09091.J3F

2nd = 74.09198.G7F

1 2

SC1U10V2KX-1GP

UMA_PX_Muxless

-1M add LDO for VCCVRM_S0

3D3V_S0 VCCVRM_S01D5V_S0

U2302

U2302 G913CF-GP

G913CF-GP

74.00913.A3F

1

SHDN#

2

GND

3

12

DY

IN

DY

SC4D7U6D3V3KX-GP

Vout=1.25*(1+R1/R2)

Refer to NPCE795 shared SPI flash architecture

VIN

VOUT GND EN3NC#4

5

SET

4

OUT

C2329

1

3D3V_DAC_S0

5 4

12

UMA_PX_Muxless

SB add C2327

SC22P50V2JN-4GP

12

C2330

DY

SCD1U10V2KX-5GP

12

C2331

DY

C2331

DY

C2312

SC1U6D3V2KX-GP

12

R2316

R2316 2K8R2F-GP

2K8R2F-GP

DY

12

R2317

DY

10KR2J-3-GP

12

C2327

SC10U6D3V3MX-GP

The same BIOS SPI ROM power

A A

5

4

3

2

HR UMA

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Thursday, December 02, 2010

Date: Sheet

PCH (POWER1)

JE40-HR

1

of

23 102

-1

5

4

3

2

1

JE40 modify 07/16

PCH1J

SSID = PCH

(0.1uFx1)

(10uFx1) (1uFx1)

D D

C2402

SC1U10V2KX-1GP

1D05V_VTT

3D3V_S5

3D3V_S0

12

1D05V_VTT

JE40 modify

0.002A

JE40 modify

(10uFx1)

JE40 modify

1.01A (Total current of VCCASW)

12

C2403

C2404

SC10U6D3V5KX-1GP

C C

1D05V_VTT

B B

L2402

L2402 IND-10UH-218-GP

IND-10UH-218-GP

1 2

68.10050.10Y

2nd = 68.10090.10B

L2403

L2403 IND-10UH-218-GP

IND-10UH-218-GP

1 2

68.10050.10Y

2nd = 68.10090.10B

0.08A

+1.05VS_VCCA_A_DPL+1.05VS_VCCA_A_DPL

0.08A

+1.05VS_VCCA_B_DPL+1.05VS_VCCA_B_DPL

(1uFx1) (220uFx1)

12

C2409

C2409 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

(1uFx1) (220uFx1)

12

C2410

C2410 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

12

C2411

SCD1U10V2KX-5GP

JE40 modify 07/16

1D05V_VTT

(1uFx1)

SC1U6D3V2KX-GP

C2414

12

+VCCRTCEXT

SC10U6D3V5KX-1GP

0.16A (Totally current of VCCVRM

(0.1uFx1)

1D05V_VTT

0.055A

1D05V_VTT

(1uFx1)

1D05V_VTT

12

C2406

C2407

SC1U6D3V2KX-GP

(22uFx2_0603)

(1uFx3)

C2412

C2412 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

1 2

C2413

C2413 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

1 2

12

C2408

DY

Do Not Stuff

-1M

VCCVRM_S0

+1.05VS_VCCA_A_DPL +1.05VS_VCCA_B_DPL

JE40 modify

(1uFx1)

0.095A

JE40 modify

(1uFx1)

+VCCSST

12

(0.1uFx1)

C2415

C2415 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

JE40 modify

0.001A

(0.1uFx2)

A A

(4.7uFx1_0603)

RTC_AUX_S5

12

C2417

SC4D7U6D3V3KX-GP

12

C2418

SCD1U10V2KX-5GP

DY

C2419

Do Not Stuff

6uA

(0.1uFx2) (1uFx1)

5

12

C2420

C2420 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

4

PCH1J

AD49

VCCACLK

T16

VCCDSW3_3

V12

DCPSUSBYP

T38

VCC3_3

BH23

VCCAPLLDMI2

AL29

VCCIO

AL24

DCPSUS

AA19

VCCASW

AA21

VCCASW

AA24

VCCASW

AA26

VCCASW

AA27

VCCASW

AA29

VCCASW

AA31

VCCASW

AC26

VCCASW

AC27

VCCASW

AC29

VCCASW

AC31

VCCASW

AD29

VCCASW

AD31

VCCASW

W21

VCCASW

W23

VCCASW

W24

VCCASW

W26

VCCASW

W29

VCCASW

W31

VCCASW

W33

VCCASW

N16

DCPRTC

Y49

VCCVRM

BD47

VCCADPLLA

BF47

VCCADPLLB

AF17

VCCIO

AF33

VCCDIFFCLKN

AF34

VCCDIFFCLKN

AG34

VCCDIFFCLKN

AG33

VCCSSC

V16

DCPSST

T17

DCPSUS

V19

DCPSUS

BJ8

V_PROC_IO

A22

VCCRTC

COUGAR-GP-U2-NF

POWER

Cougar

Cougar Point

Point

Clock and Miscellaneous

PCI/GPIO/LPCMISC

SATA USB

CPURTC

HDA

3

10 OF 10

VCCIO VCCIO VCCIO VCCIO VCCIO

VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3

VCCIO

V5REF_SUS

DCPSUS

VCCSUS3_3

V5REF

VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3

VCC3_3 VCC3_3 VCC3_3

VCC3_3

VCCIO

VCCIO VCCIO

VCCIO

VCCAPLLSATA

VCCVRM

VCCIO VCCIO

VCCIO

VCCASW

VCCSUSHDA

N26 P26 P28 T27 T29

T23 T24 V23 V24 P24

T26

M26

AN23 AN24

P34

N20 N22 P20 P22

AA16 W16 T34

AJ2

AF13

AH13 AH14

AF14 AK1

AF11

AC16 AC17 AD17

T21

V21

T19

P32

1D05V_VTT

12

(1uFx1)

C2423

C2423 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

0.097A (Totally current of VCCSUS3_3)

12

C2424

C2424 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

12

C2425

C2425 SCD1U10V2KX-5GP

1D05V_VTT

+5VA_PCH_VCC5REFSUS

JE40 modify

3D3V_S5

+5VS_PCH_VCC5REF

JE40 modify

SCD1U10V2KX-5GP

JE40 modify

-1M modify power net name

VCCVRM_S0

JE40 modify

1D05V_VTT

JE40 modify

3D3V_S5

12

C2428

C2428 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

12

C2430

12

C2429

C2429 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

12

C2432

C2432 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

1D05V_VTT

(1uFx1)

12

C2435

C2435 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

+3VS_+1.5VS_HDA_IO

(1uFx1)

SCD1U10V2KX-5GP

JE40 modify 07/16

3D3V_S0

(0.1uFx2)

12

C2431

C2431 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

3D3V_S0

(0.1uFx1)

1D05V_VTT

(1uFx1)

JE40 modify 07/16

0.01A

(0.1uFx1)

12

C2433

C2433 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

2

3D3V_S5

(0.1uFx1)

3D3V_S5

(0.1uFx1)

0.001A

JE40 modify 07/16

3D3V_S5

D2401

21

Do Not Stuff

DY

Do Not Stuff

DY

2nd = 83.R2004.B8F

1 2

R2408

R2408 10R2J-2-GP

10R2J-2-GP

12

C2426

C2426 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

3D3V_S0

D2402

21

Do Not Stuff

DY

Do Not Stuff

DY

2nd = 83.R2004.B8F

1 2

R2407

R2407 10R2J-2-GP

12

3D3V_S5 1D5V_S5

3D3V_S5

12

C2436

Do Not Stuff

DY

+3VS_+1.5VS_HDA_IO

HR UMA

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Thursday, December 02, 2010

Date: Sheet

1 2

U2401

U2401 Do Not Stuff

Do Not Stuff

1

VIN

2

GND EN3NC#4

R2409 Do Not StuffR2409 Do Not Stuff

R2415 Do Not Stuff

R2413 Do Not Stuff

PCH (POWER2)

JE40-HR

10R2J-2-GP

C2427

C2427 SC1U10V2KX-1GP

SC1U10V2KX-1GP

R2414

R2414 Do Not Stuff

Do Not Stuff

DY

VOUT

-1M

1 2

DY

1 2

DY

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

DY

5 4

12

R2402

R2402 Do Not Stuff

Do Not Stuff

1

5V_S5

(0.1uFx1)

5V_S0

(1uFx1)

1D5V_S5

12

C2416

Do Not Stuff

DY

3D3V_S5

1D5V_S0

1D5V_S5

of

24 102

12

C2405

Do Not Stuff

-1

5

4

3

2

1

SSID = PCH

D D

C C

B B

A A

5

PCH1H

H5

VSS

AA17

VSS

AA2

VSS

AA3

VSS

AA33

VSS

AA34

VSS

AB11

VSS

AB14

VSS

AB39

VSS

AB4

VSS

AB43

VSS

AB5

VSS

AB7

VSS

AC19

VSS

AC2

VSS

AC21

VSS

AC24

VSS

AC33

VSS

AC34

VSS

AC48

VSS

AD10

VSS

AD11

VSS

AD12

VSS

AD13

VSS

AD19

VSS

AD24

VSS

AD26

VSS

AD27

VSS

AD33

VSS

AD34

VSS

AD36

VSS

AD37

VSS

AD38

VSS

AD39

VSS

AD4

VSS

AD40

VSS

AD42

VSS

AD43

VSS

AD45

VSS

AD46

VSS

AD8

VSS

AE2

VSS

AE3

VSS

AF10

VSS

AF12

VSS

AD14

VSS

AD16

VSS

AF16

VSS

AF19

VSS

AF24

VSS

AF26

VSS

AF27

VSS

AF29

VSS

AF31

VSS

AF38

VSS

AF4

VSS

AF42

VSS

AF46

VSS

AF5

VSS

AF7

VSS

AF8

VSS

AG19

VSS

AG2

VSS

AG31

VSS

AG48

VSS

AH11

VSS

AH3

VSS

AH36

VSS

AH39

VSS

AH40

VSS

AH42

VSS

AH46

VSS

AH7

VSS

AJ19

VSS

AJ21

VSS

AJ24

VSS

AJ33

VSS

AJ34

VSS

AK12

VSS

AK3

VSS

COUGAR-GP-U2-NF

Cougar

Cougar Point

Point

8 OF 10

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AK38 AK4 AK42 AK46 AK8 AL16 AL17 AL19 AL2 AL21 AL23 AL26 AL27 AL31 AL33 AL34 AL48 AM11 AM14 AM36 AM39 AM43 AM45 AM46 AM7 AN2 AN29 AN3 AN31 AP12 AP19 AP28 AP30 AP32 AP38 AP4 AP42 AP46 AP8 AR2 AR48 AT11 AT13 AT18 AT22 AT26 AT28 AT30 AT32 AT34 AT39 AT42 AT46 AT7 AU24 AU30 AV16 AV20 AV24 AV30 AV38 AV4 AV43 AV8 AW14 AW18 AW2 AW22 AW26 AW28 AW32 AW34 AW36 AW40 AW48 AV11 AY12 AY22 AY28

4

PCH1I

AY4

VSS

AY42

VSS

AY46

VSS

AY8

VSS

B11

VSS

B15

VSS

B19

VSS

B23

VSS

B27

VSS

B31

VSS

B35

VSS

B39

VSS

B7

VSS

F45

VSS

BB12

VSS

BB16

VSS

BB20

VSS

BB22

VSS

BB24

VSS

BB28

VSS

BB30

VSS

BB38

VSS

BB4

VSS

BB46

VSS

BC14

VSS

BC18

VSS

BC2

VSS

BC22

VSS

BC26

VSS

BC32

VSS

BC34

VSS

BC36

VSS

BC40

VSS

BC42

VSS

BC48

VSS

BD46

VSS

BD5

VSS

BE22

VSS

BE26

VSS

BE40

VSS

BF10

VSS

BF12

VSS

BF16

VSS

BF20

VSS

BF22

VSS

BF24

VSS

BF26

VSS

BF28

VSS

BD3

VSS

BF30

VSS

BF38

VSS

BF40

VSS

BF8

VSS

BG17

VSS

BG21

VSS

BG33

VSS

BG44

VSS

BG8

VSS

BH11

VSS

BH15

VSS

BH17

VSS

BH19

VSS

H10

VSS

BH27

VSS

BH31

VSS

BH33

VSS

BH35

VSS

BH39

VSS

BH43

VSS

BH7

VSS

D3

VSS

D12

VSS

D16

VSS

D18

VSS

D22

VSS

D24

VSS

D26

VSS

D30

VSS

D32

VSS

D34

VSS

D38

VSS

D42

VSS

D8

VSS

E18

VSS

E26

VSS

G18

VSS

G20

VSS

G26

VSS

G28

VSS

G36

VSS

G48

VSS

H12

VSS

H18

VSS

H22

VSS

H24

VSS

H26

VSS

H30

VSS

H32

VSS

H34

VSS

F3

VSS

COUGAR-GP-U2-NF

3

Cougar

Cougar Point

Point

9 OF 10

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 P16 M18 M22 M24 M30 M32 M34 M38 M4 M42 M46 M8 N18 P30 N47 P11 P18 T33 P40 P43 P47 P7 R2 R48 T12 T31 T37 T4 W34 T46 T47 T8 V11 V17 V26 V27 V29 V31 V36 V39 V43 V7 W17 W19 W2 W27 W48 Y12 Y38 Y4 Y42 Y46 Y8 BG29 N24 AJ3 AD47 B43 BE10 BG41 G14 H16 T36 BG22 BG24 C22 AP13 M14 AP3 AP1 BE16 BC16 BG28 BJ28

HR UMA

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Thursday, December 02, 2010

Date: Sheet of

Date: Sheet

2

Date: Sheet

PCH (VSS)

JE40-HR

25 102

1

-1

of

-1

5

D D

C C

4

3

2

1

B B

HR UMA

Wistron Corporation

A A

Title

Clock(colay)

Size Document Number Rev

Size Document Number Rev A4

A4

Thursday, December 02, 2010

Date: Sheet

5

4

3

Date: Sheet

2

Clock(colay)

JE40-HR

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

-1

26 102

of

1

-1

A

3D3V_AUX_KBC

0628 Modify: Move R2771 to closed 3D3V_AUX_KBC power

D D

12

C2701

SC2D2U10V3KX-1GP

12

C2704

rail base on layout placement.

12

C2706

C2705

DY

Do Not Stuff

SCD1U10V2KX-5GP

SB to -1 default active Low

JE40 delete USB Charger function

JE40 VGA_THRM

C C

0604 Modify: RN2704 pull-Low 10K Resistor to DY on BLUETOOTH_EN.

3D3V_S0

RN2708

RN2708 SRN10KJ-6-GP

SRN10KJ-6-GP

1 2 3

3D3V_AUX_KBC

4 5

RN2707

SRN100KJ-6-GP

1 2 3

R2770

1KR2J-1-GP

1 2

B B

EC_GPIO47 High Active

PROCHOT_EC

12

R2732

100KR2J-1-GP

AC_PRESENT19

PCIE_RST#

8

WIRELESS_LED_OFF#

7

HDMI_IN#

6

SB LID_CLOSE# can not pull high, because push pull suggest RN2708 Pin5 change FAN_TACH1

CHG_ON#

4

STOP_CHG#

AD_OFF

G

S

Q2702

Q2702 2N7002K-2-GP

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

12

C2707

DY

SCD1U10V2KX-5GP

AD_IA40

C2714 Do Not Stuff

1 2

DY

T8_THERM28

EC_GPIO9560

3G_EN66

SUS_PWR_ACK19

TP2715Do Not Stuff TP2715Do Not Stuff

SYS_THRM28

ALL_POWER_OK37,42,48

DC_BATFULL68

AD_OFF38

S5_ENABLE36,97

BAT_IN#39

LID_CLOSE#70

RSMRST#_KBC19

PM_SLP_S4#19,46

ME_UNLOCK21

DBC_EN49

WIFI_RF_EN65 BLUETOOTH_EN63,65 S0_PWR_GOOD19,42

WLAN_TEST_LED68

USB_PWR_EN#61,82

FAN_TACH1 28

H_PROCHOT#_EC

D

SSID = KBC

12

C2708

Do Not Stuff

DY

EC_GPIO95

12

C2712

C2712 SC1U10V3ZY-6GP

SC1U10V3ZY-6GP

C2709

Do Not Stuff

PCB_VER_AD ADT_TYPE

VGA_THRM

1

EC_GPIO6

AC_IN_KBC EC_ENABLE EC_GPIO72

DISCRETE#

KBC_VCORF

R2733

R2733 Do Not Stuff

Do Not Stuff

1 2

C2710

SCD1U10V2KX-5GP

U2701A

U2701A NPCE795PA0DX-GP-U

NPCE795PA0DX-GP-U

102

115

GND

5

116

4

AVCC

GPIO11/CLKRUN#

ECSCI#/GPIO54

GPIO10/LPCPD#

GPIO67/PWUREQ#

KBRST#/GPIO86

GPIO52/PSDAT3/RDY#

GPIO50/PSCLK3/TDO

GPIO27/PSDAT2 GPIO26/PSCLK2 GPIO35/PSDAT1 GPIO37/PSCLK1

F_SDI/F_SDIO1

F_SDIO/F_SDIO0

VCC19VCC46VCC76VCC88VCC

104

VREF

97

GPIO90/AD0

98

GPIO91/AD1

99

GPIO92/AD2

100

GPIO93/AD3

101

GPIO94/DA0

105

GPIO95/DA1

106

GPIO96/DA2

79

GPIO2

95

GPIO3/AD6

96

GPIO4/AD5

108

GPIO5/AD4

93

PSL_IN2#_GPIO6

94

GPIO7/AD7

114

GPIO16

6

GPIO24

109

GPIO30

14

GPIO34/CIRRXL

15

GPIO36

80

GPIO41

17

GPIO42/TCK

20

GPIO43/TMS

21

GPIO44/TDI

23

GPIO46/CIRRXM/TRST#

26

GPIO51

73

PSL_IN1_GPIO70

74

PSL_OUT_GPIO71

75

VBKUP

82

GPIO75

83

GPO76/SHBM

84

GPIO77

91

GPIO81

110

GPO82/IOX_LDSH/TEST#

112

GPIO84/IOX_SCLK/XORTR#

107

GPIO97

44

VCORF

GND18GND45GND78GND89GND

NOTE: Connect GND and AGND planes via either 0R resistor or one point layout connection.

EC_SPI_DI_C

12

R2773

R2773 100KR2J-1-GP

100KR2J-1-GP

0604 Modify: Add Pull down 100k ohm at F_SDI for Power consumption concern.

H_PROCHOT# 5,42

5

4

3D3V_S0

12

C2702

SCD1U10V2KX-5GP

1 OF 2

VDD

PLT_RST#_EC

7

LRESET#

2

LCLK

3

LFRAME#

GPIO65/SMI#

GPIO85/GA20

GPIO17/SCL1 GPIO22/SDA1 GPIO73/SCL2 GPIO74/SDA2 GPIO23/SCL3 GPIO31/SDA3 GPIO47/SCL4 GPIO53/SDA4

103

LPC_AD3

1

LAD3

LPC_AD2

128

LAD2

LPC_AD1

127

LAD1

LPC_AD0

126

LAD0

125

SERIRQ

8 9

ECSCI#_KBC

29 124

ECSWI#_KBC

123 121 122

27

PCIE_RST#

25 11 10 71 72

70 69 67 68 119 120

PROCHOT_EC

24 28

EC_SPI_CS#_C

90

F_CS0#

EC_SPI_CLK_C

92

F_SCK

EC_SPI_DI_C

86

EC_SPI_DO_C

87

AGND

NOTE: Locate resistors R2719 and R2722 close to the NPCE791L.

PURE_HW_SHUTDOWN#28,36

4

12

DY

10KR2J-3-GP

C2703

C2703 Do Not Stuff

Do Not Stuff

R2705

C2711

C2711 Do Not Stuff

Do Not Stuff

1 2

DY

1 2

12

R2735

R2735 Do Not Stuff

Do Not Stuff

INT_SERIRQ 21 PM_CLKRUN# 19 PANEL_BLEN 94

PCH_TEMP_ALERT# 22

H_A20GATE 22 H_RCIN# 22

BLON_OUT 49

WIRELESS_LED_OFF# 68 HDMI_IN# 51

TPDATA 69

BAT_SCL 39,40 BAT_SDA 39,40 SML1_CLK 20,86 SML1_DATA 20,86 CRT_DEC# 50

Wireless_SW 82

CHG_ON# 40

33R2J-2-GPR2736 33R2J-2-GPR2736

12

33R2J-2-GPR2719 33R2J-2-GPR2719

12

R2737 0R2J-2-GPR2737 0R2J-2-GP

12

R2722 33R2J-2-GPR2722 33R2J-2-GP

12

RN2709

RN2709 SRN10KJ-5-GP

SRN10KJ-5-GP

1

4

2 3

3D3V_AUX_KBC

12

R2724

R2724 64K9R2F-1-GP

64K9R2F-1-GP

-1M

PCB_VER_AD

PLT_RST# 5,18,31,36,65,66,71,82,97

CLK_PCI_KBC 18

LPC_FRAME# 21,71

LPC_AD[0..3] 21,71

12

R2726

R2726 100KR2F-L1-GP

100KR2F-L1-GP

0806 chagne GND

<------ TP

<------ BATTERY / CHARGER <------PCH / EDP

SB to -1

SPI_CS0#_R 21,60 SPI_CLK_R 21,60

SPI_SO_R 21,60

SPI_SI_R 21,60

ECRST#

PURE_HW_SHUTDOWN#

E

B

C

Q2701

Q2701 MMBT3906-4-GP

MMBT3906-4-GP

84.T3906.A11

2nd = 84.03906.F11

3

PCB VERSION A/D(PIN98) PULL-LOW RESISTOR

SA SB SC

-1

-1M Reserved

FAN_TACH128

PM_PWRBTN#19,97

TP2705Do Not Stuff TP2705Do Not Stuff

PM_SLP_S3#19,36,37,47,92 CHARGE_LED68

KBC_BEEP29TPCLK 69

BRIGHTNESS94

STOP_CHG#40

FAN1_PWM28

TP2709Do Not Stuff TP2709Do Not Stuff

1

STDBY_LED68

PWRLED68

JE40 delete AMP function

PCH_SUSCLK_KBC19

H_PECI5,22

1D05V_VTT

R2721 43R2J-GPR2721 43R2J-GP

1 2

R2720

1 2

Do Not Stuff

C2716 need very close to EC

Do Not Stuff

PURE_HW_SHUTDOWN#

Prevent BIOS data loss

12

C2715

DY

ADT_TYPE A/D(PIN99) PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE

90W 30W

40W 120W 0.82V33.0K Reserved

100.0K

1

E51_RxD65

E51_TxD65

U2702

U2702 Do Not Stuff

Do Not Stuff

1 2

GND RESET#

N/A65W

100.0K

10.0K

20.0K

47.0K

64.9K

FAN_TACH2

EC_GPIO33

ECRST#

PECI EC_VTT

12

C2716

SCD1U16V2KX-3GP

VCC

PULL-HIGH RESISTOR VOLTAGE

31

117

63 64

32

118

62 65 81 66 22 16

85

113 111

30 77

13 12

3D3V_AUX_S53D3V_AUX_S5

DY

3

10.0K

20.0K

33.0K

47.0K

64.9K

76.8

100.0K

U2701B

U2701B NPCE795PA0DX-GP-U

NPCE795PA0DX-GP-U

GPIO56/TA1 GPIO20/TA2 GPIO14/TB1 GPIO01/TB2

GPIO15/A_PWM GPIO21/B_PWM GPIO13/C_PWM GPIO32/D_PWM GPIO66/G_PWM GPIO33/H_PWM GPIO45/E_PWM GPIO40/F_PWM

VCC_POR#

GPIO87/CIRRXM/SIN_CR GPIO83/SOUT_CR/TRIST#

GPIO55/CLKOUT/IOX_DIN_DIO GPIO00/EXTCLK

PECI VTT

3.0V

2.75V

2.48V

2.24V

2.0V

1.87V

1.65VReserved

KBSOUT0/JENK#

KBSOUT4/JEN0#

KBSOUT9/SDP_VIS# KBSOUT10/P80_CLK

KBSOUT11/P80_DAT

KBSOUT12/GPIO64 KBSOUT13/GPIO63 KBSOUT14/GPIO62

KBSOUT15/GPIO61/XOR_OUT

GPIO60/KBSOUT16 GPIO57/KBSOUT17

EC GPIO standard PH/PL

3D3V_AUX_KBC

100.0K N/A

100.0K

3.3V 0V

0.3V

0.55V

1.06V

1.3VReserved 100.0K

EC_ENABLE

2 OF 2

KCOL0

53

KCOL1

52

KBSOUT1/TCK KBSOUT2/TMS

KBSOUT3/TDI

KBSOUT5/TDO

KBSOUT6/RDY#

KBSOUT7 KBSOUT8

RN2701

RN2701 SRN4K7J-8-GP

SRN4K7J-8-GP

2 3 1

RN2705

SRN10KJ-6-GP

1 2 3 4 5

KCOL2

51

KCOL3

50

KCOL4

49

KCOL5

48

KCOL6

47

KCOL7

43

KCOL8

42

KCOL9

41

KCOL10

40

KCOL11

39

KCOL12

38

KCOL13

37

KCOL14

36

KCOL15

35

KCOL16

34

KCOL17

33

KROW0

54

KBSIN0

KROW1

55

KBSIN1

KROW2

56

KBSIN2

KROW3

57

KBSIN3

KROW4

58

KBSIN4

KROW5

59

KBSIN5

KROW6

60

KBSIN6

KROW7

61

KBSIN7

BAT_SCL BAT_SDA

4

R2775

R2775 100KR2J-1-GP

100KR2J-1-GP

BAT_IN#

12

S5_ENABLE

8

ECRST#

7 6

Wireless_SW

SB to -1

65W_90W# High: 65W / Low 90W DISCRETE# High: UMA / Low: Discrete

2

R2767

R2767 Do Not Stuff

Do Not Stuff

1 2

DY

G

S

Q2705

Q2705 Do Not Stuff

Do Not Stuff

2ND = 84.2N702.031

1

ADT_TYPE DISCRETE#

2

3D3V_AUX_S5

RN2706

RN2706 Do Not Stuff

Do Not Stuff

KBC_ON#_R

D

PSL

PSL SOLUTION (Power Switch Control Logic)

PSL

1234

KBC_ON#_GATE

SB modify R2756 stuff, R2760 change DY

R2756

1 2

KCOL[0..16] 69

KCOL17 69

TP2701 Do Not StuffTP2701 Do Not Stuff

KROW[0..7] 69

RTC_AUX_S5

3D3V_AUX_S5

Do Not Stuff

1 2

DY

R2760

R2760 Do Not Stuff

Do Not Stuff

ڕ࣠ฝೈ

ECSWI#_KBC

R2758

3D3V_AUX_KBC

12

65W

12

90W

R2707

R2701

100KR2F-L1-GP

1 2

1

2

10KR2J-3-GP

Do Not Stuff

ECSCI#_KBC

R2759

R2759 Do Not Stuff

Do Not Stuff

3

DY

D2701

D2701 Do Not Stuff

Do Not Stuff

2nd = 83.BAT54.N81

3nd = 83.00054.T81

12

R2710

UMA

12

R2739

DIS_PX_Muxless

EC_SWI#20

EC_SCI#22

JE40 modify

SB EC_AGND , change GND

3D3V_AUX_S5

S

G

D

C2713

Do Not Stuff

12

D

PSL

3D3V_AUX_KBC

EC_GPIO72

KBC_PWRBTN#82

PLS function

AC_OK40

HR UMA

Title

Size Document Number Rev

Size Document Number Rev Custom

Custom

Custom Date: Sheet

Date: Sheet

1

Q2703

Q2703 Do Not Stuff

Do Not Stuff

2ND = 84.03413.A31

Do Not Stuff

૞ޏګ

0604 Modify: RN2704 pull-Low 10K Resistor to DY on BLUETOOTH_EN.

Thursday, December 02, 2010

3D3V_AUX_KBC

NO PSL SOLUTION

3D3V_AUX_S5

R2704

R2704 330KR2J-L1-GP

330KR2J-L1-GP

1 2

R2757

R2757 470R2J-2-GP

470R2J-2-GP

G2701

2 1

pull high 3D3V_AUX_S5

BLUETOOTH_EN

1 2

DY

R2774

R2774 Do Not Stuff

Do Not Stuff

R2768

R2768 Do Not Stuff

Do Not Stuff

AC_IN_KBC

1 2

12

R2769

R2769 100KR2J-1-GP

100KR2J-1-GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

KBC Nuvoton NPCE795

JE40-HR

1

R2772

1 2

Do Not Stuff

EC_GPIO6

12

DY

27 102

3D3V_AUX_S5

C2717

Do Not Stuff

-1

of

A

5

4

3

2

1

SSID = Thermal

12

C2801

DY

P2800_DXP

P2800_DXN

3D3V_S0

12

Do Not Stuff

C2802

SCD1U10V2KX-5GP

12

C2807

SC2200P50V2KX-2GP

D D

Q2801

Q2801 PMBS3904-1-GP

PMBS3904-1-GP

84.03904.L06

12

C C

R2808

DY

Do Not Stuff

3

2

Layout notice : Both DXN and DXP routing 10 mil trace width and 10 mil spacing.

12

C2806

C2806 SC470P50V3JN-2GP

SC470P50V3JN-2GP

1

2.System Sensor, Put on palm rest

Thermal sensor P2800

3D3V_DAC_S0

12

ADJ

12

R2804

226KR2F-GP

U2801

3D3V_S0

THERM_SYS_SHDN# ADJ

U2801 P2800EA1-GP

P2800EA1-GP

74.02800.A71

5

VCC

6

DXP

7

DXN

8

OTZ

1.H/W T8 Shutdown

SB to -1

R2803

R2803 107KR2F-GP

107KR2F-GP

SB modify R2803,R2804 setting

12

C2805

SCD1U10V2KX-5GP

4

TDR

3

TDL

2

GND

1

ADJ

SYS_THRM 27 T8_THERM 27

JE40 HR modify

Fan controller P2793

C2815

C2815 Do Not Stuff

Do Not Stuff

1 2

DY

FAN_TACH1_C

5V_S0

12

C2809

SC4D7U6D3V3KX-GP

FAN1_PWM_C

5V_S0

12

C2808

SCD1U10V2KX-5GP

4 3 2

1

5 6

FAN1

FAN1 ACES-CON4-4-GP

ACES-CON4-4-GP

20.F0765.004

2nd = 20.F1808.004

2nd = 20.F1808.004 3rd = 20.F1426.004

3rd = 20.F1426.004

*Layout* 15 mil

21

D2802

D2802 CH551H-30PT-GP

CH551H-30PT-GP

83.R5003.C8F

2ND = 83.R5003.H8H

3rd = 83.5R003.08F

3D3V_S0

R2807

R2807 Do Not Stuff

Do Not Stuff

1 2

DY

FAN_TACH127

D2801

D2801 CH551H-30PT-GP

CH551H-30PT-GP

83.R5003.C8F

2ND = 83.R5003.H8H

3rd = 83.5R003.08F

12

R2805

R2805 Do Not Stuff

Do Not Stuff

DY

21

FAN_TACH1_C

FAN1_PWM27

3rd = 83.5R003.08F

1 2

R2806

R2806 Do Not Stuff

Do Not Stuff

For PWM FAN

B B

3D3V_AUX_S5

1

12

Do Not Stuff

DY

3

DY

C2811

Do Not Stuff

THERM_SYS_SHDN#

2

D

Q2802

Q2802 2N7002K-2-GP

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

2

S

G

D2803

D2803 Do Not Stuff

Do Not Stuff

2ND = 83.BAT54.D81

3rd = 83.BAT54.S81

VGA Thermal sensor P2800

PURE_HW_SHUTDOWN#27,36

3rd = 83.BAT54.S81

12

R2812

DY

SMBUS modify to Page 84

A A

5

4

3

3D3V_S0

12

R2809

R2809 100KR2J-1-GP

100KR2J-1-GP

R2810

R2810 Do Not Stuff

Do Not Stuff

1 2

DY

1 2

R2811

R2811 Do Not Stuff

Do Not Stuff

HR UMA

Title

Thermal P2800/Fan Controllor P2793

Size Document Number Rev

Size Document Number Rev Custom

Custom

Custom Date: Sheet

Date: Sheet

3D3V_S0

IMVP_PWRGD 36,42

JE40-HR

Thursday, December 02, 2010

JE40-HR

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

of

28 102

of

28 102

of

28 102

1

-1

5

4

3

2

1

5V_S0

D D

-1 PVDD timeing vensor suggest ,

12

C2927

SC1U10V3KX-4GP

R2921

R2921 Do Not Stuff

Do Not Stuff

1 2

DY

1

EN

NC#5

2

GND VIN3VOUT

U2902

U2902 G9091-475T12U-GP

G9091-475T12U-GP

74.09091.F3F

2ND = 74.09198.A7F

Ꮑ૞ֺ

Ꮑ૞ᖄԵႯ

SB

C C

PD#

B B

CLOSE TO PIN38

A A

5

5 4

AVDDඡ,

3D3V_S05V_S0

1

23

RN2905

RN2905 Do Not Stuff

Do Not Stuff

4

SB

5VA_S0

12

C2928

Q2902

Q2902 Do Not Stuff

Do Not Stuff

D

.

AUD_AGND

AUD_HP1_JACK_R282 AUD_HP1_JACK_L282

SC10U10V5KX-2GP

.

...

.

...

AUD_SPK_R+82

AUD_SPK_R-82

AUD_SPK_L-82 AUD_SPK_L+82

12

C2910

SCD1U10V2KX-5GP

3D3V_S0

12

C2903

SC10U6D3V3MX-GP

ࠌش

PW 74.00545.079

HDA_SDIN021

HDA_CODEC_BITCLK21

HDA_CODEC_SDOUT21

3D3V_S0

G

S

DIGITAL

(include thermal pad) Spilt by DGND

EAPD

5V_S0

AUD_AGND

ALC271X-VB3-GR-GP

71.00271.A03

CLOSE TO PIN35

5V_S0

12

C2904

SCD1U10V2KX-5GP

EAPD PD#

1 2

EAPD

49 48 47 46 45 44 43 42 41 40 39 38 37

U2901

C2911

SC2D2U10V3KX-1GP

1 2

12

C2906

SC10U6D3V3MX-GP

R2915

1 2

22R2J-2-GP

R2914

1 2

33R2J-2-GP

DY

R2924

R2924 Do Not Stuff

Do Not Stuff

3D3V_S0

GND SPDIFO EAPD PVDD2 SPK-OUT-R+ SPK-OUT-RPVSS2 PVSS1 SPK-OUT-LSPK-OUT-L+ PVDD1 AVDD2 AVSS2

12

1

DVDD

CBP36CBN35CPVEE34HPOUT-R/PORT-I-R33HPOUT-L/PORT-I-L32MIC1-VREFO-L31MIC1-VREFO-R30MIC2-VREFO29LDO-CAP28VREF27AVSS126AVDD1

AUD_CBP

C2907

SCD1U10V2KX-5GP

װၲ

ACZ_BITCLK_AUDIO_+

3

4

5

7

2

6

PD#

BCLK

SDATA-OUT

GPIO1/DMIC-CLK

GPIO0/DMIC-DATA

MIC1-VREFO_L

CPVEE

AUD_CBN

HP_OUT_R_AUD

HP_OUT_L_AUD

R2922

R2922 2D2R3J-2-GP

2D2R3J-2-GP

1 2

G2901

1 2

Do Not Stuff

G2903

1 2

Do Not Stuff

AUD_3VD_R

AC97_DATIN

AUDIO_PC_BEEP

10

9

12

8

11

DVSS

SYNC

RESET#

DVDD-IO

SDATA-IN

LINE2-L/PORT-E-L

LINE2-R/PORT-E-R

MIC2-L/PORT-F-L

MIC2-R/PORT-F-R

MIC1-L/PORT-B-L MIC1-R/PORT-B-R LINE1-L/PORT-C-L

LINE1-R/PORT-C-R

25

MIC1-VREFO_R

MIC2V

VREF

LDO_CAP_AUDIO

AUD_AGND

CLOSE TO PIN1 and 9

R2925

R2925 Do Not Stuff

Do Not Stuff

1 2

R2902

R2902 0R2J-2-GP

0R2J-2-GP

1 2

DY

HDA_CODEC_SYNC 21

HDA_CODEC_RST# 21

12

C2909

Do Not Stuff

DY

PCBEEP

SENSE_A

SENSE_B

JDREF

MONO-OUT

ALC268_SENSE_A

13

LIN2-L_PORT-B

14

LIN2-R_PORT-B

15

MIC2-L_PORT-B

16

MIC2-R_PORT-B

17

ALC268_SENSE_B

18 19 20 21 22 23 24

ANALOG

5VA_S0

AUD_AGND

12

C2913

SCD1U10V2KX-5GP

AUD_AGND

CLOSE TO PIN34

C2912

12

SC2D2U10V3KX-1GP

RN2903

RN2904

SRN68J-5-GP

2 3 1

MIC2V

4

RN2903 SRN4K7J-8-GP

SRN4K7J-8-GP

4

HDA_CODEC_SDOUT

12

DY

3D3V_S0

1D5V_S0

MIC1-L_PORT-B MIC1-R_PORT-B

JDREF

12

R2909

R2909 20KR2F-L-GP

20KR2F-L-GP

1 23

HDA_CODEC_BITCLK

12

RFC2902

RFC2901

RFC2902

Do Not Stuff

DY

AUDIO_PC_BEEP

R2907 39K2R2F-L-GPR2907 39K2R2F-L-GP

1 2

R2908 20KR2F-L-GPR2908 20KR2F-L-GP

1 2

C2925 SC1U25V3KX-1-GPC2925 SC1U25V3KX-1-GP

1 2

C2924 SC1U25V3KX-1-GPC2924 SC1U25V3KX-1-GP

1 2

C2920 SC2D2U10V3KX-1GPC2920 SC2D2U10V3KX-1GP

1 2

C2919 SC2D2U10V3KX-1GPC2919 SC2D2U10V3KX-1GP

1 2

1 2 1 2

COMBO_MIC_JD#

R2920

1 2

20KR2F-L-GP

C2918 SC2D2U10V3KX-1GPC2918 SC2D2U10V3KX-1GP C2917 SC2D2U10V3KX-1GPC2917 SC2D2U10V3KX-1GP

CLOSE TO PIN19

C2916

1 2

SCD1U10V2KX-5GP

1 2

C2914

SC10U6D3V5KX-1GP

MIC_IN_R MIC_IN_L

3

CLOSE TO PIN39 and 46

12

C2921

SC1U6D3V2KX-GP

COMBO_MIC

AUD_HP1_JD# 82 EXT_MIC_JD# 82

CLOSE TO PIN18

AUD_MIC_L AUD_MIC_R

AUD_AGND

12

C2922

SC100P50V2JN-3GP

R2919

1 2

Do Not Stuff

12

R2906

4K7R2J-2-GP

COMBO_MIC_Q

12

C2926

Do Not Stuff

DY

AUD_AGND

INT_MIC1_R COMBO_MIC_R

2

RN2901

RN2901 SRN47K-2-GP-U

SRN47K-2-GP-U

4

RN2902

RN2902 SRN1KJ-4-GP

SRN1KJ-4-GP

4 5 3 2 1

R2926

R2926 10KR2J-3-GP

10KR2J-3-GP

R2904

1 23

G

KBC_BEEP_1AUDIO_BEEP SPKR_SB_1

COMBO_MIC_JD#

DS

Q2901

Q2901 BSS138-7F-GP

BSS138-7F-GP

84.00138.F31

2ND = 84.00138.H31

R2904 Do Not Stuff

Do Not Stuff

1 2 1 2

R2905

R2905 Do Not Stuff

Do Not Stuff

KBC_BEEP 27

HDA_SPKR 21

Max Vgs(th) 1.8V

AUD_AGND

INT_MIC_L_R 49,97

6 7

MIC_IN_L 82

8

MIC_IN_R 82

INT_MIC_L_R

12

HR UMA

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Thursday, December 02, 2010

Date: Sheet

MIC2V Ref voltage is 2.5V becasue Vgs(th)concern cann't use 2N702 for desing

MIC2V

R2917

R2917 2K2R2J-2-GP

2K2R2J-2-GP

1 2

COMBO_MIC 82

12

R2927

R2927 22K1R2F-L-GP

22K1R2F-L-GP

SB modify

AUD_AGND

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Audio Codec

JE40-HR

29 102

1

-1

of

-1

5

4

3

2

1

AUDIO OP AMPLIFIER

D D

JE40 delete AMP function

C C

B B

HR UMA

Wistron Corporation

A A

Title

Audio AMP

Size Document Number Rev

Size Document Number Rev A4

A4

Thursday, December 02, 2010

Date: Sheet

5

4

3

Date: Sheet

2

Audio AMP

JE40-HR

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

-1

30 102

of

1

-1