Wistron Gannet Schematic
A
B
C
D
E
PCB Layer Stackup
CLK GEN
3
CYPRESS
CY28331-2
4 4
31
1394
Gannet Block Diagram
4,5,6,7
AMD CPU
Athlon 64
DDR 333/400
200-PIN DDR SODIMM
UNBUFFERED
11,12,13
DDR SODIMM
UNBUFFERED
11,12,13
DDR SODIMM
Conn
17,18
LCD
TVOUT
22
21
32
2 SLOTS
Support
TypeIII
Power
Switch
5532V
PCMCIA I/F
31,32
RICOH
R5C554PCMCIA
2* Slot Cardbus
+
2* 1394 Ports
HyperTransport
6.4GB/S 16b/8b
8,9,10
VIA
K8T800
AGTL+ CPU I/F AGP 8x
VGA
ATI
M10-P
14,15,16
DDR-SDRAM
K4D263238A-GC36
LVDS
SVIDEO/COMP
AGP 8X
3 3
2 2
33
Mini-PCI
802.11a/b/g
10/100/Giga LAN
29,30
BCM4401/5705M
28
MDC
28
RJ11
PCI Bus / 33MHz
AC LINK
23,24,25
PCI
6-CH
AC97 2.1
8 bit V-LINK
66MHZ 8x/4x/2x
VIA
ATA 133
VT8235CE
ACPI 2.0
8xUSB 2.0
LPC I/F
ATA 133
USB 2.0
Card Reader
W83L518D-VD6
SD/MS/MMC/CF
42
RGB CRT
P EIDE
S EIDE
MediaBay
Socket
CRT
HDD
DVD/
CD-RW
USB x 4
21
26
26
DCBATOUT
28
Controller-HIP6301 Drive-ISL6207*2(2
Phase)
42
DCBATOUT
CONN
MIC IN
AC'97 CODEC
35,36
VT1612A
MP3
OZ263
34
NS SIO
PC87392
LPC Bus / 33MHz
40
KBC
M38859
FWH
SST-49LF040
STM-M50FW040
3937
5V_S3
3D3V_S5
DCBATOUT
2D5V_S3
VVGADDR
L1: Signal 1
For
L2: GND
High
L3: Signal 2
L4: VCC
Speed
L5: Signal 3
Trace
L6: GND
L7: Signal 4
L8: Signal 5
L1: Signal 1
L2: GND
For
L3: Signal 2
Low
L4: Signal 3
Speed
L5: VCC
Trace
L6: GND
L7: Signal 4
L8: Signal 5
Battery Charger
ATINY12/MAX1645
INPUTS
AD+
BAT+
OUTPUTS
DCBATOUT
SYSTEM DC/DC
MAX1999
INPUT
DCBATOUT
OUTPUT
5V_S5
,
3D3V_S5
+5V_UP_S5
DDR&VDDR DC/DC
MAX1715/CM8500
INPUT OUTPUT
VGA VCORE
VVGAEER
1D25V_SO
CPU V_CORE
INPUT
SYSTEM POWER
TPS5110/FDC653N/APL1117
G913C/LP2951ACM/FDS9412
INPUT
OUTPUT
VCC_CORE
OUTPUT
5V_S0
3D3V_S3
3D3V_S0
3D3V_LAN_S3
1D8V_S5
2D5V_S3
1D8V_S0
+5V_AUX_S5
2D5V_S0
1D5V_S0
44
45
46
47
48,49
1 1
LINE OUT
OP AMP
APA2020
A
FIR
TFDU6101E
414036
MAX3243
RS232
Transceiver
B
Parallel
Port
FDD
4041
LPC Debug
Board Conn
39
C
38 38 27
Touch
Pad
Int.
KB
Thermal
& Fan
G768D
Title
Size Document Number Rev
A3
D
Date: Sheet
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Block Diagram
Gannet
151Thursday, December 04, 2003
E
-1
of
6/12 EMI Bypass Cap.
J8 REVISION HISTORY
PCI RESOURCE TABLE
IDSEL
PCI IRQDEVICE REQ# / GNT#
3D3V_S0 3D3V_S0 3D3V_S0 3D3V_S0 3D3V_S0
12
C615
SCD1U10V2KX
3D3V_S0 3D3V_S0 3D3V_S0 3D3V_S0 3D3V_S0
12
C625
SCD1U10V2KX
3D3V_S0 3D3V_S0 3D3V_S0 3D3V_S0 3D3V_S0
12
C634
SCD1U10V2KX
3D3V_S0 3D3V_S0 3D3V_S0 3D3V_S0 3D3V_S0
12
C643
SCD1U10V2KX
3D3V_S0 3D3V_S03D3V_S03D3V_S0
12
C655
SCD1U10V2KX
5V_S0
12
C660
SCD1U10V2KX
12
C616
SCD1U10V2KX
12
C626
SCD1U10V2KX
12
C635
SCD1U10V2KX
12
C644
SCD1U10V2KX
12
C656
SCD1U10V2KX
12
C661
SCD1U10V2KX
12
C617
SCD1U10V2KX
12
C627
SCD1U10V2KX
12
C636
SCD1U10V2KX
12
C645
SCD1U10V2KX
12
C657
SCD1U10V2KX
12
C662
SCD1U10V2KX
5V_S0 5V_S05V_S0 5V_S0
12
C618
SCD1U10V2KX
12
C628
SCD1U10V2KX
12
C637
SCD1U10V2KX
12
C646
SCD1U10V2KX
12
C658
SCD1U10V2KX
12
C663
SCD1U10V2KX
12
12
12
12
12
C619
SCD1U10V2KX
C629
SCD1U10V2KX
C638
SCD1U10V2KX
C647
SCD1U10V2KX
C664
SCD1U10V2KX
5V_S0
12
C665
SCD1U10V2KX
1D5V_S0
12
C620
SCD1U10V2KX
VDD
12
C630
SCD1U10V2KX
3D3V_S0
12
C639
SCD1U10V2KX
1D2V_S0
12
C648
SCD1U10V2KX
12
C621
SCD1U10V2KX
12
C631
SCD1U10V2KX
12
C641
SCD1U10V2KX
12
C649
SCD1U10V2KX
VCC_CORE_S0
12
C659
SCD1U10V2KX
C623
SCD1U10V2KX
C633
SCD1U10V2KX
C642
SCD1U10V2KX
C650
SCD1U10V2KX
1D5V_S01D5V_S0
12
C624
SCD1U10V2KX
1D2V_HT0A_S0
12
C640
SCD1U10V2KX
1D2V_S0
12
C652
SCD1U10V2KX
12
C653
SCD1U10V2KX
12
1D5V_S0
12
VDDVDD
12
3D3V_S03D3V_S0
12
1D2V_S01D2V_S0 1D2V_S0 1D2V_S0
12
Mini-PCI
R5C554-CardBus A
R5C554-CardBus B
R5C554-IEEE 1394
VGA-ATI M10-P
BCM-5705M
C654
SCD1U10V2KX
AD21
AD22
AD22
AD22
P_INTF# P_REQ#0/P_GNT#0
P_INTB#
P_INTC#
P_INTD#
P_INTA#
AD23 P_INTE#
P_REQ#1/P_GNT#1
P_REQ#1/P_GNT#1
P_REQ#1/P_GNT#1
P_REQ#2/P_GNT#2
1D2V_S016,46
1D2V_HT0A_S04,8,10,50
1D2V_HT0B_S04,6
1D2V_LAN_S529
1D25V_S35,6,7,12,13,46,50
1D5V_S09,10,14,16,20,49
1D8V_S015,16,49,50
VVGADDR15,16,17,18,46,49
2D5V_S06,8,9,10,16,19,20,23,24,25,31,48,50
2D5V_S35,6,7,10,11,13,46,48,49,50
2D5V_S56,24,25
3D3V_S03,8,9,10,11,14,16,19,20,21,22,23,24,25,27,28,29,31,32,33,34,35,36,37,38,39,40,41,42,43,47,48,49,51
3D3V_S310,22,28,34,37,48
3D3V_S522,23,24,25,27,29,34,37,43,45,48,50,51
5V_S019,21,22,23,24,25,26,27,28,30,32,33,35,36,37,38,39,40,41,42,43,46,47,48,50,51
5V_S337,46,48,49
5V_S527,45,48,50,51
+5V_AUX_S534,43,49,50,51
+5V_UP_S522,43,44,48,49
DCBATOUT22,27,44,45,46,47,48,49
VCC_CORE_S07,47
AD+43,44
1D2V_S0
1D2V_HT0A_S0
1D2V_HT0B_S0
1D2V_LAN_S5
1D25V_S3
1D5V_S0
1D8V_S0
VVGADDR
2D5V_S0
2D5V_S3
2D5V_S5
3D3V_S0
3D3V_S3
3D3V_S5
5V_S0
5V_S3
5V_S5
+5V_AUX_S5
+5V_UP_S5
DCBATOUT
VCC_CORE_S0
AD+
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Title
REVISION HISTORY
Size Document Number Rev
A3
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
GANNET
251Thursday, December 04, 2003
-1
A
BLM21A121S
L20
1 2
3D3V_S0
L22
1 2
4 4
12
C254
SCD1U10V2MX-1
CONNECT TO CLKGEN PIN 42
BLM21A121S
12
C255
SCD1U10V2MX-1
CONNECT TO CLKGEN PIN 33
C285 SC33P50V2JN
1 2
1 2
1 2
Internal 100K pull-up VDD
3D3V_S0
R403 10KR2
1 2
63.10334.1D1
R429 DUMMY-R2
3 3
1 2
R353 10KR2
1 2
63.10334.1D1
R321 DUMMY-R2
1 2
R489 10KR2
1 2
63.10334.1D1
R490 DUMMY-R2
1 2
R487 DUMMY-R2
1 2
FS0 CLK33_NOTUS_CYPCISEL
FS1
FS2
FS3
C272 SC33P50V2JN
78.33034.1F1
CPUCLK6
CPUCLKJ6
GUICLK9
SIO_OSC24
APICCLKSB25
CLK14_SIO40
CLK48_USB23
SMBC_SB11,25,30
SMBD_SB11,25,30
Internal 100K pull-down
Input Configuration
FS1
2 2
*
1 1
FS2 FS0XPCI_HT#FS3
0
001
0
0
011
0
0
0
101
0
001
0
0
1
0
1
0
1
1
1
1
1
1
1
1111
1
A
X
00
X
010
X
X
010
X
X
011
X
11
001
10
00
X
X
10
X
X
11
X
X
10
X
0
X
CPU (MHz)
Hi-Z
133.9
166.9
200.9
100
133.33
166.66
200
105.0
110.0
210.0
240.0
270.0
233.3
266.7
300.0
B
LAYOUT: Connect grounds at single point.
3D3V_CLKVDDA_S0
C251
SC1000P50V
3D3V_CLKVDDF_S0
C252
SCD01U50V2ZY
78.10394.4F1
X2
X-14D318MHZ-1-U
82.30005.031
R324 15R3
R325 15R3
R405
R407 33R3
R322 33R3
R323 33R3
R488 33R3
R327 0R3-U
R326 0R3-U
XI_CLK
XO_CLK
1 2
1 2
DUMMY-R2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
12
C249
SC100P50V2JN
78.10134.1F1
C250
SC1000P50V
12
R394
DUMMY-R3
CPUCLK_CY
CPUCLKJ_CY
FS0
FS1
FS2
FS3
SMBC_CLK
SMBD_CLK
16
19
29
35
38
46
43
32
41
37
40
36
48
45
31
25
26
Internal 100K pull-up VDD
Clock Generator Output
PCI33_HT66 (MHz)
PCI33 (MHz)
Hi-Z Hi-Z
33.5 or 67.0
33.4 or 66.8
33.5 or 67.0
33.3 or 66.7
33.3 or 66.7
33.3 or 66.7
33.3 or 66.7
33.5
33.4
33.5
33.3
33.3
33.3
33.3
35.0 or 70.0 35.0
36.7 or 73.3
35.0 or 70.0
30.0 or 60.0
33.8 or 67.5
27.2 or 58.3
33.3 or 66.7
37.5 or 75.0
B
36.7
35.0
30.00
33.8
27.2
33.3
37.5
C132
SCD01U50V2ZY
C118
SCD01U50V2ZY
U31
2
VDD
9
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDA
VDDF
3
XIN
4
XOUT
CPUT0
CPUT1
CPUC0
CPUC1
1
FS0/REF0
FS1/REF1
FS2/REF2
USB/FS3
SCLK
SDATA
CY28331OC-2
C133
SCD01U50V2ZY
C117
SCD01U50V2ZY
Internal 100K pull-up VDD
All output Tri-state
Normal Hammer operation
C
3D3V_CLK_S0
C134
SCD01U50V2ZY
C116
SCD01U50V2ZY
PCI33_HT66_0/PCIHT66SEL0#
PCI33_HT66_1/PCIHT66SEL1#
C135
SCD01U50V2ZY
78.10394.4F1
C115
SCD01U50V2ZY
PCISEL/PCI33_5
PCI33_6/PCISTOP#
PCI33_HT66_2
PCI33_HT66_3
SRESET#/PD#
24_48MHZ/SEL#
Change to CY28331-2
71.95401.00I
C
PCI33_0
PCI33_1
PCI33_2
PCI33_3
PCI33_4
PCI33_7
PCI33_F
VSSF
VSSA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
*
L26
1 2
C259
SC4D7U10V5ZY
78.47593.411
CLK33_PCM_CY
13
CLK33_LAN_CY
14
CLK33_MINI_CY
17
CLK33_KBC_CY
18
CLK33_SIO_CY
21
PCISEL
22
PCISTP#_CY
24
CLK33_NOTUS_CY
12
CLK33_HT66SEL#0
6
CLK33_HT66SEL#1
7
PCI33_HT66_2
8
PCI33_HT66_3
11
CLK33_SB_CY
23
SRESET#/PD#
44
CLK_24_48SEL#
28
33
42
5
10
15
20
27
30
34
39
47
PCISEL
0
1
PCIHT66 SEL[1:0]#
SEL1 SEL0
0
*
0
10
11
3D3V_S03D3V_S0
BLM21A121S
PIN22
PCI33_6
PCISTOP#
0
1
D
R361 22R3
1 2
R362 22R3
1 2
R422 22R3
1 2
R423 22R3
1 2
R424 22R3
1 2
R425 22R3
1 2
R426 22R3
1 2
R428 22R3
1 2
R421 22R3
1 2
R409 22R3
1 2
R413 22R3
1 2
R420 22R3
1 2
R427 22R3
1 2
24_48 SEL# 24_48MHz
0
*
1
PCI33_HT66[3:0]
PIN6 PIN7
HT66 HT66 HT66 HT66
HT66HT66
PCI33 PCI33 PCI33
HT66
D
E
3D3V_S02,8,9,10,11,14,16,19,20,21,22,23,24,25,27,28,29,31,32,33,34,35,36,37,38,39,40,41,42,43,47,48,49,51
CLK33_PCM_CARD 42
CLK33_PCM 31
CLK33_LAN 29
CLK33_MINI 33
CLK33_KBC 37
CLK33_SIO 40
CLK33_LPCROM 39
PCISTP# 24
CLK33_NOTUS 34
CLK66_NB 9
CLK66_VGA 14
CLK66_VCLK 25
CLK33_SB 25
1 2
R363 22R3
Modify-0606
For ICS CLKGEN use
Internal 100K pull-up VDD
R368 DUMMY-R2
CLK33_HT66SEL#0
48MHz
CLK33_HT66SEL#1
24MHz
PCISEL
SRESET#/PD#
PIN8 PIN11
PCI33HT66HT66HT66
PCI33PCI33
Title
Size Document Number Rev
A3
Date: Sheet
Internal 100K pull-down
CLK_24_48SEL#
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
CLKGEN_CY28331
Gannet
1 2
1 2
R367 10KR2
R370 DUMMY-R2
1 2
R377 10KR2
1 2
R376 DUMMY-R2
1 2
R491 10KR2
1 2
R492 DUMMY-R2
1 2
R350
1 2
DUMMY-R2
351Thursday, December 04, 2003
E
1 2
3D3V_S0
3D3V_S0
R374 10KR2
3D3V_S0
-1
of
A
LAYOUT: Close to CPU within 1 inch
#24665 PG:135
1D2V_HT0A_S0
4 4
12
C25
SCD22U10V3KX
78.22423.2B1
Between CPU and NB
1D2V_HT0A_S0
12
C28
SCD22U10V3KX
78.22423.2B1
3 3
12
C27
SCD22U10V3KX
78.22423.2B1
12
C29
SCD22U10V3KX
78.22423.2B1
12
C587
SCD22U10V3KX
78.22423.2B1
12
C33
SCD22U10V3KX
78.22423.2B1
NB0CADOUT[15..0]8
NB0CADOUTJ[15..0]8
12
C588
SCD22U10V3KX
78.22423.2B1
12
C34
SCD22U10V3KX
78.22423.2B1
11/11 add SCD22U
for AMD suggest.
C586
SCD1U16V
Used SideB Power Plane
2 2
1D2V_HT0B_S0
NB0HTTCLKOUT18
NB0HTTCLKOUTJ18
NB0HTTCLKOUT08
NB0HTTCLKOUTJ08
NB0HTTCTLOUT8
NB0HTTCTLOUTJ8
R796 49D9R3F
1 2
R795 49D9R3F
1 2
B
Clawhammer HT Interface
HTT for CPU sideA
Transmit power
and NB sideA Receive
power
1D2V_HT0A_S0
NB0CADOUT15
NB0CADOUTJ15
NB0CADOUT14
NB0CADOUTJ14
NB0CADOUT13
NB0CADOUTJ13
NB0CADOUT12
NB0CADOUTJ12
NB0CADOUT11
NB0CADOUTJ11
NB0CADOUT10
NB0CADOUTJ10
NB0CADOUT9
NB0CADOUTJ9
NB0CADOUT8
NB0CADOUTJ8
NB0CADOUT7
NB0CADOUTJ7
NB0CADOUT6
NB0CADOUTJ6
NB0CADOUT5
NB0CADOUTJ5
NB0CADOUT4
NB0CADOUTJ4
NB0CADOUT3
NB0CADOUTJ3
NB0CADOUT2
NB0CADOUTJ2
NB0CADOUT1
NB0CADOUTJ1
NB0CADOUT0
NB0CADOUTJ0
NB0HTTCLKOUT1
NB0HTTCLKOUTJ1
NB0HTTCLKOUT0
NB0HTTCLKOUTJ0
CPUHTTCTLIN1
CPUHTTCTLINJ1
NB0HTTCTLOUT
NB0HTTCTLOUTJ
D29
D27
D25
C28
C26
B29
B27
T25
R25
U27
U26
V25
U25
W27
W26
AA27
AA26
AB25
AA25
AC27
AC26
AD25
AC25
T27
T28
V29
U29
V27
V28
Y29
W29
AB29
AA29
AB27
AB28
AD29
AC29
AD27
AD28
Y25
W25
Y27
Y28
R27
R26
T29
R29
U20A
VLDT0_A
VLDT0_A
VLDT0_A
VLDT0_A
VLDT0_A
VLDT0_A
VLDT0_A
L0_CADIN_H15
L0_CADIN_L15
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H0
L0_CADIN_L0
L0_CLKIN_H1
L0_CLKIN_L1
L0_CLKIN_H0
L0_CLKIN_L0
L0_CTLIN_H1
L0_CTLIN_L1
L0_CTLIN_H0
L0_CTLIN_L0
BGA754-SKT-U
62.10030.041
C
VLDT0_B
VLDT0_B
VLDT0_B
VLDT0_B
VLDT0_B
VLDT0_B
VLDT0_B
L0_CADOUT_H15
L0_CADOUT_L15
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H0
L0_CADOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
AH29
AH27
AG28
AG26
AF29
AE28
AF25
N26
N27
L25
M25
L26
L27
J25
K25
G25
H25
G26
G27
E25
F25
E26
E27
N29
P29
M28
M27
L29
M29
K28
K27
H28
H27
G29
H29
F28
F27
E29
F29
J26
J27
J29
K29
N25
P25
P28
P27
HTT for CPU sideB
Receive power
and NB sideA
Transmit power
1D2V_HT0B_S0
CPUCADOUT15
CPUCADOUTJ15
CPUCADOUT14
CPUCADOUTJ14
CPUCADOUT13
CPUCADOUTJ13
CPUCADOUT12
CPUCADOUTJ12
CPUCADOUT11
CPUCADOUTJ11
CPUCADOUT10
CPUCADOUTJ10
CPUCADOUT9
CPUCADOUTJ9
CPUCADOUT8
CPUCADOUTJ8
CPUCADOUT7
CPUCADOUTJ7
CPUCADOUT6
CPUCADOUTJ6
CPUCADOUT5
CPUCADOUTJ5
CPUCADOUT4
CPUCADOUTJ4
CPUCADOUT3
CPUCADOUTJ3
CPUCADOUT2
CPUCADOUTJ2
CPUCADOUT1
CPUCADOUTJ1
CPUCADOUT0
CPUCADOUTJ0
CPUHTTCLKOUT1
CPUHTTCLKOUTJ1
CPUHTTCLKOUT0
CPUHTTCLKOUTJ0
CPUHTTCTLOUT1
CPUHTTCTLOUTJ1
CPUHTTCTLOUT0
CPUHTTCTLOUTJ0
D
C578
SCD1U16V
CPUCADOUT[15..0] 8
CPUCADOUTJ[15..0] 8
Used SideA Power Plane
CPUHTTCLKOUT1 8
CPUHTTCLKOUTJ1 8
CPUHTTCLKOUT0 8
CPUHTTCLKOUTJ0 8
CPUHTTCTLOUT0 8
CPUHTTCTLOUTJ0 8
E
1D2V_HT0A_S0
1D2V_HT0A_S02,8,10,50
1D2V_HT0B_S06
LAYOUT: Place bypass cap on topside of board near
HTT power pins that are not connected directly to
downstream HTT device, but connected internally to
other HTT power pins.
1D2V_HT0B_S0
C576
SC4D7U10V5ZY
78.47593.411
CPUHTTCTLOUT1
CPUHTTCTLOUTJ1
TP176
TP177
1D2V_HT0B_S0
1 1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Title
Size Document Number Rev
A3
A
B
C
D
Date: Sheet
CPU(1/4)_HyperTransport I/F
Taipei Hsien 221, Taiwan, R.O.C.
Gannet
451Thursday, December 04, 2003
-1
E
of
A
Clawhammer DDR Interface
4 4
VREF_DDR_MEM
NOTE: Test with passive probes only.
NOTE: Install to bypass op-amp
2D5V_S3
12
R388
100R3
3 3
12
R312
100R3
NOTE: Remove to bypass op-amp
2 2
VREF_DDR_CLAW
1 1
1D25V_S3
12
R364
DUMMY-R2
12
C100
SCD1U10V2MX-1
LAYOUT: Locate close to DIMMs.
2D5V_S3 1D25V_S3
12
12
12
R660
100R3
R641
100R3
R659
DUMMY-R2
12
C486
SCD1U10V2MX-1
LAYOUT: Locate close to CPU.
A
VREF_DDR_MEM
C103
SC1000P50V
VREF_DDR_CLAW
C497
SC1000P50V
B
DDRVTT_SENSE46
VREF_DDR_CLAW
2D5V_S3
R644 44D2R3F
1 2
R653 44D2R3F
1 2
M_DATA[63..0]12
M_ADM[8..0]12
M_DQS[8..0]12
B
DDRVTT_SENSE
MEMZN
MEMZP
M_DATA63
M_DATA62
M_DATA61
M_DATA60
M_DATA59
M_DATA58
M_DATA57
M_DATA56
M_DATA55
M_DATA54
M_DATA53
M_DATA52
M_DATA51
M_DATA50
M_DATA49
M_DATA48
M_DATA47
M_DATA46
M_DATA45
M_DATA44
M_DATA43
M_DATA42
M_DATA41
M_DATA40
M_DATA39
M_DATA38
M_DATA37
M_DATA36
M_DATA35
M_DATA34
M_DATA33
M_DATA32
M_DATA31
M_DATA30
M_DATA29
M_DATA28
M_DATA27
M_DATA26
M_DATA25
M_DATA24
M_DATA23
M_DATA22
M_DATA21
M_DATA20
M_DATA19
M_DATA18
M_DATA17
M_DATA16
M_DATA15
M_DATA14
M_DATA13
M_DATA12
M_DATA11
M_DATA10
M_DATA9
M_DATA8
M_DATA7
M_DATA6
M_DATA5
M_DATA4
M_DATA3
M_DATA2
M_DATA1
M_DATA0
M_ADM8
M_ADM7
M_ADM6
M_ADM5
M_ADM4
M_ADM3
M_ADM2
M_ADM1
M_ADM0
M_DQS8
M_DQS7
M_DQS6
M_DQS5
M_DQS4
M_DQS3
M_DQS2
M_DQS1
M_DQS0
AE13
AG12
D14
C14
A16
B15
A12
B11
A17
A15
C13
A11
A10
C11
AC1
AC3
AC2
AD1
AE1
AE3
AG3
AJ4
AE2
AF1
AH3
AJ3
AJ5
AJ6
AJ7
AH9
AG5
AH5
AJ9
AJ10
AH11
AJ11
AH15
AJ15
AG11
AJ12
AJ14
AJ16
A13
AA1
AG1
AH7
AH13
A14
AB1
AJ2
AJ8
AJ13
B9
C7
A6
A9
A5
B5
C5
A4
E2
E1
A3
B3
E3
F1
G2
G1
L3
L1
G3
J2
L2
M1
W1
W3
W2
Y1
R1
A7
C2
H1
T1
A8
D1
J1
U20B
VTT_SENSE
MEMVREF1
MEMZN
MEMZP
MEMDATA63
MEMDATA62
MEMDATA61
MEMDATA60
MEMDATA59
MEMDATA58
MEMDATA57
MEMDATA56
MEMDATA55
MEMDATA54
MEMDATA53
MEMDATA52
MEMDATA51
MEMDATA50
MEMDATA49
MEMDATA48
MEMDATA47
MEMDATA46
MEMDATA45
MEMDATA44
MEMDATA43
MEMDATA42
MEMDATA41
MEMDATA40
MEMDATA39
MEMDATA38
MEMDATA37
MEMDATA36
MEMDATA35
MEMDATA34
MEMDATA33
MEMDATA32
MEMDATA31
MEMDATA30
MEMDATA29
MEMDATA28
MEMDATA27
MEMDATA26
MEMDATA25
MEMDATA24
MEMDATA23
MEMDATA22
MEMDATA21
MEMDATA20
MEMDATA19
MEMDATA18
MEMDATA17
MEMDATA16
MEMDATA15
MEMDATA14
MEMDATA13
MEMDATA12
MEMDATA11
MEMDATA10
MEMDATA9
MEMDATA8
MEMDATA7
MEMDATA6
MEMDATA5
MEMDATA4
MEMDATA3
MEMDATA2
MEMDATA1
MEMDATA0
MEMDQS17
MEMDQS16
MEMDQS15
MEMDQS14
MEMDQS13
MEMDQS12
MEMDQS11
MEMDQS10
MEMDQS9
MEMDQS8
MEMDQS7
MEMDQS6
MEMDQS5
MEMDQS4
MEMDQS3
MEMDQS2
MEMDQS1
MEMDQS0
C
1D25V_S3
D17
VTT_A
A18
VTT_A
B17
VTT_A
C17
VTT_A
AF16
VTT_B
AG16
VTT_B
AH16
VTT_B
AJ17
VTT_B
MEMRESET_L
MEMCKEA
MEMCKEB
MEMCLK_H7
MEMCLK_L7
MEMCLK_H6
MEMCLK_L6
MEMCLK_H5
MEMCLK_L5
MEMCLK_H4
MEMCLK_L4
MEMCLK_H3
MEMCLK_L3
MEMCLK_H2
MEMCLK_L2
MEMCLK_H1
MEMCLK_L1
MEMCLK_H0
MEMCLK_L0
MEMCS_L7
MEMCS_L6
MEMCS_L5
MEMCS_L4
MEMCS_L3
MEMCS_L2
MEMCS_L1
MEMCS_L0
MEMRASA_L
MEMCASA_L
MEMWEA_L
MEMBANKA1
MEMBANKA0
NC_E13
NC_C12
MEMADDA13
MEMADDA12
MEMADDA11
MEMADDA10
MEMADDA9
MEMADDA8
MEMADDA7
MEMADDA6
MEMADDA5
MEMADDA4
MEMADDA3
MEMADDA2
MEMADDA1
MEMADDA0
MEMRASB_L
MEMCASB_L
MEMWEB_L
MEMBANKB1
MEMBANKB0
NC_E14
NC_D12
MEMADDB13
MEMADDB12
MEMADDB11
MEMADDB10
MEMADDB9
MEMADDB8
MEMADDB7
MEMADDB6
MEMADDB5
MEMADDB4
MEMADDB3
MEMADDB2
MEMADDB1
MEMADDB0
MEMCHECK7
MEMCHECK6
MEMCHECK5
MEMCHECK4
MEMCHECK3
MEMCHECK2
MEMCHECK1
MEMCHECK0
C
AG10
AE8
AE7
D10
C10
E12
E11
AF8
AG8
AF10
AE10
V3
V4
K5
K4
R5
P5
P3
P4
D8
C8
E8
E7
D6
E6
C4
E5
H5
D4
G5
K3
H3
E13
C12
E10
AE6
AF3
M5
AE5
AB5
AD3
Y5
AB4
Y3
V5
T5
T3
N5
H4
F5
F4
L5
J5
E14
D12
E9
AF6
AF4
M4
AD5
AC5
AD4
AA5
AB3
Y4
W5
U5
T4
M3
N3
N1
U3
V1
N2
P1
U1
U2
BGA754-SKT-U
62.10030.041
MEMRESET#
M_CKE#0
M_CKE#1
M_CLK7
M_CLK#7
M_CLK6
M_CLK#6
M_CLK5
M_CLK#5
M_CLK4
M_CLK#4
M_CLK3
M_CLK#3
M_CLK2
M_CLK#2
M_CLK1
M_CLK#1
M_CLK0
M_CLK#0
M_CS#7
M_CS#6
M_CS#5
M_CS#4
M_CS#3
M_CS#2
M_CS#1
M_CS#0
M_ARAS#
M_ACAS#
M_AWE#
M_ABS#1
M_ABS#0
RSVD_M_AA15
RSVD_M_AA14
M_AA13
M_AA12
M_AA11
M_AA10
M_AA9
M_AA8
M_AA7
M_AA6
M_AA5
M_AA4
M_AA3
M_AA2
M_AA1
M_AA0
M_BRAS#
M_BCAS#
M_BWE#
M_BBS#1
M_BBS#0
RSVD_M_BA15
RSVD_M_BA14
M_BA13
M_BA12
M_BA11
M_BA10
M_BA9
M_BA8
M_BA7
M_BA6
M_BA5
M_BA4
M_BA3
M_BA2
M_BA1
M_BA0
CB7
CB6
CB5
CB4
CB3
CB2
CB1
CB0
D
C151
SCD1U16V
For REGISTED DIMM Only
UNBUFFER DIMM NC
D
C515
SC1000P50V
M_CKE#0 12
M_CKE#1 12
M_CLK7 11,12
M_CLK#7 11,12
M_CLK6 11,12
M_CLK#6 11,12
M_CLK5 11,12
M_CLK#5 11,12
M_CLK4 11,12
M_CLK#4 11,12
M_CLK1 11,12
M_CLK#1 11,12
M_CLK0 11,12
M_CLK#0 11,12
M_CS#[3..0] 11,12
M_ARAS# 11,12
M_ACAS# 11,12
M_AWE# 11,12
M_ABS#1 11,12
M_ABS#0 11,12
M_AA[13..0] 11,12
11/11 AMD suggested M_AA13
connect to DIMM pin123
TP97
TP110
TP95
TP120
TP111
TP146
TP132
TP109
TP101
TP130
TP128
TP106
TP126
TP93
TP105
11/11 NOT SUPPORT ECC CHECK
TP123
TP122
AMD suggested remove PULL-HI
TP102
TP88
resistor.
TP89
TP52
TP90
TP94
TP40
TP53
TP69
TP91
Title
Size Document Number Rev
A3
Date: Sheet
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
CPU(2/4)_DDR
Gannet
E
VREF_DDR_MEM11
M_DQS8
M_ADM8
M_CLK3
M_CLK#3
M_CLK2
M_CLK#2
MEMZN
MEMZP
MEMRESET#
M_CS#7
M_CS#6
M_CS#5
M_CS#4
RSVD_M_AA15
RSVD_M_AA14
RSVD_M_BA15
RSVD_M_BA14
E
2D5V_S36,7,10,11,13,46,48,49,50
1D25V_S36,7,12,13,46,50
551Thursday, December 04, 2003
5V_S02,19,21,22,23,24,25,26,27,28,30,32,33,35,36,37,38,39,40,41,42,43,46,47,48,50,51
VREF_DDR_MEM
TP66
TP65
TP92
TP104
TP116
TP100
TP153
TP158
TP149
TP142
TP139
TP144
TP136
TP159
TP154
TP161
TP155
of
5V_S0
2D5V_S3
1D25V_S3
-1
A
4 4
2D5V_VDDA_S0
2D5V_VDDA_S02D5V_S0
Change
L270H
L49 MLB201209
1 2
12
C577
SCD1U16V
TC21
ST100U6D3V-U
77.21071.011
Need to check which should be used
3 3
5/12-->AMD Suggested
U87
PWROK_SB23,25,50
PWROK_NB#9,24
1
A
2
B
3 4
GND Y
NC7SZ08-U
VCC
5
HDT Connectors
2D5V_S0
2 2
DBREQJ
DBRDY
TCK
TMS
TDI
TRST_L
TDO
10/22 CHANGE FROM 1KR3 TO 680R2 FOR
AMD CHECK LIST
NC_AG17
NC_AJ18
NC_D18
NC_B19
1 1
NC_C19
NC_D20
NC_C21
12
C147
SCD1U16V
R152
680R2
R663 680R2
1 2
R676 680R2
1 2
R203 680R2
1 2
R182 680R2
1 2
R695 680R2
1 2
R724 680R2
1 2
R727 680R2
1 2
A
12
R168
680R2
12
R179
680R2
12
LAYOUT: Route trace 50 mils wide and
500 to 750 mils long between these
caps.
C575
SC4D7U10V5ZY
78.47593.411
1D2V_HT0B_S0
R786 44D2R3F
1 2
R784 44D2R3F
1 2
11/11 AMD suggest
voltege from 2D5V_S0 to
2D5V_S3
differentially impedance 100
2D5V_S5
PWROK
11/11 Add HDT connector
for AMD suggested
2D5V_S0
SCD1U16V
R205
680R2
12
R664
680R2
12
R679
680R2
C610
1
3
5
7
9
11
13
15
17
19
21
23
DUMMY-SMC-CONN26A-FP
ZZ.F0357.025
B
C
Clawhammer Control and Debug
LAYOUT: Route VDDA trace approx.
50 mils wide (use 2x25 mil traces to
exit ball field) and 500 mils long.
12
C569
SCD22U10V3KX
78.22423.2B1
C584
SC1000P50V
VDDIOSENSE46
CPUCLK3
CPUCLKJ3
10/22 CHANGE FROM 1KR3 TO 680R2 FOR
AMD CHECK LIST
1 2
C552
C559 SC3900P50V3KX
1 2
12
R791
680R2
CN4
64.44R25.551
2
4
6
8
10
12
14
16
18
20
22
24
26
C572
SC3300P50V3KX
C585
SC1000P50V
2D5V_S3
R731 820R3
1 2
1 2
R734 820R3
Validation Test Points
B
LAYOUT: Place close to the CPU.
CORE_SENSE
NC_C15
NC_AE23
NC_AF23
NC_AF22
NC_AF21
TP25
TP163
TP182
TP183
TP184
TP185
RST_CPU#
CLKIN
CLKINJ
CORE_SENSE
VDDIOFB
VDDIOFBJ
VDDIOSENSE
NC_AE24
NC_AF24
RST_CPU#23
HTT_STOP#8,25
COREFB47
COREFB#47
SC3900P50V3KX
NC_AJ23
NC_AH23
1D25V_S3
2D5V_S0
R196 680R2
1 2
R184 680R3
1 2
12
12
R793
R792
680R2
680R2
C
PWROK
L0_REF1
L0_REF0
COREFB
COREFB#
CORE_SENSE
VDDIOFB
VDDIOFBJ
VDDIOSENSE
CLKIN
12
R725
169R3F
64.16905.651
CLKINJ
NC_AE24
NC_AF24
DBRDY
NC_C15
TMS
TCK
TRST_L
TDI
NC_AE23
NC_AF23
NC_AF22
NC_AF21
12
R794
680R2
TP171
TP172
TP173
TP23
TP156
TP157
TP151
TP174
TP175
NC_C18
NC_A19
AH25
AJ25
AF20
AE18
AJ27
AF27
AE26
A23
A24
B23
AE12
AF12
AE11
AJ21
AH21
AJ23
AH23
AE24
AF24
C16
AG15
AH17
C15
E20
E17
B21
A21
C18
A19
A28
AJ28
AE23
AF23
AF22
AF21
AA2
AG2
B18
AH1
AE21
C20
AG4
AG6
AE9
AG9
C1
J3
R3
D3
C6
U20C
VDDA1
VDDA2
RESET_L
PWROK
LDTSTOP_L
L0_REF1
L0_REF0
COREFB_H
COREFB_L
CORE_SENSE
VDDIOFB_H
VDDIOFB_L
VDDIO_SENSE
CLKIN_H
CLKIN_L
NC_AJ23
NC_AH23
NC_AE24
NC_AF24
VTT_A
VTT_B
DBRDY
NC_C15
TMS
TCK
TRST_L
TDI
NC_C18
NC_A19
KEY1
KEY0
NC_AE23
NC_AF23
NC_AF22
NC_AF21
NC_C1
NC_J3
NC_R3
NC_AA2
NC_D3
NC_AG2
NC_B18
NC_AH1
NC_AE21
NC_C20
NC_AG4
NC_C6
NC_AG6
NC_AE9
NC_AG9
BGA754-SKT-U
62.10030.041
THERMTRIP_L
THERMDA
THERMDC
VID4
VID3
VID2
VID1
VID0
NC_AG18
NC_AH18
NC_AG17
NC_AJ18
FBCLKOUT_H
FBCLKOUT_L
DBREQ_L
NC_D20
NC_C21
NC_D18
NC_C19
NC_B19
TDO
NC_AF18
NC_D22
NC_C22
NC_B13
NC_B7
NC_C3
NC_K1
NC_R2
NC_AA3
NC_F3
NC_C23
NC_AG7
NC_AE22
NC_C24
NC_A25
NC_C9
D
THERMTRIP#
A20
A26
A27
AG13
AF14
AG14
AF15
AE15
AG18
AH18
AG17
AJ18
VID4
VID3
VID2
VID1
VID0
NC_AG18
NC_AH18
NC_AG17
NC_AJ18
THERMDP1 27
THERMDN 27
TP170
TP169
VID[4..0] 47
E
3D3V_S5
3D3V_S522,23,24,25,27,29,34,37,43,45,48,50,51
2D5V_S08,9,10,16,19,20,23,24,25,31,48,50
2D5V_S35,7,10,11,13,46,48,49,50
1D2V_HT0B_S04
VCC_CORE_S02,7,47
1D25V_S35,7,12,13,46,50
2D5V_S0
2D5V_S3
1D2V_HT0B_S0
VCC_CORE_S0
1D25V_S3
LAYOUT: Route FBCLKOUT_H/L
FBCLKOUT
AH19
AJ19
FBCLKOUTJ
AE19
D20
C21
D18
C19
B19
A22
AF18
D22
C22
B13
B7
C3
K1
R2
AA3
F3
C23
AG7
AE22
C24
A25
C9
D
DBREQJ
NC_D20
NC_C21
NC_D18
NC_C19
NC_B19
TDO
10/22 CHANGE VCC FROM 2D5V_S3 TO 2D5V_S0
differentially impedance 80
12
R678
80D6R3F-U
64.80R65.651
R688 DUMMY-R2
1 2
2D5V_S0
12
R763
680R3
THERMTRIP#
THERMTRIPJ Level shift to VT8235
EM_OFF PIN near VT8235
Title
Size Document Number Rev
Date: Sheet
CPU(3/4)_Control & Debug
A3
2
1
Gannet
3
Q63
MMBT3904-U1
NS3
R757 DUMMY-R3
NS2
1 2
2D5V_S0
1 2
R768 1KR3
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
651Thursday, December 04, 2003
E
EM_OFF 24
of
-1
A
Clawhammer Power and Ground Connections
B
C
D
E
1D25V_S3
1D25V_S35,6,12,13,46,50
2D5V_S3
2D5V_S35,6,10,11,13,46,48,49,50
VCC_CORE_S0
VCC_CORE_S02,47
4 4
3 3
2 2
1 1
Y17
K17
H17
F17
E18
AJ26
AE29
AC16
AA16
J16
G16
E16
AH14
AD15
AB15
K15
E15
D16
AE14
AC14
AA14
J14
G14
AF17
AD13
AB13
Y13
K13
H13
F13
AH12
AC12
AA12
G12
B12
AD11
AB11
Y11
K11
H11
F11
AH10
AC10
W10
U10
R10
N10
L10
J10
G10
B10
AD9
Y9
V9
P9
M9
K9
H9
AH8
AC8
W8
U8
R8
N8
G8
B8
AD7
AB7
V7
P7
M7
K7
H7
AH6
AC6
AA6
U6
R6
N6
G6
B6
AH4
B4
AH2
AD2
AB2
Y2
V2
P2
M2
C29
AH28
AF28
AC28
W28
R28
L28
U20E
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
T9
VSS
VSS
VSS
VSS
VSS
F9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
L8
VSS
J8
VSS
VSS
VSS
VSS
VSS
VSS
T7
VSS
VSS
VSS
VSS
VSS
F7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
L6
VSS
J6
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
T2
VSS
VSS
VSS
K2
VSS
H2
VSS
F2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
BGA754-SKT-U
62.10030.041
N20
VSS
L20
VSS
J20
VSS
AF19
VSS
AD19
VSS
AB19
VSS
Y19
VSS
K19
VSS
H19
VSS
F19
VSS
D19
VSS
AC18
VSS
AA18
VSS
G18
VSS
B16
VSS
AD17
VSS
AB17
VSS
H15
VSS
F15
VSS
G28
VSS
D28
VSS
B28
VSS
C27
VSS
AH26
VSS
AF26
VSS
AD26
VSS
Y26
VSS
T26
VSS
M26
VSS
H26
VSS
D26
VSS
B26
VSS
C25
VSS
B25
VSS
AJ24
VSS
AG24
VSS
AC24
VSS
AA24
VSS
W24
VSS
U24
VSS
R24
VSS
N24
VSS
J24
VSS
G24
VSS
E24
VSS
AG23
VSS
AD23
VSS
AB23
VSS
Y23
VSS
V23
VSS
T23
VSS
P23
VSS
K23
VSS
H23
VSS
F23
VSS
D23
VSS
AJ22
VSS
AH22
VSS
AG22
VSS
AC22
VSS
AA22
VSS
AG29
VSS
U22
VSS
R22
VSS
N22
VSS
L22
VSS
J22
VSS
G22
VSS
E22
VSS
B22
VSS
AG21
VSS
AD21
VSS
Y21
VSS
V21
VSS
T21
VSS
P21
VSS
M21
VSS
K21
VSS
H21
VSS
F21
VSS
D21
VSS
AJ20
VSS
AG20
VSS
AE20
VSS
AC20
VSS
AA20
VSS
W20
VSS
U20
VSS
R20
VSS
G20
VSS
J18
VSS
AE16
VSS
Y15
VSS
B14
VSS
J12
VSS
AA10
VSS
AB9
VSS
AA8
VSS
Y7
VSS
W6
VSS
AF2
VSS
D2
VSS
AG27
VSS
AG25
VSS
L24
VSS
M23
VSS
W22
VSS
AB21
VSS
AH20
VSS
B2
VSS
VCC_CORE_S0 2D5V_S3
AC15
AB14
AA15
AB16
AA17
AC17
AE17
AB18
AD18
AG19
AC19
AA19
AB20
AD20
AA21
AC21
AB22
AD22
AA23
AC23
AB24
AD24
AH24
AE25
H18
B20
E21
H22
J23
H24
F26
V10
G13
K14
Y14
G15
J15
H16
K16
Y16
G17
J17
F18
K18
Y18
E19
G19
J19
F20
H20
K20
M20
P20
T20
V20
Y20
G21
J21
L21
N21
R21
U21
W21
F22
K22
M22
P22
T22
V22
Y22
E23
G23
L23
N23
R23
U23
W23
B24
D24
F24
K24
M24
P24
T24
V24
Y24
K26
P26
V26
U20D
L7
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
N7
VDD
L9
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
BGA754-SKT-U
62.10030.041
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
E4
G4
J4
L4
N4
U4
W4
AA4
AC4
AE4
D5
AF5
F6
H6
K6
M6
P6
T6
V6
Y6
AB6
AD6
D7
G7
J7
AA7
AC7
AF7
F8
H8
AB8
AD8
D9
G9
AC9
AF9
F10
AD10
D11
AF11
F12
AD12
D13
AF13
F14
AD14
F16
AD16
D15
R4
N28
VDD
U28
VDD
AA28
VDD
AE27
VDD
R7
VDD
U7
VDD
W7
VDD
K8
VDD
M8
VDD
P8
VDD
T8
VDD
V8
VDD
Y8
VDD
J9
VDD
N9
VDD
R9
VDD
U9
VDD
W9
VDD
AA9
VDD
H10
VDD
K10
VDD
M10
VDD
P10
VDD
T10
VDD
Y10
VDD
AB10
VDD
G11
VDD
J11
VDD
AA11
VDD
AC11
VDD
H12
VDD
K12
VDD
Y12
VDD
AB12
VDD
J13
VDD
AA13
VDD
AC13
VDD
H14
VDD
AB26
VDD
E28
VDD
J28
VDD
VCC_CORE_S0
EMI
VCC_CORE_S0
C567
C564
78.6R834.1B1
SC6D8PF50VJ
SC6D8PF50VJ
LAYOUT: Place 1000pF capacitors
between VRM & CPU.
LAYOUT: Place in uPGA socket cavity.
VCC_CORE_S0
12
C75
VCC_CORE_S0
12
C529
VCC_CORE_S0
12
C106
VCC_CORE_S0
12
C548
12
C76
SCD22U10V3KX
12
C530
SCD22U10V3KX
12
C161
SCD22U10V3KX
12
C549
SCD22U10V3KX
0.22u x 9
12
12
12
C78
C77
C105
SCD22U10V3KX
SCD22U10V3KX
SCD22U10V3KX
LAYOUT: Place on backside of processor.
0.22u x 26
12
12
12
C502
C499
SCD22U10V3KX
12
C511
SCD22U10V3KX
12
C550
SCD22U10V3KX
SCD22U10V3KX
12
C516
SCD22U10V3KX
12
C535
SCD22U10V3KX
C589
12
C484
12
C518
SCD22U10V3KX
SCD22U10V3KX
SCD22U10V3KX
12
C160
SCD22U10V3KX
SCD22U10V3KX
12
C590
SCD22U10V3KX
SCD22U10V3KX
12
C460
SCD22U10V3KX
SCD22U10V3KX
12
C514
SCD22U10V3KX
SCD22U10V3KX
VCC_CORE_S0
1000p x 4
C58
12
C159
SCD22U10V3KX
12
C592
SCD22U10V3KX
12
C461
SCD22U10V3KX
12
C498
SCD22U10V3KX
SC1000P50V
12
C158
12
C591
12
C462
12
C479
C35
C36
SC1000P50V
12
C157
SCD22U10V3KX
SCD22U10V3KX
78.22423.2B1
SCD22U10V3KX
78.22423.2B1
SCD22U10V3KX
12
C465
SCD22U10V3KX
SCD22U10V3KX
SC1000P50V
12
C152
78.22423.2B1
SCD22U10V3KX
2D5V_S3
VCC_CORE_S0
12
C463
78.22423.2B1
SCD22U10V3KX
12
C194
SCD22U10V3KX
12
C555
SCD22U10V3KX
12
C206
12
C570
12
12
C207
C456
SCD22U10V3KX
12
C593
SCD22U10V3KX
12
C199
SCD22U10V3KX
SCD22U10V3KX
12
C551
SCD22U10V3KX
12
C198
SCD22U10V3KX
78.22423.2B1
12
C539
78.22423.2B1
SCD22U10V3KX
SCD22U10V3KX
1D25V_S3 1D25V_S32D5V_S3
12
C531
SCD22U10V3KX
SCD22U10V3KX
C201
1 2
SCD22U10V3KX
C200
1 2
SCD22U10V3KX
78.22423.2B1
LAYOUT: Locate close to socket.
2D5V_S3
12
12
C189
2D5V_S3
12
C443
VCC_CORE_S0
C524
2D5V_S3
12
C478
12
C547
SCD22U10V3KX
2D5V_S3
C181
12
C546
SCD22U10V3KX
12
C187
C184
SC10U6D3V5MX
SC10U6D3V5MX
12
12
C435
C430
SC10U6D3V5MX
SC10U6D3V5MX
4.7u x 7
C526
C505
SC4D7U10V5ZY
SC4D7U10V5ZY
SC4D7U10V5ZY
11/11 add 10UX1 for AMD suggest.
0.22u x 6
12
12
C329
C407
SCD22U10V3KX
SCD22U10V3KX
SCD22U10V3KX
4.7u x 6
C179
C180
SC4D7U10V5ZY
SC4D7U10V5ZY
SC4D7U10V5ZY
12
C183
SC10U6D3V5MX
12
C423
SC10U6D3V5MX
C509
C595
SC4D7U10V5ZY
12
12
C204
C308
SCD22U10V3KX
C178
C177
SC4D7U10V5ZY
SC10U6D3V5MX
SC10U6D3V5MX
NOTE: Populate 270uF
caps or 100uF caps
in these footprints.
It is impossible that
have 100U 50V 0805
78.10610.511
ceramic cap. Use 10U
6D3V X7R ceramic cap.
10u x 1
12
C506
C525
78.47593.411
SC4D7U10V5ZY
12
C205
SCD22U10V3KX
C176
SC4D7U10V5ZY
78.22423.2B1
78.47593.411
C596
SC4D7U10V5ZY
SC4D7U10V5ZY
SCD22U10V3KX
SC4D7U10V5ZY
SC10U6D3V5MX
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Title
Size Document Number Rev
A2
A
B
C
D
Date: Sheet
Taipei Hsien 221, Taiwan, R.O.C.
CPU(4/4)_Power
Gannet
E
751Thursday, December 04, 2003
-1
of
A
3D3VA_HT_S0
4 4
CPUCADOUT[15..0]4
CPUHTTCLKOUT04
CPUHTTCLKOUT14
3 3
2 2
1 1
CPUCADOUTJ[15..0]4
HT_RST#23
CPUHTTCTLOUT04
CPUHTTCLKOUTJ04
CPUHTTCLKOUTJ14
CPUHTTCTLOUTJ04
HT_RST#
HTT_STOP#6,25
2D5V_S0
12
R193
470R3F
1 2
R192
DUMMY-R3
CPUCADOUT0
CPUCADOUT1
CPUCADOUT2
CPUCADOUT3
CPUCADOUT4
CPUCADOUT5
CPUCADOUT6
CPUCADOUT8
CPUCADOUT9
CPUCADOUT10
CPUCADOUT11
CPUCADOUT12
CPUCADOUT13
CPUCADOUT14
CPUCADOUT15
CPUHTTCLKOUT0
CPUHTTCLKOUT1
CPUHTTCTLOUT0
CPUCADOUTJ0
CPUCADOUTJ1
CPUCADOUTJ2
CPUCADOUTJ3
CPUCADOUTJ4
CPUCADOUTJ5
CPUCADOUTJ6
CPUCADOUTJ7
CPUCADOUTJ8
CPUCADOUTJ9
CPUCADOUTJ10
CPUCADOUTJ11
CPUCADOUTJ12
CPUCADOUTJ13
CPUCADOUTJ14
CPUCADOUTJ15
CPUHTTCLKOUTJ0
CPUHTTCLKOUTJ1
CPUHTTCTLOUTJ0
HT_RST#
HTT_STOP#
RPCOMP
RNCOMP
RTCOMP
1D2V_HT0A_S0
T26
P24
P26
M24
K24
K26
H24
H26
R24
R22
N24
N22
L22
J24
J22
G24
M26
L24
F24
R26
P25
N26
M25
K25
J26
H25
G26
R23
P22
N23
M22
K22
J23
H22
G23
L26
L23
F25
B11
A12
D25
D26
C26
U24
U25
U26
V21
V22
V23
V24
V25
V26
C22
AVDD2
RCADP0
RCADP1
RCADP2
RCADP3
RCADP4
RCADP5
RCADP6
RCADP7
RCADP8
RCADP9
RCADP10
RCADP11
RCADP12
RCADP13
RCADP14
RCADP15
RCLKP0
RCLKP1
RCTLP
RCADN0
RCADN1
RCADN2
RCADN3
RCADN4
RCADN5
RCADN6
RCADN7
RCADN8
RCADN9
RCADN10
RCADN11
RCADN12
RCADN13
RCADN14
RCADN15
RCLKN0
RCLKN1
RCTLN
LDTRST
LDTSTP
RPCOMP
RNCOMP
RTCOMP
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
AGND2
C21
AGND2
VSS
A23
For debug purpose
A
A10
A8
A24
VLDT
VSS
B8
A25
VLDT
VSS
B13
A26A9B10
VLDT
VLDT
VSS
VSS
B15
B17
VLDT
VSS
B19
B
B23
VLDT
VSS
B21
B
VLDT
VSS
B24
B25
B26B9C10
VLDT
VLDT
VLDT
VSS
VSS
VSS
D6
B22C8D8
VLDT
VSS
D12
C11
VLDT
VSS
D14
C23
VLDT
VSS
D16
C24
VLDT
VSS
D18
C25C9D10
VLDT
VLDT
VSS
VSS
D20
E5E6E8F7F8
VLDT
VSS
D11
VLDT
VSS
D22
VLDT
VSS
D23
VLDT
VSS
D24D9E10
VLDT
VLDT
VSS
VSS
F13
F12
1D2V_HT0A_S0
E11
E21
VLDT
VLDT
VLDT
VLDT
VSS
VSS
VSS
VSS
F14
F17
F18
E22
F26
E23
VLDT
VSS
E24E9F10
VLDT
VLDT
VSS
VSS
G25H1H23
VLDT
VSS
F11
VLDT
VSS
F15
VLDT
VSS
J18
F16
VLDT
VSS
J2
F19
VLDT
VSS
J3
F20
VLDT
VSS
J21
F21
VLDT
VSS
J25
F22
VLDT
VSS
K4G1K10
F23
VLDT
VSS
C
G21
VLDT
VSS
K11
C
G22
VLDT
VSS
K12
H21
VLDT
VSS
K13
J10
VLDT
VSS
K14
J11
VLDT
VSS
K15
J12
VLDT
VSS
K16
J13
VLDT
VSS
K17
J14
VLDT
VSS
K23H2L10
J15
VLDT
VSS
J16
VLDT
VLDT
TCADP10
TCADP11
TCADP12
TCADP13
TCADP14
TCADP15
TCADN10
TCADN11
TCADN12
TCADN13
TCADN14
TCADN15
VSS
VSS
L11
J17
K18
K21
L18
U24A
VLDT
VLDT
VLDT
VLDT
B12
TCADP0
A13
TCADP1
B14
TCADP2
A15
TCADP3
A17
TCADP4
B18
TCADP5
A19
TCADP6
B20
TCADP7
E12
TCADP8
D13
TCADP9
E14
D15
D17
E18
D19
E20
B16
TCLKP0
E16
TCLKP1
A21
TCTLP
C12
TCADN0
A14
TCADN1
C14
TCADN2
A16
TCADN3
A18
TCADN4
C18
TCADN5
A20
TCADN6
C20
TCADN7
E13
TCADN8
C13
TCADN9
E15
C15
C17
E19
C19
D21
C16
TCLKN0
E17
TCLKN1
A22
TCTLN
L21
VLDT
M18
VLDT
N18
VLDT
N21
VLDT
P18
VLDT
P21
VLDT
R18
VLDT
T18
VLDT
T21
VLDT
T22
VLDT
T23
VLDT
T24
VLDT
T25
VLDT
U18
VLDT
U21
VLDT
U22
VLDT
U23
VLDT
VSS
VSS
VSS
VSS
K8M400-VD7
L13
L12
L14
L15
71.K8T00.00U
NB TO CLAW HAMMERCLAW HAMMER TO NB
NB0CADOUT0
NB0CADOUT1
NB0CADOUT2
NB0CADOUT3
NB0CADOUT4
NB0CADOUT5
NB0CADOUT6
NB0CADOUT7CPUCADOUT7
NB0CADOUT8
NB0CADOUT9
NB0CADOUT10
NB0CADOUT11
NB0CADOUT12
NB0CADOUT13
NB0CADOUT14
NB0CADOUT15
NB0HTTCLKOUT0
NB0HTTCLKOUT1
NB0HTTCTLOUT
NB0CADOUTJ0
NB0CADOUTJ1
NB0CADOUTJ2
NB0CADOUTJ3
NB0CADOUTJ4
NB0CADOUTJ5
NB0CADOUTJ6
NB0CADOUTJ7
NB0CADOUTJ8
NB0CADOUTJ9
NB0CADOUTJ10
NB0CADOUTJ11
NB0CADOUTJ12
NB0CADOUTJ13
NB0CADOUTJ14
NB0CADOUTJ15
NB0HTTCLKOUTJ0
NB0HTTCLKOUTJ1
NB0HTTCTLOUTJ
1D2V_HT0A_S0
D
NB0CADOUT[15..0] 4
NB0HTTCLKOUT0 4
NB0HTTCLKOUT1 4
NB0HTTCTLOUT 4
NB0CADOUTJ[15..0] 4
NB0HTTCLKOUTJ0 4
NB0HTTCLKOUTJ1 4
NB0HTTCTLOUTJ 4
D
E
3D3V_S0
3D3V_S02,3,9,10,11,14,16,19,20,21,22,23,24,25,27,28,29,31,32,33,34,35,36,37,38,39,40,41,42,43,47,48,49,51
1D2V_HT0A_S0
1D2V_HT0A_S02,4,10,50
2D5V_S0
2D5V_S06,9,10,16,19,20,23,24,25,31,48,50
C144
SC1000P50V
C234
SCD1U16V
3D3VA_HT_S03D3V_S0
C74
SC1U10V5KX
Modify-0602
AGND2
L11
1 2
SBK201209T-1
L12
1 2
SBK201209T-1
Note: When use K8T400M, this
power circuit for analog
power should be NOPOPed.
1D2V_HT0A_S0
C141
SCD1U16V
AROUND NB
E
1D2V_HT0A_S0
851Thursday, December 04, 2003
of
Modify-0602
R206 49D9R3F
RNCOMP
RTCOMP
RPCOMP
1 2
R201 100R3F
1 2
R195 49D9R3F
1 2
Modify-0602
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Title
Size Document Number Rev
A3
Date: Sheet
NB-K8T800M(1/3)_HT
Taipei Hsien 221, Taiwan, R.O.C.
Gannet
-1
A
VD0
VD1
VD2
VD3
VD4
VD5
VD6
VD7
VBE
VPAR
UPSTB
UPSTB
DNSTB
DNSTB
UPCMD
DNCMD
LVREF
LCOMPP
PWRGD
PCIRST
TESTIN
SUSTAT
DEBUG
B3
AR/NC
A3
AG/NC
A2
AB/NC
C4
RSET/NC
A1
HSYNC/NC
B1
VSYNC/NC
C6
XIN/NC
E7
INTA/NC
D3
BISTIN/NC
P2
SPCLK1/NC
C2
SPCLK2/NC
P1
SPD1/NC
C1
SPD2/NC
J1
TVD00/DVP0D00/NC
K2
TVD01/DVP0D01/NC
K3
TVD02/DVP0D02/NC
L4
TVD03/DVP0D03/NC
K1
TVD04/DVP0D04/NC
L2
TVD05/DVP0D05/NC
L3
TVD06/DVP0D06/NC
M4
TVD07/DVP0D07/NC
L1
TVD08/DVP0D08/NC
M2
TVD09/DVP0D09/NC
M3
TVD10/DVP0D10/NC
M1
TVD11/DVP0D11/NC
P4
TVCLKIN/DVP0DET/NC
N1
TVDE/DVP0DE/NC
N4
TVHS/DVP0HS/NC
N3
TVVS/DVP0VS/NC
P3
TVCLK/DVP0DCLK/NC
N2
GPO0/NC
D2
GPOUT/NC
VSS
VSS
VSS
L17
L25
L16
D1
VCC4/NC
VCC4/NC
VCC4/NC
VCC4/NC
VCC4/NC
VSS
VSS
VSS
VSS
VSS
M10
M11
M12
M13
M14
4 4
VLAD0
VLAD1
VLAD2
VLAD[7..0]25
VBE#25
LPAR25
UPSTB25
UPSTB#25
DNSTB25
DNSTB#25
UPCMD25
DNCMD25
PM_SUS_STAT#14,24
PWROK_NB#6,24
DP0_HSYNC19
DP0_VSYNC19
R190
R191
R189
R186
R185
R236
R226
RST_NB#23
GUICLK3
DP0_DET19
DP0_CLK19
A
1 2
SMBC119
SMBD119
Modify-0602
1 2
1 2
1 2
1 2
1 2
1 2
1 2
3 3
P_INTA#14,23
2 2
DP0_D[11..0]19
DUMMY-0R3-U
Close to CRT CONN
1 1
VGA_RED14,21
VGA_GREEN14,21
VGA_BLUE14,21
VGA_HSYNC14,21
VGA_VSYNC14,21
VGA_DDCCLK_314,21
VGA_DDCDAT_314,21
VLAD3
VLAD4
VLAD5
VLAD6
VLAD7
VBE#
LPAR
UPSTB
UPSTB#
DNSTB
DNSTB#
UPCMD
DNCMD
VL_VREF
VL_PCOMP
TESTIN
DEBUG
CRT_A/R
CRT_A/G
CRT_A/B
CRT_RSET
CRT_HSYNC
CRT_VSYNC
GUICLK
INTA#
R602 DUMMY-R2
SMBC1
SMBC2
SMBD1
SMBD2
DP0_DET
DP0_HSYNC
DP0_VSYNC
DP0_CLK
DUMMY-R2
DUMMY-R2
DUMMY-R2
DUMMY-R2
DUMMY-R2
DUMMY-R2
DUMMY-R2
CRT_HSYNC
CRT_VSYNC
DP0_D0
DP0_D1
DP0_D2
DP0_D3
DP0_D4
DP0_D5
DP0_D6
DP0_D7
DP0_D8
DP0_D9
DP0_D10
DP0_D11
CRT_A/R
CRT_A/G
CRT_A/B
SMBC2
SMBD2
AD20
AD21
AF24
AE24
AE19
AF20
AD24
AF25
AE21
AF19
AE23
AF23
AF22
AD22
AF26
AD23
AF21
AD19
AE26
AD25
AC26
AD26
AC17
B
F1K5E4E2E3F6F2
F5E1F4
F3
G2G3G4G5H3H4H5J4J5
VCC4/NC
VCC4/NC
VCC4/NC
VCC4/NC
VCC4/NC
VCC4/NC
VCC4/NC
VCC4/NC
VCC4/NC
V_LINK
CRT
SM Bus
TV Encoder/
Digital
Display
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
M15
M16
M17
M21
M23
N10
N11
N12
N13
B
3D3V_S0
VCC4/NC
VSS
N14
N15
VCC4/NC
VSS
C
1D5V_S0
M5K8M9L8N9P9R9
L5K9L9
J9
VCC4/NC
VCC4/NC
VCC4/NC
VCC4/NC
VCC4/NC
VCC4/NC
VCC4/NC
VCC4/NC
VCC4/NC
VCC4/NC
VCC4/NC
VCC4/NC
VCC4/NC
AGP 8X
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
N16
N17
N25P5P10
P11
P12
P13
P14
P15
P16
P17
P23R1R2R3R4R5R10
U1
N5
VCCQQ
VCC4/NC
GSTOP/FPDVICLK_N
GREQ/DVI_DDCCK
GGNT/DVI_DDCDA
SBA7/DVP1CLK_N
SB_STBS/DVP1D02
SB_STBF/DVP1D01
VSS
VSS
VSS
VSS
VSS
R11
R12
GD2/FPDVICLK
GD8/FPDVIDET
GD9/FPDVIHS
GD24/DVP1D09
GD26/DVP1D10
GD28/DVP1D07
GD29/DVP1D06
GD30/DVP1D08
GD31/DVP1D04
GCBE0/FPD03
GCBE1/SB_DA
GCBE2/FPD19
GCBE3/DVP1D11
ADSTB0S/FPD02
ADSTB0F/FPD04
ADSTB1S/FPDET
ADSTB1F/FPD12
GFRAME/FPHS
GIRDY/SB_CK
GDEVSEL/FPVS
GPAR/FPDVIVS
WBF/FPCLK_N
GSERR/FPDVIDE
SBA0/DVP1VS
SBA1/DVP1DE
SBA2/DVP1D00
SBA3/DVP1HS
SBA4/DVP1D05
SBA5/DVP1D03
SBA6/DVP1CLK
ST1/DVP1DET
VSS
VSS
R13
R14
VCC4/NC
VSS
VCC4/NC
VSS
VCC4/NC
VSS
GD0/FPD10
GD1/FPD11
GD3/FPD09
GD4/FPD08
GD5/FPD07
GD6/FPD06
GD7/FPD05
GD10/FPD01
GD11/FPD23
GD12/FPD00
GD13/FPD22
GD14/FPD21
GD15/FPD20
GD16/FPD18
GD17/FPD17
GD18/FPD16
GD19/FPDE
GD20/FPD14
GD21/FPCLK
GD22/FPD13
GD23/FPD15
GD25
GD27
GTRDY
RBF
GCLK
ST0
ST2
AGPPCOMP
AGPNCOMP
AGPVREF0
AGPVREF1
AGP8XDET
DBIL
DBIH
VSSQQ
VSS
T1
R15
U24B
AF18
AD18
AE18
AF17
AD17
AD16
AE16
AF16
AF14
AD14
AD13
AE13
AF13
AD12
AF12
AE12
AD10
AE10
AF10
AD9
AF9
AF8
AE9
AD8
AF6
AD7
AE6
AD5
AF5
AF4
AE4
AD4
AD15
AF11
AD11
AC7
AF15
AE15
AF7
AE7
AC9
AC10
AC14
AC11
AC12
AC16
AD6
AC1
Y1
AA3
AC15
A11
AC2
AC3
AD1
AD2
AF2
AD3
AE3
AF3
AE1
AF1
AA2
AA1
AB1
V1
W1
AC13
AC6
Y2
AC4
AC5
K8M400-VD7
C
AGP_AD0
AGP_AD1
AGP_AD2
AGP_AD3
AGP_AD4
AGP_AD5
AGP_AD6
AGP_AD7
AGP_AD8
AGP_AD9
AGP_AD10
AGP_AD11
AGP_AD12
AGP_AD13
AGP_AD14
AGP_AD15
AGP_AD16
AGP_AD17
AGP_AD18
AGP_AD19
AGP_AD20
AGP_AD21
AGP_AD22
AGP_AD23
AGP_AD24
AGP_AD25
AGP_AD26
AGP_AD27
AGP_AD28
AGP_AD29
AGP_AD30
AGP_AD31
AGP_C/BE#0
AGP_C/BE#1
AGP_C/BE#2
AGP_C/BE#3
AGP_ADSTB0#
AGP_ADSTB0
AGP_ADSTB1#
AGP_ADSTB1
AGP_FRAME#
AGP_IRDY#
AGP_TRDY#
AGP_DEVSEL#
AGP_STOP#
AGP_PAR
AGP_RBF#
AGP_WBF#
AGP_REQ#
AGP_GNT#
AGP_SERR#
CLK66_NB
AGP_SBA0
AGP_SBA1
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA6
AGP_SBA7
AGP_SB_STB#
AGP_SB_STB
AGP_ST0
AGP_ST1
AGP_ST2
AGP_PCOMP
AGP_NCOMP
AGP_VREF_GC
AGP_VREF_CG
AGP_VREF_CG
1 2
R318 2K2R3
Note: When use K8T400M, GFX relative
circuit should be NOPOPed.
3D3V_S0
C452
SC1U16V5KX-U
AGP_AD[31..0] 14,20
AGP_C/BE#[3..0] 14,20
AGP_ADSTB0# 14,20
AGP_ADSTB0 14,20
AGP_ADSTB1# 14,20
AGP_ADSTB1 14
AGP_FRAME# 14,20
AGP_IRDY# 14
AGP_TRDY# 14
AGP_DEVSEL# 14,20
AGP_STOP# 14
AGP_PAR 14
AGP_RBF# 14
AGP_WBF# 14,20
AGP_REQ# 14
AGP_GNT# 14
CLK66_NB 3
AGP_SB_STB# 14
AGP_SB_STB 14
AGP_VREF_CG 14
AGP_ADB_LO 14
AGP_PIPE# 14
AGP_SBA[7..0] 14
TESTIN
AGP_NCOMP
AGP_ST[2..0] 14
AGP_PCOMP
VL_PCOMP
CRT_RSET
DEBUG
D
AGP_SERR#
AGP_DEVSEL#
AGP_STOP#
AGP_IRDY#
AGP_ADSTB0
AGP_PAR
AGP_TRDY#
AGP_GNT#
AGP_REQ#
AGP_WBF#
AGP_SB_STB
AGP_FRAME#
AGP_ADSTB1
AGP_RBF#
AGP_ADSTB0#
AGP_ADSTB1#
AGP_SB_STB#
1D5V_S0
12
12
R355 4K7R3
1 2
R319 60R3F
1 2
R310 60R3F
1 2
R378 360R3F
1 2
R677 140R3F
1 2
R502 DUMMY-R3
1 2
R501 10KR3
1 2
D
1
2
3
4 5
1
2
3
4 5
1
2
3
4 5
1
2
3
4 5
1
2
3
4 5
R457
324R3F
AGP_VREF_GC
R459
100R3F
Decoupling capacitors
On NB Bottom Side
2D5V_S0
1D5V_S0
2D5V_S0
E
3D3V_S02,3,8,10,11,14,16,19,20,21,22,23,24,25,27,28,29,31,32,33,34,35,36,37,38,39,40,41,42,43,47,48,49,51
DP0_D4_1
DP0_D5_1
DP0_D6_1
DP0_D0
DP0_D1
DP0_D2
DP0_D3
DP0_D10
DP0_D7
1D5V_S0
C148 SC4D7U10V-U
C262 SC47U10V-1
C253 SC47U10V-1
2D5V_S06,8,10,16,19,20,23,24,25,31,48,50
1D5V_S02,10,14,16,20,49
R264 4K7R3
1 2
R279 4K7R3
1 2
R288 4K7R3
1 2
R633 DUMMY-4K7R3
1 2
R630 DUMMY-4K7R3
1 2
R632 DUMMY-4K7R3
1 2
R627 DUMMY-4K7R3
1 2
R625 4K7R3
1 2
R623 4K7R3
1 2
C138 SC1U16V5KX-U
C131 SC1U16V5KX-U
1 2
1 2
1D5V_S0
RN11
8
7
6
SRN8K2-U
RN12
8
7
6
SRN8K2-U
RN9
8
7
6
SRN8K2-U
RN10
8
7
6
SRN8K2-U
RN8
8
7
6
SRN8K2-U
C146 SCD1U16V
C149 SC1U16V5KX-U
2D5V_S0
12
R380
3KR3F
VL_VREF
12
R379
1KR3F
Use this function for K8M400
GFX power up strapping setting:
TVD/DVP0D[3:0] => Panel type selection
TVD4/DVP0D4 => FP-port multiplexed on AGP
interface selection
0: Two 12-bit DVI interface
1: One 24-bit panel interface
TVD5/DVP0D5 => Dedicated DVI port configuration
0: TMDS
1: TV Encoder
TVD6/DVP0D6 => Dedicated DVI port selection
0: Disable
1: Enable
R263DUMMY-R3
DP0_D4
1 2
R271DUMMY-R3
DP0_D5
1 2
R280DUMMY-R3
DP0_D6
1 2
Note: All of these power up strapping
pin have internal pull down. Put an
external pull up resister if want to
set the default value to 1.
C271
SCD1U16V
C270
SCD1U16V
Layout trace 20 mil
The voltage level of
VL_VREF is 0.625V
Cross NB as short as possible
Title
Size Document Number Rev
A3
Date: Sheet
NB-K8T800M(2/3)_AGP_VLINK
Decoupling capacitors
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Gannet
951Thursday, December 04, 2003
E
3D3V_S0
2D5V_S0
1D5V_S0
3D3V_S0
3D3V_S0
-1
of
A
Layout trace 20 mil
2D5V_NB_S3
3D3VA_S0
4 4
1D5V_PLL1_S0
1D5V_PLL2_S0
3D3V_DAC_S0
3D3V_RGB_S0
3 3
2 2
1 1
VDD
AC25
AB17
AB18
AB19
AB20
AC18
AC19
AC20
AC21
W15
W16
W17
W18
W21
W22
W23
W24
W25
W26
AB10
AB15
E25
E26
V14
V15
V16
V17
R16
R17
R21
R25
T10
T11
T12
T13
T14
T15
T16
T17
U10
U11
U12
U13
U14
U15
U16
U17
AB2
AB3
AB4
AB5
AB6
AB9
D5
A5
C5
B5
A6
B6
B2
C3
D4
A4
B4
A7
D7
B7
C7
V5
W5
U24C
VSUS15/VSUS25
For Suspend
AVDD1
AGND1
For HT Receive
VCCPLL1/NC
VCCPLL2/NC
GNDPLL1/NC
GNDPLL2/NC
For Graphics
Controller PLL
1&2
VCCPLL3/NC
GNDPLL3/NC
For Graphics
Controller
PLL3
DACVDD/NC
GNDDAC1/NC
GNDDAC2/NC
For DAC
VCCRGB/NC
GNDRGB/NC
For CRT RGB
NC
NC
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VSS/NC
VSS/NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
K8M400-VD7
A
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AA4
AA5
AB11
AB12
AB13
AB14
AB7
AB8
M8
N8
T2
T3
T4
T5
T8
T9
U2
U3
U4
U5
U8
U9
V10
V11
V12
V13
V2
V3
V4
V8
V9
W2
W3
W4
W9
Y3
Y4
Y5
AA21
AA22
AA23
AA24
AA25
AA26
AB21
AB22
AB23
AB24
AB25
AB26
F9
H10
H11
H12
H15
H16
H8
H9
J8
K19
L19
M19
P8
R19
R8
T19
U19
V18
V19
W10
W11
W12
W13
W14
W19
Y20
Y21
Y22
Y23
Y24
Y25
Y26
AB16
AC8
AC22
AC23
AC24
AE2
AE5
AE8
AE11
AE14
AE17
AE20
AE22
AE25
1D5V_S0
VDD
Layout trace 20 mil
1D5V_S0 1D5V_S0
L43
1 2
SBK201209T-1
Note: When use K8T400M, these
power circuit for GFX analog
power should be NOPOPed.
R455 0R1206
1 2
R571
1 2
DUMMY-R3
2D5V_S0
1D5V_S0
C219 SCD1U16V
C214 SCD01U16V2KX
C175 SCD1U16V
C165 SCD01U16V2KX
C217 SCD1U16V
C155 SCD01U16V2KX
C193 SCD1U16V
3D3V_S0
C475 SCD1U16V
C440 SCD1U16V
C223 SC1U16V5KX-U
C436 SCD1U16V
C429 SCD1U16V
C457 SCD1U16V
C220 SC1U16V5KX-U
C425 SC1U16V5KX-U
1 2
1 2
1 2
B
2D5V_NB_S3 2D5V_S3
1D5V_PLL1_S0 1D5V_PLL2_S0
C519
SC1000P50V
G36
1 2
GAP-CLOSE
C532
SC1U16V5KX-U
L10
1 2
SBK201209T-1
L15
1 2
SBK201209T-1
C142
SC1000P50V
3D3VA_S0
C197
SC1000P50V
NEAR N/B ON BOT SIDE
C154 SCD01U16V2KX
1 2
C476 SCD01U16V2KX
1 2
C433 SCD01U16V2KX
1 2
C439 SCD01U16V2KX
1 2
C213 SCD1U16V
C140 SCD1U16V
C153 SCD1U16V
C241 SCD1U16V
B
C
C73
SC1U16V5KX-U
C188
SC1U16V5KX-U
1D2V_HT0A_S0VDD
C534 SC4D7U10V-U
C455 SC1000P50V
C434 SC1000P50V
C438 SCD1U16V
C418 SCD1U16V
C453 SCD1U16V
C504 SCD1U16V
C522 SCD1U16V
C404 SCD01U16V2KX
1 2
C216 SCD01U16V2KX
1 2
C444 SCD01U16V2KX
1 2
C503 SCD01U16V2KX
1 2
C307 SCD01U16V2KX
1 2
C523 SCD01U16V2KX
1 2
C242 SCD01U16V2KX
1 2
C
3D3V_S0 3D3V_RGB_S03D3V_S0
L13
1 2
SBK201209T-1
L9
1 2
SBK201209T-1
3D3V_DAC_S03D3V_S0
C150
SC1000P50V
C143
SC1000P50V
1D2V_HT0A_S0
C528 SCD22U10V3KX
1 2
C482 SC2200P50V2KX
1 2
1D5V_S0
C368 SC1U16V5KX-U
C306 SC1U16V5KX-U
C231 SC1U16V5KX-U
C237 SC1U16V5KX-U
C239 SC1U16V5KX-U
C309 SCD01U16V2KX
1 2
C247 SCD01U16V2KX
1 2
C328 SCD01U16V2KX
1 2
C417 SCD01U16V2KX
1 2
C166 SCD01U16V2KX
1 2
C156 SCD01U16V2KX
1 2
C167 SCD01U16V2KX
1 2
C212 SCD01U16V2KX
1 2
D
C162
SC1U16V5KX-U
C72
SC1U16V5KX-U
D
E
3D3V_S0
3D3V_S02,3,8,9,11,14,16,19,20,21,22,23,24,25,27,28,29,31,32,33,34,35,36,37,38,39,40,41,42,43,47,48,49,51
3D3V_S322,28,34,37,48
2D5V_S06,8,9,16,19,20,23,24,25,31,48,50
1D5V_S02,9,14,16,20,49
1D2V_HT0A_S02,4,8,50
3D3V_S3
2D5V_S0
1D5V_S0
5V_S0
5V_S02,19,21,22,23,24,25,26,27,28,30,32,33,35,36,37,38,39,40,41,42,43,46,47,48,50,51
1D2V_HT0A_S0
Power for NB Core and VLINK interface
5V_S0
1D5V_S0
LDO
VDD=1.5V for K8M400
VDD=2.5V for K8T400M(Default)
DUMMY
3D3V_S3
R352 DUMMY-R3
1 2
R365 DUMMY-R3
1 2
D16
DUMMY-SC431L
ZZ.00431.C3B
VSUSNB=1.5V for K8M400
When R1=100, R2=500
VSUSNB=2.5V for K8T400M
When R1=102, R2=100
(Default)
Title
Size Document Number Rev
A3
Date: Sheet
Layout trace 20 mil
C260
SCD1U16V
2D5V_NB_S3
C263
SC1U16V5KX-U
R865 DUMMY-R3
1 2
N10-1
12
R320
R1
DUMMY-100R3F
2
ZZ.10005.651
K8M400_TM
1
12
3
R309
R2
DUMMY-100R3F
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
NB-K8T800M(3/3)_POWER
Gannet
10 51Thursday, December 04, 2003
E
of
-1
A
M_AA0
M_AA1
M_AA2
M_AA3
M_AA4
M_AA6
M_AA5
M_AA7
M_AA8
M_AA9
M_AA10
M_AA11
M_ABS#15,12
TP7
TP165
TP6
M_DATA_R_0
M_DATA_R_1
M_DATA_R_2
M_DATA_R_3
M_DATA_R_4
M_DATA_R_5
M_DATA_R_6
M_DATA_R_7
M_DATA_R_8
M_DATA_R_9
M_DATA_R_10
M_DATA_R_11
M_DATA_R_12
M_DATA_R_13
M_DATA_R_14
M_DATA_R_15
M_DATA_R_16
M_DATA_R_17
M_DATA_R_18
M_DATA_R_19
M_DATA_R_20
M_DATA_R_21
M_DATA_R_22
M_DATA_R_23
M_DATA_R_24
M_DATA_R_25
M_DATA_R_26
M_DATA_R_27
M_DATA_R_28
M_DATA_R_29
M_DATA_R_30
M_DATA_R_31
M_DATA_R_32
M_DATA_R_33
M_DATA_R_34
M_DATA_R_35
M_DATA_R_36
M_DATA_R_37
M_DATA_R_38
M_DATA_R_39
M_DATA_R_40
M_DATA_R_41
M_DATA_R_42
M_DATA_R_43
M_DATA_R_44
M_DATA_R_45
M_DATA_R_46
M_DATA_R_47
M_DATA_R_48
M_DATA_R_49
M_DATA_R_50
M_DATA_R_51
M_DATA_R_52
M_DATA_R_53
M_DATA_R_54
M_DATA_R_55
M_DATA_R_56
M_DATA_R_57
M_DATA_R_58
M_DATA_R_59
M_DATA_R_60
M_DATA_R_61
M_DATA_R_62
M_DATA_R_63
12
A
M_AA12
DM1_RESET#
DM1_A13
DM1_BA2
3D3V_S0
C343
SC1000P50V
4 4
M_ABS#05,12
3 3
2 2
1 1
M_ARAS#5,12
M_ACAS#5,12
M_AWE#5,12
VREF_DDR_MEM VREF_DDR_MEM
Layout trace 20 mil Layout trace 20 mil
C338
SCD1U10V2MX-1
DM1
112
A0
111
A1
110
A2
109
A3
108
A4
107
A5
106
A6
105
A7
102
A8
101
A9
115
A10 / AP
100
A11
99
A12
117
BA0
116
BA1
5
DQ0
7
DQ1
13
DQ2
17
DQ3
6
DQ4
8
DQ5
14
DQ6
18
DQ7
19
DQ8
23
DQ9
29
DQ10
31
DQ11
20
DQ12
24
DQ13
30
DQ14
32
DQ15
41
DQ16
43
DQ17
49
DQ18
53
DQ19
42
DQ20
44
DQ21
50
DQ22
54
DQ23
55
DQ24
59
DQ25
65
DQ26
67
DQ27
56
DQ28
60
DQ29
66
DQ30
68
DQ31
127 57
DQ32 VDD
129
DQ33
135
DQ34
139
DQ35
128
DQ36
130
DQ37
136
DQ38
140
DQ39
141
DQ40
145
DQ41
151
DQ42
153
DQ43
142
DQ44
146
DQ45
152
DQ46
154
DQ47
163
DQ48
165
DQ49
171
DQ50
175
DQ51
164
DQ52
166
DQ53
172
DQ54
176
DQ55
177
DQ56
181
DQ57
187
DQ58
189
DQ59
178
DQ60
182
DQ61
188
DQ62
190
DQ63
71
CB0
73
CB1
79
CB2
83
CB3
72
CB4
74
CB5
80
CB6
84
CB7
85
NC
86
NC/(RESET#)
97
NC/A13
98
NC/BA2
123
NC
124
NC
200
NC
118
/RAS
120
/CAS
119
/WE
1
VREF
2
VREF
197
VDDSPD
199
VDDID
DDR-SODIMM-N
/CS0
/CS1
CKE0
CKE1
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
CK0
/CK0
CK1
/CK1
CK2
/CK2
SCL
SDA
SA0
SA1
SA2
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
NORMAL TYPE
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
GNDGND
B
TP167
TP1
TP166
M_DATA_R_0
M_DATA_R_1
M_DATA_R_2
M_DATA_R_3
M_DATA_R_4
M_DATA_R_5
M_DATA_R_6
M_DATA_R_7
M_DATA_R_8
M_DATA_R_9
M_DATA_R_10
M_DATA_R_11
M_DATA_R_12
M_DATA_R_13
M_DATA_R_14
M_DATA_R_15
M_DATA_R_16
M_DATA_R_17
M_DATA_R_18
M_DATA_R_19
M_DATA_R_20
M_DATA_R_21
M_DATA_R_22
M_DATA_R_23
M_DATA_R_24
M_DATA_R_25
M_DATA_R_26
M_DATA_R_27
M_DATA_R_28
M_DATA_R_29
M_DATA_R_30
M_DATA_R_31
M_DATA_R_32
M_DATA_R_33
M_DATA_R_34
M_DATA_R_35
M_DATA_R_36
M_DATA_R_37
M_DATA_R_38
M_DATA_R_39
M_DATA_R_40
M_DATA_R_41
M_DATA_R_42
M_DATA_R_43
M_DATA_R_44
M_DATA_R_45
M_DATA_R_46
M_DATA_R_47
M_DATA_R_48
M_DATA_R_49
M_DATA_R_50
M_DATA_R_51
M_DATA_R_52
M_DATA_R_53
M_DATA_R_54
M_DATA_R_55
M_DATA_R_56
M_DATA_R_57
M_DATA_R_58
M_DATA_R_59
M_DATA_R_60
M_DATA_R_61
M_DATA_R_62
M_DATA_R_63
12
M_AA0
M_AA1
M_AA2
M_AA3
M_AA4
M_AA6
M_AA5
M_AA7
M_AA8
M_AA9
M_AA10
M_AA11
M_AA12
M_ABS#0
M_ABS#1
DM2_RESET#
DM2_A13
DM2_BA2
M_AA13M_AA13
M_ARAS#
M_ACAS#
M_AWE#
3D3V_S0
C374
SC1000P50V
121
122
96
95
M_DQS_R0
11
M_DQS_R1
25
M_DQS_R2
47
M_DQS_R3
61
M_DQS_R4
133
M_DQS_R5 M_DQS_R5
147
M_DQS_R6
169
M_DQS_R7
183
77
M_ADM_R0
12
M_ADM_R1
26
M_ADM_R2
48
M_ADM_R3
62
134
M_ADM_R5 M_ADM_R5
148
M_ADM_R6
170
M_ADM_R7
184
78
35
37
160
158
89
91
SMBC_SB
195
SMBD_SB
193
194
196
198
9
10
21
22
33
34
36
45
46
58
69
70
81
82
92
93
94
113
114
131
132
143
144
155
156
157
167
168
179
180
191
192
3
4
15
16
27
28
38
39
40
51
52
63
64
75
76
87
88
90
103
104
125
126
137
138
149
150
159
161
162
173
174
185
186
202201
B
M_CS#0 5,12
M_CS#1 5,12
M_CKE#_R0 12
M_CKE#_R1 12
M_ADM#0
M_ADM#1
M_ADM#2
M_ADM#3
M_ADM#4
M_ADM#5
M_ADM#6
M_ADM#7
M_CLK5 5,12
M_CLK#5 5,12
M_CLK7 5,12
M_CLK#7 5,12
M_CLK0 5,12
M_CLK#0 5,12
2D5V_S3
NOT SUPPORT ECC CHECK
ALi suggested pull-low
C351
SCD1U10V2MX-1
C
DM2
112
A0
111
A1
110
A2
109
A3
108
A4
107
A5
106
A6
105
A7
102
A8
101
A9
115
A10 / AP
100
A11
99
A12
117
BA0
116
BA1
5
DQ0
7
DQ1
13
DQ2
17
DQ3
6
DQ4
8
DQ5
14
DQ6
18
DQ7
19
DQ8
23
DQ9
29
DQ10
31
DQ11
20
DQ12
24
DQ13
30
DQ14
32
DQ15
41
DQ16
43
DQ17
49
DQ18
53
DQ19
42
DQ20
44
DQ21
50
DQ22
54
DQ23
55
DQ24
59
DQ25
65
DQ26
67
DQ27
56
DQ28
60
DQ29
66
DQ30
68
DQ31
127 57
DQ32 VDD
129
DQ33
135
DQ34
139
DQ35
128
DQ36
130
DQ37
136
DQ38
140
DQ39
141
DQ40
145
DQ41
151
DQ42
153
DQ43
142
DQ44
146
DQ45
152
DQ46
154
DQ47
163
DQ48
165
DQ49
171
DQ50
175
DQ51
164
DQ52
166
DQ53
172
DQ54
176
DQ55
177
DQ56
181
DQ57
187
DQ58
189
DQ59
178
DQ60
182
DQ61
188
DQ62
190
DQ63
71
CB0
73
CB1
79
CB2
83
CB3
72
CB4
74
CB5
80
CB6
84
CB7
85
NC
86
NC/(RESET#)
97
NC/A13
98
NC/BA2
123
NC
124
NC
200
NC
118
/RAS
120
/CAS
119
/WE
1
VREF
2
VREF
197
VDDSPD
199
VDDID
202 201
GND GND
DDR-SODIMM-R
C
/CS0
/CS1
CKE0
CKE1
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
CK0
/CK0
CK1
/CK1
CK2
/CK2
SCL
SDA
SA0
SA1
SA2
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
REVERSE TYPE
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
121
122
96
95
11
25
47
61
133
147
169
183
77
12
26
48
62
134
148
170
184
78
35
37
160
158
89
91
195
193
194
196
198
9
10
21
22
33
34
36
45
46
58
69
70
81
82
92
93
94
113
114
131
132
143
144
155
156
157
167
168
179
180
191
192
3
4
15
16
27
28
38
39
40
51
52
63
64
75
76
87
88
90
103
104
125
126
137
138
149
150
159
161
162
173
174
185
186
M_CKE#_R0
M_CKE#_R1
M_ADM_R1
M_ADM_R2
M_ADM_R3
M_ADM_R4M_ADM_R4
M_ADM_R6
M_ADM_R7
DM2_SA0
M_DQS_R0
M_DQS_R1
M_DQS_R2
M_DQS_R3
M_DQS_R4
M_DQS_R6
M_DQS_R7
M_ADM_R0
M_CS#2 5,12
M_CS#3 5,12
M_ADM#0
M_ADM#1
M_ADM#2
M_ADM#3
M_ADM#4
M_ADM#5
M_ADM#6
M_ADM#7
M_CLK4 5,12
M_CLK#4 5,12
M_CLK6 5,12
M_CLK#6 5,12
M_CLK1 5,12
M_CLK#1 5,12
SMBC_SB 3,25,30
SMBD_SB 3,25,30
2D5V_S3
D
1 2
R648 4K7R3
D
E
M_ADM_R[7..0] 12
M_DATA_R_[63..0] 12
M_DQS_R[7..0] 12
M_AA[13..0] 5,12
M_ABS#[0..1] 5,12
3D3V_S0
AMD K8
ClawHummar
MD63
DDR SOCKET PLACEMENT
TOP VIEW PERSPECTIVE DRAWING
DM1
Pin 199
Pin 200 Pin 2
DM2(Reverse)
Title
Size Document Number Rev
A3
Date: Sheet
DDR SO-DIMM SKT
SMA10
SMA11
SMA0
SMA14
SMA12
Pin 200
Pin 199
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Gannet
E
Pin 2
Pin 1
VREF_DDR_MEM5
MD0
Pin 1
11 51Thursday, December 04, 2003
3D3V_S02,3,8,9,10,14,16,19,20,21,22,23,24,25,27,28,29,31,32,33,34,35,36,37,38,39,40,41,42,43,47,48,49,51
2D5V_S35,6,7,10,13,46,48,49,50
VREF_DDR_MEM
of
3D3V_S0
2D5V_S3
-1
A
SERIES DAMPING PARALLEL TERMINATION
PLACE RNs CLOSE TO FIRST DM ( DM2 ), < 0.75"
STRICT EQUAL LENGTH LIMITATION WITH DQS,
CB PINS
M_CKE#0 5
M_CKE#1 5
RN32
1
2
3
4
5
6
7
8 9
RN23
1
2
3
4
5
6
7
8 9
SRN10J-3
RN30
1
2
3
4
5
6
7
8 9
SRN10J-3
RN21
1
2
3
4
5
6
7
8 9
RN31 SRN10J
2
1 4
66.10036.040
RN36 SRN10J
2
1 4
66.10036.040
RN24 SRN10J
2
1 4
66.10036.040
M_DATA0
M_DATA1 M_DATA_R_33
M_DQS0 M_DQS_R0
M_DATA2
M_DATA3
M_DATA8
M_DATA9
4 4
M_DQS1
M_DATA4 M_DATA_R_4
M_DATA5
M_ADM0
M_DATA6
M_DATA7
M_DATA12
M_DATA13
M_ADM1
M_DATA16
M_DATA17 M_DATA_R_17
M_DQS2 M_DQS_R2
M_DATA18
M_DATA19
M_DATA24
M_DATA25
M_DQS3 M_DQS_R3
3 3
M_DATA22
M_ADM2
M_DATA28
M_DATA23
M_DATA29
M_ADM3
M_DATA31
M_DATA30
M_DATA11
M_DATA10
M_CKE#0
M_CKE#1
2 2
1 1
M_ADM_R[7..0]11
M_ADM[8..0]5
M_DATA_R_0
16
M_DATA_R_1 M_DATA_R_1
15
14
M_DATA_R_2
13
M_DATA_R_3
12
M_DATA_R_8
11
M_DATA_R_9
10
M_DQS_R1
SRN10J-3
16
M_DATA_R_5
15
M_ADM_R0
14
M_DATA_R_6
13
M_DATA_R_7
12
M_DATA_R_12
11
M_DATA_R_13
10
M_ADM_R1
M_DATA_R_16 M_DATA48
16
15
14
M_DATA_R_18
13
M_DATA_R_19
12
M_DATA_R_24
11
M_DATA_R_25
10
M_DATA_R_22
16
M_ADM_R2
15
M_DATA_R_28
14
M_DATA_R_23
13
M_DATA_R_29
12
M_ADM_R3
11
M_DATA_R_31
10
M_DATA_R_30
SRN10J-3
M_DATA_R_11
3
M_DATA_R_10
M_DATA_R_26M_DATA26
3
M_DATA_R_27M_DATA27
M_CKE#_R0
3
M_CKE#_R1
11/11 add RN30 for AMD
suggest.
M_DATA14
M_DATA15
M_DATA21
M_DATA20
M_DATA47
M_DATA46
M_DATA53
M_DATA52
A
M_DATA32
M_DATA33
M_DQS4 M_DQS_R4
M_DATA34 M_DATA_R_34
M_DATA35
M_DATA40
M_DATA41
M_DQS5
M_DATA36
M_DATA37
M_ADM4
M_DATA38
M_DATA39
M_DATA44
M_DATA45 M_DATA_R_45
M_ADM5
M_DATA49
M_DQS6 M_DQS_R6
M_DATA50
M_DATA51
M_DATA56
M_DATA57
M_DQS7 M_DQS_R7
M_ADM6
M_DATA54
M_DATA55
M_DATA60
M_DATA61
M_ADM7
M_DATA62
M_DATA63
M_DATA43
M_DATA42 M_DATA_R_42
M_DATA58
M_DATA59
RN22
1
2
3
4
5
6
7
8 9
SRN10J-3
RN19
1
2
3
4
5
6
7
8 9
SRN10J-3
16
15
14
13
12
11
10
16
15
14
13
12
11
10
1
2
3
4
5
6
7
8 9
1
2
3
4
5
6
7
8 9
1
2
3
4
5
6
7
8 9
1
2
3
4
5
6
7
8 9
M_DATA_R_14
M_DATA_R_15
M_DATA_R_47
M_DATA_R_46
M_DATA_R_53
M_DATA_R_52
RN34
SRN10J-3
RN20
SRN10J-3
RN28
SRN10J-3
RN18
SRN10J-3
RN33 SRN10J
2
1 4
66.10036.040
RN27 SRN10J
2
1 4
66.10036.040
M_DATA_R_21
M_DATA_R_20
B
M_DATA_R_32
16
15
14
13
M_DATA_R_35
12
M_DATA_R_40
11
M_DATA_R_41
10
M_DQS_R5
Modify at 05-08 03'
M_DATA_R_36
16
M_DATA_R_37
15
M_ADM_R4
14
M_DATA_R_38
13
M_DATA_R_39
12
M_DATA_R_44
11
10
M_ADM_R5
M_DATA_R_48
16
M_DATA_R_49
15
14
M_DATA_R_50
13
M_DATA_R_51
12
M_DATA_R_56
11
M_DATA_R_57
10
M_ADM_R6
16
M_DATA_R_54
15
M_DATA_R_55
14
M_DATA_R_60
13
M_DATA_R_61
12
M_ADM_R7
11
M_DATA_R_62
10
M_DATA_R_63
M_DATA_R_43
3
M_DATA_R_58
3
M_DATA_R_59
B
C
PULL HIGH STUBS < 0.8", PLACE RPs CLOSE TO SECOND DM ( DM1 )
1D25V_S3
M_DATA_R_0
M_DQS_R0
M_DATA_R_2
M_DATA_R_3
M_DATA_R_8
M_DATA_R_9
M_DQS_R1
M_DATA_R_4
M_DATA_R_5
M_ADM_R0
M_DATA_R_6
M_DATA_R_7
M_DATA_R_12
M_DATA_R_13
M_DATA_R_16
M_DATA_R_17
M_DQS_R2
M_DATA_R_18
M_DATA_R_19
M_DATA_R_24
M_DATA_R_25
M_DQS_R3
M_DATA_R_21
M_ADM_R2
M_DATA_R_22
M_DATA_R_23
M_DATA_R_28
M_DATA_R_29
M_ADM_R3
M_DATA_R_11 M_DATA_R_43
M_DATA_R_10 M_DATA_R_42
M_DATA_R_14
M_DATA_R_15
M_DATA_R_26
M_DATA_R_27
M_DATA_R_30
M_DATA_R_31
PLACE BETWEEN DM1, DM2
CLOSE TO FIRST DM ( DM 2 ) < 0.2", TO SECOND DM ( DM1 ) < 1.1"
EQUAL LENGTH LIMITATION WITH SCK/SCK#
1
2
3
4
5
6
7
8 9
1
2
3
4
5
6
7
8 9
1
2
3
4
5
6
7
8 9
1
2
3
4
5
6
7
8 9
RN80
1 4
2
SRN68J
RN44
1 4
2
SRN68J
RN79
1 4
2
SRN68J
RN52
1 4
2
SRN68J
R637 121R3F
1 2
64.12105.651
R645 121R3F
1 2
R634 121R3F
1 2
R639 121R3F
1 2
R592 121R3F
1 2
R590 121R3F
1 2
RN91
SRN68J-1
RN62
SRN68J-1
RN90
SRN68J-1
RN57
SRN68J-1
C
16
15
14
13
12
11
10
16
15
14
13
12
11
10
16
15
14
13
12
11
10
16
15
14
13
12
11
10
3
3
3
3
M_CLK7
M_CLK#7
M_CLK6
M_CLK#6
M_CLK5
M_CLK#5
M_CLK4
M_CLK#4
M_CLK1
M_CLK#1
M_CLK0
M_CLK#0
RN89
1
2
3
4
5
6
7
8 9
SRN68J-1
RN85
1
2
3
4
5
6
7
8 9
SRN68J-1
RN78
1 4
2
SRN68J
RN43
1 4
2
SRN68J
RN77
1 4
2
SRN68J
RN42
1 4
2
SRN68J
NO EQUAL LENGTH LIMITATION
M_DATA_R_41
16
M_DQS_R5
15
M_DATA_R_40
14
M_DATA_R_35
13
M_DQS_R4
12
M_DATA_R_34
11
M_DATA_R_32
10
M_DATA_R_33
Modify at 05-08 03'
RN56
1
2
3
4
5
6
7
8 9
SRN68J-1
16
15
14
13
12
11
10
RN54
1
2
3
4
5
6
7
8 9
SRN68J-1
3
3
3
3
M_CLK7 5,11
M_CLK#7 5,11
M_CLK6 5,11
M_CLK#6 5,11
M_CLK5 5,11
M_CLK#5 5,11
M_CLK4 5,11
M_CLK#4 5,11
M_CLK1 5,11
M_CLK#1 5,11
M_CLK0 5,11
M_CLK#0 5,11
M_DATA_R_45
16
M_DATA_R_44
15
M_ADM_R4
14
M_DATA_R_39
13
M_DATA_R_38
12
M_DATA_R_37
11
M_DATA_R_36
10
M_DATA_R_57
M_DQS_R7
M_DATA_R_51
M_DATA_R_56
M_DATA_R_50
M_DQS_R6
M_DATA_R_48
M_DATA_R_49
Modify at 05-08 03'
M_ADM_R7
16
M_DATA_R_60
15
M_DATA_R_61
14
M_DATA_R_55
13
M_DATA_R_54
12
M_DATA_R_52
11
10
M_DATA_R_53
M_DATA_R_46
M_DATA_R_47
M_DATA_R_58
M_DATA_R_59
M_DATA_R_62
M_DATA_R_63
D
M_ADM_R1
M_DATA_R_20
M_ADM_R5
M_ADM_R6
D
M_ARAS#
M_AA8
M_AA5
M_AA2
M_AA4
M_AWE#
M_CS#3
M_CS#2
M_AA13
M_AA3
M_AA6
M_AA10
M_ABS#0
M_AA12
M_AA9
M_AA11
M_AA7
E
1D25V_S3
R631 68R2
1 2
RN39
1
2
3
4 5
1 4
2
RN40
1
8
2
7
3
6
4 5
SRN68-1
RN71
1
8
2
7
3
6
4 5
SRN68-1
1D25V_S3
R712 68R2
1 2
R711 68R2
1 2
RN72
1
2
3
4 5
SRN68-1
RN74
1
2
3
4 5
SRN68-1
RN61
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8 9
SRN68J-1
RN55
1
2
3
4
5
6
7
8 9
SRN68J-1
Title
Size Document Number Rev
Date: Sheet
11/11 add R1267 for
AMD suggest.
8
7
6
8
7
6
16
15
14
13
12
11
10
A3
M_CS#1
8
M_ACAS#
7
M_ABS#1
6
M_AA0
SRN68-1
RN35
SRN68J
R640 68R2
1 2
R713 68R2
1 2
M_CS#0
M_AA1
3
M_CKE#_R0
M_CKE#_R1
M_CS#3
M_CS#2
M_CS#0
M_CS#1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
DDR DAMPING & TERMINATION
Gannet
E
2D5V_S35,6,7,10,11,13,46,48,49,50
1D25V_S35,6,7,13,46,50
M_CKE#_R0 11
M_CKE#_R1 11
M_CS#3 5,11
M_CS#2 5,11
M_CS#0 5,11
M_CS#1 5,11
M_AWE# 5,11
M_ACAS# 5,11
M_ARAS# 5,11
M_DATA[63..0] 5
M_DATA_R_[63..0] 11
M_DQS[7..0] 5
M_DQS_R[7..0] 11
M_AA[13..0] 5,11
M_ABS#[0..1] 5,11
12 51Thursday, December 04, 2003
of
2D5V_S3
1D25V_S3
-1
A
1D25V_S3 TO GND
1D25V_S3 TO 2D5V_S3
B
0.22u
4.7u
10u
100u 0.1u341000p42100p
2
10
10
220u10.22u100.1u
34
C
4
D
E
2D5V_S3
2D5V_S35,6,7,10,11,46,48,49,50
1D25V_S35,6,7,12,46,50
1D25V_S3
4 4
2D5V_S3
1D25V_S3
12
12
12
C400
C398
C396
C394
SCD1U10V2MX-1
SCD1U10V2MX-1
SCD1U10V2MX-1
SCD1U10V2MX-1
SCD1U10V2MX-1
SC4D7U10V5ZY
SCD1U10V2MX-1
12
C401
C403
SCD1U10V2MX-1
12
C451
C458
SCD1U10V2MX-1
12
C454
C450
SCD1U10V2MX-1
12
C123
C332
SCD22U10V3KX
12
12
C397
C399
SCD1U10V2MX-1
3 3
2D5V_S3
1D25V_S3
C469
C446
2 2
1D25V_S3
C129
12
12
C464
SCD1U10V2MX-1
12
12
C448
SCD1U10V2MX-1
12
C124
SCD22U10V3KX
LAYOUT:Place altemating caps to GND and 2D5_DRAM
12
12
12
12
12
12
12
C392
C390
C388
C386
C384
C382
SCD1U10V2MX-1
SCD1U10V2MX-1
SCD1U10V2MX-1
SCD1U10V2MX-1
SCD1U10V2MX-1
12
12
12
SCD1U10V2MX-1
SCD1U10V2MX-1
SCD1U10V2MX-1
SC4D7U10V5ZY
12
12
12
12
C412
C414
C416
C421
SCD1U10V2MX-1
SCD1U10V2MX-1
SCD1U10V2MX-1
12
12
12
12
C336
C442
C447
C449
SCD1U10V2MX-1
SCD1U10V2MX-1
SCD1U10V2MX-1
12
12
C459
C339
C344
SCD1U10V2MX-1
SCD1U10V2MX-1
LAYOUT:Place a cap every 1 in. on VTT
traces between Clawhammer and DDR.
12
C322
SCD22U10V3KX
C317
C320
SC4D7U10V5ZY
12
12
C352
SCD1U10V2MX-1
12
C321
SCD22U10V3KX
SC4D7U10V5ZY
SCD1U10V2MX-1
12
12
C441
C375
SCD1U10V2MX-1
SCD1U10V2MX-1
12
12
C341
C348
SCD1U10V2MX-1
SCD1U10V2MX-1
12
12
C337
C342
SCD1U10V2MX-1
SCD1U10V2MX-1
12
C325
C282
SCD22U10V3KX
SC4D7U10V5ZY
0.22u x 9 4.7u x 9
12
12
12
12
12
12
12
C369
C422
C420
C415
C413
C411
C402
SCD1U10V2MX-1
SCD1U10V2MX-1
SCD1U10V2MX-1
SCD1U10V2MX-1
SCD1U10V2MX-1
SCD1U10V2MX-1
SCD1U10V2MX-1
SCD1U10V2MX-1
SCD1U10V2MX-1
SCD1U10V2MX-1
SC4D7U10V5ZY
C288
C395
C471
C467
12
SCD1U10V2MX-1
12
SCD1U10V2MX-1
12
SCD1U10V2MX-1
12
SCD1U10V2MX-1
78.22423.2B1
SCD22U10V3KX
C295
12
12
12
12
12
C385
C387
C389
C383
SCD1U10V2MX-1
SCD1U10V2MX-1
SCD1U10V2MX-1
SC4D7U10V5ZY
SCD1U10V2MX-1
12
C353
SCD1U10V2MX-1
12
C481
SCD1U10V2MX-1
12
C264
SCD22U10V3KX
SCD1U10V2MX-1
SCD1U10V2MX-1
12
12
C345
C340
SCD1U10V2MX-1
SCD1U10V2MX-1
C349
SCD1U10V2MX-1
C278
12
12
C370
SCD1U10V2MX-1
12
C286
SCD22U10V3KX
C391
SCD1U10V2MX-1
12
C480
C376
SCD1U10V2MX-1
12
C474
C472
SCD1U10V2MX-1
C273
C266
SC4D7U10V5ZY
12
C393
SCD1U10V2MX-1
12
12
C473
SCD1U10V2MX-1
12
12
C470
SCD1U10V2MX-1
12
C292
SCD22U10V3KX
1D25V_S3
LAYOUT:Place one 10uF capacitor
on each end of the VTT island.
1D25V_S3
78.47593.411
SC4D7U10V5ZY
LAYOUT:Add 100pF and 1000pF on VTT fill near
Clawhammer and near DIMMs(both sides).
C104
SC1000P50V
12
C333
SC10U6D3V5MX
78.10610.511
12
C112
SC100P50V2JN
78.10134.1F1
12
12
C335
SC10U6D3V5MX
78.10610.511
C269
SC100P50V2JN
78.10134.1F1
C265
SC1000P50V
LAYOUT:Locate close to Clawhammer socket.
12
TC12
ST100U6D3V-U
77.21071.011
C466 SCD22U10V3KX
C130 SCD22U10V3KX
C202 SCD22U10V3KX
C303 SCD22U10V3KX
C276 SCD22U10V3KX
12
TC8
ST100U6D3V-U
77.21071.011
LAYOUT:Place on backside,
evenly spaced around VTT
fill.
1D25V_S32D5V_S3 1D25V_S32D5V_S3
1 2
78.22423.2B1
1 2
78.22423.2B1
1 2
78.22423.2B1
1 2
78.22423.2B1
1 2
78.22423.2B1
C185
SC4D7U10V-U
78.47523.221
12
C291 SCD22U10V3KX
1 2
C409 SCD22U10V3KX
1 2
C182 SCD22U10V3KX
1 2
C196 SCD22U10V3KX
1 2
C99 SCD22U10V3KX
1 2
C296
SC1000P50V
C203
SCD22U10V3KX
78.22423.2B1
78.22423.2B1
78.22423.2B1
78.22423.2B1
78.22423.2B1
78.22423.2B1
12
C293
SC100P50V2JN
78.10134.1F1
12
C127
SC100P50V2JN
78.10134.1F1
2D5V_S3 1D25V_S31D25V_S3
C125
SC1000P50V
TC16
1 2
ST220U2D5VDM-2
77.22271.071
0.22u x 10
1 1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Title
Size Document Number Rev
A3
A
B
C
D
Date: Sheet
DDR DECOUPLING
Taipei Hsien 221, Taiwan, R.O.C.
Gannet
13 51Thursday, December 04, 2003
-1
E
of
A
AGP_AD[31..0]9,20
Layout trace 20 mil
4 4
3 3
2 2
1 1
Notes:Remove S0,dute to leakage
NEAR NB-MCH
1D5V_S0
12
R228
324R3F
PM_SUS_STAT#9,24
BC244
A
AGP_VREF_VGA
C222
SCD1U16V3KX
78.10421.2B1
12
1D5V_S0
VGA_T_YCLK
VGA_T_MCLK
3D3V_S0
R345
1 2
0R3-U
RN4
3
SRN10KJ
R342 10KR3
12
R244
100R3F
1.5V x (100/(324+100)
= 0.3537V
Set AGP_VREF_VGA to 0.35V for AGP 3.0
SCD01U16V3KX
78.10321.2B1
R687 0R2-0
1 2
R169 0R2-0
1 2
AGP_C/BE#[3..0]9,20
AGP_SBA[7..0]9
AGP_ST[2..0]9
R337
1 2
715R3F64.71505.551
1 2
R347 1KR3
2
14
R302 1KR3
CLK66_VGA3
PCIRST_BUF#19,23,29,31,33,34,37,39,40,42
AGP_REQ#9
AGP_GNT#9
AGP_PAR9
AGP_STOP#9
AGP_DEVSEL#9,20
AGP_TRDY#9
AGP_IRDY#9
AGP_FRAME#9,20
P_INTA#9,23
AGP_WBF#9,20
AGP_RBF#9
AGP_ADSTB09,20
AGP_ADSTB19
AGP_SB_STB9
AGP_SB_STB#9
AGP_ADSTB0#9,20
AGP_ADSTB1#9,20
1 2
R212 39R3F
AGP_ADB_LO9
AGP_PIPE#9
AGP_VREF_CG9
CRMA19,21
LUMA19,21
VGA_COMP_B19,21
12
R339 10KR3
12
R344
10KR3
TP38
TP78
VGA_SUS
PM_C3_STAT#
AGP_BUSY#
1 2
1 2
AGP_AD0
AGP_AD1
AGP_AD2
AGP_AD3
AGP_AD4
AGP_AD5
AGP_AD6
AGP_AD7
AGP_AD8
AGP_AD9
AGP_AD10
AGP_AD11
AGP_AD12
AGP_AD13
AGP_AD14
AGP_AD15
AGP_AD16
AGP_AD17
AGP_AD18
AGP_AD19
AGP_AD20
AGP_AD21
AGP_AD22
AGP_AD23
AGP_AD24
AGP_AD25
AGP_AD26
AGP_AD27
AGP_AD28
AGP_AD29
AGP_AD30
AGP_AD31
AGP_C/BE#0
AGP_C/BE#1
AGP_C/BE#2
AGP_C/BE#3
AGP_SBA0
AGP_SBA1
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA6
AGP_SBA7
AGP_ST0
AGP_ST1
AGP_ST2
AGP_VREF_VGA
VGA_AGPTEST
VGA_R2SET
DACB_HSYNC
DACB_VSYNC
DDC3DATA
1 2
R343 10KR3
XTALIN_M10
XTALOUT_M10
VGA_TESTEN
VGA_T_YCLK
VGA_T_MCLK
VGA_TP31
VGA_RSTB
B
DDC3CLK
SSIN
SSOUT
B
H29
H28
K29
K28
N28
P29
P28
R29
R28
T29
T28
U29
N25
R26
P25
R27
R25
T25
T26
U25
V27
W26
W25
Y26
Y25
AA26
AA25
AA27
N29
U28
P26
U26
AG30
AG28
AF28
AD26
M25
N26
V29
V28
W29
W28
AE26
AC26
AE29
M28
V25
AB29
AD28
AD29
AC28
AC29
AA28
AA29
Y28
Y29
AF29
AD27
AE28
AB28
M29
V26
M26
M27
AB26
AB25
AC25
AK21
AJ23
AJ22
AK22
AJ24
AK24
AG23
AG24
AK25
AJ25
AH28
AJ29
AH27
AE25
AG26
AH30
AH29
AG29
J29
J28
L29
L28
E8
B6
U23A
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
C/BE#0
C/BE#1
C/BE#2
C/BE#3
PCICLK
RST#
REQ#
GNT#
PAR
STOP#
DEVSEL#
TRDY#
IRDY#
FRAME#
INTA#
WBF#
RBF#
AD_STBF_0
AD_STBF_1
SB_STBF
SBA0
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7
ST0
ST1
ST2
SB_STBS
ADSTBS_0
ADSTBS_1
AGPREF
AGPTEST
AGP
DBI_LO
DBI_HI
AGP8X_DET#
R2SET
C_R
Y_G
COMP_B
H2SYNC
V2SYNC
DDC3CLK
DDC3DATA
SSIN
SSOUT
XTALIN
XTALOUT
TESTEN
TEST_YCLK(NC)
TEST_MCLK(NC)
PLLTEST(NC)
SUS_STAT#
STP_AGP#
AGP_BUSY#
RSTB_MSK(NC)
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
PCI/AGP
GPIO16
DVD/EXT TMDS/GPIO
DVOMODE
ZV_LCDDATA0
ZV_LCDDATA1
ZV_LCDDATA2
ZV_LCDDATA3
ZV_LCDDATA4
ZV_LCDDATA5
ZV_LCDDATA6
ZV_LCDDATA7
ZV_LCDDATA8
ZV_LCDDATA9
ZV_LCDDATA10
ZV_LCDDATA11
ZV_LCDDATA12
ZV_LCDDATA13
ZV_LCDDATA14
ZV_LCDDATA15
ZV_LCDDATA16
ZV_LCDDATA17
ZV_LCDDATA18
ZV_LCDDATA19
ZV_LCDDATA20
ZV_LCDDATA21
ZV_LCDDATA22
ZV_LCDDATA23
ZV_LCDCNTL0
ZV_LCDCNTL1
ZV_LCDCNTL2
ZV_LCDCNTL3
(NC)VREFG
TXOUT_L0N
TXOUT_L0P
TXOUT_L1N
TXOUT_L1P
TXOUT_L2N
TXOUT_L2P
TXOUT_L3N
TXOUT_L3P
AGP2X
TXCLK_LN
TXCLK_LP
TXOUT_U0N
TXOUT_U0P
TXOUT_U1N
TXOUT_U1P
TXOUT_U2N
TXOUT_U2P
TXOUT_U3N
TXOUT_U3P
TXCLK_UN
TXCLK_UP
DIGON
BLON
TX0M
TX0P
TX1M
8X 4XDAC2SSCLK
PWR
MAN
DDC2CLK
DDC2DATA
HSYNC
VSYNC
DDC1DATA
DDC1CLK
AUXWIN
DPLUS
DMINUS
THERM DAC1 TMDS LVDS
TX1P
TX2M
TX2P
TXCM
TXCP
HPD1
RSET
R
G
B
AJ5
AH5
AJ4
AK4
AH4
AF4
AJ3
AK3
AH3
AJ2
AH2
AH1
AG3
AG1
AG2
AF3
AF2
VGA_DVDMODE
AE10
AH6
AJ6
AK6
AH7
AK7
AJ7
AH8
AJ8
AH9
AJ9
AK9
AH10
AE6
AG6
AF6
AE7
AF7
AE8
AG8
AF8
AE9
AF9
AG10
AF10
AJ10
AK10
AJ11
AH11
AG4
AK16
AH16
AH17
AJ16
AH18
AJ17
AK19
AH19
AK18
AJ18
AG16
AF16
AG17
AF17
AF18
AE18
AH20
AG20
AF19
AG19
AE12
AG12
AJ13
AH14
AJ14
AH15
AJ15
AK15
AH13
AK13
AE13
AE14
AF12
AK27
AJ27
AJ26
AG25
AH25
AH26
AF25
AF24
AF26
VGA_TP32
AF11
VGA_TP33
AE11
M10-P-U
VGA_GPIO0
VGA_GPIO1
VGA_GPIO2
VGA_GPIO3
VGA_GPIO4
VGA_GPIO6
VGA_GPIO7
VGA_GPIO8
VGA_GPIO9
VGA_TP3
VGA_TP4
VGA_TP5
VGA_TP6
VGA_TP7
VGA_TP8
VGA_TP9
VGA_TP10
VGA_TP11
VGA_TP12
VGA_TP13
VGA_TP14
VGA_TP15
VGA_TP16
VGA_TP17
VGA_TP18
VGA_TP19
VGA_TP20
VGA_TP21
VGA_TP22
PL_ID3
PL_ID0
PL_ID1
PL_ID2
VGA_TP27
VGA_TP28
VGA_TP29
VGA_TP30
L3N_TEST
L3P_TEST
VGA_TP34
VGA_TP35
VGA_TP36
VGA_TP37
VGA_TP38
VGA_TP39
VGA_TP40
VGA_TP41
VGA_RSET
VGA_DDCDAT_1_3
VGA_DDCCLK_1_3
VGA_AUXWIN
C
VGA_GPIO5
VGA_GPIO10
VGA_GPIO11
VGA_GPIO12
VGA_GPIO13
VGA_GPIO14
VGA_GPIO15
VGA_GPIO16
DDC2CLK
DDC2DATA
VGA_TP42
R496
1 2
PL_ID3 22
PL_ID0 22
PL_ID1 22
PL_ID2 22
VGA_VREFG
TXAOUT0- 20,22
TXAOUT0+ 20,22
TXAOUT1- 20,22
TXAOUT1+ 20,22
TXAOUT2- 20,22
TXAOUT2+ 20,22
TP108
TP112
TXACLK- 20,22
TXACLK+ 20,22
TXBOUT0- 20,22
TXBOUT0+ 20,22
TXBOUT1- 20,22
TXBOUT1+ 20,22
TXBOUT2- 20,22
TXBOUT2+ 20,22
TXBCLK- 20,22
TXBCLK+ 20,22
LCDVDD_ON 22
BL_ON 22
VGA_RED 9,21
VGA_GREEN 9,21
VGA_BLUE 9,21
VGA_HSYNC 9,21
VGA_VSYNC 9,21
R566
R572 33R2
71.00M10.A0U
C
0R3-U
TP67TPAD30
TP63TPAD30
TP55TPAD30
TP62TPAD30
TP44TPAD30
TP54TPAD30
TP42TPAD30
TP45TPAD30
TP72TPAD30
TP64TPAD30
TP43TPAD30
TP56TPAD30
TP83TPAD30
TP70TPAD30
TP77TPAD30
TP84TPAD30
TP76TPAD30
TP81TPAD30
TP73TPAD30
TP79TPAD30
3D3V_S0
TP47TPAD30
TP96TPAD30
TP48TPAD30
TP57TPAD30
TP98TPAD30
TP86TPAD30
TP99TPAD30
TP87TPAD30
TP103TPAD30
TP107TPAD30
TP58TPAD30
TP49TPAD30
TP80TPAD30
1 2
33R2
12
12
1 2
R305 10KR3
TP74TPAD30
TP82TPAD30
SC20P50V3JX
12
R568
1KR3F
64.10015.651
12
R577
1KR3F
64.10015.651
R346499R3F
12
BC331
VGA_DDCDAT_3 9,21
VGA_DDCCLK_3 9,21
12
R402
1MR3
BC332
SC6P50V3DN
D
X7
XTAL-27MHZ-3-U
1 2
82.30034.001
C275
SCD1U16V3KX
DDC2CLK
DDC3CLK
DDC2DATA
DDC3DATA
3D3V_S0
D
XTALIN_SS
XTALOUT_SS
R393
1 2
330R3F
E
U32
1
XIN/CLKIN
2
XOUT
3
PD#
4 5
LF VSS
P2779A-08ST
ORIGNAL
P2779A-08TT
12
RN82
1
8
2
7
3
6
4 5
SRN10K
66.10336.080
Title
Size Document Number Rev
A3
Date: Sheet
USE W180-01
GEOMETRY
C283
SC270P50V
VGA_GPIO0
VGA_GPIO1
VGA_GPIO2
VGA_GPIO3
VGA_GPIO4
VGA_GPIO5
VGA_GPIO6
VGA_GPIO7
VGA_GPIO8
VGA_GPIO9
VGA_GPIO10
VGA_GPIO11
VGA_GPIO12
VGA_GPIO13
VGA_GPIO14
VGA_GPIO15
VGA(1/3)_ATI M10-P HOST
Gannet
8
VDD
7
REF
6
MODOUT
XTALIN_M10VGA_SS_LF_1 VGA_SS_LF
1 2
1 2
R329 DUMMY-R3
1 2
R328 DUMMY-R3
1 2
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
14 51Thursday, December 04, 2003
E
3D3V_S02,3,8,9,10,11,16,19,20,21,22,23,24,25,27,28,29,31,32,33,34,35,36,37,38,39,40,41,42,43,47,48,49,51
1D5V_S02,9,10,16,20,49
R397
0R5
3D3V_SS_S0
XTALIN_VGA
VGA_GPIO16
R336
R331
RN7
1
2
3
4 5
SRN10K
66.10336.080
RN5
1
2
3
4 5
SRN10K
66.10336.080
RN3
1
2
3
4 5
SRN10K
66.10336.080
of
3D3V_S0
1D5V_S0
3D3V_S0
12
12
R373
140R3F
12
R372
105R3F
10KR3
10KR3
8
7
6
8
7
6
8
7
6
C279
SCD1U
3D3V_S0
-1
A
FBAD[63:0]17 FBCD[63:0]18
FBAD0
FBAD1
FBAD2
FBAD3
FBAD4
FBAD5
FBAD6
FBAD7
FBAD8
4 4
3 3
2 2
FBAD9
FBAD10
FBAD11
FBAD12
FBAD13
FBAD14
FBAD15
FBAD16
FBAD17
FBAD18
FBAD19
FBAD20
FBAD21
FBAD22
FBAD23
FBAD24
FBAD25
FBAD26
FBAD27
FBAD28
FBAD29
FBAD30
FBAD31
FBAD32
FBAD33
FBAD34
FBAD35
FBAD36
FBAD37
FBAD38
FBAD39
FBAD40
FBAD41
FBAD42
FBAD43
FBAD44
FBAD45
FBAD46
FBAD47
FBAD48
FBAD49
FBAD50
FBAD51
FBAD52
FBAD53
FBAD54
FBAD55
FBAD56
FBAD57
FBAD58
FBAD59
FBAD60
FBAD61
FBAD62
FBAD63
K25
K26
H25
H26
G26
G30
D29
D28
E28
E29
G29
G28
F28
G25
F26
E26
F25
E24
F23
E23
D22
B29
C29
C25
C27
B28
B25
C26
B26
F17
E17
D16
F16
E15
F14
E14
F13
C17
B18
B17
B15
C13
B14
C14
C16
A13
A12
C12
B12
C10
B10
E13
E12
E10
F12
F11
U23B
L25
DQA0
L26
DQA1
DQA2
DQA3
J26
DQA4
DQA5
DQA6
DQA7
DQA8
DQA9
DQA10
DQA11
DQA12
(MAA13)MAA12
DQA13
(MAA12)MAA13
DQA14
DQA15
DQA16
DQA17
DQA18
DQA19
DQA20
DQA21
DQA22
DQA23
DQA24
DQA25
DQA26
DQA27
DQA28
DQA29
DQA30
DQA31
DQA32
DQA33
DQA34
DQA35
DQA36
DQA37
DQA38
DQA39
DQA40
DQA41
DQA42
DQA43
DQA44
DQA45
DQA46
DQA47
DQA48
DQA49
DQA50
DQA51
DQA52
C9
DQA53
B9
DQA54
DQA55
DQA56
DQA57
DQA58
DQA59
DQA60
E9
DQA61
F9
DQA62
F8
DQA63
M10-P-U
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
(NC)MAA14
DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7
QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7
RASA#
CASA#
WEA#
CSA0#
CSA1#
CKEA
CLKA0
CLKA0#
CLKA1
CLKA1#
MVREFD
MVREFS
DIMA_0
DIMA_1
E22
B22
B23
B24
C23
C22
F22
F21
C21
A24
C24
A25
E21
B20
C19
J25
F29
E25
A27
F15
C15
C11
E11
J27
F30
F24
B27
E16
B16
B11
F10
A19
E18
E19
E20
F20
B19
B21
C20
C18
A18
B7
B8
D30
B13
VGA_TP2
FBADQM0
FBADQM1
FBADQM2
FBADQM3
FBADQM4
FBADQM5
FBADQM6
FBADQM7
FBADQS0
FBADQS1
FBADQS2
FBADQS3
FBADQS4
FBADQS5
FBADQS6
FBADQS7
TP_FBACS1
MVREFD
MVREFS
FBAA0
FBAA1
FBAA2
FBAA3
FBAA4
FBAA5
FBAA6
FBAA7
FBAA8
FBAA9
FBAA10
FBAA11
FBAA12
FBAA13
DIMA_0
DIMA_1
B
FBAA[13:0] 17
TP28TPAD30
FBADQM[7:0] 17
FBADQS[7:0] 17
FBARAS# 17
FBACAS# 17
FBAWE# 17
FBACS0# 17
TP160 TPAD30
FBACLK0+ 17
FBACLK0- 17
FBACLK1+ 17
FBACLK1- 17
TP30
TP26
12
R170
10KR2
FBACKE 17
C
U23C
FBCD0
D7
AD6
AD5
AE5
AE4
AB2
AB3
AC2
AC3
AD3
AE1
AE2
AE3
AA2
AA6
AA5
AB6
AB5
G6
G5
C4
C5
C2
D3
D1
D2
G4
H6
H5
G2
H2
H3
U6
U5
U3
W5
W4
U2
W3
F7
E7
F5
E5
B5
A4
B4
J6
K5
K4
L6
L5
F3
E2
F2
J3
F1
V6
Y6
Y5
V2
V1
V3
Y2
Y3
M10-P-U
DQB0
DQB1
DQB2
DQB3
DQB4
DQB5
DQB6
DQB7
DQB8
DQB9
DQB10
DQB11
DQB12
DQB13
DQB14
DQB15
DQB16
DQB17
DQB18
DQB19
DQB20
DQB21
DQB22
DQB23
DQB24
DQB25
DQB26
DQB27
DQB28
DQB29
DQB30
DQB31
DQB32
DQB33
DQB34
DQB35
DQB36
DQB37
DQB38
DQB39
DQB40
DQB41
DQB42
DQB43
DQB44
DQB45
DQB46
DQB47
DQB48
DQB49
DQB50
DQB51
DQB52
DQB53
DQB54
DQB55
DQB56
DQB57
DQB58
DQB59
DQB60
DQB61
DQB62
DQB63
(MAB13)MAB12
(MAB12)MAB13
MEMVMODE_0
MEMVMODE_1
FBCD1
FBCD2
FBCD3
FBCD4
FBCD5
FBCD6
FBCD7
FBCD8
FBCD9
FBCD10
FBCD11
FBCD12
FBCD13
FBCD14
FBCD15
FBCD16
FBCD17
FBCD18
FBCD19
FBCD20
FBCD21
FBCD22
FBCD23
FBCD24
FBCD25
FBCD26
FBCD27
FBCD28
FBCD29
FBCD30
FBCD31
FBCD32
FBCD33
FBCD34
FBCD35
FBCD36
FBCD37
FBCD38
FBCD39
FBCD40
FBCD41
FBCD42
FBCD43
FBCD44
FBCD45
FBCD46
FBCD47
FBCD48
FBCD49
FBCD50
FBCD51
FBCD52
FBCD53
FBCD54
FBCD55
FBCD56
FBCD57
FBCD58
FBCD59
FBCD60
FBCD61
FBCD62
FBCD63
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
(NC)MAB14
DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7
QSB0
QSB1
QSB2
QSB3
QSB4
QSB5
QSB6
QSB7
RASB#
CASB#
WEB#
CSB0#
CSB1#
CKEB
CLKB0
CLKB0#
CLKB1
CLKB1#
DIMB_0
DIMB_1
ROMCS#
MEMTEST
D
N5
M1
M3
L3
L2
M2
M5
P6
N3
K2
K3
J2
P5
P3
P2
E6
B2
J5
G3
W6
W2
AC6
AD2
F6
B3
K6
G1
V5
W1
AC5
AD1
R2
T5
T6
R5
R6
R3
N1
N2
T2
T3
E3
AA3
AF5
C6
C7
C8
FBCA0
FBCA1
FBCA2
FBCA3
FBCA4
FBCA5
FBCA6
FBCA7
FBCA8
FBCA9
FBCA10
FBCA11
FBCA12
FBCA13
VGA_TP1
FBCDQM0
FBCDQM1
FBCDQM2
FBCDQM3
FBCDQM4
FBCDQM5
FBCDQM6
FBCDQM7
FBCDQS0
FBCDQS1
FBCDQS2
FBCDQS3
FBCDQS4
FBCDQS5
FBCDQS6
FBCDQS7
VGA_TP43
MEMVMODE0
MEMVMODE1
VGA_MEMTEST
TP_FBCCS1
DIMB_0
DIMB_1
FBCA[13:0] 18
TP32TPAD30
FBCDQM[7:0] 18
FBCDQS[7:0] 18
FBCRAS# 18
FBCCAS# 18
FBCWE# 18
FBCCS0# 18
TP131 TPAD30
FBCCLK0+ 18
FBCCLK0- 18
FBCCLK1+ 18
FBCCLK1- 18
TP162
TP85
TP75
R167
1 2
E
1D8V_S0
1D8V_S016,49,50
VVGADDR16,17,18,46,49
FBCCKE 18
12
R255
10KR2
47R363.47034.151
VVGADDR
VVGADDR VVGADDR
12
R165
100R3F
12
R176
100R3F
1 1
A
C40
SCD1U
78.10492.4B1
12
C69
SC10U10V5ZY
78.10693.411
12
R177
100R3F
MVREFSMVREFD
R166
100R3F
12
C55
SCD1U
78.10492.4B1
SC10U10V5ZY
78.10693.411
12
C70
MEMVMODE1
MEMVMODE0
12
12
R686
4K7R3
63.47234.151
B
C
R681
DUMMY-R3
R685 DUMMY-R3
1 2
R682
1 2
4K7R3
63.47234.151
1D8V_S0
MEMMODE0 MEMMODE1
2D5V
VDDR1
1D8V
VDDR1(ELPIDA)
Title
VGA(2/3) ATI M10-P MEM
Size Document Number Rev
A3
D
Date: Sheet
0
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Gannet
01
1
15 51Thursday, December 04, 2003
E
-1
of
A
U23E
A2
VSS
A10
VSS
A16
VSS
A22
VSS
A29
VSS
C1
VSS
C3
VSS
C28
VSS
C30
VSS
1D2V_S0
D27
D24
D21
D18
D15
D12
F27
G12
G16
G18
G21
G24
H27
H23
H21
H18
H16
H14
H12
K30
K27
K24
K23
AG15
AD12
AE27
AG5
AG9
AG11
AG18
AG22
AG27
AB4
P17
P18
P19
U12
U13
U14
U17
U18
U19
V19
V18
V17
V14
V13
V12
N18
N17
N14
W17
W18
W12
W13
W14
N13
N19
M19
M18
M12
N12
M13
M14
P12
P13
P14
M17
W19
G9
D9
D6
D4
H9
H8
H4
E4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
M10-P-U
U23F
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
M10-P-U
4 4
3 3
2 2
1 1
K8
VSS
K7
VSS
K1
VSS
L4
VSS
M30
VSS
M8
VSS
M7
VSS
N23
VSS
N24
VSS
N27
VSS
P4
VSS
R7
VSS
R8
VSS
R23
VSS
R24
VSS
R30
VSS
T27
VSS
T1
VSS
U4
VSS
U8
VSS
U23
VSS
V30
VSS
W7
VSS
W8
VSS
W23
VSS
W24
VSS
W27
VSS
Y4
VSS
AA30
VSS
AB27
VSS
AB24
VSS
AB23
VSS
AB8
VSS
AB7
VSS
AB1
VSS
AC4
VSS
AC12
VSS
AC14
VSS
AD16
VSS
AC16
VSS
AC18
VSS
AD30
VSS
AD25
VSS
AD18
VSS
AK2
VSS
AK29
VSS
AJ30
VSS
AJ1
VSS
D10
VSS
D25
VSS
1D8VLVDDR_S0
M16
VSS
N16
VSS
N15
VSS
P15
VSS
P16
VSS
R18
VSS
R17
VSS
R16
VSS
R15
VSS
R14
VSS
R13
VSS
R12
VSS
T13
VSS
T14
VSS
T15
VSS
W15
VSS
V16
VSS
V15
VSS
U15
VSS
U16
VSS
T19
VSS
T18
VSS
T17
VSS
T16
VSS
1D2V_S0
W16
VDDC1
M15
VDDC1
R19
VDDC1
T12
VDDC1
A
1D8VAVDD_S0
1D8VAVDDDI_S0
1D8VMPVDD_S0
12
BCB5
SCD01U16V3KX
2D5V_S0
1D8VPLL_S0
1D8VLVDDR_S0
VVGADDR
2D5VATI_S0
1D8VPVDD_S0
1D2V_S0
VVGADDR
BC309
SC10U10V6ZY-U
78.10693.4I1
B
U23D
T7
VDDR1
R4
VDDR1(CLKBFB)
R1
VDDR1
N8
VDDR1
N7
VDDR1
M4
VDDR1
L27
VDDR1
L8
VDDR1
J24
VDDR1
J23
VDDR1
J8
VDDR1
J7
VDDR1
J4
VDDR1
J1
VDDR1
H10
VDDR1
H13
VDDR1
H15
VDDR1
H17
VDDR1
T8
VDDR1
V4
VDDR1
V7
VDDR1
V8
VDDR1
AA1
VDDR1
AA4
VDDR1
AA7
VDDR1
AA8
VDDR1
A3
VDDR1
A9
VDDR1
A15
VDDR1
A21
VDDR1
A28
VDDR1
B1
VDDR1
B30
VDDR1
D26
VDDR1
D23
VDDR1
D20
VDDR1
D17
VDDR1
D14
VDDR1
D11
VDDR1
D8
VDDR1
D5
VDDR1
E27
VDDR1
F4
VDDR1
G7
VDDR1
G10
VDDR1
G13
VDDR1
G15
VDDR1
G19
VDDR1
G22
VDDR1
G27
VDDR1
H22
VDDR1
H19
VDDR1
AD4
VDDR1
T4
VDDR1
N4
VDDR1
D19
VDDR1(CLKAFB)
D13
VDDR1
AE17
LVDDR_25(LVDDR18_25)
AE20
LVDDR_25(LVDDR18_25)
AE15
LVDDR_18
AF21
LVDDR_18
AJ20
LPVDD
AK12
TPVDD
AF13
TXVDDR
AF14
TXVDDR
F18
VDDRH0
N6
VDDRH1
AG21
A2VDD
AH21
A2VDD
AF22
A2VDDQ
AH24
AVDD
AE24
VDD1DI
AE22
VDD2DI
AK28
PVDD
A7
MPVDD
BC294
SC10U10V6ZY-U
78.10693.4I1
B
D11
2 1
SSM5818SL
12
BC226
SCD1U10V2KX
(VDDC18)VDD15
(VDDC18)VDD15
(VDDC18)VDD15
(VDDC18)VDD15
(VDDC18)VDD15
(VDDC18)VDD15
(VDDC18)VDD15
(VDDC18)VDD15
M10-P-U
3D3V_S0
12
BC227
SCD1U10V2KX
VDDC
VDDC
VDDC
VDDC
VDDC
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR4
VDDR4
VDDR4
VDDR4
VDDR4
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
AVSSQ
LVSSR
LVSSR
LVSSR
LVSSR
LPVSS
TPVSS
TXVSSR
TXVSSR
TXVSSR
VSSRH0
VSSRH1
A2VSSN
A2VSSN
A2VSSQ
AVSSN
ASS1DI
VSS2DI
PVSS
MPVSS
12
BC230
SCD1U10V2KX
AC13
AD13
AD15
AC15
AC17
P8
Y8
AC11
AC20
Y23
L23
H20
H11
AD7
AD19
AD21
AD22
AC22
AC21
AC19
AC8
AG7
AD9
AC9
AC10
AD10
J30
AF27
AE30
AC27
AC23
AB30
AA24
AA23
Y27
W30
V23
V24
M23
M24
N30
P23
P27
T23
T24
T30
U27
AD24
AF20
AE19
AE16
AF15
AJ19
AJ12
AH12
AG13
AG14
F19
M6
AH22
AJ21
AF23
AH23
AE23
AE21
AJ28
A6
12
BC203
SCD1U10V2KX
1D2V_S0
1D5V_S0
3D3V_S0
3D3V_S0
1D5V_S0
12
BC213
SCD1U10V2KX
C
3D3V_S0
SSM5818SL
12
BC212
SCD1U10V2KX
C
D3
12
BC238
SCD1U10V2KX
1D2V_S0: 7020mA
1D5V_S0: 500mA
1D8V_S0: 407mA
VVGADDR: 490mA
2D5V_S0 2D5VATI_S0
L36
1 2
1D8V_S0
VVGADDR
21
12
BCB11
SCD01U16V3KX
BC293
SC22U10V6ZY-U
0R5
L35
1 2
0R5
BC268
SC10U10V6ZY-U
78.10693.4I1
12
BCB12
SCD01U16V3KX
1D5V_S0
3D3V_S0
SC10U10V6ZY-U
78.10693.4I1
1D8V_S0 1D8VPLL_S0 1D8VPVDD_S0
1 2
BC162
SC22U10V6ZY-U
SC4D7U16V6ZY-U
1D8VLVDDR_S0
12
SCD1U10V2KX
12
SCD1U10V2KX
12
SCD1U10V2KX
BC265
SC10U10V6ZY-U
78.10693.4I1
High limit. 1.0 mm
BC188
L25
0R5
BC311
BC177
BC215
BC254
DUMMY-SC4D7U10V5ZY
ZZ.47593.411
SCD1U10V2KX
SCD1U10V2KX
12
BC175
SCD1U10V2KX
12
BC202
SCD1U10V2KX
12
BC255
SCD1U10V2KX
BC261
SC10U10V6ZY-U
78.10693.4I1
BC180
SCD1U10V2KX
12
12
BC306
SCD1U10V2KX
D
12
BC307
SCD1U10V2KX
12
BC174
SCD1U10V2KX
12
BC240
SCD1U10V2KX
12
BC285
SCD1U10V2KX
12
BC211
SCD1U10V2KX
SCD1U10V2KX
12
BC198
SCD1U10V2KX
1D8V_S0
L33
1 2
0R5
BC304
D
12
BC310
12
BC171
SCD1U10V2KX
12
BC250
SCD1U10V2KX
12
BC258
SCD1U10V2KX
12
BC192
12
BC183
SCD1U10V2KX
SCD1U10V2KX
E
1D8V_S0
12
12
BC172
BC173
SCD1U10V2KX
SCD1U10V2KX
12
12
BC252
BC253
SCD1U10V2KX
SCD1U10V2KX
12
BC219
BC284
SCD1U10V2KX
SC22U10V6ZY-U
12
12
BC199
BC251
SCD1U10V2KX
SCD1U10V2KX
12
12
BC269
BC194
SCD1U10V2KX
SCD1U10V2KX
1D8V_S0
L8
12
BC170
1 2
0R5
Title
Size Document Number Rev
A3
Date: Sheet
1D8VAVDD_S0
L34
1 2
12
SCD1U10V2KX
12
BC195
0R5
12
BC193
SCD1U10V2KX
BC223
SC22U10V6ZY-U
BC200
SCD1U10V2KX
12
SCD1U10V2KX
12
SCD1U10V2KX
12
12
BC179
BC182
SCD1U10V2KX
SCD1U10V2KX
BC282
SC22U10V6ZY-U
12
12
BC241
BC256
SC22U10V6ZY-U
SCD1U10V2KX
BC166
BC196
BC167
BC168
SC22U10V6ZY-U
SC22U10V6ZY-U
1D8V_S0
L41
1 2
0R5
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
SCD1U10V2KX
BC208
VGA(3/3) ATI M10-P POWER
Gannet
E
1D2V_S02,46
1D5V_S02,9,10,14,20,49
1D8V_S015,49,50
2D5V_S06,8,9,10,19,20,23,24,25,31,48,50
3D3V_S02,3,8,9,10,11,14,19,20,21,22,23,24,25,27,28,29,31,32,33,34,35,36,37,38,39,40,41,42,43,47,48,49,51
VVGADDR15,17,18,46,49
12
BC181
SC4D7U16V6ZY-U
BC291
SC22U10V6ZY-U
BC201
SC22U10V6ZY-U
BC302
SC22U10V6ZY-U
SC22U10V6ZY-U
1D8VAVDDDI_S01D8VMPVDD_S0
12
BC189
SCD1U10V2KX
16 51Thursday, December 04, 2003
of
BC187
BC164
SCD1U10V2KX
1D2V_S0
1D5V_S0
1D8V_S0
2D5V_S0
3D3V_S0
VVGADDR
12
BC191
-1
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