Wistron G48, G58 Schematic

5

4

3

2

1

D D

UMA & Optimus Schematics Document

IVY Bridge(rPGA989)

Intel PCH(Panther Point)

C C

DY :None Installed UMA:UMA platform installed OPS:Optimus HR:Huron River

B B

CRV:Chief River

A A

5

4

3

2

JV10-CS

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet of

Date: Sheet of

Cover Page

Taipei Hsien 221, Taiwan, R.O.C.

G48/G58

1

1 103Friday, February 17, 2012

SC

5

##OnMainBoard

VRAM

D D

2GB/1GB/512MB

88,89,90,91

DDR3 900MHz

NVIDIA

N13P-GL N13M-GE

83.84,85,86,87

C C

HDMI 1.4

LCD 14"/15"

CRT

B B

SD/MMC+

51

49

50

Bluetooth

CAMERA

63

49

CardReader

AU6435

74

4

3

Block Diagram (UMA/Optimus co-lay)

4

(Discrete only)

USB 2.0 x 1

PCIe x 16

HDMI

LVDS

RGB CRT

USB2.0 x 2

AZALIA

Intel CPU

IVY Bridge

FDI x 4 x 2 (UMA only)

PCH Panther Point

USB 3.0/2.0 ports (14)

ETHERNET (10/100/1000Mb)

High Definition Audio

SATA ports (6) PCIE ports (8)

17,18,19,20,21,22,23,24,25

4,5,6,7,8,9,10

DMI x 4

Intel

LPC I/F ACPI 1.1

Project code : 91.4SG01.001 PCB P/N : Revision :

DDRIII 1600/1333/1066 Channel A

DDRIII 1600/1333/1066 Channel B

10/100/1000M LAN

PCIE x 1

PCIE x 1/USB2.0 x 1

USB3_TX/USB3_RX x 2

USB 2.0 x 2

SATA x 2

AR8161/AR8162

Mini-Card

WLAN/WiMAX

USB3.0 x 2

USB2.0 x 2

DDRIII 1600/1333/1066

31

65

HDD

2

Slot 0

Slot 1

RJ45 CONN

56

SYSTEM DC/DC

INPUTS

DCBATOUT

SYSTEM DC/DC

INPUTS

DCBATOUT

14

15

59

TPS51461

OUTPUTS

VCCSA

TPS51211

OUTPUTS

1D05V_S0

1

48 42~44

CPU DC/DC

TPS51640RSLR

INPUTS

DCBATOUT

SYSTEM DC/DC

45

G977F

INPUTS

DCBATOUT

SYSTEM DC/DC

TPS51123

INPUTS

DCBATOUT 5V_S5

SYSTEM DC/DC

RT8207

INPUTS

DCBATOUT

GFX DC/DC

TPS51640RSLR

INPUTS

DCBATOUT

VGA

ISL62882C

INPUTS

DCBATOUT

CHARGER

BQ24745

INPUTS

AD+ BT+

26

SYSTEM DC/DC

RT9025

INPUTS

3D3V_S5

VGA switchs

INPUTS OUTPUTS

26

1D5V_S3 3D3V_S0 1D05V_VTT 1D05V_VGA_S0

OUTPUTS

VCC_CORE

OUTPUTS

1D0V_S0

OUTPUTS

5V_AUX_S5 3D3V_AUX_S5

3D3V_S5

OUTPUTS

1D5V_S3 0D75V_S0 DDR_VREF_S3

OUTPUTS

VCC_GFXCORE

OUTPUTS

VGA_CORE

OUTPUTS

DCBATOUT

OUTPUTS

1D8V_S0

1D5V_VGA_S0 3D3V_VGA_S0

45

41

46

42~44

92

40

47

93

Switches

Internal AMIC

Azalia CODEC

Combo Jack

A A

Codec_ALC269Q

29

Fan

SPI

Flash ROM

8MB

28

60

LPC Bus

KBC

NUVOTON NPCE885P

LPC debug port

SMBus

27

71

ODD

56

JV10-CS

2CH SPEAKER

Title

Touch PAD

5

4

69

KB

69 25

ThermalInt.

EMC1423

3

28

2

Title

Size Document Number Rev

A3

Date: Sheet of

Block Diagram

INPUTS OUTPUTS

1D5V_S3 5V_S5

1D5V_S0 5V_S0 3D3V_S03D3V_S5

PCB LAYER

L1:Top L2:VCC L3:Signal

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

G48/G58

1

L4:Signal L5:GND L6:Bottom

2

SC

103Friday, February 17, 2012

5

PCH Strapping

Huron River Schematic Checklist Rev.0_7

Name Schematics Notes

SPKR

INIT3_3V# Weak internal pull-up. Leave as "No Connect". GNT3#/GPIO55

D D

GNT2#/GPIO53 GNT1#/GPIO51

SPI_MOSI

NV_ALE

Reboot option at power-up

Internal weak Pull-down.

Default Mode:

Connect to Vcc3_3 with 8.2-kΩ

No Reboot Mode with TCO Disabled:

- 10-kΩ weak pull-up resistor.

GNT[3:0]# functionality is not available on Mobile. Mobile: Used as GPIO only Pull-up resistors are not required on these signals. If pull-ups are used, they should be tied to the Vcc3_3power rail.

Enable Danbury:

Disable Danbury:

Enable Danbury:

Disable Danbury:

Connect to Vcc3_3 with 8.2-k? weak pull-up resistor.

Left floating, no pull-down required.

Connect to +NVRAM_VCCQ with 8.2-kohm weak pull-up resistor [CRB has it pulled up with 1-kohm no-stuff resistor]

Leave floating (internal pull-down)

4

3

Processor Strapping

Pin Name Strap Description Configuration (Default value for each bit is

CFG[2]

PCI-Express Static Lane Reversal

CFG[4]

CFG[6:5]

CFG[7]

PCI-Express Port Bifurcation Straps

PEG DEFER TRAINING

1 unless specified otherwise)

1:

Normal Operation. Lane Numbers Reversed 15 -> 0, 14 -> 1, ...

0:

Disabled - No Physical Display Port attached to

1:

Embedded DisplayPort. Enabled - An external Display Port device is

0:

connectd to the EMBEDDED display Port

11 : x16 - Device 1 functions 1 and 2 disabled 10 : x8, x8 - Device 1 function 1 enabled ; function 2 disabled 01 : Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00 : x8, x4, x4 - Device 1 functions 1 and 2 enabled

1:

PEG Train immediately following xxRESETB de assertion PEG Wait for BIOS for training

0:

2

Huron River Schematic Checklist Rev.0_7

Default Value

1

0

11

1

NC_CLE DMI termination voltage. Weak internal pull-up. Do not pull low.

Low (0) - Flash Descriptor Security will be overridden. Also, when this signals is sampled on the rising edge of PWROK then it will also disable Intel ME and its features.

HAD_DOCK_EN# /GPIO[33]

C C

High (1) - Security measure defined in the Flash Descriptor will be enabled. Platform design should provide appropriate pull-up or pull-down depending on the desired settings. If a jumper option is used to tie this signal to GND as required by the functional strap, the signal should be pulled low through a weak pull-down in order to avoid asserting HDA_DOCK_EN# inadvertently. Note: CRB recommends 1-kohm pull-down for FD Override. There is an internal pull-up of 20 kohm for DA_DOCK_EN# which is only enabled at boot/reset for strapping functions.

HDA_SDO Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#. HDA_SYNC

GPIO15

GPIO8

B B

GPIO27

Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#. Low (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with no

confidentiality High (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with confidentiality

Note : This is an un-muxed signal. This signal has a weak internal pull-down of 20 kohm which is enabled when PWROK is low. Sampled at rising edge of RSMRST#. CRB has a 1-kohm pull-up on this signal to +3.3VA rail.

GPIO8 on PCH is the Integrated Clock Enable strap and is required to be pulled-down using a 1k +/- 5% resistor. When this signal is sampled high at the rising edge of RSMRST#, Integrated Clocking is enabled, When sampled low, Buffer Through Mode is enabled.

Default = Do not connect (floating)

High(1) = Enables the internal VccVRM to have a clean supply for analog rails. No need to use on-board filter circuit. Low (0) = Disables the VccVRM. Need to use on-board filter circuits for analog rails.

POWER PLANE

5V_S0 3D3V_S0 1D8V_S0 1D5V_S0 1D05V_VTT 0D85V_S0 0D75V_S0 VCC_CORE VCC_GFXCORE 1D8V_VGA_S0 3D3V_VGA_S0 1V_VGA_S0

5V_USBX_S3 1D5V_S3 DDR_VREF_S3

BT+ DCBATOUT 5V_S5 5V_AUX_S5 3D3V_S5 3D3V_AUX_S5

3D3V_AUX_KBC

3D3V_AUX_S5

All Not update

VOLTAGE DESCRIPTION

5V

3.3V

1.8V

1.5V

1.05V

0.95 - 0.85V

0.75V

0.35V to 1.5V

0.4 to 1.25V

1.8V

3.3V 1V

5V

1.5V

0.75V

6V-14.1V 6V-14.1V 5V 5V

3.3V

3.3V3D3V_LAN_S5

3.3V

Voltage Rails

ACTIVE IN

S0

CPU Core Rail Graphics Core Rail

S3

AC Brick Mode only

All S states

WOL_EN

DSW, Sx ON for supporting Deep Sleep states

G3, Sx

Legacy WOL

Powered by Li Coin Cell in G3 and +V3ALW in Sx

USB Table

PCIE Routing

LANE1 Mini Card2(WWAN) LANE2 LANE3 Card Reader LANE4

A A

LANE5 LANE6 LANE7 LANE8 New Card

Onboard LAN

Mini Card1(WLAN)

USB3.0

Intel GBE LAN

Dock

5

SATA Table

SATA

Pair

0 1 2 3 4 5

Device

N/A

HDD1

N/A N/A

ODD

N/A

Pair

0 1

2 3 4 5 6 7 8 9 10 11 12 13

4

Device X

USB3.0 ext port 1

USB2.0 ext port 4

USB3.0 ext port 2

BLUETOOTH CARD READER

X X X USB2.0 ext port 3

X

WLAN(Bluetooth) CAMERA X

SMBus ADDRESSES

2

I C / SMBus Addresses

Device

EC SMBus 1 Battery CHARGER

EC SMBus 2 PCH eDP

PCH SMBus SO-DIMMA (SPD) SO-DIMMB (SPD) Digital Pot G-Sensor MINI

3

Address Hex Bus Ref Des

HURON RIVER ORB

BAT_SCL/BAT_SDA BAT_SCL/BAT_SDA BAT_SCL/BAT_SDA

SML1_CLK/SML1_DATA SML1_CLK/SML1_DATA SML1_CLK/SML1_DATA

PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK

2

JV10-CS

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet of

Date: Sheet of

mTable of Content

Taipei Hsien 221, Taiwan, R.O.C.

G48/G58

1

3

SC

103Friday, February 17, 2012

5

4

3

2

1

SSID = CPU

D D

DMI_TXN[3:0]19

DMI_TXP[3:0]19

DY

DMI_TXN3 DMI_TXP3

Note: Form DMI R410, R405, R403 and R404 are for SIV debug and validation purposes

C C

B B

Note: EDP_ICOMPO and EDP_COMPIO should not be left floating.

Signal Routing Guideline: EDP_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils. EDP_COMPIO keep W/S=4/15 mils and routing length less than 500 mils.

NOTE: Select a Fast FET similar to 2N7002E whose rise/ fall time is less than 6 ns. If HPD on eDP interface is disabled, connect it to CPU VCCIO via a 10-kΩ pull-Up resistor on the motherboard.

NOTE.

A A

Processor strap CFG[4] should be pulled low to enable Embedded DisplayPort.

DY

R404 49D9R2F-GP

1 2

R406 49D9R2F-GP

1 2

DY

Note: Intel FDI supports both Lane Reversal and polarity inversion but only at PCH side. This is enabled via a soft strap.

Note: Lane reversal does not apply to FDI sideband signals.

5

Note: Intel DMI supports both Lane Reversal and polarity inversion but only at PCH side. This is enabled via a soft strap.

DMI_TXN0 DMI_TXN1 DMI_TXN2

1D0V_S0

DMI_TXN3

DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3

R402 24D9R2F-L-GPR402 24D9R2F-L-GP R403

R403

DMI_RXN[3:0]19

DMI_RXP[3:0]19

FDI_TXN[7:0]19

FDI_TXP[7:0]19

FDI_FSYNC019 FDI_FSYNC119

FDI_INT19 FDI_LSYNC019

FDI_LSYNC119

1 2 1 2

DY

R410

1 2

0R2J-2-GP

R405

10KR2J-3-GP

1 2

4

0R2J-2-GP

FDI_TXN0 FDI_TXN1 FDI_TXN2 FDI_TXN3 FDI_TXN4 FDI_TXN5 FDI_TXN6 FDI_TXN7

FDI_TXP0 FDI_TXP1 FDI_TXP2 FDI_TXP3 FDI_TXP4 FDI_TXP5 FDI_TXP6 FDI_TXP7

DMI_TXN3_R

DMI_TXP3_R

DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3

DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3

DP_COMP eDP_HPD

CPU1A

B27

DMI_RX#0

B25

DMI_RX#1

A25

DMI_RX#2

B24

DMI_RX#3

B28

DMI_RX0

B26

DMI_RX1

A24

DMI_RX2

B23

DMI_RX3

G21

DMI_TX#0

E22

DMI_TX#1

F21

DMI_TX#2

D21

DMI_TX#3

G22

DMI_TX0

D22

DMI_TX1

F20

DMI_TX2

C21

DMI_TX3

A21

FDI0_TX#0

H19

FDI0_TX#1

E19

FDI0_TX#2

F18

FDI0_TX#3

B21

FDI1_TX#0

C20

FDI1_TX#1

D18

FDI1_TX#2

E17

FDI1_TX#3

A22

FDI0_TX0

G19

FDI0_TX1

E20

FDI0_TX2

G18

FDI0_TX3

B20

FDI1_TX0

C19

FDI1_TX1

D19

FDI1_TX2

F17

FDI1_TX3

J18

FDI0_FSYNC

J17

FDI1_FSYNC

H20

FDI_INT

J19

FDI0_LSYNC

H17

FDI1_LSYNC

A18

EDP_COMPIO

A17

EDP_ICOMPO

B16

EDP_HPD

C15

EDP_AUX

D15

EDP_AUX#

C17

EDP_TX0

F16

EDP_TX1

C16

EDP_TX2

G15

EDP_TX3

C18

EDP_TX#0

E16

EDP_TX#1

D16

EDP_TX#2

F15

EDP_TX#3

IVY-1

62.10040.821

1st = 22.10252.171

2nd = 62.10040.821

3rd = 62.10055.551

IVY-BRIDGE

DMI

Intel(R) FDI

eDP

Signal Routing Guideline: PEG_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils. PEG_ICOMPI & PEG_RCOMPO keep W/S=4/15 mils and routing length less than 500 mils.

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#0 PEG_RX#1 PEG_RX#2 PEG_RX#3 PEG_RX#4 PEG_RX#5 PEG_RX#6 PEG_RX#7 PEG_RX#8

PEG_RX#9 PEG_RX#10 PEG_RX#11 PEG_RX#12 PEG_RX#13 PEG_RX#14 PEG_RX#15

PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8

PEG_RX9 PEG_RX10 PEG_RX11 PEG_RX12 PEG_RX13 PEG_RX14 PEG_RX15

PEG_TX#0 PEG_TX#1 PEG_TX#2 PEG_TX#3 PEG_TX#4 PEG_TX#5 PEG_TX#6 PEG_TX#7 PEG_TX#8 PEG_TX#9

PEG_TX#10 PEG_TX#11

PCI EXPRESS* - GRAPHICS

PEG_TX#12 PEG_TX#13 PEG_TX#14 PEG_TX#15

PEG_TX0

PEG_TX1

PEG_TX2

PEG_TX3

PEG_TX4

PEG_TX5

PEG_TX6

PEG_TX7

PEG_TX8

PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15

BOM_CTRL

3

1 OF 9

J22 J21 H22

K33 M35 L34 J35 J32 H34 H31 G33 G30 F35 E34 E32 D33 D31 B33 C32

J33 L35 K34 H35 H32 G34 G31 F33 F30 E35 E33 F32 D34 E31 C33 B32

M29 M32 M31 L32 L29 K31 K28 J30 J28 H29 G27 E29 F27 D28 F26 E25

M28 M33 M30 L31 L28 K30 K27 J29 J27 H28 G28 E28 F28 D27 E26 D25

PEG_IRCOMP_R

PEG_RXN15_L PEG_RXN14 PEG_RXN13 PEG_RXN12 PEG_RXN11 PEG_RXN10 PEG_RXN9 PEG_RXN8 PEG_RXN7 PEG_RXN6 PEG_RXN5 PEG_RXN4 PEG_RXN3 PEG_RXN2 PEG_RXN1 PEG_RXN0

PEG_RXP15_L PEG_RXP14 PEG_RXP13 PEG_RXP12 PEG_RXP11 PEG_RXP10 PEG_RXP9 PEG_RXP8 PEG_RXP7 PEG_RXP6 PEG_RXP5 PEG_RXP4 PEG_RXP3 PEG_RXP2 PEG_RXP1 PEG_RXP0

PEG_C_TXN15 PEG_C_TXN14 PEG_C_TXN13 PEG_C_TXN12 PEG_C_TXN11 PEG_C_TXN10 PEG_C_TXN9 PEG_C_TXN8 PEG_C_TXN7 PEG_C_TXN6 PEG_C_TXN5 PEG_C_TXN4 PEG_C_TXN3 PEG_C_TXN2 PEG_C_TXN1 PEG_C_TXN0

PEG_C_TXP15 PEG_C_TXP14 PEG_C_TXP13 PEG_C_TXP12 PEG_C_TXP11 PEG_C_TXP10 PEG_C_TXP9 PEG_C_TXP8 PEG_C_TXP7 PEG_C_TXP6 PEG_C_TXP5 PEG_C_TXP4 PEG_C_TXP3 PEG_C_TXP2 PEG_C_TXP1 PEG_C_TXP0

R401 24D9R2F-L-GPR401 24D9R2F-L-GP

1 2

0R2J-2-GP

OPS

1 2

OPS

R411 0R2J-2-GP

1 2

C401 SCD22U10V2KX-1GP

1 2

C402 SCD22U10V2KX-1GP

1 2

C403 SCD22U10V2KX-1GP

1 2

C404 SCD22U10V2KX-1GP

1 2

C405 SCD22U10V2KX-1GP

1 2

C406 SCD22U10V2KX-1GP

1 2

C407 SCD22U10V2KX-1GP

1 2

C408 SCD22U10V2KX-1GP

1 2

C409 SCD22U10V2KX-1GP

1 2

C410 SCD22U10V2KX-1GP

1 2

C411 SCD22U10V2KX-1GP

1 2

C412 SCD22U10V2KX-1GP

1 2

C413 SCD22U10V2KX-1GP

1 2

C414 SCD22U10V2KX-1GP

1 2

C415 SCD22U10V2KX-1GP

1 2

C416 SCD22U10V2KX-1GP

1 2

C417 SCD22U10V2KX-1GP

1 2

C418 SCD22U10V2KX-1GP

1 2

C419 SCD22U10V2KX-1GP

1 2

C420 SCD22U10V2KX-1GP

1 2

C421 SCD22U10V2KX-1GP

1 2

C422 SCD22U10V2KX-1GP

1 2

C423 SCD22U10V2KX-1GP

1 2

C424 SCD22U10V2KX-1GP

1 2

C425 SCD22U10V2KX-1GP

1 2

C426 SCD22U10V2KX-1GP

1 2

C427 SCD22U10V2KX-1GP

1 2

C428 SCD22U10V2KX-1GP

1 2

C429 SCD22U10V2KX-1GP

1 2

C430 SCD22U10V2KX-1GP

1 2

C431 SCD22U10V2KX-1GP

1 2

C432 SCD22U10V2KX-1GP

1 2

R412

N13P_GL

N13P_GL N13P_GL

N13P_GL OPS

OPS OPS

OPS N13P_GL

N13P_GL N13P_GL

N13P_GL OPS

OPS OPS

OPS

G48-SA Modify

20110601

PEG_RXN15

PEG_RXP15

2

1D0V_S0

NOTE. If PEG is not implemented, the RX&TX pairs can be left as No Connect

PEG_RXN[0..15]

PEG_RXN15 PEG_RXP15

Note: Form PEG R412, R411, R413 and R414 are for SIV debug and validation purposes

PEG_RXP[0..15]

JV10-CS

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet of

Date: Sheet of

PEG_RXN[0..15] 83

DY

R413 49D9R2F-GP

1 2

R414 49D9R2F-GP

1 2

DY

PEG_RXP[0..15] 83

PEG_TXN[0..15]

PEG_TXN15 PEG_TXN14 PEG_TXN13 PEG_TXN12 PEG_TXN11 PEG_TXN10 PEG_TXN9 PEG_TXN8 PEG_TXN7 PEG_TXN6 PEG_TXN5 PEG_TXN4 PEG_TXN3 PEG_TXN2 PEG_TXN1 PEG_TXN0

PEG_TXP15 PEG_TXP14 PEG_TXP13 PEG_TXP12 PEG_TXP11 PEG_TXP10 PEG_TXP9 PEG_TXP8 PEG_TXP7 PEG_TXP6 PEG_TXP5 PEG_TXP4 PEG_TXP3 PEG_TXP2 PEG_TXP1 PEG_TXP0

CPU (PCIE/DMI/FDI)

PEG_TXP[0..15]

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

G48/G58

1

PEG_TXN[0..15] 83

PEG_TXP[0..15] 83

4

SC

103Friday, February 17, 2012

5

SSID = CPU

H_SNB_IVB#22

1

R513

1 2

56R2J-4-GP

1

R504

1 2

0R2J-2-GP

1 2

DY

PLT_RST#18,27,31,36,65,83,97

TP501TPAD14-OP-GP TP501TPAD14-OP-GP

TP502TPAD14-OP-GP TP502TPAD14-OP-GP

R505

R505 0R2J-2-GP

0R2J-2-GP

D D

1D0V_S0

62R2J-GP

62R2J-GP R501

R501

C502

H_PROCHOT#

12

SIV

H_PECI22,27

H_PROCHOT#27,42

1 2

SC43P50V2JN-GP

Intel recommends 43pf

H_THERMTRIP#22,36

TP521TPAD14-OP-GP TP521TPAD14-OP-GP

SVT

EC502

SC10P50V2JN-4GP

C C

R503

1 2

B B

H_CPUPW RGD22,36,97

10KR2J-3-GP

SC10P50V2JN-4GP

H_CPUPW RGD_R

H_PM_SYNC19

1 2

PM_DRAM_PWRGD19,37

VDDPWRGOOD37

TP524TPAD14-OP-GP TP524TPAD14-OP-GP

TP522TPAD14-OP-GP TP522TPAD14-OP-GP

TP520TPAD14-OP-GP TP520TPAD14-OP-GP

Buffered reset to CPU Close CPU side

4

SKTOCC#_R

1

H_CATERR#

1

H_PROCHOT#_R

H_CPUPW RGD_R

VDDPWRGOOD

BUF_CPU_RST#

BOM_CTRL

BOM_CTRL 1st = 22.10252.171

1st = 22.10252.171 2nd = 62.10040.821

2nd = 62.10040.821 3rd = 62.10055.551

3rd = 62.10055.551

CPU1B

C26

PROC_SELECT#

AN34

SKTOCC#

AL33

CATERR#

AN33

PECI

AL32

PROCHOT#

AN32

THERMTRIP#

AM34

PM_SYNC

AP33

UNCOREPWRGOOD

V8

SM_DRAMPWROK

AR33

RESET#

IVY-1

DY

R512

1 2

0R2J-2-GP

U501

1

IN B

2

IN A GND3OUT Y

74VHC1G09DFT2G-GP

73.01G09.AAH

VCC

IVY-BRIDGE

62.10040.821

1D0V_S0

12

5

4

MISCTHERMALPWR MANAGEMENT

R519

R519 75R2J-1-GP

75R2J-1-GP

BUFO_CPU_RST#

CLOCKS

DDR3

MISC

DDR3

MISC

JTAG & BPM

3D3V_S0

12

C503

C503 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

1 2

3

2 OF 9

BCLK

BCLK#

DPLL_REF_CLK

DPLL_REF_CLK#

SM_DRAMRST#

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

PRDY# PREQ#

TMS

TRST#

TDO

DBR#

BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7

R517

43R2J-GP

DY

TCK

TDI

A28 A27

A16 A15

R8

AK1 A5 A4

AP29 AP27

AR26 AR27 AP30

AR28 AP26

AL35

AT28 AR29 AR30 AT30 AP32 AR31 AT31 AR32

12

R515

R515 750R2F-GP

750R2F-GP

CLK_DP_P_R CLK_DP_N_R

SM_DRAMRST#SM_DRAMRST#

SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2

XDP_PRDY# XDP_PREQ#

XDP_TCLK XDP_TMS XDP_TRST#

XDP_TDI XDP_TDO

XDP_DBRESET#

BUF_CPU_RST#

12

DY

1 1

CLK_DP_P_R 20 CLK_DP_N_R 20

1

TP523 TPAD14-OP-GPTP523 TPAD14-OP-GP

SM_DRAMRST# 37

1 2 1 2 1 2

1 1

1 1 1

1 1

1 1 1 1 1 1 1 1

12

TP511 TPAD14-OP-GPTP511 TPAD14-OP-GP TP512 TPAD14-OP-GPTP512 TPAD14-OP-GP

TP513 TPAD14-OP-GPTP513 TPAD14-OP-GP TP514 TPAD14-OP-GPTP514 TPAD14-OP-GP TP515 TPAD14-OP-GPTP515 TPAD14-OP-GP

TP516 TPAD14-OP-GPTP516 TPAD14-OP-GP TP517 TPAD14-OP-GPTP517 TPAD14-OP-GP

TP503 TPAD14-OP-GPTP503 TPAD14-OP-GP TP504 TPAD14-OP-GPTP504 TPAD14-OP-GP TP505 TPAD14-OP-GPTP505 TPAD14-OP-GP TP506 TPAD14-OP-GPTP506 TPAD14-OP-GP TP507 TPAD14-OP-GPTP507 TPAD14-OP-GP TP508 TPAD14-OP-GPTP508 TPAD14-OP-GP TP509 TPAD14-OP-GPTP509 TPAD14-OP-GP TP510 TPAD14-OP-GPTP510 TPAD14-OP-GP

R502 4K99R2F-L-GPR502 4K99R2F-L-GP

R506 140R2F-GPR506 140R2F-GP R507 25D5R2F-GPR507 25D5R2F-GP R508 200R2F-L-GPR508 200R2F-L-GP

XDP_BPM0 XDP_BPM1 XDP_BPM2 XDP_BPM3 XDP_BPM4 XDP_BPM5 XDP_BPM6 XDP_BPM7

C501

C501 SC220P50V2KX-3GP

SC220P50V2KX-3GP

2

TP518 TPAD14-OP-GPTP518 TPAD14-OP-GP TP519 TPAD14-OP-GPTP519 TPAD14-OP-GP

CLK_EXP_P 20 CLK_EXP_N 20

1

Disabling Guidelines: If motherboard only supports external graphics: Connect DPLL_REF_SSCLK on Processor to GND through 1K +/- 5% resistor. Connect DPLL_REF_SSCLK# on Processor to VCCP through 1K +/- 5% resistorpower (~15 mW) may be wasted.

R523

51R2J-2-GP

1 2 3 4 5

SRN51J-1-GP

1D05V_VTT

1 2

RN501

1 2

R516

R516 1KR2J-1-GP

1KR2J-1-GP

R520

R520 1KR2J-1-GP

1KR2J-1-GP

1 2

8 7 6

1D0V_S0

CLK_DP_P_R

20110728 for intel check list

R518

R518 1KR2J-1-GP

1KR2J-1-GP

1 2

CLK_DP_N_R

Signal Routing Guideline: SM_RCOMP keep routing length less than 500 mils.

XDP_TDO

XDP_TMS XDP_TDI XDP_TCLK XDP_TRST#

XDP_DBRESET#19

XDP_DBRESET#

3D3V_S0

A A

NOTE

HR

CRV

5

U501

DY

73.01G09.AAH

R512

0 ohm

63.R0034.1DL

DY

R519

DY

75 ohm

63.75034.1DL

R517

1.5K ohm

64.15015.6DL

43 ohm

63.43034.1DL

4

R515

750 ohm

64.75005.6DL

DY

C503

DY

0.1uF

78.10423.2FL

C501

DY

Default CRV

3

2

JV10-CS

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet of

Date: Sheet of

THERMAL/CLOCK/PM

Taipei Hsien 221, Taiwan, R.O.C.

G48/G58

1

5

SC

103Friday, February 17, 2012

5

4

3

2

1

SSID = CPU

4 OF 9

3 OF 9

CPU1C

D D

M_A_DQ[63:0]14 M_B_DQ[63:0]15

C C

B B

M_A_DQ[63:0]

M_A_BS014 M_A_BS114 M_A_BS214

M_A_CAS#14 M_A_RAS#14 M_A_WE#14

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

F10

G10

N10

M10

AG6 AG5 AK6 AK5 AH5 AH6

AJ5 AJ6 AJ8

AK8

AJ9 AK9 AH8 AH9

AL9

AL8

AP11 AN11

AL12 AM12 AM11

AL11 AP12 AN12

AJ14 AH14

AL15 AK15

AL14 AK14

AJ15 AH15

AE10

AF10

AE8 AD9

AF9

C5 D5 D3 D2 D6 C6 C2 C3

F8 G9

F9 F7 G8 G7 K4 K5 K1

K2 M8

N8 N7

M9 N9 M7

V6

J1 J5 J4 J2

SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

SA_BS0 SA_BS1 SA_BS2

SA_CAS# SA_RAS# SA_WE#

IVY-BRIDGE

DDR SYSTEM MEMORY A

3 OF 9

SA_CK0

SA_CLK#0

SA_CKE0

SA_CK1

SA_CLK#1

SA_CKE1

SA_CK2

SA_CLK#2

SA_CKE2

SA_CK3

SA_CLK#3

SA_CKE3

SA_CS#0 SA_CS#1 SA_CS#2 SA_CS#3

SA_ODT0

SA_ODT1 SA_ODT2 SA_ODT3

SA_DQS#0 SA_DQS#1 SA_DQS#2 SA_DQS#3 SA_DQS#4 SA_DQS#5 SA_DQS#6 SA_DQS#7

SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8

SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15

AB6 AA6 V9

AA5 AB5 V10

AB4 AA4 W9

AB3 AA3 W10

AK3 AL3 AG1 AH1

AH3 AG3 AG2 AH2

C4 G6 J3 M6 AL6 AM8 AR12 AM15

D4 F6 K3 N6 AL5 AM9 AR11 AM14

AD10 W1 W2 W7 V3 V2 W3 W6 V1 W5 AD8 V4 W4 AF8 V5 V7

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_DIM0_CLK_DDR0 14 M_A_DIM0_CLK_DDR#0 14 M_A_DIM0_CKE0 14

M_A_DIM0_CLK_DDR1 14 M_A_DIM0_CLK_DDR#1 14 M_A_DIM0_CKE1 14

M_A_DIM0_CS#0 14 M_A_DIM0_CS#1 14

M_A_DIM0_ODT0 14 M_A_DIM0_ODT1 14

M_A_DQS#[7:0] 14

M_A_DQS[7:0] 14

M_A_A[15:0] 14

M_B_DQ[63:0]

M_B_BS015 M_B_BS115 M_B_BS215

M_B_CAS#15

M_B_RAS#15 M_B_WE#15

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

AM5 AM6 AR3 AP3 AN3 AN2 AN1 AP2 AP5 AN9

AP6 AN8 AR6 AR5 AR9

AJ11

AH11

AR8

AJ12

AH12

AT11 AN14 AR14

AT14

AT12 AN15 AR15

AT15

AA9 AA7

AA10

AB8 AB9

D10

K10

AT5 AT6

AT8 AT9

CPU1D

IVY-BRIDGE

C9

SB_DQ0

A7

SB_DQ1 SB_DQ2

C8

SB_DQ3

A9

SB_DQ4

A8

SB_DQ5

D9

SB_DQ6

D8

SB_DQ7

G4

SB_DQ8

F4

SB_DQ9

F1

SB_DQ10

G1

SB_DQ11

G5

SB_DQ12

F5

SB_DQ13

F2

SB_DQ14

G2

SB_DQ15

J7

SB_DQ16

J8

SB_DQ17 SB_DQ18

K9

SB_DQ19

J9

SB_DQ20

J10

SB_DQ21

K8

SB_DQ22

K7

SB_DQ23

M5

SB_DQ24

N4

SB_DQ25

N2

SB_DQ26

N1

SB_DQ27

M4

SB_DQ28

N5

SB_DQ29

M2

SB_DQ30

M1

SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54

R6

SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

SB_BS0 SB_BS1 SB_BS2

SB_CAS# SB_RAS# SB_WE#

DDR SYSTEM MEMORY B

4 OF 9

SB_CK0

SB_CLK#0

SB_CKE0

SB_CK1

SB_CLK#1

SB_CKE1

SB_CK2

SB_CLK#2

SB_CKE2

SB_CK3

SB_CLK#3

SB_CKE3

SB_CS#0 SB_CS#1 SB_CS#2 SB_CS#3

SB_ODT0 SB_ODT1 SB_ODT2 SB_ODT3

SB_DQS#0 SB_DQS#1 SB_DQS#2 SB_DQS#3 SB_DQS#4 SB_DQS#5 SB_DQS#6 SB_DQS#7

SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7

SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8

SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15

AE2 AD2 R9

AE1 AD1 R10

AB2 AA2 T9

AA1 AB1 T10

AD3 AE3 AD6 AE6

AE4 AD4 AD5 AE5

D7 F3 K6 N3 AN5 AP9 AK12 AP15

C7 G3 J6 M3 AN6 AP8 AK11 AP14

AA8 T7 R7 T6 T2 T4 T3 R2 T5 R3 AB7 R1 T1 AB10 R5 R4

M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

M_B_DIM0_CLK_DDR0 15 M_B_DIM0_CLK_DDR#0 15 M_B_DIM0_CKE0 15

M_B_DIM0_CLK_DDR1 15 M_B_DIM0_CLK_DDR#1 15 M_B_DIM0_CKE1 15

M_B_DIM0_CS#0 15 M_B_DIM0_CS#1 15

M_B_DIM0_ODT0 15 M_B_DIM0_ODT1 15

M_B_DQS#[7:0] 15

M_B_DQS[7:0] 15

M_B_A[15:0] 15

IVY-1

A A

5

IVY-1

BOM_CTRL

BOM_CTRL 1st = 22.10252.171

1st = 22.10252.171 2nd = 62.10040.821

2nd = 62.10040.821 3rd = 62.10055.551

3rd = 62.10055.551

62.10040.821

4

3

IVY-1

BOM_CTRL

BOM_CTRL 1st = 22.10252.171

1st = 22.10252.171 2nd = 62.10040.821

2nd = 62.10040.821 3rd = 62.10055.551

3rd = 62.10055.551

2

62.10040.821

JV10-CS

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet of

Date: Sheet of

CPU (DDR)

Taipei Hsien 221, Taiwan, R.O.C.

G48/G58

1

6

SC

103Friday, February 17, 2012

5

SSID = CPU

4

3

2

1

CFG2

D D

12

R702

R702 1KR2J-1-GP

1KR2J-1-GP

OPS

PEG Static Lane Reversal

CFG2

1: Normal Operation; Lane # definition matches socket pin map definition

0:Lane Reversed

CFG4

12

R703

R703 1KR2J-1-GP

1KR2J-1-GP

DY

CFG5 CFG6

C C

B B

DY

12

R701

1KR2J-1-GP

12

R704

N13M-GE

Display Port Presence Strap

CFG4

1: Disabled; No Physical Display Port attached to Embedded Display Port

0: Enabled; An external Display Port device is connected to the Embedded Display Port

PCIE Port Bifurcation Straps

CFG[6:5]

11: x16 - Device 1 functions 1 and 2 disabled

10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled 01: Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

1KR2J-1-GP

TP717TPAD14-OP-GP TP717TPAD14-OP-GP

CFG2 CFG4

CFG5 CFG6 CFG7

CFG0

1

CFG7

CPU1E

AK28

CFG0

AK29

CFG1

AL26

CFG2

AL27

CFG3

AK26

CFG4

AL29

CFG5

AL30

CFG6

AM31

CFG7

AM32

CFG8

AM30

CFG9

AM28

CFG10

AM26

CFG11

AN28

CFG12

AN31

CFG13

AN26

CFG14

AM27

CFG15

AK31

CFG16

AN29

CFG17

AJ31

VAXG_VAL_SENSE

AH31

VSSAXG_VAL_SENSE

AJ33

VCC_VAL_SENSE

AH33

VSS_VAL_SENSE

AJ26

RSVD#AJ26

F25

RSVD#F25

F24

RSVD#F24

F23

RSVD#F23

D24

RSVD#D24

G25

RSVD#G25

G24

RSVD#G24

E23

RSVD#E23

D23

RSVD#D23

C30

RSVD#C30

A31

RSVD#A31

B30

RSVD#B30

B29

RSVD#B29

D30

RSVD#D30

B31

RSVD#B31

A30

RSVD#A30

C29

RSVD#C29

J20

RSVD#J20

B18

RSVD#B18

DY

12

CFG

R705

R705 1KR2J-1-GP

1KR2J-1-GP

IVY-BRIDGE

RESERVED

PEG DEFER TRAINING

CFG7

5 OF 9

VCC_DIE_SENSE

VSS_DIE_SENSE

RSVD#L7

RSVD#AG7

RSVD#AE7 RSVD#AK2

RSVD#W8

RSVD#AT26

RSVD#AM33

RSVD#AJ27

RSVD#T8

RSVD#J16 RSVD#H16 RSVD#G16

RSVD_NCTF#AR35 RSVD_NCTF#AT34 RSVD_NCTF#AT33 RSVD_NCTF#AP35 RSVD_NCTF#AR34

RSVD_NCTF#B34 RSVD_NCTF#A33 RSVD_NCTF#A34 RSVD_NCTF#B35 RSVD_NCTF#C35

RSVD#AJ32

RSVD#AK32

BCLK_ITP

BCLK_ITP#

1: PEG Train immediately following xxRESETB de assertion

0: PEG Wait for BIOS for training

TP713

NCTF#AR35 NCTF#AT34 NCTF#AT33 NCTF#AP35 NCTF#AR34

NCTF#A33 NCTF#A34

1

TP720 TPAD14-OP-GPTP720 TPAD14-OP-GP

1

TP721 TPAD14-OP-GPTP721 TPAD14-OP-GP

1

TP722 TPAD14-OP-GPTP722 TPAD14-OP-GP

1

TP723 TPAD14-OP-GPTP723 TPAD14-OP-GP

1

TP724 TPAD14-OP-GPTP724 TPAD14-OP-GP

1

TP725 TPAD14-OP-GPTP725 TPAD14-OP-GP

1

TP727 TPAD14-OP-GPTP727 TPAD14-OP-GP

1

TP728 TPAD14-OP-GPTP728 TPAD14-OP-GP

AH27 AH26

L7 AG7 AE7 AK2

W8

AT26 AM33 AJ27

T8 J16 H16 G16

AR35 AT34 AT33 AP35 AR34

B34 A33 A34 B35 C35

SIV

AJ32 AK32

AN35 AM35

CLK_XDP_ITP_P CLK_XDP_ITP_N

1

TP718 TPAD14-OP-GPTP718 TPAD14-OP-GP

1

TP719 TPAD14-OP-GPTP719 TPAD14-OP-GP

J15

RSVD#J15

A A

IVY-1

BOM_CTRL

5

4

3

62.10040.821

RSVD_NCTF#AT2 RSVD_NCTF#AT1

RSVD_NCTF#AR1

AT2 AT1 AR1

JV10-CS

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet of

Date: Sheet of

2

Date: Sheet of

CPU (RESERVED)

Taipei Hsien 221, Taiwan, R.O.C.

G48/G58

1

SC

103Friday, February 17, 2012

7

103Friday, February 17, 2012

5

4

3

2

1

SSID = CPU

VCC_CORE

D D

C C

B B

A A

VCC_CORE

VCC CORE:53A

12

C801

SC10U6D3V5KX-1GP

12

C816

SC10U6D3V5KX-1GP

12

C837

SC10U6D3V5KX-1GP

5

12

C802

C803

DY

SC10U6D3V5KX-1GP

C817

SC10U6D3V5KX-1GP

12

C822

C821

SC10U6D3V5KX-1GP

12

C836

C835

SC10U6D3V5KX-1GP

12

C804

C811

DY

SC10U6D3V5KX-1GP

12

C820

SC10U6D3V5KX-1GP

12

C823

SC10U6D3V5KX-1GP

12

C834

DY

SC10U6D3V5KX-1GP

12

C825

SC10U6D3V5KX-1GP

12

DY

C832

C833

SC10U6D3V5KX-1GP

12

C827

C826

SC10U6D3V5KX-1GP

12

C831

C828

SC10U6D3V5KX-1GP

BOM_CTRL

4

AG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26

Y35 Y34 Y33 Y32 Y31 Y30 Y29 Y28 Y27 Y26 V35 V34 V33 V32 V31 V30 V29 V28 V27 V26 U35 U34 U33 U32 U31 U30 U29 U28 U27 U26 R35 R34 R33 R32 R31 R30 R29 R28 R27 R26 P35 P34 P33 P32 P31 P30 P29 P28 P27 P26

CPU1F

VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76 VCC77 VCC78 VCC79 VCC80 VCC81 VCC82 VCC83 VCC84 VCC85 VCC86 VCC87 VCC88 VCC89 VCC90 VCC91 VCC92 VCC93 VCC94 VCC95 VCC96 VCC97 VCC98 VCC99 VCC100

IVY-1

POWER

IVY-BRIDGE

CORE SUPPLY

62.10040.821

PEG AND DDR

VIDALERT#

VCC_SENSE

VSS_SENSE

VCCIO_SENSE

VSS_SENSE_VCCIO

SENSE LINES SVID

3

6 OF 9

VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCIO8

VCCIO9 VCCIO10 VCCIO11 VCCIO12 VCCIO13 VCCIO14 VCCIO15 VCCIO16 VCCIO17 VCCIO18 VCCIO19 VCCIO20 VCCIO21 VCCIO22 VCCIO23 VCCIO24

VCCIO25 VCCIO26 VCCIO27 VCCIO28 VCCIO29 VCCIO30 VCCIO31 VCCIO32 VCCIO33 VCCIO34 VCCIO35 VCCIO36 VCCIO37 VCCIO38 VCCIO39

VCCIO40

VIDSCLK

VIDSOUT

12

C806

SC10U6D3V5KX-1GP

12

C813

SC10U6D3V5KX-1GP

VCCIO:8.5A

12

C808

C807

SC10U6D3V5KX-1GP

12

C829

C814

SC10U6D3V5KX-1GP

12

C809

SC10U6D3V5KX-1GP

12

C830

SC10U6D3V5KX-1GP

12

C810

C838

SC10U6D3V5KX-1GP

12

C843

C842

SC10U6D3V5KX-1GP

AH13 AH10 AG10 AC10 Y10 U10 P10 L10 J14 J13 J12 J11 H14 H12 H11 G14 G13 G12 F14 F13 F12 F11 E14 E12

E11 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11

J23

12

C805

SC10U6D3V5KX-1GP

12

C812

SC10U6D3V5KX-1GP

R807 need to close to CPU

R807

1 2

75R2F-2-GP

VCC_CORE

2

75R2F-2-GP

VR_SVID_ALERT# 42

H_CPU_SVIDCLK 42

R801, R802 need to close to CPU

12

R801

R801 100R2F-L1-GP-U

100R2F-L1-GP-U

12

R802

R802 100R2F-L1-GP-U

100R2F-L1-GP-U

H_CPU_SVIDALRT#

AJ29

H_CPU_SVIDCLK_R

AJ30

H_CPU_SVIDDAT_R

AJ28

For CRB VIDSOUT need to pull high 130 ohm closr to CPU and IMVP7 For CRB VIDALERT# need to pull high 75 ohm close to CPU

AJ35 AJ34

VCCIO_SENSE

B10

VSSIO_SENSE

A10

R803 43R2J-GPR803 43R2J-GP

1 2

R805 0R2J-2-GPR805 0R2J-2-GP

1 2

R806 0R2J-2-GPR806 0R2J-2-GP

1 2

R804

1 2

130R2F-1-GP

1

TP802 TPAD14-OP-GPTP802 TPAD14-OP-GP

1

TP803 TPAD14-OP-GPTP803 TPAD14-OP-GP

1D0V_S0

110722 Ge

1D0V_S0

H_CPU_SVIDDAT 42

JV10-CS

Title

Size Document Number Rev

Size Document Number Rev Custom

Custom

Custom Date: Sheet of

Date: Sheet of

VCCSENSE 42 VSSSENSE 42

1D0V_S0

12

C840

C839

SC10U6D3V5KX-1GP

1D0V_S0

12

C845

C844

SC10U6D3V5KX-1GP

mCPU (VCC_CORE)

G48/G58

C841

SC10U6D3V5KX-1GP

-to 17pcs

TC8xx

470uF

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

10R2F-L-GP

VCCIO_SENSE VSSIO_SENSE

10R2F-L-GP

1

8

R808

R809

x2

1D0V_S0

12

SC

103Friday, February 17, 2012

5

4

3

2

1

SSID = CPU

VCC_GFXCORE

D D

12

C C

B B

C901

SC10U6D3V5KX-1GP

C907

SC10U6D3V5KX-1GP

1D8V_S0

C902

SC10U6D3V5KX-1GP

12

C908

SC10U6D3V5KX-1GP

12

C903

SC10U6D3V5KX-1GP

12

C918

SC10U6D3V5KX-1GP

12

RC901

C904

C905

SC10U6D3V5KX-1GP

12

C920

C919

SC10U6D3V5KX-1GP

RC901

C906

DY

SC33P50V2JN-3GP

SC10U6D3V5KX-1GP

12

RC902

C921

DY

SC33P50V2JN-3GP

SC10U6D3V5KX-1GP

VCCPLL:1.5A

12

C923

C925

SC10U6D3V5KX-1GP

C923

SC10U6D3V5KX-1GP

12

C924

C922

SC1U10V2KX-1GP

TC9xx

AT24 AT23 AT21 AT20 AT18

AT17 AR24 AR23 AR21 AR20 AR18 AR17 AP24 AP23 AP21 AP20 AP18 AP17 AN24 AN23 AN21 AN20 AN18 AN17 AM24 AM23 AM21 AM20 AM18 AM17

AL24

AL23

AL21

AL20

AL18

AL17 AK24 AK23 AK21 AK20 AK18 AK17

AJ24

AJ23

AJ21

AJ20

AJ18

AJ17 AH24 AH23 AH21 AH20 AH18 AH17

B6 A6 A2

CPU1G

VAXG1 VAXG2 VAXG3 VAXG4 VAXG5 VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG36 VAXG37 VAXG38 VAXG39 VAXG40 VAXG41 VAXG42 VAXG43 VAXG44 VAXG45 VAXG46 VAXG47 VAXG48 VAXG49 VAXG50 VAXG51 VAXG52 VAXG53 VAXG54

VCCPLL1 VCCPLL2 VCCPLL3

IVY-1

BOM_CTRL

330uF

A A

5

4

POWER

IVY-BRIDGE

SENSE

SA_DIMM_VREFDQ

VREFMISC

SB_DIMM_VREFDQ

GRAPHICS

DDR3 -1.5V RAILS

SA RAIL

1.8V RAIL

62.10040.821

SIV

10KR2F-2-GP

ES2 dummy R913

VAXG_SENSE

VSSAXG_SENSE

LINES

VCCSA_SENSE

VCCSA_VID0 VCCSA_VID1

R913

Routing Guideline: Power from DDR_VREF_S3 and +V_SM_VREF_CNT should have 10 mils trace width.

7 OF 9

AK35 AK34

Refer to the latest Huron River Mainstream PDG (Doc# 436735) for more details on S3 power reduction implementation.

+V_SM_VREF_CNT should have 10 mil trace width

+V_SM_VREF_CNT

AL1

SM_VREF

B4 D1

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8

VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15

VCCSA1 VCCSA2 VCCSA3 VCCSA4 VCCSA5 VCCSA6 VCCSA7 VCCSA8

VCCIO_SEL

3D3V_S5

12

DY

AF7 AF4 AF1 AC7 AC4 AC1 Y7 Y4 Y1 U7 U4 U1 P7 P4 P1

M27 M26 L26 J26 J25 J24 H26 H25

H23

C22 C24

A19

H_VCCP_SEL

PROCESSOR VCCSA: 6A

VCCSA_SENSE

3

PROCESSOR VDDQ: 12A

12

C909

VCCSA_SELECT0 VCCSA_SELECT1

VCC_AXG_SENSE 42 VSS_AXG_SENSE 42

+V_SM_VREF_CNT 37

12

C910

SC10U6D3V5KX-1GP

12

C916

SC10U6D3V5KX-1GP

12

C915

C911

VCCSA

SC10U6D3V5KX-1GP

12

C912

SC10U6D3V5KX-1GP

TC9xx

12

C917

330uF

SC10U6D3V5KX-1GP

R902 need be close to pin H23.

VCCSA_SENSE 48

VCCSA_SELECT0 48 VCCSA_SELECT1 48

1D0V_S0 1D0V_S0

R917

10KR2J-3-GP

DY

1 2

R918

1KR2J-1-GP

1 2

SIT

M3 - Processor Generated SO-DIMM VREF_DQ

DY

R915 0R2J-2-GP

1 2

R916 0R2J-2-GP

1 2

DY

VCC_GFXCORE

VCC_AXG_SENSE VSS_AXG_SENSE

SIV for intel recommend

12

R906

R906 100R2F-L1-GP-U

100R2F-L1-GP-U

12

R907

R907 100R2F-L1-GP-U

100R2F-L1-GP-U

Close to CPU

12

C913

SC10U6D3V5KX-1GP

M_VREF_DQ_DIMM0 M_VREF_CA_DIMM0

1D5V_S0

SIV

12

TC902

C914

DY

SC10U6D3V5KX-1GP

DDR_WR_VREF0112 DDR_WR_VREF0212

ST330U2D5VDM-17GP

TC9xx

330uF

NOTE

R906/R907

100 ohm

HR

64.10005.6DL

10 ohm

CRV

64.10R05.6DL

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

G48/G58

1

R920

10KR2J-3-GP

DY

1 2

1KR2J-1-GP

1 2

2

R919

Default CRV

JV10-CS

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet of

Date: Sheet of

mCPU (VCC_GFXCORE)

4

1

2 3

RN903

RN903 SRN1KJ-7-GP

SRN1KJ-7-GP

DY

9

SC

103Friday, February 17, 2012

5

4

3

2

1

SSID = CPU

9 OF 9

8 OF 9

CPU1H

D D

C C

B B

AT35 AT32 AT29 AT27 AT25 AT22 AT19 AT16 AT13 AT10

AT7 AT4

AT3 AR25 AR22 AR19 AR16 AR13 AR10

AR7 AR4

AR2 AP34 AP31 AP28 AP25 AP22 AP19 AP16 AP13 AP10

AP7

AP4

AP1 AN30 AN27 AN25 AN22 AN19 AN16 AN13 AN10

AN7

AN4 AM29 AM25 AM22 AM19 AM16 AM13 AM10

AM7

AM4

AM3

AM2

AM1

AL34 AL31 AL28 AL25 AL22 AL19 AL16 AL13 AL10

AL7 AL4

AL2 AK33 AK30 AK27 AK25 AK22 AK19 AK16 AK13 AK10

AK7 AK4

AJ25

CPU1H

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80

IVY-BRIDGE

VSS

8 OF 9

VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS98

VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160

AJ22 AJ19 AJ16 AJ13 AJ10 AJ7 AJ4 AJ3 AJ2 AJ1 AH35 AH34 AH32 AH30 AH29 AH28 AH25 AH22 AH19 AH16 AH7 AH4 AG9 AG8 AG4 AF6 AF5 AF3 AF2 AE35 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE9 AD7 AC9 AC8 AC6 AC5 AC3 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 Y9 Y8 Y6 Y5 Y3 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 U9 U8 U6 U5 U3 U2

M34

G35 G32 G29 G26 G23 G20 G17 G11

N35 N34 N33 N32 N31 N30 N29 N28 N27 N26

K35 K32 K29 K26

H33 H30 H27 H24 H21 H18 H15 H13 H10

F34 F31 F29

CPU1I

IVY-BRIDGE

T35

VSS161

T34

VSS162

T33

VSS163

T32

VSS164

T31

VSS165

T30

VSS166

T29

VSS167

T28

VSS168

T27

VSS169

T26

VSS170

P9

VSS171

P8

VSS172

P6

VSS173

P5

VSS174

P3

VSS175

P2

VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187

L33

VSS188

L30

VSS189

L27

VSS190

L9

VSS191

L8

VSS192

L6

VSS193

L5

VSS194

L4

VSS195

L3

VSS196

L2

VSS197

L1

VSS198 VSS199 VSS200 VSS201 VSS202

J34

VSS203

J31

VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213

H9

VSS214

H8

VSS215

H7

VSS216

H6

VSS217

H5

VSS218

H4

VSS219

H3

VSS220

H2

VSS221

H1

VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233

IVY-BRIDGE

VSS

9 OF 9

VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285

F22 F19 E30 E27 E24 E21 E18 E15 E13 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 D35 D32 D29 D26 D20 D17 C34 C31 C28 C27 C25 C23 C10 C1 B22 B19 B17 B15 B13 B11 B9 B8 B7 B5 B3 B2 A35 A32 A29 A26 A23 A20 A3

IVY-1

A A

5

IVY-1

BOM_CTRL

62.10040.821

4

3

IVY-1

BOM_CTRL

62.10040.821

2

JV10-CS

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet of

Date: Sheet of

CPU(VSS)

Taipei Hsien 221, Taiwan, R.O.C.

G48/G58

1

10

SC

103Friday, February 17, 2012

5

D D

C C

4

3

2

1

(Reserved)

B B

JV10-CS

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

A A

Title

Size Document Number Rev

Date: Sheet of

5

4

3

Date: Sheet of

XDP

2

Taipei Hsien 221, Taiwan, R.O.C.

G48/G58

11

SC

103Friday, February 17, 2012

1

103Friday, February 17, 2012

5

4

3

2

1

VREF circuit -M1 (Voltage Driver Network) & M3 (Driven by Processor) Implementation

For CRV:

R1226

1 2

DY

R1228

SA_DIMM_VREFDQ

D D

Driven by process (PIN#B4)

DDR_WR_VREF019

DRAMRST_CNTRL_PCH20,37

DDR_WR_VREF01_D1

R1228 1KR2F-3-GP

1KR2F-3-GP

DY

1 2

84.2N702.A3F

2nd = 84.2N702.F3F

SIV

DY

0R2J-2-GP

U1203

5 6

2N7002KDW-GP

R1208

1 2

0R2J-2-GP

DY

34 2 1

DDR_WR_VREF01_B4

R1227

1KR2F-3-GP

DRAMRST_CNTRL_PCH 20,37

12

DY

DDR_WR_VREF02 9

Driven by process (PIN#D1)

SB_DIMM_VREFDQ

DY

DDR_WR_VREF01_B4

12

R1204

R1204 0R2J-2-GP

0R2J-2-GP

12

R1209

R1209 0R2J-2-GP

0R2J-2-GP

12

R1210

R1210 0R2J-2-GP

0R2J-2-GP

M_VREF_DQ_DIMM0

12

C1205

SCD1U10V2KX-4GP

12

C1206

SCD1U10V2KX-4GP

M_VREF_DQ_DIMM1

DDR_VREF_S3

R1232

0R0402-PAD

DDR_VREF_S3

R1229

0R2J-2-GP

DY

1 2

R1212

1KR2F-3-GP

R1211

1KR2F-3-GP

R1214

1KR2F-3-GP

R1215

1KR2F-3-GP

1D5V_S3

12

1D5V_S3

12

DY

+V_VREF_VD2

DY

1 2

12

C1203

C1203 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

1 2

12

C1204

C1204 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

R1213

0R0402-PAD

R1216

0R0402-PAD

R1217

R1218

R1222

1 2

0R0402-PAD

12

M_VREF_CA_DIMM

12

TP1201

TP1201 TPAD14-OP-GP

TPAD14-OP-GP

1

M_VREF_CA_DIMM0

C1207

SCD1U10V2KX-4GP

1 2

0R2J-2-GP

1 2

0R2J-2-GP

M_VREF_CA_DIMM1

C1208

SCD1U10V2KX-4GP

R1219

R1220

+V_SM_VREF 37

DY

DDR_WR_VREF01_B4

DDR_WR_VREF01_D1

C C

B B

0R0402-PAD

DDR_VREF_S3

R1230

1 2

DDR_VREF_S3

R1231

1 2

R1205

1KR2F-3-GP

R1206

1KR2F-3-GP

R1201

1KR2F-3-GP

R1202

1KR2F-3-GP

1D5V_S3

12

DY

M3_1D5V_DQ1

12

DY

1D5V_S3

12

M3_1D5V_DQ0

DY

12

DY

12

C1201

SCD1U10V2KX-4GP

R1207

1 2

0R0402-PAD

C1202

SCD1U10V2KX-4GP

R1203

1 2

0R0402-PAD

SIV

DDR_WR_VREF01_D1

A A

5

4

3

2

JV10-CS

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet of

M1 & M3 Implementation

Taipei Hsien 221, Taiwan, R.O.C.

G48/G58

1

12

SC

103Friday, February 17, 2012

5

D D

C C

4

3

2

1

(Blanking)

B B

JV10-CS

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

A A

Title

Size Document Number Rev

Date: Sheet of

5

4

3

Date: Sheet of

Reserved

2

Taipei Hsien 221, Taiwan, R.O.C.

G48/G58

13

SC

103Friday, February 17, 2012

1

103Friday, February 17, 2012

5

SSID = MEMORY

M_A_A[15:0] 6

D D

M_A_BS26 M_A_BS06

M_A_BS16

M_A_DQ[63:0]6

C C

12

C1419

SC1U6D3V2KX-GP

Place these caps close to VTT1 and VTT2.

12

C1420

SC1U6D3V2KX-GP

DY

5

12

C1418

C1422

C1421

SC1U6D3V2KX-GP

DY

SC10U6D3V5KX-1GP

M_A_DQS#[7:0] 6 M_A_DQS[7:0] 6

M_A_DIM0_ODT06 M_A_DIM0_ODT16

M_VREF_CA_DIMM0 M_VREF_DQ_DIMM0

DDR3_DRAMRST#15,37

0D75V_S0

B B

A A

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

DY

SIV

4

DIMM1

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12

119

A13

80

A14

78

A15

79

A16/BA2

109

BA0

108

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3#

135

DQS4#

152

DQS5#

169

DQS6#

186

DQS7#

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

116

ODT0

120

ODT1

126

VREF_CA

1

VREF_DQ

30

RESET#

203

VTT1

204

12

FC1402

SCD1U10V2KX-5GP

VTT2

DDR3-240P-28-GP

NC#125/TEST

62.10017.R91

1st = 62.10017.V61

1st = 62.10017.V61 2nd = 62.10017.X51

2nd = 62.10017.X51 3rd = 62.10017.R91

3rd = 62.10017.R91

After layout, BOM change P/N

4

RAS#

WE#

CAS# CS0#

CS1# CKE0

CKE1

CK0#

CK1#

EVENT#

VDDSPD

NC#77

NC#122

3

NP1

NP2

110

113

115

114

121

73

74

101

CK0

103

102

CK1

104

11

DM0

28

DM1

46

DM2

63

DM3

136

DM4

153

DM5

170

DM6

187

DM7

200

SDA

202

SCL

198

199

SA0_DIM0

197

SA0

SA1_DIM0

201

SA1

77

122

125

75

VDD

76

VDD

81

VDD

82

VDD

87

VDD

88

VDD

93

VDD

94

VDD

99

VDD

100

VDD

105

VDD

106

VDD

111

VDD

112

VDD

117

VDD

118

VDD

123

VDD

124

VDD

2

VSS

3

VSS

8

VSS

9

VSS

13

VSS

14

VSS

19

VSS

20

VSS

25

VSS

26

VSS

31

VSS

32

VSS

37

VSS

38

VSS

43

VSS

44

VSS

48

VSS

49

VSS

54

VSS

55

VSS

60

VSS

61

VSS

65

VSS

66

VSS

71

VSS

72

VSS

127

VSS

128

VSS

133

VSS

134

VSS

138

VSS

139

VSS

144

VSS

145

VSS

150

VSS

151

VSS

155

VSS

156

VSS

161

VSS

162

VSS

167

VSS

168

VSS

172

VSS

173

VSS

178

VSS

179

VSS

184

VSS

185

VSS

189

VSS

190

VSS

195

VSS

196

VSS

205

VSS

206

VSS

BOM_CTRL

1D5V_S3

M_A_RAS# 6 M_A_WE# 6 M_A_CAS# 6

M_A_DIM0_CS#0 6 M_A_DIM0_CS#1 6

M_A_DIM0_CKE0 6 M_A_DIM0_CKE1 6

M_A_DIM0_CLK_DDR0 6 M_A_DIM0_CLK_DDR#0 6

M_A_DIM0_CLK_DDR1 6 M_A_DIM0_CLK_DDR#1 6

PCH_SMBDATA 15,20,65 PCH_SMBCLK 15,20,65

TS#_DIMM0_1 15

3

C1401

SCD1U10V2KX-5GP

12

C1402

C1402 SC2D2U10V3KX-1GP

SC2D2U10V3KX-1GP

DY

1D5V_S3

TC1401

SE390U2D5VM-12-GP

77.53971.01L

SIT

Layout Note: Place these Caps near SO-DIMMB.

SIV

3D3V_S0

12

2

SA0_DIM0

2 3

SA1_DIM0

1

SRN10KJ-5-GP

SODIMM A DECOUPLING

12

C1403

SC10U6D3V5KX-1GP

12

C1414

C1415

SCD1U10V2KX-5GP

2

RN1401

12

1

Note: If SA0 DIM0 = 0, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA0

4

Thermal EVENT

TS#_DIMM0_1

12

C1406

C1404

DY

SC10U6D3V5KX-1GP

C1416

SCD1U10V2KX-5GP

C1406

C1405

SC10U10V5ZY-1GP

SC10U6D3V5KX-1GP

12

C1417

SCD1U10V2KX-5GP

JV10-CS

Title

Size Document Number Rev

Date: Sheet of

SO-DIMMA TS Address is 0x30

If SA0 DIM0 = 1, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA2 SO-DIMMA TS Address is 0x32

R1403

1 2

10KR2J-3-GP

12

C1407

12

C1408

C1409

SC10U10V5ZY-1GP

DY

SC10U6D3V5KX-1GP

DDR3-SODIMM1

G48/G58

3D3V_S0

12

C1410

DY

SC10U6D3V5KX-1GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

14

1

SC

103Friday, February 17, 2012

5

SSID = MEMORY

M_B_A[15:0] 6

D D

M_B_BS26 M_B_BS06

M_B_BS16

M_B_DQ[63:0]6

C C

12

C1518

SC1U6D3V2KX-GP

5

Place these caps close to VTT1 and VTT2.

12

C1519

C1520

DY

SC1U6D3V2KX-GP

12

C1521

SC1U6D3V2KX-GP

M_B_DIM0_ODT06 M_B_DIM0_ODT16

M_VREF_CA_DIMM1 M_VREF_DQ_DIMM1

DDR3_DRAMRST#14,37

M_B_DQS#[7:0] 6 M_B_DQS[7:0] 6

0D75V_S0

B B

A A

0D75V_S0

DY

4

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7

4

H = 8mm

DIMM2

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12

119

A13

80

A14

78

A15

79

A16/BA2

109

BA0

108

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3#

135

DQS4#

152

DQS5#

169

DQS6#

186

DQS7#

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

116

ODT0

120

ODT1

126

VREF_CA

1

VREF_DQ

30

RESET#

203

VTT1

204

VTT2

DDR3-204P-108-GP

62.10017.X41

62.10017.X41 1st = 62.10024.G21

1st = 62.10024.G21 2nd = 62.10017.X41

2nd = 62.10017.X41 3rd = 62.10017.M51

3rd = 62.10017.M51

RAS#

WE#

CAS# CS0#

CS1# CKE0

CKE1

CK0#

CK1#

EVENT#

VDDSPD

NC#1 NC#2

NC#/TEST

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8

VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

NP1 NP2

CK0

CK1

DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7

SDA SCL

SA0 SA1

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

NP1 NP2

110 113 115

114 121

73 74

101 103

102 104

11 28 46 63 136 153 170 187

200 202

198 199 197

201 77

122 125

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 205 206

BOM_CTRL

SA0_DIM1 SA1_DIM1

3

M_B_RAS# 6 M_B_WE# 6 M_B_CAS# 6

M_B_DIM0_CS#0 6 M_B_DIM0_CS#1 6

M_B_DIM0_CKE0 6 M_B_DIM0_CKE1 6

M_B_DIM0_CLK_DDR0 6 M_B_DIM0_CLK_DDR#0 6

M_B_DIM0_CLK_DDR1 6 M_B_DIM0_CLK_DDR#1 6

PCH_SMBDATA 14,20,65 PCH_SMBCLK 14,20,65

TS#_DIMM0_1 14

C1501

SCD1U10V2KX-5GP

1D5V_S3

After layout, BOM change P/N

3

12

TC15xx

330uF

12

C1502

C1502 SC2D2U10V3KX-1GP

SC2D2U10V3KX-1GP

DY

1D5V_S3

DY

2

SIV

SA1_DIM1 SA0_DIM1

3D3V_S0

SODIMM B DECOUPLING

SIV

TC1502

12

DY

ST330U2D5VDM-17GP

12

2

C1503

SC10U10V5ZY-1GP

C1511

SCD1U10V2KX-5GP

2 3 1

SRN10KJ-5-GP

12

C1504

DY

12

C1512

1

RN1501

SC10U10V5ZY-1GP

SCD1U10V2KX-5GP

12

3D3V_S0

4

12

C1506

C1505

SC10U6D3V5KX-1GP

12

C1513

C1514

SCD1U10V2KX-5GP

JV10-CS

Title

Size Document Number Rev

Date: Sheet of

Note: SO-DIMMB SPD Address is 0xA4 SO-DIMMB TS Address is 0x34

SO-DIMMB is placed farther from the Processor than SO-DIMMA

12

C1507

DY

SC10U6D3V5KX-1GP

DDR3-SODIMM2

C1509

C1508

SC10U10V5ZY-1GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

G48/G58

DY

SC10U6D3V5KX-1GP

1

12

C1510

SC10U6D3V5KX-1GP

SC

103Friday, February 17, 2012

15

103Friday, February 17, 2012

5

D D

C C

4

3

2

1

(Blanking)

B B

JV10-CS

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

A A

Title

Size Document Number Rev

Date: Sheet of

5

4

3

Date: Sheet of

DDR3-SODIMM3

2

Taipei Hsien 221, Taiwan, R.O.C.

G48/G58

16

SC

103Friday, February 17, 2012

1

103Friday, February 17, 2012

5

3D3V_S0

RN1701

1

D D

2 3

SRN2K2J-1-GP

R1704

1 2

100KR2J-1-GP

R1703

1 2

10KR2J-3-GP

L_CTRL_DATA

4

L_CTRL_CLK

L_BKLT_EN

LVDS_VDD_EN

Place near PCH

SIT

C C

CRT_BLUE CRT_GREEN CRT_RED

678

RN1705

RN1705 SRN150F-1-GP

SRN150F-1-GP

Close to PCH side

123

B B

4 5

4

L_DDC_DATA(K47): This signal is on the LVDS interface. This signal needs to be left NC if eDP is used for the local flat panel display

L_BKLT_EN49

LVDS_VDD_EN49

12

R1701

R1701 2K37R2F-GP

2K37R2F-GP

L_BKLT_CTRL49

LVDS_DDC_CLK_R49 LVDS_DDC_DATA_R49

LVDSA_CLK#49 LVDSA_CLK49

LVDSA_DATA0#49 LVDSA_DATA1#49 LVDSA_DATA2#49

LVDSA_DATA049 LVDSA_DATA149 LVDSA_DATA249

CRT_BLUE50 CRT_GREEN50 CRT_RED50

CRT_DDC_CLK50 CRT_DDC_DATA50

CRT_HSYNC50 CRT_VSYNC50

Notes:

TP1701TPAD14-OP-GP TP1701TPAD14-OP-GP

1KR2D-1-GP

R1702

LVDS_DDC_CLK_R LVDS_DDC_DATA_R

L_CTRL_CLK L_CTRL_DATA

LVDS_IBG LVDS_VBG

1

DAC_IREF_R

12

1K 0.5% 0402.

3

PCH1D

J47

L_BKLTEN

M45

L_VDD_EN

P45

L_BKLTCTL

T40

L_DDC_CLK

K47

L_DDC_DATA

T45

L_CTRL_CLK

P39

L_CTRL_DATA

AF37

LVD_IBG

AF36

LVD_VBG

AE48

LVD_VREFH

AE47

LVD_VREFL

AK39

LVDSA_CLK#

AK40

LVDSA_CLK

AN48

LVDSA_DATA#0

AM47

LVDSA_DATA#1

AK47

LVDSA_DATA#2

AJ48

LVDSA_DATA#3

AN47

LVDSA_DATA0

AM49

LVDSA_DATA1

AK49

LVDSA_DATA2

AJ47

LVDSA_DATA3

AF40

LVDSB_CLK#

AF39

LVDSB_CLK

AH45

LVDSB_DATA#0

AH47

LVDSB_DATA#1

AF49

LVDSB_DATA#2

AF45

LVDSB_DATA#3

AH43

LVDSB_DATA0

AH49

LVDSB_DATA1

AF47

LVDSB_DATA2

AF43

LVDSB_DATA3

N48

CRT_BLUE

P49

CRT_GREEN

T49

CRT_RED

T39

CRT_DDC_CLK

M40

CRT_DDC_DATA

M47

CRT_HSYNC

M49

CRT_VSYNC

T43

DAC_IREF

T42

CRT_IRTN

PANTHER-GP-NF

BOM_CTRL

BOM_CTRL SIV = 71.PANTH.D0U

SIV = 71.PANTH.D0U

PCH

󲓢󲓢󲓢󲓢󴖨󴖨󴖨󴖨

SDVO_TVCLKINN SDVO_TVCLKINP

SDVO_STALLN

SDVO_STALLP

SDVO_INTN SDVO_INTP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPB_AUXN DDPB_AUXP

LVDS

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN DDPC_AUXP

DDPC_HPD

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXN DDPD_AUXP

CRT

DDPD_HPD

: 71.PANTH.D0U

4 OF 10

DDPB_HPD

DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

AP43 AP45

AM42 AM40

AP39 AP40

P38 M39

AT49 AT47 AT40

AV42 AV40 AV45 AV46 AU48 AU47 AV47 AV49

P46 P42

AP47 AP49 AT38

AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49

M43 M36

AT45 AT43 BH41

BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42

2

DDBP_DATA2# DDBP_DATA2 DDBP_DATA1# DDBP_DATA1 DDBP_DATA0# DDBP_DATA0 DDBP_CLK# DDBP_CLK

Impedance:90 ohm

3D3V_S0

4

RN1706

RN1706 SRN2K2J-1-GP

SRN2K2J-1-GP

1

2 3

C1701 SCD1U10V2KX-5GPC1701 SCD1U10V2KX-5GP

1 2

C1702 SCD1U10V2KX-5GPC1702 SCD1U10V2KX-5GP

1 2

C1703 SCD1U10V2KX-5GPC1703 SCD1U10V2KX-5GP

1 2

C1704 SCD1U10V2KX-5GPC1704 SCD1U10V2KX-5GP

1 2

C1705 SCD1U10V2KX-5GPC1705 SCD1U10V2KX-5GP

1 2

C1706 SCD1U10V2KX-5GPC1706 SCD1U10V2KX-5GP

1 2

C1707 SCD1U10V2KX-5GPC1707 SCD1U10V2KX-5GP

1 2

C1708 SCD1U10V2KX-5GPC1708 SCD1U10V2KX-5GP

1 2

1

DDI Port B Detect:(SDVO_CTRL_ DATA) 1: Port B detected 0: Port B not detected

PCH_HDMI_CLK 51 PCH_HDMI_DATA 51

HDMI_PCH_DET 51 HDMI_DATA2_R# 51

HDMI_DATA2_R 51 HDMI_DATA1_R# 51 HDMI_DATA1_R 51 HDMI_DATA0_R# 51 HDMI_DATA0_R 51 HDMI_CLK_R# 51 HDMI_CLK_R 51

Impedance:100 ohm

A A

5

4

3

2

JV10-CS

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet of

PCH ( LVDS/CRT/HDMI )

Taipei Hsien 221, Taiwan, R.O.C.

G48/G58

1

17

SC

103Friday, February 17, 2012

5

4

3

2

1

SSID = PCH

3D3V_S0

For intel check list

DY

R1821

8K2R2J-3-GP

DGPU_HOLD_RST#DGPU_PW R_EN#

8K2R2J-3-GP

R1817

10KR2J-3-GP

1 2

DY

1 2

For PPT USB3.0 feature

USB3_1_RX2_N62 USB3_2_RX4_N62 USB3_1_RX2_P62

USB3_2_RX4_P62 USB3_1_TX2_N62 USB3_2_TX4_N62 USB3_1_TX2_P62 USB3_2_TX4_P62

3D3V_S0

R1814

R1814 8K2R2J-3-GP

8K2R2J-3-GP

DY

1 2

1

TP1805TPAD14-OP-GP TP1805TPAD14-OP-GP

DGPU_PW M_SELECT# PCI_GNT3#

1

20110714

0R2J-2-GP

R1813

DY

1 2

1

TP1802TPAD14-OP-GP TP1802TPAD14-OP-GP

1 2 1 2

R1806 33R2J-2-GPR1806 33R2J-2-GP

1 2

DY

EC1801

EC1801 SC4D7P50V2CN-1GP

SC4D7P50V2CN-1GP

1 2

20110727 for vendor

TP1806

TPAD14-OP-GP

INT_PIRQG#

INT_PIRQA# INT_PIRQB# INT_PIRQC# INT_PIRQD#

DGPU_SELECT# DGPU_PW R_EN#

BBS_BIT1

INT_PIRQE# INT_PIRQF#

DBC_EN

PCI_PME#

1

PCI_PLTRST#

CLK_PCI_LPC_R CLK_PCI_FB_R CLK_PCI_KBC_R

PCH_CLK_PCI3

1

3D3V_S5

R1820

8K2R2J-3-GP

R1818

10KR2J-3-GP

3D3V_S0

RN1801

D D

3D3V_S0

DBC_EN INT_PIRQB# INT_PIRQF#

R1801 4K7R2J-2-GP

A16 swap override Strap/Top-Block Swap Override jumper

PCI_GNT#3 Low = A16 swap

C C

R1802 1KR2J-1-GP

R1802 1KR2J-1-GP R1803 1KR2J-1-GP

R1803 1KR2J-1-GP

RN1801

1 2 3 4 5 6

SRN8K2J-2-GP-U

DY

12

override/Top-Block Swap Override enabled High = Default

DY

1 2 1 2

DY

10

INT_PIRQD#

9

INT_PIRQE#

8

INT_PIRQC#INT_PIRQA#

7

INT_PIRQG#

PCI_GNT3#

BBS_BIT1 USB_PN3 BBS_BIT0

3D3V_S0

BBS_BIT0 21

BOOT BIOS Strap

GNT1#/GPIO51 BOOT BIOS LocationSATA1GP/GPIO19

DGPU_HOLD_RST#83

0 0 LPC 0 1 Reserved

Reserved 01

B B

11

R1819

10KR2J-3-GP

3D3V_S0

1 2

20110727 for DANNY

DGPU_PW M_SELECT#

SPI(Default)

110706

R1807

PLT_RST#5,27,31,36,65,83,97

A A

100KR2J-1-GP

12

DY

R1816

5

1 2

0R2J-2-GP

12

DY

C1801

C1801 SC220P50V2KX-3GP

SC220P50V2KX-3GP

CLK_PCI_LPC65 CLK_PCI_KBC27

PCI_PLTRST#

DGPU_PW R_EN#93

TP1801TPAD14-OP-GP TP1801TPAD14-OP-GP

SATA_ODD_DA#27,56

TP1804TPAD14-OP-GP TP1804TPAD14-OP-GP

SIV

DY

EC1802

SC4D7P50V2CN-1GP

4

R1804 22R2J-2-GPR1804 22R2J-2-GP R1805 22R2J-2-GPR1805 22R2J-2-GP

1 2

BG26

BJ26

BH25

BJ16 BG16 AH38 AH37 AK43 AK45

C18 N30

AH12

AM4 AM5

Y13 K24

L24 AB46 AB45

B21

M20 AY16 BG46

BE28 BC30 BE32

BJ32 BC28 BE30

BF32 BG32 AV26 BB26 AU28 AY30 AU26 AY26 AV28

AW30

K40 K38 H38 G38

C46 C44 E40

D47 E42 F46

G42 G40 C42 D44

K10

H49 H43

K42 H40

H3

C6

J48

PCH1E

TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP20

TP21 TP22 TP23 TP24

USB3RN1 USB3RN2 USB3RN3 USB3RN4 USB3RP1 USB3RP2 USB3RP3 USB3RP4 USB3TN1 USB3TN2 USB3TN3 USB3TN4 USB3TP1 USB3TP2 USB3TP3 USB3TP4

PIRQA# PIRQB# PIRQC# PIRQD#

REQ1#/GPIO50 REQ2#/GPIO52 REQ3#/GPIO54

GNT1#/GPIO51 GNT2#/GPIO53 GNT3#/GPIO55

PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5

PME# PLTRST#

CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4

PANTHER-GP-NF

PCH

󲓢󲓢󲓢󲓢󴖨󴖨󴖨󴖨

USB_OC#2_3 PCH_GPIO14

3

RSVD

PCI

USB

: 71.PANTH.00U

RN1802

1 2 3 4 5 6

SRN10KJ-L3-GP

5 OF 10

RSVD1 RSVD2 RSVD3 RSVD4

RSVD5 RSVD6

RSVD7 RSVD8

RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22

RSVD23 RSVD24

RSVD25 RSVD26

RSVD27 RSVD28

RSVD29

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P

USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P

USBRBIAS#

USBRBIAS

OC0#/GPIO59 OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43

OC5#/GPIO9 OC6#/GPIO10 OC7#/GPIO14

10 9 8 7

AY7 AV7 AU3 BG4

AT10 BC8

AU2 AT4 AT3 AT1 AY3 AT5 AV3 AV1 BB1 BA3 BB5 BB3 BB7 BE8 BD4 BF6

NV_ALE

AV5

NV_RCOMP

AV10 AT8 AY5

BA2 AT12

BF3

C24 A24

USB_PN1

C25

USB_PP1

B25

USB_PN2

C26

USB_PP2

A26 K28

USB_PP3

H28

USB_PN4

E28

USB_PP4

D28 C28 A28 C29 B29 N28 M28 L30 K30 G30 E30 C30 A30 L32 K32 G32 E32 C32 A32

USB_RBIAS

C33

B33

USB_OC#0_1

A14

USB_OC#2_3

K20

USB_OC#4_5

B17

USB_OC#6_7

C16

USB_OC#8_9

L16

USB_OC#10_11

A16

USB_OC#12_13

D14

PCH_GPIO14

C14

OC[3:0]# for Device 29 (Ports 0-7) OC[7:4]# for Device 26 (Ports 8-13)

USB_OC#12_13 USB_OC#8_9USB_OC#6_7 USB_OC#10_11USB_OC#0_1 USB_OC#4_5

3D3V_S5

Danbury Technology: Disabled when Low. Enable when High.

1

TP1803

USB_PN1 62 USB_PP1 62 USB_PN2 82 USB_PP2 82 USB_PN3 62 USB_PP3 62

USB_PN5 82 USB_PP5 82

USB_PN9 82 USB_PP9 82

USB_PN11 65 USB_PP11 65 USB_PN12 49 USB_PP12 49

1 2

R1811

R1811 22D6R2F-L1-GP

22D6R2F-L1-GP

2

1D8V_S0

12

R1810

R1810 1KR2J-1-GP

1KR2J-1-GP

DY

NV_ALE

TPAD14-OP-GP

USB Table

20110711

USB_PN4 63 USB_PP4 63

20110711

USB_OC#0_1 62 USB_OC#2_3 61 USB_OC#4_5 62

USB_OC#8_9 61CLK_PCI_FB20

JV10-CS

Title

Size Document Number Rev

Date: Sheet of

Pair

0 1

2 3 4 5 6 7 8 9 10 11 12 13

Device X

USB3.0 ext port 1

USB2.0 ext port 4

USB3.0 ext port 2

BLUETOOTH CARD READER

X X X USB2.0 ext port 3

X

WLAN(Bluetooth) CAMERA X

Utilize Port 9 for USB debug

USB3.0 port1 USB2.0 port4 USB3.0 port2

USB2.0 port3

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

PCH ( PCI/USB/NVRAM)

G48/G58

18

1

SC

103Friday, February 17, 2012

5

4

3

2

1

SSID = PCH

DY

D D

Signal Routing Guideline: DMI_ZCOMP keep W=4 mils and routing length less than 500 mils. DMI_IRCOMP keep W=4 mils and routing length less than 500 mils.

DY

R1926

1 2

10KR2J-3-GP

C C

B B

A A

10KR2J-3-GP

1 2

100KR2J-1-GP

PM_DRAM_PWRGD5,37

S0_PWR_GOOD after PM_SLP_S3# delay 200 ms

SUS_PW R_ACK27

R1926 R1904

R1904

XDP_DBRESET#5

3D3V_S0

SYS_PWROK36

TP1935TPAD14-OP-GP TP1935TPAD14-OP-GP

S0_PWR_GOOD27,36

RUNPWROK45,46,47

PM_PWRBTN#27,97

ACPRESENT27

3D3V_S5 3D3V_S0

DMI_RXN3

R193249D9R2F-GP

12

DMI_RXP3

R190049D9R2F-GP

12

DMI_RXN04 DMI_RXN14 DMI_RXN24 DMI_RXN34

DMI_RXP04 DMI_RXP14 DMI_RXP24 DMI_RXP34

1D05V_VTT

R1901 49D9R2F-GPR1901 49D9R2F-GP R1902 750R2F-GPR1902 750R2F-GP

SYS_PWROK

PWROK

1

0R2J-2-GP

R1929 0R2J-2-GP

RN1901

8 7 6

SRN10KJ-6-GP

R1921

DY

R1922 10KR2J-3-GP

R1920 10KR2J-3-GP

DY

R1908

5

DMI_RXN[3:0]4

DMI_RXP[3:0]4

DMI_TXN[3:0]4

DMI_TXP[3:0]4

DMI_TXN04 DMI_TXN14 DMI_TXN24 DMI_TXN34

DMI_TXP04 DMI_TXP14 DMI_TXP24 DMI_TXP34

1 2 1 2

R1927 0R2J-2-GP

DY

R1925 0R2J-2-GP

R1925 0R2J-2-GP R1905 10KR2J-3-GPR1905 10KR2J-3-GP

TP1936TPAD14-OP-GP TP1936TPAD14-OP-GP

R1924

1 2

R1930 0R2J-2-GPR1930 0R2J-2-GP

1 2

DY

TP1932TPAD14-OP-GP TP1932TPAD14-OP-GP

SUS_PW R_ACK

BATLOW #

1

PM_RI#

2

ACPRESENT

3

PCIE_WAKE#

45

10KR2J-3-GP

12

DY

12

SIV For intel

10KR2J-3-GP

12

R1903

1 2

0R2J-2-GP

R1906

0R2J-2-GP

DY

1 2

1 2 1 2

1

PWROK

1 2

1

SUS_PW R_ACK

PM_PWRBTN#

PM_SLP_LAN#

PM_RSMRST#

1 2

DMI_COMP_R RBIAS_CPY

R1923

1 2

DY

MEPWROK

TP1934TPAD14-OP-GP TP1934TPAD14-OP-GP

PM_RSMRST#

BATLOW #

PM_RI#

SIV

BC24

BE20

DMI_RXP3_R

SUSACK#SUS_PW R_ACK

SYS_RESET#

BG18 BG20

BE24

BC20

BJ18 BJ20

AW24 AW20

BB18 AV18

AY24 AY20 AY18

AU18

BJ24 BG25 BH21

DMI_RXN3_R

0R2J-2-GP

1

PCH_WAKE# CRB : 1K CHKLIST: 10K

4

PCH1C

DMI0RXN DMI1RXN DMI2RXN DMI3RXN

DMI0RXP DMI1RXP DMI2RXP DMI3RXP

DMI0TXN DMI1TXN DMI2TXN DMI3TXN

DMI0TXP DMI1TXP DMI2TXP DMI3TXP

DMI_ZCOMP DMI_IRCOMP DMI2RBIAS

C12

SUSACK#

K3

SYS_RESET#

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST#

K16

SUSWARN#/SUSPWRDNACK/GPIO30

E20

PWRBTN#

H20

ACPRESENT/GPIO31

E10

BATLOW#/GPIO72

A10

RI#

PANTHER-GP-NF

PCH

󲓢󲓢󲓢󲓢󴖨󴖨󴖨󴖨

: 71.PANTH.00U

DMI

FDI

DMI

FDI

CLKRUN#/GPIO32

SUS_STAT#/GPIO61

SUSCLK/GPIO62

SLP_S5#/GPIO63

System Power Management

SLP_LAN#/GPIO29

3 OF 10

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7

FDI_INT FDI_FSYNC0 FDI_FSYNC1 FDI_LSYNC0 FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE#

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

BJ14 AY14 BE14 BH13 BC12 BJ12 BG10

FDI_TXN7_L

BG9 BG14

BB14 BF14 BG13 BE12 BG12 BJ10

FDI_TXP7_L

BH9

AW16 AV12 BC10 AV14 BB10

DSWODVREN

A18

E22

B9

N3

G8

N14

D10

H4

F4

G10

G16

AP14

K14

3D3V_AUX_S5

R1916

R1916 10KR2J-3-GP

10KR2J-3-GP

1 2

3V_5V_POK_#

FDI_TXN[7:0] 4 FDI_TXP[7:0] 4

1 2

R1934 0R2J-2-GPR1934 0R2J-2-GP

1 2

R1933 0R2J-2-GPR1933 0R2J-2-GP

FDI_INT 4 FDI_FSYNC0 4 FDI_FSYNC1 4 FDI_LSYNC0 4

TP1937

12

Q1901

5 6

2N7002KDW-GP

84.2N702.A3F

FDI_LSYNC1 4

TPAD14-OP-GP

1

34 2 1

1

PCH_DPW ROK

PCIE_WAKE#_P

PM_SUS_STAT#

SUS_CLK

PM_SLP_S5#

SLP_S4#_R

SLP_S3#_R

PM_SLP_A#

PM_SLP_SUS#

H_PM_SYNC

PM_SLP_LAN#

R1909

100KR2J-1-GP

2nd = 84.2N702.F3F

3

FDI_TXN0 4 FDI_TXN1 4 FDI_TXN2 4 FDI_TXN3 4 FDI_TXN4 4 FDI_TXN5 4 FDI_TXN6 4 FDI_TXN7 4

FDI_TXP0 4 FDI_TXP1 4 FDI_TXP2 4 FDI_TXP3 4 FDI_TXP4 4 FDI_TXP5 4 FDI_TXP6 4 FDI_TXP7 4

0R2J-2-GP

0R2J-2-GP R1910

R1910

1 2

R1911 10KR2J-3-GP

1 2

DY

1 2

R1991 0R2J-2-GP

TP1901

1 2

TP1902

1 2

DY

TP1904

H_PM_SYNC 5

TP1931

PM_RSMRST#

R1928

0R2J-2-GP

TPAD14-OP-GP

R1913

TPAD14-OP-GP

R1914

R1915

TPAD14-OP-GP

PM_RSMRST#

0R2J-2-GP

R1912

1 2

1KR2J-1-GP

For platforms not supporting Deep S4/S5

1.VccSUS3_3 and VccDSW3_3 will rise at the same time (connected on board)

2.DPWROK and RSMRST# will rise at the same time (connected on board)

3.SLP_SUS# and SUSACK# are left as ‘no connect’

4.SUSWARN# used as SUSPWRDNACK/GPIO30

DY

R1935 49D9R2F-GP

1 2

R1936 49D9R2F-GP

1 2

DY

R1917

1 2

330KR2J-L1-GP

R1918 330KR2J-L1-GP

1 2

DY

R1919

1 2

20110728 for vendor

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

PCH (DMI/FDI/PM)

G48/G58

1

10KR2J-3-GP

19

RTC_AUX_S5

1

TP1933

RSMRST#_KBC 27

3V_5V_POK 41

TPAD14-OP-GP

RTC_AUX_S5

PCIE_WAKE# 31,65

PM_CLKRUN# 27

PCH_SUSCLK_KBC 27

1

TP1938

PM_SLP_S4# 27,46

PM_SLP_S3# 27,36,37,47

1

TP1939

1

TP1940

2

TPAD14-OP-GP

TPAD14-OP-GP TPAD14-OP-GP

TPAD14-OP-GP

FDI_TXN7 FDI_TXP7

DSWODVREN - On Die DSW VR Enable

HIGH Enabled (DEFAULT)

LOW Disabled

DSWODVREN

PM_CLKRUN#

JV10-CS

Title

Size Document Number Rev

Date: Sheet of

SC

103Friday, February 17, 2012

5

SSID = PCH

CLK_PCIE_WWAN_REQ#

4

RN2022

4

CLK_PCIE_USB3_REQ#

PCIE_CLK_REQ5#

PEG_B_CLKRQ#

PCIE_CLK_REQ6#

PCIE_CLK_NEW_REQ# PCIE_CLK_XDP_N

1

PCIE_CLK_XDP_P

1

PCIE_RXN1 PCIE_RXP1 PCIE_TXN1_C PCIE_TXP1_C

PCIE_TXN2_C PCIE_TXP2_C

PCIE_TXN4_C PCIE_TXP4_C

CLK_PCH_SRC1_N

PCIE_CLK_RQ2#

CLK_PCH_SRC3_N CLK_PCH_SRC3_P

SRN0J-6-GP

SIV

1

TP2004TPAD14-OP-GP TP2004TPAD14-OP-GP

1

TP2005TPAD14-OP-GP TP2005TPAD14-OP-GP

1

TP2006TPAD14-OP-GP TP2006TPAD14-OP-GP

1

D D

C C

PCIE_RXN265

PCIE_RXP265 PCIE_TXN265 PCIE_TXP265

PCIE_RXN431

PCIE_RXP431 PCIE_TXN431 PCIE_TXP431

TP2007TPAD14-OP-GP TP2007TPAD14-OP-GP

C2001 SCD1U10V2KX-5GPC2001 SCD1U10V2KX-5GP

1 2

C2002 SCD1U10V2KX-5GPC2002 SCD1U10V2KX-5GP

1 2

C2005 SCD1U10V2KX-5GPC2005 SCD1U10V2KX-5GP

1 2

C2006 SCD1U10V2KX-5GPC2006 SCD1U10V2KX-5GP

1 2

WWAN CLK

RN2023

CLK_PCIE_WLAN#65

WLAN CLK

LAN CLK

B B

3D3V_S0

PCIECLKRQ1# and PCIECLKRQ2# support S0 power only

A A

CLK_PCIE_WLAN65

CLK_PCIE_LAN#31 CLK_PCIE_LAN31

PCIE_CLK_LAN_REQ#31

RN2018

1 2 3

SRN10KJ-5-GP

CLK_PCIE_WLAN_REQ#65

CLK_PCIE_WLAN_REQ#

4

PCIE_CLK_RQ2#

5

SRN0J-6-GP

1 2 3

20110708

1 2 3

TP2010TPAD14-OP-GP TP2010TPAD14-OP-GP TP2011TPAD14-OP-GP TP2011TPAD14-OP-GP

4

PCH1B

BG34

PERN1

BJ34

PERP1

AV32

PETN1

AU32 BE34

BF34 BB32 AY32

BG36

BJ36 AV34 AU34

BF36 BE36 AY34 BB34

BG37 BH37 AY36 BB36

BJ38 BG38 AU36 AV36

BG40

BJ40 AY40 BB40

BE38 BC38

AW38

AY38

Y40 Y39

AB49 AB47

M1

AA48 AA47

V10

Y37 Y36

Y43 Y45

L12

V45 V46

L14

AB42 AB40

V40 V42

T13 V38

V37 K12

AK14 AK13

– Prioritize 27/14/24/48/25-MHz FLEX on FLEX1 and FLEX3 – Do not configure 27/14/24/48/25-MHz FLEX clock on FLEX0 and FLEX2 if more than 2 PCI clocks + PCI loopback are routed.

W-WAN

PETP1 PERN2

PERP2

WLAN

PETN2 PETP2

PERN3 PERP3 PETN3 PETP3

PERN4 PERP4

LAN

PETN4 PETP4

PERN5 PERP5 PETN5 PETP5

PERN6 PERP6 PETN6 PETP6

PERN7 PERP7 PETN7 PETP7

PERN8 PERP8 PETN8 PETP8

CLKOUT_PCIE0N CLKOUT_PCIE0P

J2

PCIECLKRQ0#/GPIO73

CLKOUT_PCIE1N CLKOUT_PCIE1P

PCIECLKRQ1#/GPIO18

CLKOUT_PCIE2N CLKOUT_PCIE2P

PCIECLKRQ2#/GPIO20

CLKOUT_PCIE3N CLKOUT_PCIE3P

A8

PCIECLKRQ3#/GPIO25

CLKOUT_PCIE4N CLKOUT_PCIE4P

PCIECLKRQ4#/GPIO26

CLKOUT_PCIE5N CLKOUT_PCIE5P

PCIECLKRQ5#/GPIO44

CLKOUT_PEG_B_N CLKOUT_PEG_B_P

E6

PEG_B_CLKRQ#/GPIO56

CLKOUT_PCIE6N CLKOUT_PCIE6P

PCIECLKRQ6#/GPIO45 CLKOUT_PCIE7N

CLKOUT_PCIE7P PCIECLKRQ7#/GPIO46 CLKOUT_ITPXDP_N

CLKOUT_ITPXDP_P

PANTHER-GP-NF

4

SMBUSController

PCI-E*

CLOCKS

SMBALERT#/GPIO11

SML0ALERT#/GPIO60

SML1ALERT#/PCHHOT#/GPIO74

SML1CLK/GPIO58

SML1DATA/GPIO75

Link

PEG_A_CLKRQ#/GPIO47

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKIN_PCILOOPBACK

CLKOUTFLEX0/GPIO64 CLKOUTFLEX1/GPIO65 CLKOUTFLEX2/GPIO66 CLKOUTFLEX3/GPIO67

FLEX CLOCKS

2 OF 10

SMBCLK

SMBDATA

SML0CLK

SML0DATA

CL_CLK1

CL_DATA1

CL_RST1#

CLKOUT_DMI_N CLKOUT_DMI_P

CLKOUT_DP_N CLKOUT_DP_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_GND1_N CLKIN_GND1_P

CLKIN_DOT_96N CLKIN_DOT_96P

CLKIN_SATA_N CLKIN_SATA_P

REFCLK14IN

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

3

EC_SWI#

E12

SMB_CLK

H14

SMB_DATA

C9

DRAMRST_CNTRL_PCH

A12

SML0_CLK

C8

SML0_DATA

G12

PCH_GPIO74

C13

SML1_CLK

E14

SML1_DATA

M16

CL_CLK

M7

CL_DATA

T11

CL_RST#

P10

PEG_CLKREQ#_R

M10

CLKOUT_PEG_A_N

AB37

CLKOUT_PEG_A_P

AB38

CLKOUT_DMI_N

AV22

CLKOUT_DMI_PCLK_PCH_SRC1_P

AU22

CLKOUT_DP_N

AM12

CLKOUT_DP_P

AM13

CLK_BUF_EXP_N

BF18

CLK_BUF_EXP_P

BE18

CLK_BUF_CPYCLK_N

BJ30

CLK_BUF_CPYCLK_P

BG30

CLK_BUF_DOT96_N

G24

CLK_BUF_DOT96_P

E24

CLK_BUF_CKSSCD_N

AK7

CLK_BUF_CKSSCD_P

AK5

CLK_BUF_REF14

K45

CLK_PCI_FB

H45

XTAL25_IN

V47

XTAL25_OUT

V49

XCLK_RCOMP

Y47

JTAG_TCK

K43

CLK_PCH_48M_L

F47

LAN_25M

H47

DGPU_PRSNT#

K49

1

SRN0J-6-GP

1 2

90D9R2F-1-GP

TP2001

TP2002

TP2003

1 2 3

2 3 1

1 2 3

1 1

R2007

1

1 2

RN2024

RN2025

RN2017

RN2008 SRN10KJ-5-GPRN2008 SRN10KJ-5-GP

TP2016

TP2016 TP2017

TP2017

1 1 1

TPAD14-OP-GP

TP2015

DRAMRST_CNTRL_PCH 12,37

SML1_CLK 27 SML1_DATA 27

TPAD14-OP-GP

OPS

R2003

0R2J-2-GP

OPS

4

DY

1 2 3

CLK_PCI_FB 18

TPAD14-OP-GP

TPAD14-OP-GP TPAD14-OP-GP

TPAD14-OP-GP

+VCCDIFFCLKN

TPAD14-OP-GP

TP2013

TPAD14-OP-GP

TP2012

TPAD14-OP-GP

TP2014

110706 modified

PCH

PEG_CLKREQ#_R

PEG_CLKREQ# 83

CLK_PCIE_VGA# 83 CLK_PCIE_VGA 83

CLK_EXP_N 5 CLK_EXP_P 5

CLK_DP_N_R 5 CLK_DP_P_R 5

4

PL 10K FOR Integrated CLOCK GEN mode.

CLK_BUF_REF14 CLK_BUF_CKSSCD_N CLK_BUF_CKSSCD_P

󲓢󲓢󲓢󲓢󴖨󴖨󴖨󴖨

: 71.PANTH.00U

2

3D3V_S5 3D3V_S5

SMB_CLK SMB_DATA

SML0_DATA SML0_CLK

SML1_CLK SML1_DATA

PCIE_CLK_REQ6# PCH_GPIO74

DRAMRST_CNTRL_PCH

4

2N7002KDW-GP

1 2 34

84.2N702.A3F

Q2001

2nd = 84.2N702.F3F

DY

1 2

R2008 0R2J-2-GP

R2008 and C2008 CO-LAY

R2006

R2006 1M1R2J-GP

1M1R2J-GP

1 2

2nd = 82.30020.791

12

10KR2J-3-GP

12

R2013

UMA

UMA_DIS#

12

DGPU_PRSNT#

12

DY

OPS

R2011

R2011 10KR2J-3-GP

10KR2J-3-GP

CLK_BUF_EXP_N

CLK_BUF_EXP_P CLK_BUF_DOT96_N CLK_BUF_DOT96_P

3D3V_S5

G48/G58

2

DY

SMB_DATA

SMB_CLK

12

R2004

R2004 10KR2J-3-GP

10KR2J-3-GP

12

R2005

R2005 10KR2J-3-GP

10KR2J-3-GP

20110715

3D3V_S0

RN2009

1 2 3 4 5 6

SRN10KJ-L3-GP

need very close to PCH

RN2007

2 3 1

SRN2K2J-1-GP

6 5

XTAL25_IN

XTAL25_OUT

3D3V_S0 3D3V_S0

10KR2J-3-GP

R2012

R2010

10KR2J-3-GP

10 9 8 7

JV10-CS

Title

PCH ( PCI-E/SMBUS/CLOCK/CL)

Size Document Number Rev

Date: Sheet of

1

4

4 2 3

1 1

2 3

R2009

1 2

1KR2J-1-GP

PCH_SMBDATA 14,15,65

PCH_SMBCLK 14,15,65

X2001

X2001 XTAL-25MHZ-102-GP

XTAL-25MHZ-102-GP

1 2

82.30020.851

DGPU_PRSNT#,UMA_DIS# UMA: 1 1 DIS : 0 1 SG(PX) : 0 0 Optimus : 1 0

UMA_DIS# 22

RN2001

1 2 3 4 5

SRN10KJ-6-GP

SRN10KJ-6-GP RN2002

RN2002

1 2 3 4 5

SRN10KJ-6-GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

RN2003

1

SRN2K2J-1-GP

23

RN2004

23

SRN2K2J-1-GP

1

RN2005

RN2005 SRN2K2J-1-GP

SRN2K2J-1-GP

4

RN2006

4

SRN10KJ-5-GP

CRB: 1K CHKLT: 10K

SIT

C2008

12

SC12P50V2JN-3GP

C2007

12

SC15P50V2JN-2-GP

CLK_PCIE_WWAN_REQ#

8 7

PCIE_CLK_LAN_REQ#

6

CLK_PCIE_USB3_REQ#

EC_SWI#

8

PCIE_CLK_REQ5#

7

PCIE_CLK_NEW_REQ#

6

PEG_B_CLKRQ#

20

SC

103Friday, February 17, 2012

5

4

3

2

1

NOTE

SSID = PCH

RTC_X1

1 2

R2101 10MR2J-L-GPR2101 10MR2J-L-GP

D D

SIT

C C

B B

C2101

12

HDA_CODEC_SDOUT29

HDA_CODEC_RST#29 HDA_CODEC_BITCLK29

+3VS_+1.5VS_HDA_IO

3D3V_S0

+3VS_+1.5VS_HDA_IO

This signal has a weak internal pull down. On Die PLL VR is supplied by 1.5V when sampled high, 1.8 V when sampled low. Needs to be pulled High for Huron River platform. co-operate with R2310

X2101

1

SC6P50V2CN-1GP

2 3

X-32D768KHZ-34GPU

R2102

1 2

1KR2J-1-GP

DY

NO REBOOT STRAP

R2106

1 2

1KR2J-1-GP

DY

1 2

4

R2103 1KR2J-1-GPR2103 1KR2J-1-GP

RTC_X2

C2102

12

SC6P50V2CN-1GP

SIT

RTCRST_ON27

R2123 33R2J-2-GPR2123 33R2J-2-GP

RN2102

1 2 3

SRN33J-5-GP-U

Flash Descriptor Security Overide

HDA_SDOUT

HDA_SPKR

HDA_SYNC

D

G

0R2J-2-GP

DY

12

HDA_RST#

4

HDA_BITCLK_C

Low = Default High = Enable

No Reboot Strap

Low = Default High = No Reboot

RTC_AUX_S5

Q2130

Q2130 2N7002K-2-GP

2N7002K-2-GP

84.2N702.J31

2nd = 84.2N702.W31

S

KBC_RTCRST#_Q

1 2

BAS16-6-GP

2

DY

1 1 2

R2130

R2131

R2131 0R2J-2-GP

0R2J-2-GP

HDA_SDOUT

D2130

2 3 1

SIT

3

1 2

ER22330R2J-2-GP ER22330R2J-2-GP

RN2104

4

SRN20KJ-1-GP

C2104

HDA_BITCLK

12

SC1U6D3V2KX-GP

12

ME_UNLOCK27

PLL ODVR VOLTAGE

HDA_SYNC

A A

HDA_SYNC

Low = 1.8V (Default) High = 1.5V

1 2

84.2N702.J31

2ND = 84.2N702.W31

Q2101

D

2N7002K-2-GP

5V_S0

5

DY

S

G

R212233R2J-2-GP

HDA_CODEC_SYNC_L

12

R2127

R2127 1MR2F-GP

1MR2F-GP

1 2

R2124

33R2J-2-GP

HDA_SYNC: This strap is sampled on rising edge of RSMRST# and is used to sample 1.5V VccVRM supply mode. 1K external pull-up resistor is required on this signal on the board. Signal may have leakage paths via powered off devices (Audio Codec) and hence contend with the external pull-up. A blocking FET is recommended in such a case to isolate HDA_SYNC from the Audio Codec device until after the Strap sampling is complete.

HDA_CODEC_SYNC 29

4

1

TP2111TPAD14-OP-GP TP2111TPAD14-OP-GP

C2103

C2103 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

21

G2101

GAP-OPEN

RTC_AUX_S5

KBC_RTCRST# 27

For EMC

SPI_CLK_R27,60,65 SPI_CS0#_R27,60,65

SPI_SI_R27,60,65

SPI_SO_R27,60,65

INTVRMEN- Integrated SUS

1.05V VRM Enable High - Enable internal VRs Low - Enable external VRs

1

TP2114TPAD14-OP-GP TP2114TPAD14-OP-GP

1

TP2115TPAD14-OP-GP TP2115TPAD14-OP-GP

1

TP2112TPAD14-OP-GP TP2112TPAD14-OP-GP

1M1R2J-GP

R2104

12

R2105

1 2

330KR2F-L-GP

HDA_SPKR29

HDA_SDIN029

TP2106TPAD14-OP-GP TP2106TPAD14-OP-GP

4K7R2J-2-GP

4K7R2J-2-GP R2121

R2121

TP2102TPAD14-OP-GP TP2102TPAD14-OP-GP TP2103TPAD14-OP-GP TP2103TPAD14-OP-GP TP2104TPAD14-OP-GP TP2104TPAD14-OP-GP

R2108

R2110

HDA_SDOUT

TP2105TPAD14-OP-GP TP2105TPAD14-OP-GP

1

12

33R2J-2-GP

1 2 1 2

R210933R2J-2-GP R210933R2J-2-GP

1 2

33R2J-2-GP

1 1 1

R2107 1KR2J-1-GPR2107 1KR2J-1-GP

1 2

RTC_X1

RTC_X2 RTC_RST# SRTC_RST# SM_INTRUDER# PCH_INTVRMEN

HDA_BITCLK HDA_SYNC

HDA_RST#

PCH_JTAG_TCK_BUF

PCH_JTAG_TMS PCH_JTAG_TDI PCH_JTAG_TDO

PCH_SPI_CLK PCH_SPI_CS0#

SIT

TP2113TPAD14-OP-GP TP2113TPAD14-OP-GP

PCH_GPIO33

1

PCH_SPI_SI

1

3

PCH1A

A20

RTCX1

C20

RTCX2

D20

RTCRST#

G22

SRTCRST#

K22

INTRUDER#

C17

INTVRMEN

N34

HDA_BCLK

L34

HDA_SYNC

T10

SPKR

K34

HDA_RST#

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

C36

HDA_DOCK_EN#/GPIO33

N32

HDA_DOCK_RST#/GPIO13

J3

JTAG_TCK

H7

JTAG_TMS

K5

JTAG_TDI

H1

JTAG_TDO

T3

SPI_CLK

Y14

SPI_CS0#

T1

SPI_CS1#

V4

SPI_MOSI

U3

SPI_MISO

PANTHER-GP-NF

PCH

󲓢󲓢󲓢󲓢󴖨󴖨󴖨󴖨

1 2

DY

RTCIHDA

JTAG

SPI

: 71.PANTH.00U

EC2102

SC4D7P50V2CN-1GP

DY

1 2

1 OF 10

FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3

LPC

FWH4/LFRAME#

LDRQ0#

LDRQ1#/GPIO23

SERIRQ

SATA0RXN SATA0RXP SATA0TXN SATA0TXP

SATA1RXN SATA1RXP

SATA 6G

SATA1TXN SATA1TXP

SATA2RXN SATA2RXP SATA2TXN SATA2TXP

SATA3RXN SATA3RXP SATA3TXN SATA3TXP

SATA4RXN SATA4RXP SATA4TXN

SATA

SATA4TXP SATA5RXN

SATA5RXP SATA5TXN SATA5TXP

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATALED# SATA0GP/GPIO21 SATA1GP/GPIO19

EC2103

SC4D7P50V2CN-1GP

LPC_AD0_TPM

C38

LPC_AD1_TPM

A38

LPC_AD2_TPM

B37

LPC_AD3_TPM

C37

LPC_FRAME#_L

D36 E36

GPIO23

K36 V5

SATA_RXN0_C

AM3

SATA_RXP0_C

AM1

SATA_TXN0_C

AP7

SATA_TXP0_C

AP5 AM10

AM8

SATA_TXN1_C

AP11

SATA_TXP1_C

AP10 AD7

AD5 AH5 AH4

AB8 AB10 AF3 AF1

Y7 Y5

SATA_TXN4_C

AD3

SATA_TXP4_C

AD1

SATA_RXN5

Y3

SATA_RXP5

Y1

SATA_TXN5

AB3

SATA_TXP5

AB1 Y11 Y10

AB12 AB13

AH1

SATA_LED#

P3

GPIO21_SATA_DET#0

V14

GPIO19_BBS_BIT0

P1

SPI_CS0#_RHDA_CODEC_BITCLK HDA_CODEC_SDOUT

EC2101

1 2

DY

SC4D7P50V2CN-1GP

2

R2111,R2118~R2120,R2125

0 ohm

HR

63.R0034.1DL

22 ohm

CRV

64.22R05.6DL

22 ohm 5%

R2111 22R2J-2-GPR2111 22R2J-2-GP

1 2

R2118 22R2J-2-GPR2118 22R2J-2-GP

1 2

R2119 22R2J-2-GPR2119 22R2J-2-GP

1 2

R2120 22R2J-2-GPR2120 22R2J-2-GP

1 2

22R2J-2-GP

INT_SERIRQ 27

1

TP2133 TPAD14-OP-GPTP2133 TPAD14-OP-GP

1

TP2134 TPAD14-OP-GPTP2134 TPAD14-OP-GP

C2105 SCD01U16V2KX-3GPC2105 SCD01U16V2KX-3GP

1 2

C2106

1 2

SCD01U16V2KX-3GP

Move Cap close to Device or Connector.

SATA_RXN4_C 56

SATA_RXP4_C 56

G48

C2109 SCD01U16V2KX-3GP

1 2

C2110 SCD01U16V2KX-3GP

1 2

G48

1

TP2107 TPAD14-OP-GPTP2107 TPAD14-OP-GP

1

TP2108 TPAD14-OP-GPTP2108 TPAD14-OP-GP

1

TP2109 TPAD14-OP-GPTP2109 TPAD14-OP-GP

1

TP2110 TPAD14-OP-GPTP2110 TPAD14-OP-GP

SATA_COMP

SATA3_COMP

RBIAS_SATA3

R2112

1 2

37D4R2F-GP

R2113 49D9R2F-GPR2113 49D9R2F-GP

1 2

R2114 750R2F-GPR2114 750R2F-GP

1 2

For Ge

1

1 2

R2232

0R2J-2-GP

1 2

R22310R2J-2-GP R22310R2J-2-GP

20110727 for vendor

PSW_CLR#22

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

R2125

TP2130 TPAD14-OP-GPTP2130 TPAD14-OP-GP

SATA_DET#0

BBS_BIT0 18

SATA_DET#0

INT_SERIRQ

SIV

GPIO23

JV10-CS

Title

PCH (SPI/RTC/LPC/SATA/IHDA)

Size Document Number Rev

Date: Sheet of

LPC_AD[0..3]

LPC_FRAME# 27,65

1

TP2131 TPAD14-OP-GPTP2131 TPAD14-OP-GP

1

TP2132 TPAD14-OP-GPTP2132 TPAD14-OP-GP

SATA_RXN1_C 56 SATA_RXP1_C 56 SATA_TXN1 56 SATA_TXP1 56

SATA_TXN4_C 56 SATA_TXP4_C 56

SATA_TXN4 56 SATA_TXP4 56

1D05V_VTT

LA37/LA57/CRV-Std:750ohm LA47: 806 ohm

R2129

1 2

1 2 3

1 2

10KR2J-3-GP

G48/G58

R2129 10KR2J-3-GP

10KR2J-3-GP

SRN10KJ-5-GP

RN2101

4

R2128

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

LPC_AD[0..3] 27,65

SATA SSD

HDD1

ODD

Delete ESATA

3D3V_S0

110706 modified

21

SC

103Friday, February 17, 2012

5

4

3

2

1

3D3V_S0

D D

GPIO27 has a weak[20K] internal pull up. To enable on-die PLL Voltage regurator, should not place external pull down.

Note

HR

CRB

C C

B B

A A

SIV

R2202 200KR2F-L-GPR2202 200KR2F-L-GP

1 2

DY

4

----

RN2201

1 2 3

RN2202

1 2 3 4 5

SRN10KJ-6-GP

1 2 3

SRN10KJ-5-GP

100KR2J-1-GP

10KR2J-3-GP

R2228

1 2

10KR2J-3-GP

DY

20110728 for Vendor

RN2204

RN2203

1 2 3

SRN10KJ-5-GP

R2202

200K ohm

64.20035.6DL

10K ohm

63.10334.1DL

PCH_GPIO24

R2234

R2234 100KR2J-1-GP

100KR2J-1-GP

DY

1 2

DGPU_HPD_INTR#

EC_SMI#

PCH_GPIO48

S_GPIO EC_SCI# PCH_GPIO22

PCH_TEMP_ALERT#

MFG_MODE

SIV

RTC_DET#

PCH_GPIO24

PCH_GPIO15

PLL_ODVR_EN

USB3_PW R_ON

20110717

SATA_ODD_PRSNT#

110706 modified

H_RCIN#

PCH_GPIO15 pull high => HM76 PCH_GPIO15 pull Low => HM70

SVT

3D3V_S0

SRN10KJ-5-GP

4

8 7 6

4

3D3V_S5

1 2

R2229

1 2

5

SIT

R2227

SVT

10K ohm for intel check list command

R2201

1KR2J-1-GP

R2226

R2226 10KR2J-3-GP

10KR2J-3-GP

Note: For PCH debug with XDP, need to NO STUFF R2218

PCH_GPIO15

R2233

R2233 100KR2J-1-GP

100KR2J-1-GP

DY

1 2

LOW: ODD exist HIGH: ODD non-exist

SATA_ODD_PRSNT#56

3D3V_S5

1 2

PSW_CLR#21

SIV

3D3V_S0

110706 modified

R2230

R2230 10KR2J-3-GP

10KR2J-3-GP

1 2

NC_FP_DET#

12

R2220

R2220 10KR2J-3-GP

10KR2J-3-GP

DY

NC_FP_DET# => Low: FP exist High: FP non-exist

3D3V_S0

12

R2214

R2216

10KR2J-3-GP

SSID = PCH

S_GPIO GPIO0

R2218

1 2

100R2J-2-GP

SIT

RTC_DET#60

R2213

1 2

0R0402-PAD

G2201

TP2207TPAD14-OP-GP TP2207TPAD14-OP-GP

100R2J-2-GP

EC_SMI# DGPU_HPD_INTR#H_A20GATE VRAM_SIZE1 EC_SCI# ICC_EN# RTC_DET# PCH_GPIO15

PCH_GPIO16

DGPU_PW ROK PCH_GPIO22 PCH_GPIO24

PLL_ODVR_EN

PSW_CLR#

NC_FP_DET# DMI_OVRVLTG FDI_OVRVLTG MFG_MODE GFX_CRB_DET PCH_GPIO48 PCH_TEMP_ALERT#

USB3_PW R_ON

1

TP2205

1

TP2205TPAD14-OP-GP TP2205TPAD14-OP-GP

NCTF_3#A45

1

TP2209TPAD14-OP-GP TP2209TPAD14-OP-GP

1

TP2206TPAD14-OP-GP TP2206TPAD14-OP-GP

TP2213TPAD14-OP-GP TP2213TPAD14-OP-GP

TP2215TPAD14-OP-GP TP2215TPAD14-OP-GP TP2216TPAD14-OP-GP TP2216TPAD14-OP-GP TP2217TPAD14-OP-GP TP2217TPAD14-OP-GP TP2218TPAD14-OP-GP TP2218TPAD14-OP-GP

TP2219TPAD14-OP-GP TP2219TPAD14-OP-GP

TP2211TPAD14-OP-GP TP2211TPAD14-OP-GP

TP2212TPAD14-OP-GP TP2212TPAD14-OP-GP

R2212

1 2

DY

NCTF_5#A5

1

NCTF_7#B3

1

NCTF_8#B47

1

NCTF_9#BD1

1

NCTF_10#BD49NCTF_10#BD49

1

NCTF_13#BF1

1

TP2212

1

1KR2J-1-GP

SVT

EC_SCI#27

DGPU_PW ROK92,93

R2225

R2225 10KR2J-3-GP

10KR2J-3-GP

GAP-OPEN

21

check remove?

VRAM_SIZE1 VRAM_SIZE2

PLL ON DIE VR ENABLE

NOTE:This signal has a weak internal pull-up 20K ENABLED -- HIGH (R2212 UNSTUFFED) DEFAULT DISABLED -- LOW (R2212 STUFFED)

PLL_ODVR_EN

4

TP2206

TP2211

PCH1F

T7

BMBUSY#/GPIO0

A42

TACH1/GPIO1

H36

TACH2/GPIO6

E38

TACH3/GPIO7

C10

GPIO8

C4

LAN_PHY_PWR_CTRL/GPIO12

G2

GPIO15

U2

SATA4GP/GPIO16

D40

TACH0/GPIO17

T5

SCLOCK/GPIO22

E8

GPIO24

E16

GPIO27

P8

GPIO28

K1

STP_PCI#/GPIO34

K4

GPIO35

V8

SATA2GP/GPIO36

M5

SATA3GP/GPIO37

N2

SLOAD/GPIO38

M3

SDATAOUT0/GPIO39

V13

SDATAOUT1/GPIO48

V3

SATA5GP/GPIO49/TEMP_ALERT#

D6

GPIO57

A4

VSS_NCTF_1#A4

A44

VSS_NCTF_2#A44

A45

VSS_NCTF_3#A45

A46

VSS_NCTF_4#A46

A5

VSS_NCTF_5#A5

A6

VSS_NCTF_6#A6

B3

VSS_NCTF_7#B3

B47

VSS_NCTF_8#B47

BD1

VSS_NCTF_9#BD1

BD49

VSS_NCTF_10#BD49

BE1

VSS_NCTF_11#BE1

BE49

VSS_NCTF_12#BE49

BF1

VSS_NCTF_13#BF1

BF49

VSS_NCTF_14#BF49

PANTHER-GP-NF

PCH

󲓢󲓢󲓢󲓢󴖨󴖨󴖨󴖨

3D3V_S0

6 OF 10

TACH4/GPIO68 TACH5/GPIO69 TACH6/GPIO70 TACH7/GPIO71

A20GATE

PROCPWRGD

GPIO

NCTF TEST PIN:

A4,A44,A45,A46,A5,A6,B3,B47,

BD1,BD49,BE1,BE49,BF1,BF49,

BG2,BG48,BH3,BH47,BJ4,BJ44,

NCTF TEST PIN:

A4,A44,A45,A46,A5,A6,B3,B47,

BD1,BD49,BE1,BE49,BF1,BF49,

BG2,BG48,BH3,BH47,BJ4,BJ44,

THRMTRIP#

CPU/MISC

VSS_NCTF_15#BG2

VSS_NCTF_16#BG48

VSS_NCTF_17#BH3

VSS_NCTF_18#BH47

VSS_NCTF_19#BJ4 VSS_NCTF_20#BJ44 VSS_NCTF_21#BJ45

NCTF

VSS_NCTF_22#BJ46

VSS_NCTF_23#BJ5

VSS_NCTF_24#BJ6

VSS_NCTF_25#C2

VSS_NCTF_26#C48

VSS_NCTF_27#D1

VSS_NCTF_28#D49

VSS_NCTF_29#E1

VSS_NCTF_30#E49

BJ45,BJ46,BJ5,BJ6,C2,C48,D1,

D49,E1,E49,F1,F49

BJ45,BJ46,BJ5,BJ6,C2,C48,D1,

D49,E1,E49,F1,F49

VSS_NCTF_31#F1

VSS_NCTF_32#F49

INIT3_3V#

DF_TVS

TS_VSS1 TS_VSS2 TS_VSS3 TS_VSS4

: 71.PANTH.00U

3D3V_S0

12

R2209

R2209 10KR2J-3-GP

10KR2J-3-GP

DY

DMI_OVRVLTG FDI_OVRVLTG

12

R2210

R2210 10KR2J-3-GP

10KR2J-3-GP

3

PECI

RCIN#

NC_1

12

C40 B41 C41 A40

P4 AU16 P5 AY11 AY10 T14 AY1

AH8 AK11 AH10 AK10

P37

BG2 BG48 BH3 BH47 BJ4 BJ44 BJ45 BJ46 BJ5 BJ6 C2 C48 D1 D49 E1 E49 F1 F49

R2207

R2207 10KR2J-3-GP

10KR2J-3-GP

DY

R2208

R2208 10KR2J-3-GP

10KR2J-3-GP

UMA_DIS#

VRAM_SIZE2

H_PECI_R

PCH_THERMTRIP_R INIT3_3V# NV_CLEPCH_GPIO27

R2219

TS_VSS

1 2

0R2J-2-GP

NCTF_16#BG48

NCTF_25#C2 NCTF_26#C48

NCTF_31#F1

SIV

ICC_EN#

SATA_ODD_PWRGT 56 UMA_DIS# 20

H_A20GATE 27

R2203

1 2

H_RCIN# 27

H_CPUPW RGD 5,36,97

R2204 390R2J-1-GPR2204 390R2J-1-GP

1 2

1

TP2201 TPAD14-OP-GPTP2201 TPAD14-OP-GP

NV_CLE

1

TP2221 TPAD14-OP-GPTP2221 TPAD14-OP-GP

1

TP2230 TPAD14-OP-GPTP2230 TPAD14-OP-GP

1

TP2231 TPAD14-OP-GPTP2231 TPAD14-OP-GP

Integrated Clock Enable functionality is achieved via soft-strap. The default is integrated clock enable.

1

TP2236 TPAD14-OP-GPTP2236 TPAD14-OP-GP

ICC_EN#

GPIO8 has a weak[20K] internal pull up.

Integrated Clock Enable functionality is achieved via soft-strap. The default is integrated clock enable.

R2211

1 2

1KR2J-1-GP

DY

2

INTERNAL GFX EXTERNAL GFX

R2205 DY 10K

R2206 100K DY

3D3V_S0

12

R2205

R2205 10KR2J-3-GP

10KR2J-3-GP

DY

Check

DY

0R2J-2-GP

R1812

1 2

1KR2J-1-GP

R1808

2K2R2J-2-GP

H_PECI 5,27

H_THERMTRIP# 5,36

1D8V_S0

DMI & FDI Termination Voltage

12

NV_CLE

R2221

1 2

0R2J-2-GP

TS Signal Disable Guideline: TS_VSS1, TS_VSS2, TS_VSS3 and TS_VSS4 should not float on the motherboard. They should be tied to GND directly.

12

R2206

R2206 100KR2J-1-GP

100KR2J-1-GP

Set to Vss when LOW Set to Vcc when HIGH

H_SNB_IVB# 5

FDI TERMINATION VOLTAGE OVERRIDE

GPIO37 (FDI_OVRVLTG)

LOW - Tx, Rx terminated to same voltage (DC Coupling Model DEFAULT)

DMI TERMINATION VOLTAGE OVERRIDE

GPIO36 (DMI_OVRVLTG)

LOW - Tx, Rx terminated to same voltage (DC Coupling Model DEFAULT)

Integrated Clock Chip Enable

HIGH (R2211 DY)- DISABLED [DEFAULT]

LOW (R2211)- ENABLED

JV10-CS

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

PCH ( GPIO/CPU )

Size Document Number Rev

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

G48/G58

1

22

GFX_CRB_DET

SC

103Friday, February 17, 2012

5

4

3

2

1

SSID = PCH

D D

1D05V_VTT

(1uFx3)

(10uFx1_0603)

C C

(1uF x4)

B B

A A

12

1D05V_VTT

2.925A(Total current of VCCIO)

12

0.159A(Totally current of VCCVRM)

0.042A (Totally current of VCCDMI)

6A

1.3A

12

EC2303

SCD1U10V2KX-5GP

C2305

SC10U6D3V5KX-1GP

0.266A (Totally VCC3_3 current)

C2301

SC10U6D3V5KX-1GP

12

C2306

SC1U6D3V2KX-GP

+VCCAFDI_VRM

12

TP2301TPAD14-OP-GP TP2301TPAD14-OP-GP

12

TP2302TPAD14-OP-GP TP2302TPAD14-OP-GP

1D05V_VTT

C2302

SC1U6D3V2KX-GP

1D05V_VTT

C2307

SC1U6D3V2KX-GP

3D3V_S0

(0.1uF x1)

1

12

C2303

SC1U6D3V2KX-GP

VCCAPLLEXP

(10uF x1)

12

C2308

SC1U6D3V2KX-GP

VCCFDIPLL

+1.05VS_VCC_DMI

12

C2304

SC1U6D3V2KX-GP

12

C2309

SC1U6D3V2KX-GP

12

C2310

C2310 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

POWER

PCH1G

AA23

VCCCORE1

AC23

VCCCORE2

AD21

VCCCORE3

AD23

VCCCORE4

AF21

VCCCORE5

AF23

VCCCORE6

AG21

VCCCORE7

AG23

VCCCORE8

AG24

VCCCORE9

AG26

VCCCORE10

AG27

VCCCORE11

AG29

VCCCORE12

AJ23

VCCCORE13

AJ26

VCCCORE14

AJ27

VCCCORE15

AJ29

VCCCORE16

AJ31

VCCCORE17

AN19

VCCIO28

BJ22

VCCAPLLEXP

AN16

VCCIO15

AN17

VCCIO16

AN21

VCCIO17

AN26

VCCIO18

AN27

VCCIO19

AP21

VCCIO20

AP23

VCCIO21

AP24

VCCIO22

AP26

VCCIO23

AT24

VCCIO24

AN33

VCCIO25

AN34

VCCIO26

BH29

VCC3_3_3

AP16

VCCVRM2

BG6

VCCAFDIPLL

AP17

VCCIO27

AU20

VCCDMI2

PANTHER-GP-NF

VCCVRM(Internal PLL and VRMs): A.1.5V for Mobile B.1.8 V for Desktop co-operate with R2103

POWER

VCC CORE

VCCIO

FDI

CRTLVDS

DMI

DFT / SPI HVCMOS

7 OF 10

VCCADAC

VSSADAC

VCCALVDS VSSALVDS

VCCTX_LVDS1 VCCTX_LVDS2 VCCTX_LVDS3 VCCTX_LVDS4

VCC3_3_6

VCC3_3_7

VCCVRM3

VCCDMI1

VCCCLKDMI

VCCDFTERM1

VCCDFTERM2

VCCDFTERM3

VCCDFTERM4

VCCSPI

+VCCA_DAC_1_2

U48

U47

AK36 AK37

AM37 AM38 AP36 AP37

V33

3D3V_S0_VCC3_3

V34

SCD1U10V2KX-5GP

AT16

+1.05VS_VCC_DMI

AT20

AB36

+1.05VS_VCC_DMI_CCI

AG16

AG17

AJ16

AJ17

V1

(0.1uF/0.01uF x1) (10uF x1_0603)

12

C2313

+1.8VS_VCCTX_LVDS

R2309

R2309 0R2J-2-GP

0R2J-2-GP

DY

1 2

12

C2319

12

C2320

C2320 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

0.02A

12

C2321

C2321 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

0.19A

12

C2322

C2322 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

0.02A

12

C2323

C2323 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

12

C2314

SCD01U16V2KX-3GP

12

C2316

(0.1uFx1)

+VCCAFDI_VRM

1 2

SCD1U10V2KX-5GP

0.06A

SCD01U16V2KX-3GP

0R3J-0-U-GP

R2306

1 2

0R2J-2-GP

R2307

(1uFx1)

L2301

1 2

HCB1608KF-181-GP

12

C2315

68.00214.051

2nd = 68.00206.041

3rd = 68.00335.081

SC10U6D3V5KX-1GP

12

C2317

SCD01U16V2KX-3GP

R2315

1 2

0R2J-2-GP

R2302

1 2

1D05V_VTT

0R2J-2-GP

(1uFx1) (10uFx1)

(0.1uFx1)

VCCSPI

R2301

DY

1 2

0R2J-2-GP

R2310

0.001A

R2310

1 2

3D3V_S0

1D8V_S0

(0.01uF x2) (22uF x1)

12

C2318

+VCCA_DAC

L2302

1 2

IND-D1UH-21-GP

SIV

3D3V_S0

SC10U6D3V5KX-1GP

1D5V_S0

1D0V_S0

(1uF x1)

1D8V_S0

R2313

1 2

0R2J-2-GP

The same BIOS SPI ROM power

0R2J-2-GP

110722 Ge

3D3V_DAC_S0

0R2J-2-GP

3D3V_S5

3D3V_S0

5V_S0 3D3V_DAC_S0

12

DY

C2311

SC1U10V2KX-1GP

Refer to NPCE795 shared SPI flash architecture

JV10-CS

SIT

3.3V CRT LDO

DY

U2301

1

VIN

2

VOUT GND EN/EN#3NC#4

RT9198-33PBR-GP

5 4

12

DY

C2312

SC1U6D3V2KX-GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

PCH ( POWER1)

Size Document Number Rev

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

G48/G58

1

SC

103Friday, February 17, 2012

23

103Friday, February 17, 2012

5

4

3

2

1

SSID = PCH

VCCACLK

TP2401TPAD14-OP-GP TP2401TPAD14-OP-GP

3D3V_S0

L2401

D D

1 2

IND-10UH-218-GP

68.10050.10Y

2nd = 68.10090.10B

SC10U6D3V5KX-1GP

C2401

SIV

+V3.3S_VCC_CLKF33

12

DY

12

C2402

C2402 SC1U10V2KX-1GP

SC1U10V2KX-1GP

(10uFx1) (1uFx1)

0.002A

(0.1uFx1)

3D3V_S5

TP2405TPAD14-OP-GP TP2405TPAD14-OP-GP

TP2404TPAD14-OP-GP TP2404TPAD14-OP-GP

1D05V_VTT

TP2402TPAD14-OP-GP TP2402TPAD14-OP-GP

after layout, place 4.7uF *3

1D05V_VTT

1.01A (Total current of VCCASW)

C2404

C2403

12

SC10U6D3V3MX-GP

+VCCRTCEXT

(0.1uFx1)

+VCCDIFFCLKN

12

C2414

(1uFx1)

SC4D7U6D3V3KX-GP

C2404

12

4

C2405

0.08A

12

DY

SIV

12

C2405

DY

C2447

ST220U2D5VBM-7GP

C2448

ST220U2D5VBM-7GP

12

C2411

R2406

0R3J-0-U-GP

SC1U6D3V2KX-GP

SC10U6D3V3MX-GP

1D05V_VTT

L2402

C C

B B

1 2

IND-10UH-218-GP

68.10050.10Y

2nd = 68.10090.10B

L2403

1 2

IND-10UH-218-GP

68.10050.10Y

2nd = 68.10090.10B

1D05V_VTT

R2404

0R2J-2-GP

R2405

0R2J-2-GP

1 2

12

R2413

0R2J-2-GP

R2414

0R2J-2-GP

SIV

+VCCDIFFCLK

12

+V1.05S_SSCVCC

12

(1uFx1) (220uFx1)

+1.05VS_VCCA_A_DPL+1.05VS_VCCA_A_DPL

12

C2409

(1uFx1) (220uFx1)

SC1U6D3V2KX-GP

+1.05VS_VCCA_B_DPL

C2410

12

C2446

SC1U6D3V2KX-GP

SC10U6D3V5KX-1GP

(1uFx1)

C2412

SC1U6D3V2KX-GP

(1uFx1)

C2413

SC1U6D3V2KX-GP

0.08A

C2445

12

SC10U6D3V5KX-1GP

12

SCD1U10V2KX-5GP

1D05V_VTT

(1uFx1)

(0.1uFx1)

1D0V_S0

A A

5

0R2J-2-GP

R2417

12

(0.1uFx2)

(4.7uFx1_0603)

RTC_AUX_S5

6uA

(0.1uFx2) (1uFx1)

1

DCPSUSBYP

1

+V3.3S_VCC_CLKF33

+VCCAPLL_CPY_PCH

1

(10uFx1)

+VCCSUS1

1

12

C2406

SC10U6D3V3MX-GP

(1uFx3)

0.16A (Totally current of VCCVRM)

+VCCAFDI_VRM

12

C2408

C2407

SC1U6D3V2KX-GP

+1.05VS_VCCA_A_DPL +1.05VS_VCCA_B_DPL

+VCCDIFFCLK

SC1U6D3V2KX-GP

0.055A

12

0.001A

12

C2417

12

C2420

0.095A

C2415

TP2406TPAD14-OP-GP TP2406TPAD14-OP-GP

12

+V1.05S_SSCVCC

+VCCSST

12

C2418

SCD1U10V2KX-5GP

C2421

SCD1U10V2KX-5GP

SC1U6D3V2KX-GP

DCPSUS

1

+V_PROC_IO

12

C2419

12

C2422

SCD1U10V2KX-5GP

AD49

T16

V12

T38

BH23

AL29

AL24

AA19 AA21 AA24 AA26 AA27 AA29 AA31 AC26 AC27 AC29 AC31 AD29 AD31

W21 W23 W24 W26 W29 W31 W33

N16

Y49

BD47

BF47

AF17 AF33 AF34

AG34

AG33

V16

T17 V19

BJ8

A22

PCH1J

VCCACLK

VCCDSW3_3

DCPSUSBYP

VCC3_3_5

VCCAPLLDMI2 VCCIO14

DCPSUS3

VCCASW1 VCCASW2 VCCASW3 VCCASW4 VCCASW5 VCCASW6 VCCASW7 VCCASW8 VCCASW9 VCCASW10 VCCASW11 VCCASW12 VCCASW13 VCCASW14 VCCASW15 VCCASW16 VCCASW17 VCCASW18 VCCASW19 VCCASW20

DCPRTC

VCCVRM4

VCCADPLLA VCCADPLLB

VCCIO7 VCCDIFFCLKN1 VCCDIFFCLKN2 VCCDIFFCLKN3

VCCSSC

DCPSST

DCPSUS1 DCPSUS2

V_PROC_IO

VCCRTC

PANTHER-GP-NF

POWER

Clock and Miscellaneous

CPURTC

3

PCI/GPIO/LPCMISC

SATA USB

HDA

10 OF 10

VCCIO29 VCCIO30 VCCIO31 VCCIO32 VCCIO33

VCCSUS3_3_7 VCCSUS3_3_8 VCCSUS3_3_9

VCCSUS3_3_10

VCCSUS3_3_6

VCCIO34

V5REF_SUS

DCPSUS4

VCCSUS3_3_1

V5REF

VCCSUS3_3_2 VCCSUS3_3_3 VCCSUS3_3_4 VCCSUS3_3_5

VCC3_3_1 VCC3_3_8 VCC3_3_4

VCC3_3_2

VCCIO5

VCCIO12 VCCIO13

VCCIO6

VCCAPLLSATA

VCCVRM1

VCCIO2 VCCIO3 VCCIO4

VCCASW22

VCCASW23

VCCASW21

VCCSUSHDA

N26 P26 P28 T27 T29

0.097A (Totally current of VCCSUS3_3)

T23 T24 V23 V24 P24

T26

M26

AN23 AN24

P34

N20 N22 P20 P22

AA16 W16 T34

AJ2

AF13

AH13 AH14

AF14 AK1

AF11

AC16 AC17 AD17

T21

V21

T19

P32

1D05V_VTT

+5VA_PCH_VCC5REFSUS

+VCCA_USBSUS +V3.3A_VCCPSUS

+5VS_PCH_VCC5REF

+V3.3A_VCCPSUS

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

SC1U6D3V2KX-GP

+V1.05S_VCCAPLL_SATA3

+VCCAFDI_VRM

+V1.05S_VCC_SATA

1D05V_VTT

SC1U6D3V2KX-GP

0.01A

C2433

SCD1U10V2KX-5GP

C2433

12

C2428

12

C2430

12

C2429

12

C2432

12

DY

12

C2435

+3VS_+1.5VS_HDA_IO

(0.1uFx1)

12

2

C2424

C2424 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

C2434

C2423

C2423 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

C2425

C2425 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SC10U6D3V5KX-1GP

(0.1uFx1)

1

0.001A

1 2

0R3J-0-U-GP

12

1 2

0R3J-0-U-GP

1 2

0R3J-0-U-GP

1D05V_VTT

(1uFx1)

3D3V_S5

(0.1uFx1)

SVT

83.R0304.A8F

2nd = 83.R3004.A8F

21

D2401

D2401 CH751H-40PT-GP

CH751H-40PT-GP

1 2

10R2J-2-GP

12

C2426

C2426 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

R2408

0.001A

TPAD14-OP-GP

TP2403

83.R0304.A8F

2nd = 83.R3004.A8F

R2410

3D3V_S5

(1uFx1)

3D3V_S0

(0.1uFx2)

C2431

C2431 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

3D3V_S0

(0.1uFx1)

1D05V_VTT

(1uFx1)

DY

R2411

1D05V_VTT

(10uFx1)

R2412

1D05V_VTT

(1uFx1)

JV10-CS

Title

PCH ( POWER2)

Size Document Number Rev

Date: Sheet of

3D3V_S0

21

SVT

12

+3VS_+1.5VS_HDA_IO

G48/G58

D2402

D2402 CH751H-40PT-GP

CH751H-40PT-GP

R2407

1 2

10R2J-2-GP

C2427

C2427 SC1U10V2KX-1GP

SC1U10V2KX-1GP

1 2

R2409

0R3J-0-U-GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

5V_S5

(0.1uFx1)

5V_S0

(1uFx1)

3D3V_S5

24

SC

103Friday, February 17, 2012

5

4

3

2

1

SSID = PCH

D D

C C

B B

A A

5

AA17

AA2

AA3 AA33 AA34 AB11 AB14 AB39

AB4 AB43

AB5

AB7 AC19

AC2 AC21 AC24 AC33 AC34 AC48 AD10 AD11 AD12 AD13 AD19 AD24 AD26 AD27 AD33 AD34 AD36 AD37 AD38 AD39

AD4 AD40 AD42 AD43 AD45 AD46

AD8

AE2

AE3

AF10

AF12 AD14 AD16

AF16

AF19

AF24

AF26

AF27

AF29

AF31

AF38

AF4 AF42 AF46

AF5

AF7

AF8

AG19

AG2 AG31 AG48 AH11

AH3 AH36 AH39 AH40 AH42 AH46

AH7

AJ19 AJ21 AJ24 AJ33 AJ34

AK12

AK3

H5

PCH1H

VSS0 VSS1

VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79

PANTHER-GP-NF

8 OF 10

AK38

VSS80

AK4

VSS81

AK42

VSS82

AK46

VSS83

AK8

VSS84

AL16

VSS85

AL17

VSS86

AL19

VSS87

AL2

VSS88

AL21

VSS89

AL23

VSS90

AL26

VSS91

AL27

VSS92

AL31

VSS93

AL33

VSS94

AL34

VSS95

AL48

VSS96

AM11

VSS97

AM14

VSS98

AM36

VSS99

AM39

VSS100

AM43

VSS101

AM45

VSS102

AM46

VSS103

AM7

VSS104

AN2

VSS105

AN29

VSS106

AN3

VSS107

AN31

VSS108

AP12

VSS109

AP19

VSS110

AP28

VSS111

AP30

VSS112

AP32

VSS113

AP38

VSS114

AP4

VSS115

AP42

VSS116

AP46

VSS117

AP8

VSS118

AR2

VSS119

AR48

VSS120

AT11

VSS121

AT13

VSS122

AT18

VSS123

AT22

VSS124

AT26

VSS125

AT28

VSS126

AT30

VSS127

AT32

VSS128

AT34

VSS129

AT39

VSS130

AT42

VSS131

AT46

VSS132

AT7

VSS133

AU24

VSS134

AU30

VSS135

AV16

VSS136

AV20

VSS137

AV24

VSS138

AV30

VSS139

AV38

VSS140

AV4

VSS141

AV43

VSS142

AV8

VSS143

AW14

VSS144

AW18

VSS145

AW2

VSS146

AW22

VSS147

AW26

VSS148

AW28

VSS149

AW32

VSS150

AW34

VSS151

AW36

VSS152

AW40

VSS153

AW48

VSS154

AV11

VSS155

AY12

VSS156

AY22

VSS157

AY28

VSS158

4

3

AY4 AY42 AY46

AY8

B11 B15 B19 B23 B27 B31 B35 B39

F45 BB12 BB16 BB20 BB22 BB24 BB28 BB30 BB38

BB4 BB46 BC14 BC18

BC2 BC22 BC26 BC32 BC34 BC36 BC40 BC42 BC48 BD46

BD5 BE22 BE26 BE40

BF10 BF12 BF16 BF20 BF22 BF24 BF26 BF28

BD3

BF30 BF38 BF40

BF8 BG17 BG21 BG33 BG44

BG8 BH11 BH15 BH17 BH19

H10 BH27 BH31 BH33 BH35 BH39 BH43

BH7

D12

D16

D18

D22

D24

D26

D30

D32

D34

D38

D42

E18

E26

G18 G20 G26 G28 G36 G48

H12

H18

H22

H24

H26

H30

H32

H34

B7

D3

D8

F3

PCH1I

VSS159 VSS160 VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233 VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258

PANTHER-GP-NF

9 OF 10

VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285 VSS286 VSS287 VSS288 VSS289 VSS290 VSS291 VSS292 VSS293 VSS294 VSS295 VSS296 VSS297 VSS298 VSS299 VSS300 VSS301 VSS302 VSS303 VSS304 VSS305 VSS306 VSS307 VSS308 VSS309 VSS310 VSS311 VSS312 VSS313 VSS314 VSS315 VSS316 VSS317 VSS318 VSS319 VSS320 VSS321 VSS322 VSS323 VSS324 VSS325 VSS328 VSS329 VSS330 VSS331 VSS333 VSS334 VSS335 VSS337 VSS338 VSS340 VSS342 VSS343 VSS344 VSS345 VSS346 VSS347 VSS348 VSS349 VSS350 VSS351 VSS352

2

H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 P16 M18 M22 M24 M30 M32 M34 M38 M4 M42 M46 M8 N18 P30 N47 P11 P18 T33 P40 P43 P47 P7 R2 R48 T12 T31 T37 T4 W34 T46 T47 T8 V11 V17 V26 V27 V29 V31 V36 V39 V43 V7 W17 W19 W2 W27 W48 Y12 Y38 Y4 Y42 Y46 Y8 BG29 N24 AJ3 AD47 B43 BE10 BG41 G14 H16 T36 BG22 BG24 C22 AP13 M14 AP3 AP1 BE16 BC16 BG28 BJ28

JV10-CS

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

PCH ( VSS)

Size Document Number Rev

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

G48/G58

1

25

SC

103Friday, February 17, 2012

5

D D

C C

4

3

2

1

(Blanking)

B B

JV10-CS

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

A A

Title

Size Document Number Rev

Date: Sheet of

5

4

3

Date: Sheet of

Reserved

2

Taipei Hsien 221, Taiwan, R.O.C.

G48/G58

26

SC

103Friday, February 17, 2012

1

103Friday, February 17, 2012

5

C2709

12

SC2D2U10V3KX-1GP

1 2

R27390R0402-PAD R27390R 0402-PAD

1 2

R27380R0402-PAD R27380R 0402-PAD

C2710

12

SCD1U10V2KX-5GP

PCB_VER_AD ADT_TYPE MODEL_ID_AD VGA_CURR ENT CPU_CUR RENT_C GSEMSE_X GSENSE_Y

BT_DISABLE# 3G_EN CAP_LED

1 2

R27410R 2J-2-GPDYR27410R 2J-2-GP

DY

USB_CHG_EN WIRELESS_LED

DC_BATFU LL PCIE_WLAN_W AKE#

EC_SPI_CS#_C EC_SPI_CLK_C EC_SPI_DI_C EC_SPI_DO_C

KBC_RTCR ST#

R2716

1 2

0R2J-2-GP

1

2

BAS16-6-GP

2ND = 83.00016.F11

SSID = KBC

3D3V_AUX_KBC

RC2702

12

DY

D D

SC33P50V2JN-3GP

RSMRST#_KBC19

SIT

PCIE_WLAN_W AKE#65

R2731

C C

100KR2J-1-GP

NOTE: Locate resistors R2719 and R2722 close to the NPCE885P.

AD_OFF

B B

DY

C2701

12

SC2D2U10V3KX-1GP

VGA_CURR ENT42,92

CPU_CUR RENT42

BT_DISABLE#65

TP2732TPAD14-OP-GP T P2732T PAD14-OP-GP

TP2738TPAD14-OP-GP T P2738T PAD14-OP-GP TP2741TPAD14-OP-GP T P2741T PAD14-OP-GP

RSMRST#_KBC

12

SIV

R2770

1KR2J-1-GP

12

C2704

12

0R3J-0-U-G P

R2702

12

DY

SCD1U10V2KX-5GP

TP2713T PAD14-OP-GP TP2713TPAD14-OP-GP TP2736T PAD14-OP-GP TP2736TPAD14-OP-GP

1

1 1

C2705

SCD1U10V2KX-5GP

SPI_CS0#_R21,60,65

SPI_CLK_R21,60,65

RTC_AUX_S5

If use PSL function, please connect to 3D3V_AUX_S5 If no use PSL function, please connect 3D3V_AUX_KBC

3D3V_AUX_KBC

12

C2706

12

SCD1U10V2KX-5GP

1 2

0R2J-2-GP

1 1

SUS_PWR _ACK19

LID_CLOSE#82 PM_SLP_S4#19,46

DC_BATFU LL68

BLUETOOTH _EN63,65 S0_PWR_GO OD19,36

SPI_SO_R21,60,65

SPI_SI_R21,60,65

KBC_RTCR ST#21

PM_PWRBT N#19,97 ACPRESENT19

USB_PWR _EN61,62

SIT

C2708

C2707

12

SCD1U10V2KX-5GP

AD_IA40

C2714 SCD 1U10V2KX-5GP

1 2

DY

R2740

CAMERA_EN49

CAP_LED68

SIV

AD_OFF38

S5_ENABLE36,97

WIFI_RF_EN65

33R2J-2-GP R 273633R2J-2-G P R2736

1 2

33R2J-2-GP R 271933R2J-2-G P R2719

1 2

R27370R2J-2-GP R27370R2J-2-GP

1 2

R272233R2J-2-GP R272233R2J-2-GP

1 2

EC_SCI#22

DY

D2704

3

83.00016.K11

SIT

VBAT

U2701A

VCC119VCC246VCC376VCC488VCC5

104

VREF

97

GPIO90/AD0

98

GPIO91/AD1

99

GPIO92/AD2

100

GPIO93/AD3

108

GPIO5/AD4

96

GPIO4/AD5

95

GPIO3/AD6

94

GPIO7/AD7

101

GPIO94/DA0

105

GPIO95/DA1

106

GPIO96/DA2

107

GPIO97/DA3

79

GPIO02

6

GPIO24

109

GPIO30/F_WP#

14

GPIO34/CIRRXL

15

GPIO36

80

GPIO41/F_WP#

17

GPIO42/TCK

20

GPIO43/TMS

21

GPIO44/TDI

26

GPIO51/N2TCK

123

GPIO67N2TMS

82

GPIO75

83

GPIO76

84

GPIO77

90

F_CS0#

92

F_SCK

86

F_SDI&F_SDIO1

87

F_SDIO&F_SDIO0

91

GPIO81/F_WP#

117

GPIO20/TA2/IOX_DIN_DIO

112

GP/I/O84/IOX_SCLK/XORTR#

110

GPO82/IOX_LDSH/TEST#

NPCE885PA0DX -GP

71.00885.A0G

ECSCI#_KBC

LILI Multi GPIO setting

SML1_CLK

Q2703

A A

5

SML1_DATA

3D3V_S0

2345 1

6

DMN66D0LDW -7-GP

84.DMN66.03F

2ND = 84.2N702.A3F

4

RTC_POW ER

115

102

4

75

114

VDD

VSBY

AVCC

GND118GND245GND378GND489GND5

GND6

5

116

VBKUP

LRESET#/GPIOF7

LCLK/GPIOF5

LFRAME#/GPIOF6

LAD3/GPIOF4 LAD2/GPIOF3 LAD1/GPIOF2 LAD0/GPIOF1

SERIRQ/GPIOF0

GPIO11/CLKRUN#

GPIO65/SMI#

ECSCI#/GPIO54

GPIO10/LPCPD#

GPIO85/GA20

KBRST#/GPIO86

GPIO52/PSDAT3/RDY#

GPIO50/PSCLK3/TDO

GPIO27/PSDAT2

GPIO26/PSCLK2

GPIO35/PSDAT1

GPIO37/PSCLK1

GPIO17/SCL1/N2TCK GPIO22/SDA1/N2TMS

GPIO73/SCL2

GPIO74/SDA2

GPIO23/SCL3

GPIO31/SDA3

GPIO47/SCL4

GPIO53/SDA4

PSL_OUT_GPIO71#

PSL_IN2_GPI06# PSL_IN1_GPI70#

VCORF

AGND

103

EC_AGND

12

R2711

R2711 0R2J-2-GP

0R2J-2-GP

EC_GPIO47 High Active

PROCHOT _EC

12

R2732

100KR2J-1-GP

RN48

SMBC_THER M SMBD_THER M

RN48

4

SRN10KJ-5-G P

SMBC_THER M 28,86

SMBD_THER M 28,86

4

3D3V_S0

SC2D2U10V3KX- 1GP

12

C2703

C2702

1 0F 2

7 2 3 1 128 127 126 125 8 9 29 124 121 122

27 25 11 10 71 72

70 69 67 68 119 120 24 28

74 93 73

44

NOTE: Connect GND and AGND planes via either 0R resistor or one point layout connection.

Q2702

G

S

2N7002K-2-GP

84.2N702.J31

2nd = 84.2N702.W31

23 1

3D3V_S0

SCD1U10V2KX-5GP

PLT_RST#_EC

LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0

ECSCI#_KBC SATA_ODD_D A#

CHG_USB_D ET# GSENSE_ON# CHG_USB_OC #

RTCRST_O N PROCHOT _EC

KBC_VCORF

DY

KBC_PWR BTN_EC# AC_IN_KBC

H_PROCHO T#_EC

D

12

DY

SC220P50V2KX-3GP

C2711

BAT_SCL 39,40 BAT_SDA 39,4 0 SML1_CLK 20 SML1_DATA 20 LAN_PWR _ON 31

RTCRST_O N 21

CHG_ON# 40

12

C2712

C2712 SC1U10V3ZY-6GP

SC1U10V3ZY-6GP

3

RC2701

RC2701 SC33P50V2JN-3G P

SC33P50V2JN-3G P

DY

1 2

0R2J-2-GP

0R2J-2-GP R2735

R2735

1 2

1

TP2739

1

TP2737

1

TP2740

1 2

R2733

R2733 0R2J-2-GP

0R2J-2-GP

PCB_VER_AD

LPC_AD[0..3] 21,65

TPAD14-OP-G P

TPAD14-OP-G P TPAD14-OP-G P

TPAD14-OP-G P

<------ BATTERY / CHARGER <------PCH / eDP

H_PROCHO T# 5,42

MODEL_ID_AD

3

3D3V_AUX_KBC

SVT

12

R2724

R2724 47KR2F-GP

47KR2F-GP

BOM_CTRL

12

R2726

R2726 100KR2F-L1-GP

100KR2F-L1-GP

PLT_RST# 5,18,31,3 6,65,83,97 CLK_PCI_KBC 18

LPC_FRAME# 21,65

INT_SERIRQ 21 PM_CLKRUN # 19 PANEL_BLEN 49

SATA_ODD_D A# 18,56

H_A20GATE 22 H_RCIN# 22

BLON_OUT 49AOAC_EN65

TPDATA 69 TPCLK 69

<------ TP

3D3V_AUX_KBC

12

R2727

R2727 47KR2F-GP

47KR2F-GP

BOM_CTRL

64.47025.6DL

12

R2728

R2728 100KR2F-L1-GP

100KR2F-L1-GP

64.47025.6DL

TP2730T PAD14-OP-GP TP2730TPAD14-OP-GP

1D05V_VTT

PURE_HW _SHUTDO WN#28,36,86

FAN_TACH28

1

PM_SLP_S3#19,36,37,47 CHARGE_LED68

KBC_BEEP29

EC_L_BKLT_CT RL49

STOP_CHG#40BAT_IN#39

SIT

AD_DETECT38

FAN_PWM28

KBC_NOVO_BT N#82

ME_UNLOCK21

E51_RxD65

PCH_SUSCL K_KBC19

KBC_MUTE#29

H_PECI5,22

R2701 and C2716 Need very close to EC

64.10025.6DL

64.20025.6DL

64.33025.6DL

64.47025.6DL

PWRLED68

E51_TxD65

43R2J-GP

R2721

1 2 1 2

R2723

10KR2J-3-GP

2nd = 84.03906.F11

2

3D3V_AUX_S53D3V_AUX_KBC

U2701B

GPIO56/TA1 GPIO14/TB1 GPIO1/TB2

GPIO15/A_PWM GPIO21/B_PWM GPIO13/C_PWM GPIO32/D_PWM GPIO45/E_PWM GPIO66/G_PWM GPIO33/H_PWM GPIO40/F_PWM

GPIO46/CIRRXM/TRIST# GPIO87/CIRRXM/SIN_CR GP/I/O83/SOUT_CR/TRIST#

GPIO0/EXTCLK GPIO55/CLKOUT/IOX_DIN_DIO

VCC_POR#

PECI VTT

NPCE885PA0DX -GP

SIV

ECRST#

1 2

12

C2715

MMBT3906-4-GP

DY

FAN_TACH WIRELESS_SW #

FAN_PWM

ECRST#

R2720

R2720 0R0402-PAD

0R0402-PAD

ECRST#_B

12

84.T3906.A11

1 2

31 63 64

32

118

62 65 22 81 66 16

23 113 111

77

30

85

PECI

13

12

EC_VTT

12

C2716

C2716 SCD1U10V2KX- 5GP

SCD1U10V2KX- 5GP

B

R2725

0R0805-PAD

E

Q2701

C

EC GPIO standard PH/PL

BAT_SCL BAT_SDA

BAT_IN#

LID_CLOSE#

CHG_USB_D ET#

S5_ENABLE

KBC_MUTE#

E51_RxD

BT_DISABLE# PCIE_WLAN_W AKE#

SIT

BLUETOOTH _EN

2

4

1 2 3

1 2 1 2

1 2

DY

1 2

DY

1 2

R2715 10KR2J-3-GP

1 2

R2717 10KR2J-3-GP

1 2

DY

110706 modified

KBSOUT0/GPOB0/JENK#

KBSOUT1/GPIOB1/TCK KBSOUT2/GPIOB2/TMS

KBSOUT3/GPIOB3/TDI

KBSOUT4/GPOB4/JEN0#

KBSOUT5/GPIOB5/TDO

KBSOUT6/GPIOB6/RDY#

KBSOUT9/GPOC1/SDP_VIS# KBSOUT10&P80_CLK/GPIOC2 KBSOUT11&P80_DAT/GPIOC3

KBSOUT15/GPIO61/XOR_OUT

KBSIN0/GPIOA0/N2TCK KBSIN1/GPIOA1/N2TMS

3D3V_AUX_KBC

R2729 10KR2J-3-GPR2729 10KR 2J-3-GP

SC1U6D3V2KX-GP

RN2701

23 1

SRN4K7J-8-G P

SRN4K7J-8-G P RN2703

RN2703

4

SRN100KJ-6-G P

SRN100KJ-6-G P R2718 10KR2J-3-GPR2718 10KR 2J-3-GP

R2710 100KR2J-1-GPR2710 100KR2J-1-GP

SIV

R2713 10KR2J-3-GP

R2708 10KR2J-3-GP

DY

DY DY

DY

R2709

10KR2J-3-GP

65W_90W# High: 65W / Low 90W

2 0F 2

KBSOUT7/GPIOB7

KBSOUT8/GPIOC0

KBSOUT12/GPIO64 KBSOUT13/GPIO63 KBSOUT14/GPIO62

GPIO60/KBSOUT16 GPIO57/KBSOUT17

KBSIN2/GPIOA2 KBSIN3/GPIOA3 KBSIN4/GPIOA4 KBSIN5/GPIOA5 KBSIN6/GPIOA6 KBSIN7/GPIOA7

Prevent BIOS data loss solution

PURE_HW _SHUTDO WN#

3D3V_AUX_KBC

3D3V_S0

1

3D3V_AUX_KBC

12

R2707

R2707 100KR2F-L1-GP

100KR2F-L1-GP

65W

R2712

1 2

0R0402-PAD

KCOL[0..17] 69

3D3V_AUX_KBC

KROW[0..7] 69

DY

U2702

GND RESET#

G690L293T73UF-G P

74.00690.I7B

12

VCC

R2701

R2701 100KR2F-L1-GP

100KR2F-L1-GP

65W

90W

R2714

R2714 10KR2J-3-GP

10KR2J-3-GP

KBC_NOVO_BT N#

EC_SPI_DI_C

R2773

R2773 100KR2J-1-GP

100KR2J-1-GP

3D3V_AUX_S5

3

AC_IN 40,86

53 52 51 50 49 48 47 43 42 41 40 39 38 37 36 35 34 33

54 55 56 57 58 59 60 61

DY

3D3V_AUX_S5

12

KCOL0 KCOL1 KCOL2 KCOL3 KCOL4 KCOL5 KCOL6 KCOL7 KCOL8 KCOL9 KCOL10 KCOL11 KCOL12 KCOL13 KCOL14 KCOL15 KCOL16 KCOL17

KROW0 KROW1 KROW2 KROW3 KROW4 KROW5 KROW6 KROW7

R2705

R2705 10KR2J-3-GP

10KR2J-3-GP

ADT_TYPE

AC_IN_KBC

R2706

R2706 100KR2J-1-GP

100KR2J-1-GP

20110728 for vendor

1 2

SIT

TP2744

TP2744 TPAD34

TPAD34

1

KBC_PWR BTN#82

JV10-CS

Title

KBC Nuvoton NPCE795

Size Document Number Rev

Date: Sheet of

3D3V_AUX_S5

TP2743

TP2743 TPAD40-GP

TPAD40-GP

12

1

12

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O. C.

Taipei Hsie n 221, Taiwan, R.O. C.

G48/G58

1

R2704

R2704 10KR2J-3-GP

10KR2J-3-GP

R2703

470R2J-2-GP

R2774

R2774 100KR2J-1-GP

100KR2J-1-GP

KBC_PWR BTN_EC#

12

27

DY

12

C2717

SC220P50V2KX-3GP

SC

103Friday, Feb ruary 17, 2012

5

4

3

2

1

SSID = Thermal

D D

C C

B B

Close to PCH on top side.

SA 0905 change to 390p

3

E

C

Q6

MMBT3904WT1G-GP

2

E

DY

C

Q42

Q42 MMBT3904WT1G-GP

MMBT3904WT1G-GP

between CPU, VGA and DIMM on bottom side

12

C183

B

SC390P50V2KX-GP

12

B

C434

C434 SC390P50V2KX-GP

SC390P50V2KX-GP

DY

C388 SCD1U10V2KX-4GPC388 SCD1U10V2KX-4GP

1 2

H_THERMDA H_THERMDC REMOTE2+ REMOTE2-

Thermal sensor

3D3V_S0

12

R260

R260 68R2-GP

68R2-GP

U2801

2103_VDD

U2801

1

VDD

2

DP1

3

DN1

4

DP2/DN3

5

DN2/DP3

EMC1423-1-AIZL-TR-GP

2200p close to smsc2103 chip

THERM_SYS_SHDN#

REMOTE2-

12

C569

C569 SC2200P50V2KX-2GP

SC2200P50V2KX-2GP

REMOTE2+

3D3V_S0

12

R2803

R2803 6K8R2J-GP

6K8R2J-GP

T8= 86 degree

10

SMCLK

9

SMDATA

ALERT#

SYS_SHDN#

GND

THERM_SCI#_R

8

THERM_SYS_SHDN#

7 6

THERM_SCI#

SMBC_THERM 27,86

SMBD_THERM 27,86

1 2

R272 0R2J-2-GPR272 0R2J-2-GP

T8

1

C

B

Q9

E

MMBT3904WT1G-GP

CPU backside or inside the socket

CPU TEMP: H_THERMDA and H_THERMDC routing 10mil trace width and spacing. Locate Capacity near Thermal diode.

4 WIRE PWM Fan Control circuit

Close to connector

D2801

3D3V_S0

12

R2802

R2802 15KR2J-1-GP

15KR2J-1-GP

THERM_SCI#

CH551H-30PT-GP

83.R5003.C8F

2ND = 83.R5003.H8H

3rd = 83.5R003.08F

21

C39

SC4D7U6D3V3KX-GP

12

DY

FAN_PW M27

FAN_TACH27

FAN_TACH

SC470P50V2JN-GP

2200p close to smsc2103 chip

12

5V_S0

R426

R426 10KR2J-3-GP

10KR2J-3-GP

SIT

12

R2801

R2801 0R3J-0-U-GP

0R3J-0-U-GP

1 2

SC470P50V2JN-GP

EC2801

12

H_THERMDA

C389

C389 SC2200P50V2KX-2GP

SC2200P50V2KX-2GP

H_THERMDC

SIT

R427

0R0402-PAD

5V_S0_FAN

EC2802

FAN_PW M_CFAN_PW M

12

ACES-CON4-GP-U1

20.F0714.004

2nd = 20.D0196.104

FAN1

5 1 2

3 4

6

R2810

DY

R2811

R2811 0R2J-2-GP

0R2J-2-GP

1 1 1 1

FAN_PW M_C FAN_TACH 5V_S0_FAN

3D3V_S0

12

R2814

R2814 10KR2J-3-GP

10KR2J-3-GP

SIT

IMVP_PWRGD 36,42

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

G48/G58

28

1

SC

103Friday, February 17, 2012

TP2803TP2803 TP2802TP2802 TP2801TP2801 AFTP2804AFTP2804

3D3V_S03D3V_AUX_S5

3D3V_S0

12

DY

100KR2J-1-GP

2

DY

R2809

3

D2803

BAT54PT-GP

83.00054.T81

2ND = 83.BAT54.D81

3rd = 83.BAT54.S81

PURE_HW _SHUTDOWN#27,36,86

A A

5

4

10KR2J-3-GP

3

DY

R2812

12

DY

1

2

DY

12

C2811

SCD1U10V2KX-5GP

Q2802

D

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.W31

THERM_SYS_SHDN#

S

IMVP_PWRGD_T

G

12

0R2J-2-GP

SIV

1 2

JV10-CS

Title

THERMAL EMC1423

Size Document Number Rev

Date: Sheet of

5

4

3

2

1

AUD_5VD5V_S0AUD_3VD3D3V_S0

R2904

12

C2913

SC1U10V2KX-1GP

R2904

1 2

0R3J-0-U-GP

R2901

1 2

0R3J-0-U-GP

D D

12

C2901

SC10U6D3V3MX-GP

5V_S0

12

C2903

0R3J-0-U-GP

SC1U10V2KX-1GP

Please next to pin38

AUD_5VA

C C

AUD_5VD

SIT

R2905

1 2

0R0603-PAD

DY

20110729 for Vendor command

B B

AUD_3VD

12

C2927

SC10U6D3V3MX-GP

12

C2902

SCD1U10V2KX-4GP

12

C2911

SC10U6D3V3MX-GP

12

C2914

SC1U10V2KX-1GP

12

C2910

C2904

12

ALC_AGND ALC_AGND

C2909

12

SCD1U10V2KX-4GP

C2905

12

SCD1U10V2KX-4GP

SC4D7U6D3V3KX-GP

SCD1U10V2KX-4GP

AUD_5VD_P

AUD_SPK_L+58 AUD_SPK_L-58

AUD_SPK_R-58 AUD_SPK_R+58

COMBOJACK82

R2902

1 2

ALC_AGND

SC2D2U10V3ZY-1GP

ALC_AGND

AUD_5VA

12

C2912

SC10U6D3V3MX-GP

ALC_AGND

C2921

U2901

37

AVSS2

38

AVDD2

39

PVDD1

40

SPK-L+

41

SPK-L-

42

PVSS1

43

PVSS2

44

SPK-R-

45

SPK-R+

46

PVDD2

47

EAPD/COMBO_JACK

48

SPDIFO

49

GND

C2920

1 2

SVT

3VD_SDOUT

12

C2929

R2911

1 2

ALC_VREF

ALC_AGND

26

27

VREF

AVSS1

R2911

1 2

R2913

1 2

C2919

SC10U6D3V3MX-GP

25

AVDD1

LINE1-R

LINE1-L

MIC1-R MIC1-L

MONO-OUT

JDREF

SENSE_B

MIC2-R MIC2-L

LINE2-R

LINE2-L

SENSE_A

12

C2917

SC1U10V2KX-1GP

75R2J-1-GP

24 23 22 21 20 19 18 17 16 15 14 13

12

C2918

SCD1U10V2KX-4GP

MIC1_IN_R MIC1_IN_L

AUD_JDREF

MIC2-RR MIC2-LL

SENSE_A

HP_OUT_R 82

HP_OUT_L 82

MIC1_VREFO_L 82

MIC2-VREFO 58

ALC_AGND

Please next to pin27

C2908

12

ALC_AGND ALC_AGND

1 2 1 2

R2918

1 2

20KR2F-L-GP

C2925 SC1U10V2KX-1GPC2925 SC1U10V2KX-1GP

1 2

C2926

1 2

12

SC4D7U6D3V3KX-GP

C2923SC2D2U6D3V2MX-GP C2923SC2D2U6D3V2MX-GP C2924SC2D2U6D3V2MX-GP C2924SC2D2U6D3V2MX-GP

Placement near Audio Codec

SC1U10V2KX-1GP

R2916 39K2R2F-L-GPR2916 39K2R2F-L-GP

C2907

SCD1U10V2KX-4GP

12

AUD_5VA

MIC1_IN_RL 82

ALC_AGND

MIC2-RL_C 58

HP_OUT_R_AUD

HP_OUT_L_AUD

AUD_LDO_CAP

CPVEE

CBN

1 2

CBP

28

29

30

31

32

33

34

35

36

CBP

CBN

CPVEE

HP-OUT-L

HP-OUT-R

LDO-CAP

MIC2-VREFO

MIC1-VREFO-L

MIC1-VREFO-R

HP_DET#

SC100P50V2JN-3GP

HDA_CODEC_SDOUT21

C2929

SC33P50V2JN-3GP

HDA_CODEC_SYNC21

HP_DET# 82

C2928

DY

1 2

12

Q2903

D

2N7002K-2-GP

84.2N702.J31

84.2N702.J31 2ND = 84.2N702.W31

2ND = 84.2N702.W31

R2929

0R2J-2-GP

3VD_SYNC_1

Q2902

D

2N7002K-2-GP

1 2

R2928

DY

AUD_3VD

DY

G

S

AUD_3VD

G

S

84.2N702.J31

2nd = 84.2N702.W31

0R2J-2-GP

12

R2927

R2927 33KR2F-GP

33KR2F-GP

DY

AUD_SDATA_OUT

12

R2926

R2926 33KR2F-GP

33KR2F-GP

AUD_SYNC

DVDD11GPIO0/DMIC-DATA2GPIO1/DMIC-CLK3PD#4SDATA-OUT5BIT-CLK6DVSS27SDATA-IN8DVDD-IO9SYNC10RESET#11PCBEEP

ALC269Q-VC-GR-GP

12

Place next to pin 1

SIV

R2917

22R2J-2-GP

1 2

84.2N702.031

2nd = 84.2N702.W31

A A

KBC_MUTE#27

2nd = 84.2N702.W31

HDA_CODEC_RST#21

5

22R2J-2-GP

3D3V_S5

G

SIT

Q50

DY

DS

2N7002K-1-GP

1 2

R2907 0R2J-2-GP

DY

1 2

R2908 0R2J-2-GP

DY

AUD_PD#_2

AUD_PD#_1

ASW_GPIO082

TP2902TP2902

D7

1

2

1

BAW56PT-U1-GP

DY

AUD_SD#

3

4

AUD_GPIO1

AUD_3VD

12

SIV

R2906

R2906 1KR2J-1-GP

1KR2J-1-GP

DY

AUD_SDATA_OUT

AUD_SDATAIN

BITCLK_1

12

C2922

C2922 SC22P50V2JN-4GP

SC22P50V2JN-4GP

DY

AUD_SYNC

R2910 22R2J-2-GPR2910 22R2J-2-GP

R2909 22R2J-2-GPR2909 22R2J-2-GP

3

AUD_PC_BEEP KBC_BEEP_R

SCD1U10V2KX-5GP

HDA_CODEC_RST# 21

12

SCD1U10V2KX-5GP

HDA_SDIN0 21 HDA_CODEC_BITCLK 21

C2915

4K7R2J-2-GP

R2915

12

SC100P50V2JN-3GP

2

12

C2916

R2914

1 2

1KR2J-1-GP

R2912

1 2

1KR2J-1-GP

JV10-CS

Title

Size Document Number Rev

Date: Sheet of

HDA_SPKR 21

KBC_BEEP 27

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

AudioCodec_ALC269

G48/G58

1

29

SC

103Friday, February 17, 2012

5

D D

C C

4

3

2

1

(Blanking)

B B

JV10-CS

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

A A

Title

Size Document Number Rev

Date: Sheet of

5

4

3

Date: Sheet of

Audio_AMP

2

Taipei Hsien 221, Taiwan, R.O.C.

G48/G58

30

SC

103Friday, February 17, 2012

1

103Friday, February 17, 2012