A
B
C
D
E
EGRET Block Diagram
200-PIN DDR SODIMM
CLK GEN
ICS
4 4
PCMCIA
SLOT
Support
TypeII
27
PWR SW
TPS2224AP
27
PCMCIA I/F
1394
3 3
Conn
27
Mini-PCI
ICS950405
TI
PCI 7420
2* Slot Cardbus
1* 1394
25,26
3
PCI Bus / 33MHz
802.11a/b/g
30
RJ45
29
TXFM
TXFM
2 2
1000Mb
29
10/100Mb
29
PCI GIGA LAN
Realtek
RTL8110SBL
LAN PHY
VIA VT6103L
28
29
AMD CPU
Claw Hammer K8
HyperTransport
6.4GB/S 16b/8b
VIA
K8N800
AGTL+ CPU I/F + UMA
8 bit V-LINK
66MHZ 8x/4x/2x
VIA
VT8235CE
ACPI 2.0
PCI
MII
ATA 133
PIDE
HDD
23
SIDE
DVD/
CD-RW
23
4,5,6,7
11,12,13
6xUSB 2.0
6-CH
AC97 2.2
LPC I/F
19,20,21
AGP 8x
NS SIO
PC87392
port
DDR 333/400
LVDS Transmitter
USB x 4
AC LINK
MODEM
MDC Card
FIRParallel
TFDU6101E
37
TV Encoder
VIA VT1623M
VIA VT1631
Graphic CONN.
AGP 8X
24
RJ11
CONN
29
LPC Bus / 33MHz
Thermal
& Fan
G791
36
36
14
15
16
AC'97 CODEC
VT1612A
OP AMP
APA2020
22
DDR x2
Touch
Pad
8,9,10
SVIDEO/COMP
LVDS
RGB CRT
31
3224
KBC
M38859
Int.
KB
34 34
TVOUT
LCD
CRT
Line In
MIC In
Line Out
(SPDIF)
Int. SPKR
SST-49LF040
32
32
32
FWH
17
18
17
PCB Layer Stackup
L1: Signal 1
L2: GND
L3: Signal 2
L4: Signal 3
L5: VCC
L6: Signal 4
Battery Charger
MAX1645BEEI
INPUTS
AD+
BAT+
OUTPUTS
DCBATOUT
SYSTEM DC/DC
MAX1999
INPUT
DCBATOUT
OUTPUT
5V_S5 ,
3D3V_S5
SYSTEM DC/DC
INPUT
DCBATOUT
2D5V_S3
TPS5110
OUTPUT
2D5V_S3
1D5V_S0
CPU V_CORE
ISL6559CR
INPUT
DCBATOUT
SYSTEM POWER
FDD6035AL/FDS9412-U
FDS9412-U/SI4892DY/LP2951ACM
APL5508-18VC/APL5308-25AC
INPUT
5V_S3
3D3V_S5
3533
3D3V_S3
3D3V_S0
DCBATOUT
OUTPUT
VCC_CORE_S0
OUTPUT
2D5V_S5
5V_S0
3D3V_S3
3D3V_S0
3D3V_LAN_S3
1D8V_S0
+5V_AUX_S5
+5V_UP_S5
2D5V_S0
46
43
44
41,42
44,45
1 1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size Document Number Rev
A3
A
B
C
D
Date: Sheet of
Block Diagram
EGRET
E
150Friday, July 23 , 2004
SC
EGRET REVISION HISTORY
PCI RESOURCE TABLE
VGA & AGP
PCI7420-CardBus A
PCI7420-CardBus B
PCI7420-IEEE1394A
Mini-PCI
Giga LAN
RTL8110SBL
IDSEL
PCI IRQDEVICE REQ# / GNT#
P_INTA#
AD22
P_INTB#
P_REQ#1/P_GNT#1
AD22 P_INTC# P_REQ#1/P_GNT#1
P_INTD#
P_REQ#1/P_GNT#1AD22
AD21 P_INTF# P_REQ#0/P_GNT#0
AD23 P_INTG#
P_REQ#2/P_GNT#2
VREF_DDR_MEM5,8
1D2V_HT0A_S04,11,13,39,45
1D2V_HT0B_S04,6
1D25V_S35,6,7,9,10,39,45
1D5V_S012,13,14,15,16,44,50
2D5V_S06,12,14,15,1 6,19,20,21,38,39,50
2D5V_S35,6,7,8,10,38,39,44,45,50
2D5V_S520,21,39
3D3V_S03,6,8,11,12,13,14,15,16,17,18,19,20,21,24,25,26,27,28,30,31,32,33,34,35,36,38,41,47,49,50
3D3V_S318,33,34,38,50
3D3V_S513,18,19,20 ,2 1 ,22,24,28,29,33,38,43,49,50
5V_S016,17,18,19,20,21,22,23,24,27,30,31,32,33,34,37,38,39,41,42,47,48,49,50
5V_S521,38,39,43,44,45,46,48,49
+5V_AUX_S519,21,22,34,38,39,45,46,49
+5V_UP_S518,48,50
DCBATOUT16,18,38,41,43,44,45,46,47,50
VCC_CORE_S07,41,42
AD+46,47
BT+46,47
DCBATOUT_ISL41,42
3D3V_LAN_S524,28,29
VCC_ASKT_S025,27
VPP_ASKT_S027
VREF_DDR_MEM
1D2V_HT0A_S0
1D2V_HT0B_S0
1D25V_S3
1D5V_S0
2D5V_S0
2D5V_S3
2D5V_S5
3D3V_S0
3D3V_S3
3D3V_S5
5V_S0
5V_S5
+5V_AUX_S5
+5V_UP_S5
DCBATOUT
VCC_CORE_S0
AD+
BT+
DCBATOUT_ISL
3D3V_LAN_S5
VCC_ASKT_S0
VPP_ASKT_S0
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size Document Number Rev
Date: Sheet
REVISION HISTORY
A3
EGRET
of
250Friday, July 23 , 2004
SC
A
B
C
D
E
3D3V_S0
L9 BLM21A121S
1 2
4 4
SC10U10V6ZY-U
12
12
C156
12
C593
SCD1U
C599
SCD1U
SC
C154
By KDS suggested change
From 78.33034.1B1
To 78.12034.1B1
3 3
GUICLK Damping only
Stuff for K8N800 UMA
1 2
SC12P
C155
1 2
SC12P
CPUCLK6
CPUCLK#6
APICCLKSB21
SIO_OSC20
CLK14_SIO36
SMBC_SB8,21
SMBD_SB8,21
CLK48_USB19
GUICLK12
3D3V_CLK_S0
3D3V_CLK_S0
12
C592
SCD1U
12
C595
SCD1U
12
X3
XTAL-14D318M-2
R86 DY-22R3
R88 22R3
R109 22R3
R110 22R3
R111 22R3
12
12
C594
SCD1U
12
12
C596
SCD1U
XI_CLK
XO_CLK
R108 15R3F
1 2
R112 15R3F
1 2
1 2
1 2
1 2
1 2
1 2
12
C645
SCD1U
12
C597
SCD1U
CLK_PD#
CPUCLK#_CY
ZZ.22034.151
C646
SCD1U
C598
SCD1U
FS0
FS1
FS2
FS3
FS3
FS0~FS2 Hav e internal Pull-up resistor
FS3 Have internal Pull-down resistor
U15
2
VDD
9
VDD
16
VDD
19
VDD
29
VDD
35
VDD
38
VDD
46
VDD
43
32
3
4
41
37
40
36
1
48
45
31
25
26
VDDA
VDDF
XIN
XOUT
CPUT0
CPUT1
CPUC0
CPUC1
FS0/REF0
FS1/REF1
FS2/REF2
USB/FS3
SCLK
SDATA
ICS950405
Library Issue
Pin32: PD#
HT66_0/PCIHT66SEL0#
PCI33_8_HT66_1/PCIHT66SEL1#
PCI33_0
PCI33_1
PCI33_2
PCI33_3
PCI33_4
PCI33_5
PCI33_6
PCI33_7
PCI33_9_HT66_2
PCI33_11_HT66_3
PCI33_10
SRESET#/PD#
24_48MHZ/SEL#
VSSF
VSSA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
13
14
17
18
21
22
23
24
6
7
8
11
12
44
28
33
42
5
10
15
20
27
30
34
39
47
PCICLK0
PCICLK1
PCICLK2
PCICLK4
PCICLK5
PCICLK6
PCICLK7
CLK33_HT66SEL#0
CLK33_HT66SEL#1
PCI33_HT66_2
PCI33_HT66_3
CLK_24_48SEL#CPUCLK_CY
SB
R105 22R3
1 2
R107 22R3
1 2
R126
1 2
22R3
RN13
4 5
3
SRN22-1
2
1
R101 22R3
1 2
R106 22R3
1 2
R102 22R3
1 2
R127 22R3
1 2
12
R128
10KR3
63.22034.151
6
7
8
CLK33_CARDBUS 25
CLK33_LAN 28
CLK33_MINI 30
CLK33_KBC 33
CLK33_SIO 36
CLK33_LPCROM 35
CLK33_SB 21
CLK66_NB 12
CLK66_VGA 16
CLK66_VCLK 21
CLK48_CARDBUS 25
3D3V_CLK_S0
R85 10KR3
1 2
R87 10KR3
1 2
R114 10KR3
1 2
CLK33_LAN Damping only
Stuff for RTL8110SB
CLK66_VGA Damping only
Stuff for K8N800 Discrete
FS0
FS1
FS2
3D3V_S06,8,11,12,13,14,15,16,17,18,19,20,21,24,25,26,27,28,30,31,32,33,34,35,36,38,41,47,49,50
3D3V_S0
Clock Generator OutputInput Configuration
FS1
2 2
FS2 FS0FS3
0
0
001
0
0
011
0
0
010
101
0
001
*
1 1
1
1
1
1
1
1
1
A
0
001
0
0
10
0
1
00
1
1
1111
00
010
011
11
10
11
10
0
CPU (MHz)
100.90
133.90
168.00
202.00
100.20
133.50
166.70
200.40
150.00
180.00
210.00
240.00
270.00
233.33
266.67
300.00
PCI33_HT66 (MHz)
PCI33 (MHz)
67.27 33.63
66.95
67.20
67.33
66.80
66.75
66.68
66.80
33.48
33.60
33.67
33.40
33.38
33.34
33.40
60.00 30.00
60.00
70.00
60.00
67.50
66.67
66.67
75.00
30.00
35.00
30.00
33.75
33.33
33.33
37.50
B
All output Tri-state
Normal Hammer operation
C
24_48 SEL# 24_48MHz
0
*
1
PCIHT66 SEL [1:0]#
SEL1SEL0
0
0
*
10
11
48MHz
24MHz
0
1
PCI33_HT66[3:0]
PIN7
PIN8 PIN11
HT66 HT66
HT66HT66
PCI33 PCI33HT66
PCI33
HT66
PCI33PCI33PCI33
D
3D3V_CLK_S0
CLK_PD#
CLK33_HT66SEL#1
CLK33_HT66SEL#0
Title
Size Document Number Rev
A3
Date: Sheet
R113 10KR3
1 2
1 2
R103 10KR3
1 2
R104 10KR3
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
CLKGEN_ICS 9 50405
EGRET
350Friday, July 23 , 2004
E
of
SC
A
B
C
D
E
1D2V_HT0A_S0
12
C105
SCD22U16V3ZY
4 4
3 3
12
C107
SCD22U16V3ZY
NB0CADOUT[15..0]11
NB0CADOUTJ[15..0]11
12
C106
SCD22U16V3ZY
Used SideB Power Plane
2 2
NB0HTTCLKOUT111
NB0HTTCLKOUTJ 111
1D2V_HT0B_S0
NB0HTTCLKOUT011
NB0HTTCLKOUTJ 011
R289 49D9R3F
1 2
R290 49D9R3F
1 2
NB0HTTCTLOUT11
NB0HTTCTLOUTJ11
12
C109
SCD22U16V3ZY
HTT for CPU sideA
Transmit power
and NB sideA Receive
power
1D2V_HT0A_S0
NB0CADOUT15
NB0CADOUTJ15
NB0CADOUT14
NB0CADOUTJ14
NB0CADOUT13
NB0CADOUTJ13
NB0CADOUT12
NB0CADOUTJ12
NB0CADOUT11
NB0CADOUTJ11
NB0CADOUT10
NB0CADOUTJ10
NB0CADOUT9
NB0CADOUTJ9
NB0CADOUT8
NB0CADOUTJ8
NB0CADOUT7
NB0CADOUTJ7
NB0CADOUT6
NB0CADOUTJ6
NB0CADOUT5
NB0CADOUTJ5
NB0CADOUT4
NB0CADOUTJ4
NB0CADOUT3
NB0CADOUTJ3
NB0CADOUT2
NB0CADOUTJ2
NB0CADOUT1
NB0CADOUTJ1
NB0CADOUT0
NB0CADOUTJ0
NB0HTTCLKOUT1
NB0HTTCLKOUTJ1
NB0HTTCLKOUT0
NB0HTTCLKOUTJ0
CPUHTTCTLIN1
CPUHTTCTLINJ1
NB0HTTCTLOUT
NB0HTTCTLOUTJ
D29
D27
D25
C28
C26
B29
B27
T25
R25
U27
U26
V25
U25
W27
W26
AA27
AA26
AB25
AA25
AC27
AC26
AD25
AC25
T27
T28
V29
U29
V27
V28
Y29
W29
AB29
AA29
AB27
AB28
AD29
AC29
AD27
AD28
Y25
W25
Y27
Y28
R27
R26
T29
R29
U11A
VLDT0_A
VLDT0_A
VLDT0_A
VLDT0_A
VLDT0_A
VLDT0_A
VLDT0_A
L0_CADIN_H15
L0_CADIN_L15
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H0
L0_CADIN_L0
L0_CLKIN_H1
L0_CLKIN_L1
L0_CLKIN_H0
L0_CLKIN_L0
L0_CTLIN_H1
L0_CTLIN_L1
L0_CTLIN_H0
L0_CTLIN_L0
VLDT0_B
VLDT0_B
VLDT0_B
VLDT0_B
VLDT0_B
VLDT0_B
VLDT0_B
L0_CADOUT_H15
L0_CADOUT_L15
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H0
L0_CADOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
AH29
AH27
AG28
AG26
AF29
AE28
AF25
N26
N27
L25
M25
L26
L27
J25
K25
G25
H25
G26
G27
E25
F25
E26
E27
N29
P29
M28
M27
L29
M29
K28
K27
H28
H27
G29
H29
F28
F27
E29
F29
J26
J27
J29
K29
N25
P25
P28
P27
HTT for CPU sideB
Receive power
and NB sideA
Transmit power
1D2V_HT0B_S0
CPUCADOUT15
CPUCADOUTJ15
CPUCADOUT14
CPUCADOUTJ14
CPUCADOUT13
CPUCADOUTJ13
CPUCADOUT12
CPUCADOUTJ12
CPUCADOUT11
CPUCADOUTJ11
CPUCADOUT10
CPUCADOUTJ10
CPUCADOUT9
CPUCADOUTJ9
CPUCADOUT8
CPUCADOUTJ8
CPUCADOUT7
CPUCADOUTJ7
CPUCADOUT6
CPUCADOUTJ6
CPUCADOUT5
CPUCADOUTJ5
CPUCADOUT4
CPUCADOUTJ4
CPUCADOUT3
CPUCADOUTJ3
CPUCADOUT2
CPUCADOUTJ2
CPUCADOUT1
CPUCADOUTJ1
CPUCADOUT0
CPUCADOUTJ0
CPUHTTCLKOUT1
CPUHTTCLKOUTJ1
CPUHTTCLKOUT0
CPUHTTCLKOUTJ0
CPUHTTCTLOUT0
CPUHTTCTLOUTJ0
LAYOUT: Place bypass cap on topside of board near
C469
SC4D7U10V5ZY
HTT power pins that are not connected directly to
downstream HTT device, but connected internally to
other HTT power pins.
CPUCADOUT[15..0] 11
CPUCADOUTJ[15..0] 11
Used SideA Power Plane
CPUHTTCLKOUT1 11
CPUHTTCLKOUTJ1 11
CPUHTTCLKOUT0 11
CPUHTTCLKOUTJ0 11
CPUHTTCTLOUT0 11
CPUHTTCTLOUTJ0 11
1D2V_HT0A_S011,13,39,45
1D2V_HT0B_S06
1D2V_HT0A_S0
1D2V_HT0B_S0
BGA754-SKT-U
62.10030.041
By ME requset U11 P/N:
1 1
A
B
Main 62.10030.041
Second 62.10053.191
Third 62.10053.201
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size Document Number Rev
A3
C
D
Date: Sheet
CPU(1/4)_HyperTransport I/F
EGRET
450Friday, July 23 , 2004
E
of
SC
A
B
C
D
E
VREF_DDR_MEM8
2D5V_S36,7,8,10,38,39,44,45,50
U11B
TP42
4 4
VREF_DDR_MEM
2D5V_S3
VREF_DDR_CLAW
R319 34D8R3F-1
1 2
R318 34D8R3F-1
1 2
AMD suggested change
to 34.8 ohm
M_DATA[63..0]9
NOTE: Test wi th p assive probes only.
2D5V_S3
3 3
NOTE: Install to bypass op-amp
R207
100R3
R206
100R3
12
C302
SCD1U
12
12
12
C300
SCD1U
VREF_DDR_MEM
12
C332
SC1000P50V3KX
78.10224.2B1
LAYOUT: Lo cate close to DI MMs.
NOTE: Remove to bypass op-amp
2 2
VREF_DDR_CLAW
2D5V_S3
12
12
1 1
12
R328
100R3
R329
100R3
C577
SCD1U
12
C579
SCD1U
VREF_DDR_CLAW
LAYOUT: Locate close to CPU .
A
12
C580
SC1000P50V3KX
78.10224.2B1
M_ADM[7..0]9
M_DQS[7..0]9
B
DDRVTT_SENSE
MEMZN
MEMZP
M_DATA63
M_DATA62
M_DATA61
M_DATA60
M_DATA59
M_DATA58
M_DATA57
M_DATA56
M_DATA55
M_DATA54
M_DATA53
M_DATA52
M_DATA51
M_DATA50
M_DATA49
M_DATA48
M_DATA47
M_DATA46
M_DATA45
M_DATA44
M_DATA43
M_DATA42
M_DATA41
M_DATA40
M_DATA39
M_DATA38
M_DATA37
M_DATA36
M_DATA35
M_DATA34
M_DATA33
M_DATA32
M_DATA31
M_DATA30
M_DATA29
M_DATA28
M_DATA27
M_DATA26
M_DATA25
M_DATA24
M_DATA23
M_DATA22
M_DATA21
M_DATA20
M_DATA19
M_DATA18
M_DATA17
M_DATA16
M_DATA15
M_DATA14
M_DATA13
M_DATA12
M_DATA11
M_DATA10
M_DATA9
M_DATA8
M_DATA7
M_DATA6
M_DATA5
M_DATA4
M_DATA3
M_DATA2
M_DATA1
M_DATA0
M_ADM8
M_ADM7
M_ADM6
M_ADM5
M_ADM4
M_ADM3
M_ADM2
M_ADM1
M_ADM0
M_DQS8
M_DQS7
M_DQS6
M_DQS5
M_DQS4
M_DQS3
M_DQS2
M_DQS1
M_DQS0
AE13
AG12
D14
C14
A16
B15
A12
B11
A17
A15
C13
A11
A10
C11
AC1
AC3
AC2
AD1
AE1
AE3
AG3
AJ4
AE2
AF1
AH3
AJ3
AJ5
AJ6
AJ7
AH9
AG5
AH5
AJ9
AJ10
AH11
AJ11
AH15
AJ15
AG11
AJ12
AJ14
AJ16
A13
AA1
AG1
AH7
AH13
A14
AB1
AJ2
AJ8
AJ13
B9
C7
A6
A9
A5
B5
C5
A4
E2
E1
A3
B3
E3
F1
G2
G1
L3
L1
G3
J2
L2
M1
W1
W3
W2
Y1
R1
A7
C2
H1
T1
A8
D1
J1
VTT_SENSE
MEMVREF1
MEMZN
MEMZP
MEMDATA63
MEMDATA62
MEMDATA61
MEMDATA60
MEMDATA59
MEMDATA58
MEMDATA57
MEMDATA56
MEMDATA55
MEMDATA54
MEMDATA53
MEMDATA52
MEMDATA51
MEMDATA50
MEMDATA49
MEMDATA48
MEMDATA47
MEMDATA46
MEMDATA45
MEMDATA44
MEMDATA43
MEMDATA42
MEMDATA41
MEMDATA40
MEMDATA39
MEMDATA38
MEMDATA37
MEMDATA36
MEMDATA35
MEMDATA34
MEMDATA33
MEMDATA32
MEMDATA31
MEMDATA30
MEMDATA29
MEMDATA28
MEMDATA27
MEMDATA26
MEMDATA25
MEMDATA24
MEMDATA23
MEMDATA22
MEMDATA21
MEMDATA20
MEMDATA19
MEMDATA18
MEMDATA17
MEMDATA16
MEMDATA15
MEMDATA14
MEMDATA13
MEMDATA12
MEMDATA11
MEMDATA10
MEMDATA9
MEMDATA8
MEMDATA7
MEMDATA6
MEMDATA5
MEMDATA4
MEMDATA3
MEMDATA2
MEMDATA1
MEMDATA0
MEMDQS17
MEMDQS16
MEMDQS15
MEMDQS14
MEMDQS13
MEMDQS12
MEMDQS11
MEMDQS10
MEMDQS9
MEMDQS8
MEMDQS7
MEMDQS6
MEMDQS5
MEMDQS4
MEMDQS3
MEMDQS2
MEMDQS1
MEMDQS0
D17
VTT_A
A18
VTT_A
B17
VTT_A
C17
VTT_A
AF16
VTT_B
AG16
VTT_B
AH16
VTT_B
AJ17
VTT_B
MEMCKEA
MEMCKEB
NC_E13
NC_C12
NC_E14
NC_D12
AG10
AE8
AE7
D10
C10
E12
E11
AF8
AG8
AF10
AE10
V3
V4
K5
K4
R5
P5
P3
P4
D8
C8
E8
E7
D6
E6
C4
E5
H5
D4
G5
K3
H3
E13
C12
E10
AE6
AF3
M5
AE5
AB5
AD3
Y5
AB4
Y3
V5
T5
T3
N5
H4
F5
F4
L5
J5
E14
D12
E9
AF6
AF4
M4
AD5
AC5
AD4
AA5
AB3
Y4
W5
U5
T4
M3
N3
N1
U3
V1
N2
P1
U1
U2
BGA754-SKT-U
MEMRESET_L
MEMCLK_H7
MEMCLK_L7
MEMCLK_H6
MEMCLK_L6
MEMCLK_H5
MEMCLK_L5
MEMCLK_H4
MEMCLK_L4
MEMCLK_H3
MEMCLK_L3
MEMCLK_H2
MEMCLK_L2
MEMCLK_H1
MEMCLK_L1
MEMCLK_H0
MEMCLK_L0
MEMCS_L7
MEMCS_L6
MEMCS_L5
MEMCS_L4
MEMCS_L3
MEMCS_L2
MEMCS_L1
MEMCS_L0
MEMRASA_L
MEMCASA_L
MEMWEA_L
MEMBANKA1
MEMBANKA0
MEMADDA13
MEMADDA12
MEMADDA11
MEMADDA10
MEMADDA9
MEMADDA8
MEMADDA7
MEMADDA6
MEMADDA5
MEMADDA4
MEMADDA3
MEMADDA2
MEMADDA1
MEMADDA0
MEMRASB_L
MEMCASB_L
MEMWEB_L
MEMBANKB1
MEMBANKB0
MEMADDB13
MEMADDB12
MEMADDB11
MEMADDB10
MEMADDB9
MEMADDB8
MEMADDB7
MEMADDB6
MEMADDB5
MEMADDB4
MEMADDB3
MEMADDB2
MEMADDB1
MEMADDB0
MEMCHECK7
MEMCHECK6
MEMCHECK5
MEMCHECK4
MEMCHECK3
MEMCHECK2
MEMCHECK1
MEMCHECK0
C
1D25V_S3
MEMRESET#
M_CKE#0
M_CKE#1
M_CLK7
M_CLK#7
M_CLK6
M_CLK#6
M_CLK5
M_CLK#5
M_CLK4
M_CLK#4
M_CLK1
M_CLK#1
M_CLK0
M_CLK#0
M_CS#7
M_CS#6
M_CS#5
M_CS#4
M_CS#3
M_CS#2
M_CS#1
M_CS#0
M_ARAS#
M_ACAS#
M_AWE#
M_ABS#1
M_ABS#0
RSVD_M_AA15
RSVD_M_AA14
M_AA13
M_AA12
M_AA11
M_AA10
M_AA9
M_AA8
M_AA7
M_AA6
M_AA5
M_AA4
M_AA3
M_AA2
M_AA1
M_AA0
M_BRAS#
M_BCAS#
M_BWE#
M_BBS#1
M_BBS#0
RSVD_M_BA15
RSVD_M_BA14
M_BA13
M_BA12
M_BA11
M_BA10
M_BA9
M_BA8
M_BA7
M_BA6
M_BA5
M_BA4
M_BA3
M_BA2
M_BA1
M_BA0
CB7
CB6
CB5
CB4
CB3
CB2
CB1
CB0
12
C578
SCD1U
For REGISTED DIMM Only
UNBUFFER DIMM NC
12
C177
SC1000P50V3KX
78.10224.2B1
M_CKE#0 8,9
M_CKE#1 8,9
M_CLK7 8,9
M_CLK#7 8,9
M_CLK6 8,9
M_CLK#6 8,9
M_CLK5 8,9
M_CLK#5 8,9
M_CLK4 8,9
M_CLK#4 8,9
M_ARAS# 8,9
M_ACAS# 8,9
M_AWE# 8,9
M_ABS#1 8,9
M_ABS#0 8,9
M_BRAS# 8,9
M_BCAS# 8,9
M_BWE# 8,9
M_BBS#1 8,9
M_BBS#0 8,9
D
M_CLK#1
M_CLK#0
M_CLK1
M_CLK0
M_CS#[3..0] 8,9
M_AA[13..0] 8,9
AMD suggested M_AA13
connect to DIMM pin123
M_BA[13..0] 8,9
AMD suggested M_BA13
connect to DIMM pin123
TP53
TP5
TP54
TP11
TP6
TP8
TP10
TP12
Title
Size Document Number Rev
A3
Date: Sheet of
1D25V_S36,7,9,10,39,45
2D5V_S3
1
8
2
7
3
6
45
RN95
SRN10K-2
MEMZN
MEMZP
M_DQS8
M_ADM8
MEMRESET#
M_CS#7
M_CS#6
M_CS#5
M_CS#4
RSVD_M_AA15
RSVD_M_AA14
RSVD_M_BA15
RSVD_M_BA14
NOT SUPPORT ECC CHECK
AMD suggested remove
PULL-HI resistor.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
CPU(2/4)_DDR
EGRET
E
550Friday, July 23 , 2004
VREF_DDR_MEM
2D5V_S3
1D25V_S3
TP35
TP34
TP9
TP7
TP51
TP48
TP47
TP50
TP49
TP40
TP37
TP39
TP38
SC
A
2D5V_VDDA_S0
2D5V_S0
4 4
12
2D5V_CPUA_S0
SC
R499
1 2
GAP-CLOSE-PWR
C472
SC10U10V6ZY-U
R500
1 2
DY-0R3-U
ZZ.R0004.151
2D5V_CPUR_S0
L23 0R5J
1 2
12
TC6
ST100U4VBM-1
80.10716.321
SB
KEMET,NT:5.7, B2 size
ST100U4VBM-1 (80.10716.321)
3 3
Iripple=1.1A,ESR=70mohm
SANYO, NT$:6.1
Iripple=1.1A,ESR=70mohm
3.5/2.8/2.0
77.21071.031
HDT Connectors
2D5V_S0
2 2
1 1
12
C437
SCD1U
DBREQJ
DBRDY
TCK
TMS
TDI
TRST_L
TDO
R277 680R3
2D5V_S3
CHANGE FROM 1KR3 TO 680R2 FOR AMD
CHECK LIST
NC_AG17
NC_AJ18
NC_D18
NC_B19
NC_C19
NC_D20
NC_C21
1 2
RN88 SRN680-U
1
2
3
4 5
RN9 SRN680-U
1
2
3
4 5
123
SB
678
RN76
SRN680-U
4 5
8
7
6
8
7
6
A
Need to check which should be used
Change
L270H
2D5V_VDDA_S0
LAYOUT: Rou te tr ace 50 mils wide and
500 to 750 mils long between these
caps.
C470
SC4D7U10V5ZY
78.47593.411
1D2V_HT0B_S0
SC
Add HDT connector
for AMD suggested
2D5V_S0
12
12
R276
R275
680R3
680R3
SB
R292 44D2R3F
1 2
R291 44D2R3F
1 2
AMD suggest voltege
from 2D5V_S0 to 2D5V_S3
differentially im pedance 100
12
C438
DY-SCD1U
1
3
5
7
9
11
13
15
17
19
21
23
DY-SMC-CONN26A-FP
ZZ.F0357.025
B
3D3V_S0
12
C442
DY-SC1U10V3ZY
LAYOUT: Route VDDA trace approx.
50 mils wid e (use 2x25 mil traces to
exit ball field) and 500 mils long.
12
C499
SCD22U16V3ZY
12
1 2
1 2
CPUCLK#3
R308 680R3
1 2
R309 680R3
1 2
C467
SC1000P50V3KX
78.10224.2B1
CPUCLK3
2D5V_S0
HTT_CPU_STOP#21
VDDIOSENSE44
1 2
C500 SC3900P50V3KX
C501 SC3900P50V3KX
1 2
1D25V_S3
2D5V_S0
CN5
64.44R25.551
2D5V_S3
2
4
6
8
10
12
14
16
18
20
22
24
26
12
C471
SC3300P50V3KX
12
C468
SC1000P50V3KX
78.10224.2B1
R310 820R3
R311 820R3
RST_CPU#
ALL_PWROK
Validation Test Points
LAYOUT: Place close to the CPU.
NC_C15
NC_AE23
NC_AF23
NC_AF22
NC_AF21
B
TP36
TP24
TP25
TP26
TP27
RST_CPU#
CLKIN
CLKIN#
CORE_SENSE
VDDIOFB
VDDIOFBJ
VDDIOSENSE
NC_AE24
NC_AF24
C
Iomax=120mA
U42
1
SHDN#
2
GND
3
IN
DY-G913C-U
RST_CPU#19
ALL_PWROK12,19,21,39
COREFB41
COREFB#41
R80 680R3
1 2
R79 680R3
1 2
123
C
ALL_PWROK
L0_REF1
L0_REF0
COREFB
COREFB#
CORE_SENSE
VDDIOFB
VDDIOFBJ
VDDIOSENSE
CLKIN
12
R307
169R3F
CLKIN#
NC_AJ23
NC_AH23
NC_AE24
NC_AF24
DBRDY
NC_C15
TMS
TCK
TRST_L
TDI
NC_AE23
NC_AF23
NC_AF22
NC_AF21
678
4 5
TP30
TP32
TP33
TP28
TP43
TP44
TP41
TP29
TP31
SET
OUT
RN80
SRN680-U
2D5V_CPUA_S0
2D5V_VDDA_VREF
5
4
NC_C18
NC_A19
12
C441
DY-SC22P
12
C440
DY-SC1U10V3ZY
U11C
AH25
VDDA1
AJ25
VDDA2
AF20
RESET_L
AE18
PWROK
AJ27
LDTSTOP_L
AF27
L0_REF1
AE26
L0_REF0
A23
COREFB_H
A24
COREFB_L
B23
CORE_SENSE
AE12
VDDIOFB_H
AF12
VDDIOFB_L
AE11
VDDIO_SENSE
AJ21
CLKIN_H
AH21
CLKIN_L
AJ23
NC_AJ23
AH23
NC_AH23
AE24
NC_AE24
AF24
NC_AF24
C16
VTT_A
AG15
VTT_B
AH17
DBRDY
C15
NC_C15
E20
TMS
E17
TCK
B21
TRST_L
A21
TDI
C18
NC_C18
A19
NC_A19
A28
KEY1
AJ28
KEY0
AE23
NC_AE23
AF23
NC_AF23
AF22
NC_AF22
AF21
NC_AF21
C1
NC_C1
J3
NC_J3
R3
NC_R3
AA2
NC_AA2
D3
NC_D3
AG2
NC_AG2
B18
NC_B18
AH1
NC_AH1
AE21
NC_AE21
C20
NC_C20
AG4
NC_AG4
C6
NC_C6
AG6
NC_AG6
AE9
NC_AE9
AG9
NC_AG9
BGA754-SKT-U
12
R278
DY-20KR3F
12
R279
DY-20KR3F
D
R1
Vout = 1.25*(1+ R1/R2)
R2
THERMTRIP#
THERMDA
THERMDC
VID4
VID3
VID2
VID1
VID0
NC_AG18
NC_AH18
NC_AG17
NC_AJ18
DBREQ_L
NC_D20
NC_C21
NC_D18
NC_C19
NC_B19
TDO
NC_AF18
A20
A26
A27
AG13
AF14
AG14
AF15
AE15
AG18
AH18
AG17
AJ18
AH19
AJ19
AE19
D20
C21
D18
C19
B19
A22
AF18
VID4
VID3
VID2
VID1
VID0
NC_AG18
NC_AH18
NC_AG17
NC_AJ18
DBREQJ
NC_D20
NC_C21
NC_D18
NC_C19
NC_B19
TDO
THERMTRIP_L
FBCLKOUT_H
FBCLKOUT_L
Connect to VDDIO for AMD suggest.
D22
NC_D22
C22
NC_C22
B13
NC_B13
B7
NC_B7
C3
NC_C3
K1
NC_K1
R2
NC_R2
AA3
NC_AA3
F3
NC_F3
C23
NC_C23
AG7
NC_AG7
AE22
NC_AE22
C24
NC_C24
A25
NC_A25
C9
NC_C9
D
E
1D25V_S35,7,9,10,39,45
2D5V_S012,14,15,16,19,20,21,38,39,50
2D5V_S35,7,8,10,38,39,44,45,50
1D2V_HT0B_S04
THERMDP 22
THERMDN 22
VID[4..0] 41
TP45
TP46
LAYOUT: Route FBCLKOUT_H/L
FBCLKOUT
FBCLKOUTJ
differentially i mpedance 80
12
R323
80D6R3F-U
R322 DU MMY- R 3
1 2
2D5V_S3
SB
2D5V_S0
12
R193
680R3
THERMTRIP#
THERMTRIPJ Level shift to VT8235
EM_OFF PIN near VT8235
Title
Size Document Number Rev
A3
Date: Sheet of
CPU(3/4)_Control & Debug
2
1
EGRET
3
Q20
MMBT3904-U1
R194 1KR3
NS3
1 2
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
CPU_THERMTRIP# 38
2D5V_S0
650Friday, July 23 , 2004
E
1D25V_S3
2D5V_S0
2D5V_S3
1D2V_HT0B_S0
SC
U11E
Y17
VSS
K17
VSS
H17
VSS
F17
VSS
E18
VSS
AJ26
VSS
AE29
VSS
AC16
VSS
AA16
VSS
J16
VSS
G16
VSS
E16
VSS
AH14
4 4
3 3
2 2
1 1
AD15
AB15
K15
E15
D16
AE14
AC14
AA14
G14
AF17
AD13
AB13
Y13
K13
H13
F13
AH12
AC12
AA12
G12
B12
AD11
AB11
Y11
K11
H11
F11
AH10
AC10
W10
U10
R10
N10
G10
B10
AD9
AH8
AC8
AD7
AB7
AH6
AC6
AA6
AH4
AH2
AD2
AB2
C29
AH28
AF28
AC28
W28
R28
J14
L10
J10
Y9
V9
T9
P9
M9
K9
H9
F9
W8
U8
R8
N8
L8
J8
G8
B8
V7
T7
P7
M7
K7
H7
F7
U6
R6
N6
L6
J6
G6
B6
B4
Y2
V2
T2
P2
M2
K2
H2
F2
L28
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
BGA754-SKT-U
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VCC_CORE_S0 2D5V_S3
N20
L20
J20
AF19
AD19
AB19
Y19
K19
H19
F19
D19
AC18
AA18
G18
B16
AD17
AB17
H15
F15
G28
D28
B28
C27
AH26
AF26
AD26
Y26
T26
M26
H26
D26
B26
C25
B25
AJ24
AG24
AC24
AA24
W24
U24
R24
N24
J24
G24
E24
AG23
AD23
AB23
Y23
V23
T23
P23
K23
H23
F23
D23
AJ22
AH22
AG22
AC22
AA22
AG29
U22
R22
N22
L22
J22
G22
E22
B22
AG21
AD21
Y21
V21
T21
P21
M21
K21
H21
F21
D21
AJ20
AG20
AE20
AC20
AA20
W20
U20
R20
G20
J18
AE16
Y15
B14
J12
AA10
AB9
AA8
Y7
W6
AF2
D2
AG27
AG25
L24
M23
W22
AB21
AH20
B2
A
AC15
H18
B20
E21
H22
H24
F26
V10
G13
K14
Y14
AB14
G15
AA15
H16
K16
Y16
AB16
G17
AA17
AC17
AE17
F18
K18
Y18
AB18
AD18
AG19
E19
G19
AC19
AA19
F20
H20
K20
M20
P20
T20
V20
Y20
AB20
AD20
G21
N21
R21
U21
W21
AA21
AC21
F22
K22
M22
P22
T22
V22
Y22
AB22
AD22
E23
G23
N23
R23
U23
W23
AA23
AC23
B24
D24
F24
K24
M24
P24
T24
V24
Y24
AB24
AD24
AH24
AE25
K26
P26
V26
L7
J23
N7
L9
J15
J17
J19
J21
L21
L23
U11D
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
BGA754-SKT-U
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
E4
G4
J4
L4
N4
U4
W4
AA4
AC4
AE4
D5
AF5
F6
H6
K6
M6
P6
T6
V6
Y6
AB6
AD6
D7
G7
J7
AA7
AC7
AF7
F8
H8
AB8
AD8
D9
G9
AC9
AF9
F10
AD10
D11
AF11
F12
AD12
D13
AF13
F14
AD14
F16
AD16
D15
R4
N28
U28
AA28
AE27
R7
U7
W7
K8
M8
P8
T8
V8
Y8
J9
N9
R9
U9
W9
AA9
H10
K10
M10
P10
T10
Y10
AB10
G11
J11
AA11
AC11
H12
K12
Y12
AB12
J13
AA13
AC13
H14
AB26
E28
J28
B
VCC_CORE_S0
B
VCC_CORE_S0
12
C525
DY-SC6D8P50V2DC
0402
VCC_CORE_S0
12
C130
VCC_CORE_S0
1 2
C528
DY-SCD22U16V3ZY
0.22u x 4
2D5V_S3
12
C194
SCD22U16V3ZY
1D25V_S3
12
C535
SCD22U16V3ZY
0.22u x 2
EMI
12
C672
DY-SC6D8P50V2DC
C
LAYOUT: Place in uPGA socket cavity.
0.22u x 6
12
12
12
12
12
C132
C138
C137
C131
SCD22U16V3ZY
SCD22U16V3ZY
SCD22U16V3ZY
SCD22U16V3ZY
SCD22U16V3ZY
C139
SCD22U16V3ZY
LAYOUT: Place on backside of processor.
12
12
C530
DY-SCD22U16V3ZY
C531
SC10U10V5ZY
SC10U10V5ZY
1 2
1 2
1 2
C527
C533
C532
DY-SCD22U16V3ZY
DY-SCD22U16V3ZY
10u x 2
2D5V_S3
12
12
C198
C200
SCD22U16V3ZY
SCD22U16V3ZY
12
12
C196
SCD22U16V3ZY
12
C195
C626
SCD22U16V3ZY
SCD22U16V3ZY
C178
10u x 1 4.7u x 6
1D25V_S3
12
C534
SCD22U16V3ZY
C128
SC4D7U10V5ZY
SC4D7U10V5ZY
C129
4.7u x 2
VCC_CORE_S0
1000p x 3
12
12
C108
DY-SC1000P50V3KX
LAYOUT: Place 1000pF capacitors
between VRM & CPU.
C
12
C682
C660
DY-SC1000P50V3KX
DY-SC1000P50V3KX
C133
12
10u x 4
12
SC10U10V5ZY
C625
SC10U10V5ZY
C136
SC4D7U10V5ZY
12
SC10U10V5ZY
C526
C134
12
SC4D7U10V5ZY
SC10U10V5ZY
C257
C135
D
12
SC4D7U10V5ZY
D
SC10U10V5ZY
C254
SC4D7U10V5ZY
E
1D25V_S35,6,9,10,39,45
2D5V_S35,6,8,10,38,39,44,45,50
VCC_CORE_S041,42
C250
C253
78.47593.411
SC4D7U10V5ZY
SC4D7U10V5ZY
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size Document Number Rev
A3
Date: Sheet of
CPU(4/4)_Power
EGRET
E
1D25V_S3
2D5V_S3
VCC_CORE_S0
SC
750Friday, July 23 , 2004
A
M_AA0
M_AA1
M_AA2
M_AA3
M_AA4
M_AA6
M_AA5
M_AA7
M_AA8
M_AA9
M_AA10
M_AA11
M_ARAS#5,9
M_ACAS#5,9
M_AWE#5,9
TP65
TP15
TP64
C276
SCD1U
M_AA12
M_ABS#0
M_ABS#1
M_DATA_R_0
M_DATA_R_1
M_DATA_R_2
M_DATA_R_3
M_DATA_R_4
M_DATA_R_5
M_DATA_R_6
M_DATA_R_7
M_DATA_R_8
M_DATA_R_9
M_DATA_R_10
M_DATA_R_11
M_DATA_R_12
M_DATA_R_13
M_DATA_R_14
M_DATA_R_15
M_DATA_R_16
M_DATA_R_17
M_DATA_R_18
M_DATA_R_19
M_DATA_R_20
M_DATA_R_21
M_DATA_R_22
M_DATA_R_23
M_DATA_R_24
M_DATA_R_25
M_DATA_R_26
M_DATA_R_27
M_DATA_R_28
M_DATA_R_29
M_DATA_R_30
M_DATA_R_31
M_DATA_R_32
M_DATA_R_33
M_DATA_R_34
M_DATA_R_35
M_DATA_R_36
M_DATA_R_37
M_DATA_R_38
M_DATA_R_39
M_DATA_R_40
M_DATA_R_41
M_DATA_R_42
M_DATA_R_43
M_DATA_R_44
M_DATA_R_45
M_DATA_R_46
M_DATA_R_47
M_DATA_R_48
M_DATA_R_49
M_DATA_R_50
M_DATA_R_51
M_DATA_R_52
M_DATA_R_53
M_DATA_R_54
M_DATA_R_55
M_DATA_R_56
M_DATA_R_57
M_DATA_R_58
M_DATA_R_59
M_DATA_R_60
M_DATA_R_61
M_DATA_R_62
M_DATA_R_63
M_AA13
12
A
DM1_RESET#
DM1_A13
DM1_BA2
3D3V_S0
4 4
3 3
2 2
1 1
VREF_DDR_MEM VREF_DDR_MEM
Layout trace 20 mil Layout trace 20 mil
DM1
112
A0
111
A1
110
A2
109
A3
108
A4
107
A5
106
A6
105
A7
102
A8
101
A9
115
A10 / AP
100
A11
99
A12
117
BA0
116
BA1
5
DQ0
7
DQ1
13
DQ2
17
DQ3
6
DQ4
8
DQ5
14
DQ6
18
DQ7
19
DQ8
23
DQ9
29
DQ10
31
DQ11
20
DQ12
24
DQ13
30
DQ14
32
DQ15
41
DQ16
43
DQ17
49
DQ18
53
DQ19
42
DQ20
44
DQ21
50
DQ22
54
DQ23
55
DQ24
59
DQ25
65
DQ26
67
DQ27
56
DQ28
60
DQ29
66
DQ30
68
DQ31
127
DQ32
129
DQ33
135
DQ34
139
DQ35
128
DQ36
130
DQ37
136
DQ38
140
DQ39
141
DQ40
145
DQ41
151
DQ42
153
DQ43
142
DQ44
146
DQ45
152
DQ46
154
DQ47
163
DQ48
165
DQ49
171
DQ50
175
DQ51
164
DQ52
166
DQ53
172
DQ54
176
DQ55
177
DQ56
181
DQ57
187
DQ58
189
DQ59
178
DQ60
182
DQ61
188
DQ62
190
DQ63
71
CB0
73
CB1
79
CB2
83
CB3
72
CB4
74
CB5
80
CB6
84
CB7
85
NC
86
NC/(RESET#)
97
NC/A13
98
NC/BA2
123
NC
124
NC
200
NC
118
/RAS
120
/CAS
119
/WE
1
VREF
2
VREF
197
VDDSPD
199
VDDID
201
GND
DDR-SODIMM-N-U1
/CS0
/CS1
CKE0
CKE1
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
CK0
/CK0
CK1
/CK1
CK2
/CK2
SCL
SDA
SA0
SA1
SA2
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
NORMAL TYPE
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
GND
62.10017.191
B
M_BRAS#5,9
M_BCAS#5,9
M_BWE#5,9
TP23
TP69
TP22
C299
SCD1U
M_BA0
M_BA1
M_BA2
M_BA3
M_BA4
M_BA6
M_BA5
M_BA7
M_BA8
M_BA9
M_BA10
M_BA11
M_BA12
M_BBS#0
M_BBS#1
M_DATA_R_0
M_DATA_R_1
M_DATA_R_2
M_DATA_R_3
M_DATA_R_4
M_DATA_R_5
M_DATA_R_6
M_DATA_R_7
M_DATA_R_8
M_DATA_R_9
M_DATA_R_10
M_DATA_R_11
M_DATA_R_12
M_DATA_R_13
M_DATA_R_14
M_DATA_R_15
M_DATA_R_16
M_DATA_R_17
M_DATA_R_18
M_DATA_R_19
M_DATA_R_20
M_DATA_R_21
M_DATA_R_22
M_DATA_R_23
M_DATA_R_24
M_DATA_R_25
M_DATA_R_26
M_DATA_R_27
M_DATA_R_28
M_DATA_R_29
M_DATA_R_30
M_DATA_R_31
M_DATA_R_32
M_DATA_R_33
M_DATA_R_34
M_DATA_R_35
M_DATA_R_36
M_DATA_R_37
M_DATA_R_38
M_DATA_R_39
M_DATA_R_40
M_DATA_R_41
M_DATA_R_42
M_DATA_R_43
M_DATA_R_44
M_DATA_R_45
M_DATA_R_46
M_DATA_R_47
M_DATA_R_48
M_DATA_R_49
M_DATA_R_50
M_DATA_R_51
M_DATA_R_52
M_DATA_R_53
M_DATA_R_54
M_DATA_R_55
M_DATA_R_56
M_DATA_R_57
M_DATA_R_58
M_DATA_R_59
M_DATA_R_60
M_DATA_R_61
M_DATA_R_62
M_DATA_R_63
DM2_RESET#
DM2_A13
DM2_BA2
M_BA13
M_BRAS#
M_BCAS#
M_BWE#
12
3D3V_S0
121
122
M_CKE#0
96
95
M_DQS_R0
11
M_DQS_R1
25
M_DQS_R2
47
M_DQS_R3
61
M_DQS_R4
133
M_DQS_R5 M_DQS_R5
147
M_DQS_R6
169
M_DQS_R7
183
77
M_ADM_R0
12
M_ADM_R1
26
M_ADM_R2
48
M_ADM_R3
62
134
M_ADM_R5 M_ADM_R5
148
M_ADM_R6
170
M_ADM_R7
184
78
35
37
160
158
DDR_CLK0
89
DDR_CLK#0
91
SMBC_SB
195
SMBD_SB
193
194
196
198
9
10
21
22
33
34
36
45
46
57
58
69
70
81
82
92
93
94
113
114
131
132
143
144
155
156
157
167
168
179
180
191
192
3
4
15
16
27
28
38
39
40
51
52
63
64
75
76
87
88
90
103
104
125
126
137
138
149
150
159
161
162
173
174
185
186
202
B
M_CS#0 5,9
M_CS#1 5,9
M_CKE#0 5,9
M_ADM#0
M_ADM#1
M_ADM#2
M_ADM#3
M_ADM#4
M_ADM#5
M_ADM#6
M_ADM#7
M_CLK5 5,9
M_CLK#5 5,9
M_CLK7 5,9
2D5V_S3
NOT SUPPORT ECC CHECK
ALi suggested pull-low
C
DM2
112
A0
111
A1
110
A2
109
A3
108
A4
107
A5
106
A6
105
A7
102
A8
101
A9
115
A10 / AP
100
A11
99
A12
117
BA0
116
BA1
5
DQ0
7
DQ1
13
DQ2
17
DQ3
6
DQ4
8
DQ5
14
DQ6
18
DQ7
19
DQ8
23
DQ9
29
DQ10
31
DQ11
20
DQ12
24
DQ13
30
DQ14
32
DQ15
41
DQ16
43
DQ17
49
DQ18
53
DQ19
42
DQ20
44
DQ21
50
DQ22
54
DQ23
55
DQ24
59
DQ25
65
DQ26
67
DQ27
56
DQ28
60
DQ29
66
DQ30
68
DQ31
127
DQ32
129
DQ33
135
DQ34
139
DQ35
128
DQ36
130
DQ37
136
DQ38
140
DQ39
141
DQ40
145
DQ41
151
DQ42
153
DQ43
142
DQ44
146
DQ45
152
DQ46
154
DQ47
163
DQ48
165
DQ49
171
DQ50
175
DQ51
164
DQ52
166
DQ53
172
DQ54
176
DQ55
177
DQ56
181
DQ57
187
DQ58
189
DQ59
178
DQ60
182
DQ61
188
DQ62
190
DQ63
71
CB0
73
CB1
79
CB2
83
CB3
72
CB4
74
CB5
80
CB6
84
CB7
85
NC
86
NC/(RESET#)
97
NC/A13
98
NC/BA2
123
NC
124
NC
200
NC
118
/RAS
120
/CAS
119
/WE
1
VREF
2
VREF
197
VDDSPD
199
VDDID
202
GND
DDR-SODIMM-R-U2
62.10017.201
C
/CS0
/CS1
CKE0
CKE1
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
CK0
/CK0
CK1
/CK1
CK2
/CK2
SCL
SDA
SA0
SA1
SA2
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
REVERSE TYPE
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
GND
121
122
96
95
11
25
47
61
133
147
169
183
77
12
26
48
62
134
148
170
184
78
35
37
160
158
89
91
195
193
194
196
198
9
10
21
22
33
34
36
45
46
57
58
69
70
81
82
92
93
94
113
114
131
132
143
144
155
156
157
167
168
179
180
191
192
3
4
15
16
27
28
38
39
40
51
52
63
64
75
76
87
88
90
103
104
125
126
137
138
149
150
159
161
162
173
174
185
186
201
M_CS#2 5,9
M_CKE#1
M_DQS_R0
M_DQS_R1
M_DQS_R2
M_DQS_R3
M_DQS_R4
M_DQS_R6
M_DQS_R7
M_ADM_R0
M_ADM_R1
M_ADM_R2
M_ADM_R3
M_ADM_R4M_ADM_R4
M_ADM_R6
M_ADM_R7
DDR_CLK1
DDR_CLK#1
DM2_SA0
M_CS#3 5,9
M_CKE#1 5,9
M_ADM#0
M_ADM#1
M_ADM#2
M_ADM#3
M_ADM#4
M_ADM#5
M_ADM#6
M_ADM#7
M_CLK4 5,9
M_CLK#4 5,9
M_CLK6 5,9
M_CLK#6 5,9M_CLK#7 5,9
SMBC_SB 3,21
SMBD_SB 3,21
2D5V_S3
1 2
R204 4K7R3
By ME requset DM1 P/N:
Main 62.10017.191
Second 62.10017.381
By ME requset DM2 P/N:
Main 62.10017.201
Second 62.10017.371
Third 62.10017.701
D
M_ADM_R[7..0] 9
M_DATA_R_[63..0] 9
M_DQS_R[7..0] 9
M_AA[13..0] 5,9
M_ABS#[1..0] 5,9
M_BA[13..0] 5,9
M_BBS#[1..0] 5,9
3D3V_S0
DDR_CLK#1
DDR_CLK#0
DDR_CLK1
DDR_CLK0
8
7
6
RN39
SRN10K-2
VREF_DDR_MEM5
2D5V_S3
1
2
3
45
E
VREF_DDR_MEM
3D3V_S03,6,11,12,13,14,15,16,17,18,19,20,21,24,25,26,27,28,30,31,32,33,34,35,36,38,41,47,49,50
2D5V_S35,6,7,10,38,39,44,45,50
3D3V_S0
2D5V_S3
AMD K8
ClawHummar
MD63
DDR SOCKET PLACEMENT
TOP VIEW PERSPECTIVE DRAWING
DM1
Pin 199
Pin 200 Pin 2
DM2(Reverse)
Title
Size Document Number Rev
A3
D
Date: Sheet of
DDR SO-DIMM SKT
SMA11
Pin 200
Pin 199
EGRET
SMA10
SMA0
SMA14
SMA12
MD0
Pin 2
Pin 1
Pin 1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
850Friday, July 23 , 2004
E
SC
A
SERIES DAMPING PARALLEL TERMINATION
PLACE RNs CLOSE TO FIRST DM ( DM1 ), < 0.75"
STRICT EQUAL LENGTH LIMITATION WITH DQS,
CB PINS
M_DATA4
M_ADM0
M_DATA6
M_DATA7
M_DATA13
M_DATA12
4 4
M_ADM1
M_DATA1
M_DATA0
M_DQS0
M_DATA2
M_DATA3
M_DATA8
M_DATA9
M_DQS1
M_DATA14
M_DATA15
M_DATA21
M_DATA20
M_ADM2
M_DATA23
M_DATA22
M_DATA25 M_DATA_R_25
3 3
M_DATA11
M_DATA10
M_DATA17
M_DATA16
M_DQS2 M_DQS_R2
M_DATA19 M_DATA_R_19
M_DATA18
M_DATA24
M_DATA29
M_DATA28
M_ADM3
M_DATA26
M_DATA27
M_DATA30 M_DATA_R_30
M_DATA31
2 2
RN23
1
2
3
4
5
6
7
8 9
SRN10J-3
RN44
1
2
3
4
5
6
7
8 9
SRN10J-3
RN22
1
2
3
4
5
6
7
8 9
SRN10J-3
RN42
1
2
3
4
5
6
7
8 9
SRN10J-3
RN21
1
2
3
4
5
6
7
8 9
SRN10J-3
16
15
14
13
12
11
10
16
15
14
13
12
11
10
16
15
14
13
12
11
10
16
15
14
13
12
11
10
16
15
14
13
12
11
10
M_DATA_R_4
M_DATA_R_5M_DATA5
M_ADM_R0
M_DATA_R_6
M_DATA_R_7
M_DATA_R_13
M_DATA_R_12
M_ADM_R1
M_DATA_R_1
M_DATA_R_0
M_DQS_R0
M_DATA_R_2
M_DATA_R_3
M_DATA_R_8
M_DATA_R_9
M_DQS_R1
M_DATA_R_14
M_DATA_R_15
M_DATA_R_21
M_DATA_R_20
M_ADM_R2
M_DATA_R_23
M_DATA_R_22
M_DATA_R_11
M_DATA_R_10
M_DATA_R_17
M_DATA_R_16
M_DATA_R_18
M_DATA_R_24
M_DATA_R_29
M_DATA_R_28
M_DQS_R3M_DQS3
M_ADM_R3
M_DATA_R_26
M_DATA_R_27
M_DATA_R_31
M_DATA34
M_DATA32
M_DQS4
M_DATA33
M_DATA36
M_DATA37
M_ADM4
M_DATA39
M_DATA35
M_DATA41
M_DATA40
M_DQS5
M_DATA42
M_DATA43
M_DATA49
M_DATA48
M_DATA38
M_DATA45
M_DATA44
M_ADM5
M_DATA47
M_DATA46
M_DATA53
M_DATA52
M_DQS6
M_DATA50
M_DATA51
M_DATA56
M_DATA57
M_DQS7
M_DATA58
M_DATA59
M_ADM6
M_DATA54
M_DATA55
M_DATA61
M_DATA60
M_ADM7
M_DATA62
M_DATA63
1
2
3
4
5
6
7
8 9
1
2
3
4
5
6
7
8 9
1
2
3
4
5
6
7
8 9
1
2
3
4
5
6
7
8 9
1
2
3
4
5
6
7
8 9
RN20
SRN10J-3
RN32
SRN10J-3
RN19
SRN10J-3
RN29
SRN10J-3
RN18
SRN10J-3
B
16
15
14
13
12
11
10
16
15
14
13
12
11
10
16
15
14
13
12
11
10
16
15
14
13
12
11
10
16
15
14
13
12
11
10
M_DATA_R_34
M_DATA_R_32
M_DQS_R4
M_DATA_R_33
M_DATA_R_36
M_DATA_R_37
M_ADM_R4
M_DATA_R_39
M_DATA_R_35
M_DATA_R_41
M_DATA_R_40
M_DQS_R5
M_DATA_R_42
M_DATA_R_43
M_DATA_R_49
M_DATA_R_48
M_DATA_R_38
M_DATA_R_45
M_DATA_R_44
M_ADM_R5
M_DATA_R_47
M_DATA_R_46
M_DATA_R_53
M_DATA_R_52
M_DQS_R6
M_DATA_R_50
M_DATA_R_51
M_DATA_R_56
M_DATA_R_57
M_DQS_R7
M_DATA_R_58
M_DATA_R_59
M_ADM_R6
M_DATA_R_54
M_DATA_R_55
M_DATA_R_61
M_DATA_R_60
M_ADM_R7
M_DATA_R_62
M_DATA_R_63
M_ADM_R1
M_DATA_R_13
M_DATA_R_12
M_DATA_R_6
M_DATA_R_7
M_ADM_R0
M_DATA_R_5
M_DATA_R_4
M_DATA_R_1
M_DATA_R_0
M_DQS_R0
M_DATA_R_2
M_DATA_R_3
M_DATA_R_8
M_DATA_R_9
M_DQS_R1
M_DATA_R_25
M_DATA_R_22
M_DATA_R_23
M_ADM_R2
M_DATA_R_20
M_DATA_R_21
M_DATA_R_14
M_DATA_R_15
M_DATA_R_11
M_DATA_R_10
M_DATA_R_16
M_DATA_R_17
M_DQS_R2
M_DATA_R_19
M_DATA_R_18
M_DATA_R_24
M_DATA_R_30
M_DATA_R_31
M_DATA_R_26
M_DATA_R_27
M_ADM_R3
M_DQS_R3
M_DATA_R_29
M_DATA_R_28
RN45
1
2
3
4
5
6
7
8 9
SRN68J-1
RN65
1
2
3
4
5
6
7
8 9
SRN68J-1
RN43
1
2
3
4
5
6
7
8 9
SRN68J-1
RN64
1
2
3
4
5
6
7
8 9
SRN68J-1
RN41
1
2
3
4
5
6
7
8 9
SRN68J-1
C
PULL HIGH STUBS < 0.8", PLACE RPs CLOSE TO SECOND DM ( DM2 )
1D25V_S3 1D25V_S3
16
15
14
13
12
11
10
16
15
14
13
12
11
10
16
15
14
13
12
11
10
16
15
14
13
12
11
10
16
15
14
13
12
11
10
RN33
1
2
3
4
5
6
7
8 9
SRN68J-1
RN61
1
2
3
4
5
6
7
8 9
SRN68J-1
RN31
1
2
3
4
5
6
7
8 9
SRN68J-1
RN60
1
2
3
4
5
6
7
8 9
SRN68J-1
RN30
1
2
3
4
5
6
7
8 9
SRN68J-1
NO EQUAL LENGTH LIMITATION
M_DATA_R_36
16
M_DATA_R_32
15
M_DATA_R_37
14
M_DATA_R_33
13
M_ADM_R4
12
M_DQS_R4
11
M_DATA_R_38
10
M_DATA_R_39
M_DATA_R_48
16
M_DATA_R_49
15
M_DATA_R_43
14
M_DATA_R_42
13
M_DQS_R5
12
M_DATA_R_41
11
M_DATA_R_40
10
M_DATA_R_34
M_DATA_R_35
16
M_DATA_R_46
15
M_DATA_R_47
14
M_ADM_R5
13
M_DATA_R_44
12
M_DATA_R_45
11
M_DATA_R_53
10
M_DATA_R_52
M_DATA_R_59
16
M_DATA_R_58
15
M_DQS_R7
14
M_DATA_R_57
13
M_DATA_R_56
12
M_DATA_R_51
11
M_DATA_R_50
10
M_DQS_R6
M_DATA_R_55
16
M_DATA_R_54
15
M_ADM_R6
14
M_DATA_R_60
13
M_DATA_R_61
12
M_ADM_R7
11
M_DATA_R_63
10
M_DATA_R_62
D
M_CKE#1
M_BA12
M_CKE#0
M_AA12
M_AA11
M_AA9
M_AA7
M_AA5
M_AA4
M_AA8
M_AA6
M_AA3
M_CS#3
M_BA13
M_CS#2
M_BRAS#
M_BBS#1
M_BCAS#
M_BA0
M_BA2
M_AA1
M_AA10
M_AA2
M_AA0
M_ABS#1
M_ARAS#
M_AWE#
M_ABS#0
M_BA7
M_BA3
M_BA6
M_BA9
M_BA10
M_BA1
M_BBS#0
M_BWE#
M_BA5
M_BA8
M_BA11
M_BA4
M_AA13
M_CS#0
M_CS#1
M_ACAS#
RN63
2
1 4
SRN47J
RN40
2
1 4
SRN47J
RN37
1
2
3
4
5
6
7
8 9
SRN47J-1-U
RN36
1
2
3
4
5
6
7
8 9
SRN47J-1-U
RN35
1
2
3
4
5
6
7
8 9
SRN47J-1-U
RN62
1
2
3
4
5
6
7
8 9
SRN47J-1-U
RN38
1
2
3
4 5
SRN47-1
RN34
1
2
3
4 5
SRN47-1
3
3
16
15
14
13
12
11
10
16
15
14
13
12
11
10
16
15
14
13
12
11
10
16
15
14
13
12
11
10
8
7
6
8
7
6
E
1D25V_S35,6,7,10,39,45
1D25V_S3
M_ADM_R[7..0] 8
M_ADM[7..0] 5
M_DATA[63..0] 5
M_DATA_R_[63..0] 8
M_DQS[7..0] 5
M_DQS_R[7..0] 8
M_AA[13..0] 5,8
M_ABS#[1..0] 5,8
M_BA[13..0] 5,8
M_BBS#[1..0] 5,8
M_AWE# 5,8
M_ACAS# 5,8
M_ARAS# 5,8
M_BWE# 5,8
M_BCAS# 5,8
M_BRAS# 5,8
M_CS#0 5,8
M_CS#1 5,8
M_CS#2 5,8
M_CS#3 5,8
PLACE BETWEEN DM1, DM2
M_CKE#05,8
M_CKE#15,8
05/10
Remove the damping resistor for AMD suggest.
1 1
M_CKE#0
M_CKE#1
A
B
CLOSE TO FIRST DM ( DM 2 ) < 0.2", TO SECOND DM ( DM1 ) < 1.1"
EQUAL LENGTH LIMITATION WITH SCK/SCK#
R171 121R3F
1 2
R239 121R3F
1 2
R205 121R3F
1 2
R240 121R3F
1 2
M_CLK7
M_CLK#7
M_CLK6
M_CLK#6
M_CLK5
M_CLK#5
M_CLK4
M_CLK#4
C
M_CLK7 5,8
M_CLK#7 5,8
M_CLK6 5,8
M_CLK#6 5,8
M_CLK5 5,8
M_CLK#5 5,8
M_CLK4 5,8
M_CLK#4 5,8
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size Document Number Rev
A3
D
Date: Sheet of
DDR DAMPING & TERMINATION
EGRET
950Friday, July 23 , 2004
E
SC
A
B
C
D
E
2D5V_S35,6,7,8,38,39,44,45,50
1D25V_S35,6,7,9,39,45
4 4
2D5V_S3
1D25V_S3
3 3
1D25V_S3
12
12
2D5V_S3
12
12
C269
SCD1U
C249
SCD1U
C367
SCD1U
C366
SCD1U
12
12
C347
C349
SCD1U
DY-SCD1U
12
12
C346
C348
SCD1U
DY-SCD1U
12
12
C328
C369
SCD1U
DY-SCD1U
12
12
C327
C368
SCD1U
LAYOUT:Place altemating caps to GND and 2D5_S3
12
12
12
12
12
12
C351
SCD1U
C350
SCD1U
C330
SCD1U
C329
SCD1U
12
12
C319
DY-SCD1U
12
12
C318
DY-SCD1U
12
12
C301
DY-SCD1U
12
12
C370
C353
SCD1U
C352
SCD1U
C258
SCD1U
C303
SCD1U
12
12
12
C355
SCD1U
C354
SCD1U
C214
SCD1U
C259
SCD1U
12
C296
C357
SCD1U
DY-SCD1U
12
12
C297
C356
SCD1U
DY-SCD1U
12
12
C197
C316
SCD1U
DY-SCD1U
12
12
C230
C199
SCD1U
12
12
12
12
C322
SCD1U
C358
SCD1U
C288
SCD1U
C315
SCD1U
12
12
C359
C361
SCD1U
DY-SCD1U
12
12
C323
C360
SCD1U
DY-SCD1U
12
12
C324
SCD1U
C325
SCD1U
12
C293
DY-SCD1U
12
C291
DY-SCD1U
12
12
C292
SCD1U
C294
SCD1U
12
12
C363
SCD1U
C362
SCD1U
12
C365
DY-SCD1U
12
C364
DY-SCD1U
LAYOUT:Locate close to CPU socket.
2D5V_S3 1D25V_S3
TC16
1 2
DY-SE220U2VDM-6
C659
1 2
SC22U10V6ZY-U
SB
12
C268
DY-SCD1U
12
C287
12
12
C227
SCD1U
C267
SCD1U
12
12
C333
SCD1U
C226
SCD1U
12
12
12
12
C371
SCD1U
C251
SCD1U
12
C213
DY-SCD1U
12
C193
C252
C256
SCD1U
DY-SCD1U
12
12
C229
C334
SCD1U
1D25V_S3
12
C804
12
C805
DY-SCD1U
DY-SCD1U
12
12
C806
C807
DY-SCD1U
DY-SCD1U
12
C809
12
C810
DY-SCD1U
DY-SCD1U
12
C808
DY-SCD1U
2D5V_S3
1D25V_S3
DY-SCD1U
2 2
DY-SCD1U
DY-SCD1U
DY-SCD1U
DY-SCD1U
DY-SCD1U
LAYOUT:Place close to Power Pin of DDR socket.
LAYOUT:Place at end of the DIMMs
1D25V_S3
12
1 1
SC
TC23
DY-ST100U4VBM
12
TC24
ST100U4VBM-1
80.10716.321
KEMET,NT:5.7, B2 size
ST100U4VBM-1 (80.10716.321)
Iripple=1.1A,ESR=70mohm
SANYO, NT$:6.1
Iripple=1.1A,ESR=70mohm
3.5/2.8/2.0
77.21071.031
A
12
C786
SC22U10V6ZY-U
12
C787
SC22U10V6ZY-U
12
C795
SC22U10V6ZY-U
B
12
C796
SC22U10V6ZY-U
C
2D5V_S3 2D5V_S3
C271
SCD22U16V3ZY
1 2
C289
DY-SCD22U16V3ZY
1 2
C298
DY-SCD22U16V3ZY
1 2
C290
SCD22U16V3ZY
1 2
C321
SCD22U16V3ZY
1 2
0.22u x 10
D
C273
SCD22U16V3ZY
1 2
C274
DY-SCD22U16V3ZY
1 2
C295
DY-SCD22U16V3ZY
1 2
C320
SCD22U16V3ZY
1 2
C326
SCD22U16V3ZY
1 2
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size Document Number Rev
A3
Date: Sheet of
DDR DECOUPLING
EGRET
E
10 50Friday, July 23 , 2004
SC
A
B
C
D
E
3D3V_S03,6,8,12,13,14,15,16,17,18,19,20,21,24,25,26,27,28,30,31,32,33,34,35,36,38,41,47,49,50
1D2V_HT0A_S04,13,39,45
2D5V_S06,12,14,15,1 6,19,20,21,38,39,50
4 4
CLAW HAMMER TO NB
CPUCADOUT[15..0]4
3 3
2 2
CPUHTTCLKOUT04
CPUHTTCLKOUT14
CPUHTTCTLOUT04
CPUCADOUTJ[15..0]4
CPUHTTCLKOUTJ14
CPUHTTCTLOUTJ04
LDTRST#21
LDTSTP#21
CPUCADOUT0
CPUCADOUT1
CPUCADOUT2
CPUCADOUT3
CPUCADOUT4
CPUCADOUT5
CPUCADOUT6
CPUCADOUT7
CPUCADOUT8
CPUCADOUT9
CPUCADOUT10
CPUCADOUT11
CPUCADOUT12
CPUCADOUT13
CPUCADOUT14
CPUCADOUT15
CPUHTTCLKOUT0
CPUHTTCLKOUT1
CPUHTTCTLOUT0
CPUCADOUTJ0
CPUCADOUTJ1
CPUCADOUTJ2
CPUCADOUTJ3
CPUCADOUTJ4
CPUCADOUTJ5
CPUCADOUTJ6
CPUCADOUTJ7
CPUCADOUTJ8
CPUCADOUTJ9
CPUCADOUTJ10
CPUCADOUTJ11
CPUCADOUTJ12
CPUCADOUTJ13
CPUCADOUTJ14
CPUCADOUTJ15
CPUHTTCLKOUTJ0
CPUHTTCLKOUTJ1
CPUHTTCTLOUTJ0
LDTRST#
LDTSTP#
RPCOMP
RNCOMP
RTCOMP
1D2V_HT0A_S0
3D3VA_HT_S0
C22
AVDD2
T26
RCADP0
P24
RCADP1
P26
RCADP2
M24
RCADP3
K24
RCADP4
K26
RCADP5
H24
RCADP6
H26
RCADP7
R24
RCADP8
R22
RCADP9
N24
RCADP10
N22
RCADP11
L22
RCADP12
J24
RCADP13
J22
RCADP14
G24
RCADP15
M26
RCLKP0
L24
RCLKP1
F24
RCTLP
R26
RCADN0
P25
RCADN1
N26
RCADN2
M25
RCADN3
K25
RCADN4
J26
RCADN5
H25
RCADN6
G26
RCADN7
R23
RCADN8
P22
RCADN9
N23
RCADN10
M22
RCADN11
K22
RCADN12
J23
RCADN13
H22
RCADN14
G23
RCADN15
L26
RCLKN0
L23
RCLKN1
F25
RCTLN
B11
LDTRST
A12
LDTSTP
D25
RPCOMP
D26
RNCOMP
C26
RTCOMP
U24
VLDT
U25
VLDT
U26
VLDT
V21
VLDT
V22
VLDT
V23
VLDT
V24
VLDT
V25
VLDT
V26
VLDT
AGND2
C21
A10
VLDT
VSSA8VSS
VSS
A23
A24
A25
VLDT
VSSB8VSS
B13
AGND2
A26
B10
B23
B24
B25
B26
C10
C11
C23
C24
C25
D10
D11
D22
D23
D24
E10
E11
E21
E22
E23
E24
F10
F11
F15
F16
F19
F20
F21
F22
F23
G21
G22
H21
VLDT
VLDT
VLDTA9VLDT
VLDT
VLDT
VLDT
VLDT
VLDTB9VLDT
VLDT
VLDT
VLDT
VLDT
VLDTC9VLDT
VLDT
VLDT
VLDT
VLDT
VLDTD9VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDTE9VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VSS
VSSD6VSS
VSS
VSSC8VSS
VSS
VSS
B15
B21
B22
B17
B19
VSS
VSSE5VSSE6VSSE8VSSF7VSSF8VSS
VSS
VSS
VSS
D8
D18
D20
D12
D14
D16
VSS
VSS
VSS
VSS
VSS
VSS
VSSH1VSS
G25
VSS
VSS
VSS
J2
J3
H2
J18
H23
VSS
G1
F13
F14
F17
F18
F26
F12
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
K4
J21
J25
K12
K10
K13
K11
1D2V_HT0A_S03D3VA_HCK_S0
J11
J12
J13
J14
J15
J16
J17
K18
K21
VLDT
VSS
L10
VLDT
VLDT
TCADP0
TCADP1
TCADP2
TCADP3
TCADP4
TCADP5
TCADP6
TCADP7
TCADP8
TCADP9
TCADP10
TCADP11
TCADP12
TCADP13
TCADP14
TCADP15
TCLKP0
TCLKP1
TCADN0
TCADN1
TCADN2
TCADN3
TCADN4
TCADN5
TCADN6
TCADN7
TCADN8
TCADN9
TCADN10
TCADN11
TCADN12
TCADN13
TCADN14
TCADN15
TCLKN0
TCLKN1
VSS
VSS
L11
L12
VLDT
TCTLP
TCTLN
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VSS
L13
VLDT
VSS
L18
VLDT
VSS
L14
L15
J10
VLDT
VLDT
VLDT
VLDT
VSS
VSS
VSS
VSS
K16
K17
K23
K15
K14
NB TO CLAW HAMMER
U16A
VLDT
NB0CADOUT0
B12
NB0CADOUT1
A13
NB0CADOUT2
B14
NB0CADOUT3
A15
NB0CADOUT4
A17
NB0CADOUT5
B18
NB0CADOUT6
A19
NB0CADOUT7
B20
NB0CADOUT8
E12
NB0CADOUT9
D13
NB0CADOUT10
E14
NB0CADOUT11
D15
NB0CADOUT12
D17
NB0CADOUT13
E18
NB0CADOUT14
D19
NB0CADOUT15
E20
NB0HTTCLKOUT0
VSS
K8N800
B16
E16
A21
C12
A14
C14
A16
A18
C18
A20
C20
E13
C13
E15
C15
C17
E19
C19
D21
C16
E17
A22
L21
M18
N18
N21
P18
P21
R18
T18
T21
T22
T23
T24
T25
U18
U21
U22
U23
NB0HTTCLKOUT1
NB0HTTCTLOUT
NB0CADOUTJ0
NB0CADOUTJ1
NB0CADOUTJ2
NB0CADOUTJ3
NB0CADOUTJ4
NB0CADOUTJ5
NB0CADOUTJ6
NB0CADOUTJ7
NB0CADOUTJ8
NB0CADOUTJ9
NB0CADOUTJ10
NB0CADOUTJ11
NB0CADOUTJ12
NB0CADOUTJ13
NB0CADOUTJ14
NB0CADOUTJ15
NB0HTTCLKOUTJ0
NB0HTTCLKOUTJ1
NB0HTTCTLOUTJ
1D2V_HT0A_S0
NB0HTTCLKOUT0 4
NB0HTTCLKOUT1 4
NB0HTTCTLOUT 4
NB0HTTCLKOUTJ 0 4CPUHTTCLKOUTJ04
NB0HTTCLKOUTJ 1 4
NB0HTTCTLOUTJ 4
NB0CADOUT[15..0] 4
NB0CADOUTJ[15..0] 4
SC
L8
1 2
GAP-CLOSE-PWR
L25
1 2
DY-SBK201209T-1
R317
1 2
DY-0R3-U
Only for K8T800PRO.
When use K8N800,
Please remove them.
12
C125
SC1000P50V3KX
78.10224.2B1
12
C521
DY-SC1000P50V3KX
1D2V_HT0A_S0
12
C175
SCD1U
AROUND NB
R91 49D9R3F
RNCOMP
RTCOMP
RPCOMP
1 2
R90 100R3
1 2
R89 49D9R3F
1 2
12
3D3VA_HCK_S03D3V_S0
C618
SCD1U
3D3VA_HT_S03D3V_S0
1D2V_HT0A_S0
3D3V_S0
1D2V_HT0A_S0
2D5V_S0
12
C126
SC1U10V3ZY
12
C520
DY-SC1U10V3ZY
AGND2
1 1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size Document Number Rev
A3
A
B
C
D
Date: Sheet of
NB-K8N800(1/3)_HT
EGRET
E
11 50Friday, July 23 , 2004
SC
A
4 4
3 3
2 2
For K8T800PRO remove.
For K8N800 install.
Close to the AGP connector
1 1
AGP_CLK_DDC_316
AGP_DAT_DDC_316
VLAD[7..0]21
VBE#21
LPAR21
UPSTB21
UPSTB#21
DNSTB21
DNSTB#21
UPCMD21
DNCMD21
ALL_PWROK6,19,21,39
RST_NB#19
PM_SUS_STAT#16,20,33
GUICLK3
INT_PIRQA#16,19
RN83
AGP_CRT_G16,17
AGP_CRT_B16,17
AGP_CRT_R16,17
AGP_JVGA_HS16,17
AGP_JVGA_VS16,17
1
2
3
4 5
DY-SRN0-1-U
RN78
1
2
3
4 5
DY-SRN0-1-U
A
VLAD0
VLAD1
VLAD2
VLAD3
VLAD4
VLAD5
VLAD6
VLAD7
VBE#
LPAR
UPSTB
UPSTB#
DNSTB
DNSTB#
UPCMD
DNCMD
VL_VREF
VL_PCOMP
TESTIN
DEBUG
NB_CRT_R
NB_CRT_G
NB_CRT_B
CRT_RSET
CRT_HSYNC
CRT_VSYNC
GUICLK
BISTIN
SMBC2
SMBD2
DP0_D4
DP0_D5
DP0_D6
DP0_D7
DP0_D8
DP0_D10
NB_CRT_G
8
NB_CRT_B
7
NB_CRT_R
6
CRT_HSYNC
8
CRT_VSYNC
7
SMBC2
6
SMBD2
AD20
AD21
AF24
AE24
AE19
AF20
AD24
AF25
AE21
AF19
AE23
AF23
AF22
AD22
AF26
AD23
AF21
AD19
AE26
AD25
AC26
AD26
AC17
B3
A3
A2
C4
A1
B1
C6
E7
D3
P2
C2
P1
C1
J1
K2
K3
L4
K1
L2
L3
M4
L1
M2
M3
M1
P4
N1
N4
N3
P3
N2
D2
A7
D7
3D3VA_GCK_S0
E3
E1
D1
VD0
VD1
VD2
VD3
VD4
VD5
VD6
VD7
VBE
VPAR
UPSTB
UPSTB
DNSTB
DNSTB
UPCMD
DNCMD
LVREF
LCOMPP
PWRGD
PCIRST
TESTIN
SUSTAT
DEBUG
AR/NC
AG/NC
AB/NC
RSET/NC
HSYNC/NC
VSYNC/NC
XIN/NC
INTA/NC
BISTIN/NC
SPCLK1/NC
SPCLK2/NC
SPD1/NC
SPD2/NC
TVD00/DVP0D00/NC
TVD01/DVP0D01/NC
TVD02/DVP0D02/NC
TVD03/DVP0D03/NC
TVD04/DVP0D04/NC
TVD05/DVP0D05/NC
TVD06/DVP0D06/NC
TVD07/DVP0D07/NC
TVD08/DVP0D08/NC
TVD09/DVP0D09/NC
TVD10/DVP0D10/NC
TVD11/DVP0D11/NC
TVCLKIN/DVP0DET/NC
TVDE/DVP0DE/NC
TVHS/DVP0HS/NC
TVVS/DVP0VS/NC
TVCLK/DVP0DCLK/NC
GPO0/NC
GPOUT/NC
DISPCLKO/NC
DISPCLKI/NC
VSS
VSS
L17
L16
VCC4/NCE4VCC4/NCE2VCC4/NC
VCC4/NC
VCC4/NC
VSS
VSS
VSS
VSS
VSS
VSS
L25
M10
M11
M12
M13
M14
F1
V_LINK
SM Bus
M15
B
3D3V_S0
F6
F5
F3
VCC4/NC
VCC4/NC
VCC4/NCF2VCC4/NC
VCC4/NCF4VCC4/NC
VCC4/NCG2VCC4/NCG3VCC4/NCG4VCC4/NCG5VCC4/NCH3VCC4/NCH4VCC4/NCH5VCC4/NCJ4VCC4/NCJ5VCC4/NC
CRT
TV Encoder/
Digital
Display
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
N10
N11
N12
N13
M23
N14
B
M16
M17
M21
N15
VSS
N16
VSS
N17
VSS
N25
VSS
J9
VSSP5VSS
P10
K8
K5
VCC4/NC
VCC4/NC
AGP 8X
VSS
VSS
VSS
P11
P12
P13
P14
L8
VCC4/NCL5VCC4/NCK9VCC4/NC
VSS
P15
VSS
L9
VSS
P16
M5
N5
VCC4/NC
VCC4/NCM9VCC4/NC
VCC4/NC
VSS
VSS
VSSR1VSSR2VSSR3VSSR4VSSR5VSS
P17
P23
R9
VCC4/NCN9VCC4/NCP9VCC4/NC
1D5V_S0
U1
VCCQQ
GD2/FPDVICLK
GD8/FPDVIDET
GD24/DVP1D09
GD26/DVP1D10
GD28/DVP1D07
GD29/DVP1D06
GD30/DVP1D08
GD31/DVP1DET
GCBE3/DVP1D11
ADSTB0S/FPD02
ADSTB0F/FPD04
ADSTB1S/FPDET
ADSTB1F/FPD12
GFRAME/FPHS
GDEVSEL/FPVS
GSTOP/FPDVICLK_N
GPAR/FPDVIVS
WBF/FPCLK_N
GREQ/DVI_DDCCK
GGNT/DVI_DDCDA
GSERR/FPDVIDE
SBA2/DVP1D00
SBA4/DVP1D05
SBA5/DVP1D03
SBA6/DVP1CLK
SBA7/DVP1CLK_N
SB_STBS/DVP1D02
SB_STBF/DVP1D01
VSS
VSS
VSS
R10
R11
R12
R13
R14
GD0/FPD10
GD1/FPD11
GD3/FPD09
GD4/FPD08
GD5/FPD07
GD6/FPD06
GD7/FPD05
GD9/FPDVIHS
GD10/FPD01
GD11/FPD23
GD12/FPD00
GD13/FPD22
GD14/FPD21
GD15/FPD20
GD16/FPD18
GD17/FPD17
GD18/FPD16
GD19/FPDE
GD20/FPD14
GD21/FPCLK
GD22/FPD13
GD23/FPD15
GD25
GD27
GCBE0/FPD03
GCBE1/SB_DA
GCBE2/FPD19
GIRDY/SB_CK
GTRDY
RBF
GCLK
SBA0/DVP1VS
SBA1/DVP1DE
SBA3/DVP1HS
ST0
ST1/DVP1D04
ST2
AGPPCOMP
AGPNCOMP
AGPVREF0
AGPVREF1
AGP8XDET
DBIL
DBIH
VSSQQ
VSS
VSS
T1
R15
C
U16B
AGP_AD0
AF18
AGP_AD1
AD18
AGP_AD2
AE18
AGP_AD3
AF17
AGP_AD4
AD17
AGP_AD5
AD16
AGP_AD6
AE16
AGP_AD7
AF16
AGP_AD8
AF14
AGP_AD9
AD14
AGP_AD10
AD13
AGP_AD11
AE13
AGP_AD12
AF13
AGP_AD13
AD12
AGP_AD14
AF12
AGP_AD15
AE12
AGP_AD16
AD10
AGP_AD17
AE10
AGP_AD18
AF10
AGP_AD19
AD9
AGP_AD20
AF9
AGP_AD21
AF8
AGP_AD22
AE9
AGP_AD23
AD8
AGP_AD24
AF6
AGP_AD25
AD7
AGP_AD26
AE6
AGP_AD27
AD5
AGP_AD28
AF5
AGP_AD29
AF4
AGP_AD30
AE4
AGP_AD31
AD4
AGP_CBE#0
AD15
AGP_CBE#1
AF11
AGP_CBE#2
AD11
AGP_CBE#3
AC7
AGP_ADSTB0#
AF15
AGP_ADSTB0
AE15
AGP_ADSTB1#
AF7
AGP_ADSTB1
AE7
AGP_FRAME#
AC9
AGP_IRDY#
AC10
AGP_TRDY#
AC14
AGP_DEVSEL#
AC11
AGP_STOP#
AC12
AGP_PAR
AC16
AGP_RBF#
AD6
AGP_WBF#
AC1
AGP_REQ#
Y1
AGP_GNT#
AA3
AGP_SERR#
AC15
CLK66_NB
A11
AGP_SBA0
AC2
AGP_SBA1
AC3
AGP_SBA2
AD1
AGP_SBA3
AD2
AGP_SBA4
AF2
AGP_SBA5
AD3
AGP_SBA6
AE3
AGP_SBA7
AF3
AGP_SB_STB#
AE1
AGP_SB_STB
AF1
AGP_ST0
AA2
AGP_ST1
AA1
AGP_ST2
AB1
AGP_PCOMP
V1
AGP_NCOMP
W1
AGP_VREF_GC
AC13
AC6
AGP_MBDET#
Y2
AC4
AC5
K8N800
AGP_MBDET#
05/10
For VIA suggest.
K8N800 UMA Need to Pull-UP,
K8T800Pro Discrete should be Pull-down.
C
R129 DY-10KR3
1 2
R131 2K2R3
1 2
3D3V_S0
C561
1 2
SC1U10V3ZY
AGP_AD[31..0] 14,15,16
AGP_SBA6
AGP_CBE#[3..0] 14,15,16
AGP_ADSTB0# 15,16
AGP_ADSTB0 15,16
AGP_ADSTB1# 14,16
AGP_ADSTB1 15,16
AGP_FRAME# 15,16
AGP_IRDY# 14,16
AGP_TRDY# 16
AGP_DEVSEL# 15,16
AGP_STOP# 16
AGP_PAR 16
AGP_RBF# 16
AGP_WBF# 15,16
AGP_REQ# 16
AGP_GNT# 16
TP55
CLK66_NB 3
AGP_SBA[7..0] 14,16
AGP_SB_STB# 14,16
AGP_SB_STB 14,16
AGP_ST[2..0] 15,16
AGP_MBDET# 16
AGP_DBIL 16
AGP_DBIH 16
D
R133 4K7R3
TESTIN
R132 60D4R3F
AGP_NCOMP
R130 60D4R3F
AGP_PCOMP
R144 360R3F
VL_PCOMP
R326 82R3F
CRT_RSET
R143 10KR3
DEBUG
R327 1KR3
BISTIN
R78 DY-33R3
1 2
For K8T800PRO remove.
For K8N800 install.
05/10
For VIA suggest.
UMA AGPVREF 0.75V, Use 100 ohm
64.10005.651
Discrete 8X AGPVREF 0.35V, Use 324 ohm
64.32405.651
1D5V_S0
12
R358
324R3F
12
100R3F
AGP_VREF_GC
12
R359
1623_XCLK 14
C650
SC1U10V3ZY
Layout trace 20 mil
2D5V_S0
D
E
3D3V_S03,6,8,11,13,14,15,16,17,18,19,20,21,24,25,26,27,28,30,31,32,33,34,35,36,38,41,47,49,50
2D5V_S06,14,15,16,19,20,21,38,39,50
1D5V_S013,14 ,15,16,44,50
12
C158
RN11
1
2
3
4 5
SRN4K7-1-U
R115 4K7R3
1 2
R116 4K7R3
1 2
3D3VA_GCK_S03D3V_S0
1D5V_S0
DP0_D6
DP0_D8
DP0_D4
DP0_D5
For K8T800PRO remove.
For K8N800 install.
DP0_D10
DP0_D7
DY-SC1000P50V3KX
1 2
1 2
1 2
1 2
64.82R05.551
1 2
1 2
1 2
C648
SCD1U
1 2
2D5V_S0
1D5V_S0
Use this function for K8N800
GFX power up strapping setting:
TVD/DVP0D[3:0] => Panel type selection
TVD4/DVP0D4 => FP-port multiplexed on AGP
interface selection
0: Two 12-bit DVI interface
SB
2D5V_S0
1: One 24-bit panel interface
TVD5/DVP0D5 => Dedicated DVI port configuration
0: TMDS
1: TV Encoder
TVD6/DVP0D6 => Dedicated DVI port selection
0: Disable
1: Enable
Note: All of these power up strapping
pin have internal pull down. Put an
external pull up resister if want to
set the default value to 1.
L10
1 2
DY-0R5J
Only for K8T800PRO.
When use K8N800,
Please remove them.
SC
12
R146
3K6R3D
12
R145
1K13R3F
VL_VREF
12
12
C210
SCD1U
C211
SCD1U
Layout trace 20 mil
The voltage level of
VL_VREF is 0.625V
Cross NB as short as possible
Title
Size Document Number Rev
A3
Date: Sheet
NB-K8N800(2/3)_AGP_VLINK
EGRET
Decoupling capacitors
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
12 50Friday, July 23 , 2004
E
3D3V_S0
2D5V_S0
1D5V_S0
3D3V_S0
8
7
6
12
C157
DY-SC1U10V3ZY
C607 SC1U10V3ZY
1 2
C651 SC1U10V3ZY
1 2
1 2
C171
SC22U10V6ZY-U
1 2
C192
SC22U10V6ZY-U
1 2
C172
SC22U10V6ZY-U
of
SC
A
Layout trace 20 mil
1D5V_NB_S5
3D3VA_S0
4 4
1D5V_PLL1_S0
1D5V_PLL2_S0
3D3V_DAC_S0 1D5V_NB_S5
1D5V_S0
3 3
2 2
1 1
AC25
AB17
AB18
AB19
AB20
AC18
AC19
AC20
AC21
W15
W16
W17
W18
W21
W22
W23
W24
W25
W26
AB10
AB15
AB16
AC8
AC22
AC23
R16
R17
R21
R25
T10
T11
T12
T13
T14
T15
T16
T17
U10
U11
U12
U13
U14
U15
U16
U17
AB2
AB3
AB4
AB5
AB6
AB9
E25
E26
V14
V15
V16
V17
W5
D5
A5
C5
B5
A6
B6
A4
B2
B4
C3
D4
B7
C7
V5
U16C
VSUS15/VSUS25
For Suspend
AVDD1
AGND1
For HT Receive
VCCPLL1/NC#D5
VCCPLL2/NC#A5
GNDPLL1/NC#C5
GNDPLL2/NC#B5
For Graphics
Controller PLL
1&2
VCCPLL3/NC#A6
GNDPLL3/NC#B6
For Graphics
Controller
PLL3
DACAVDD1/NC#A4
DACAVDD2/NC#B2
DACAGND1/NC#B4
DACAGND2/NC#C3
DACAGND3/NC#D4
For DAC
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VSS/NC#B7
VSS/NC#C7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
K8N800
A
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AA4
AA5
AB11
AB12
AB13
AB14
AB7
AB8
M8
N8
T2
T3
T4
T5
T8
T9
U2
U3
U4
U5
U8
U9
V10
V11
V12
V13
V2
V3
V4
V8
V9
W2
W3
W4
W9
Y3
Y4
Y5
AA21
AA22
AA23
AA24
AA25
AA26
AB21
AB22
AB23
AB24
AB25
AB26
F9
H10
H11
H12
H15
H16
H8
H9
J8
K19
L19
M19
P8
R19
R8
T19
U19
V18
V19
W10
W11
W12
W13
W14
W19
Y20
Y21
Y22
Y23
Y24
Y25
Y26
AC24
AE2
AE5
AE8
AE11
AE14
AE17
AE20
AE22
AE25
1D5V_S0
1D5V_S0
Layout trace 20 mil
1D5V_S0
1D5V_S0
3D3V_S0
L4
1 2
GAP-CLOSE-PWR
L24
1 2
GAP-CLOSE-PWR
C617 SC D 1 U
1 2
C612 SCD01U50V3KX
1 2
C564 SC D 1 U
1 2
C568 SCD01U50V3KX
1 2
C571 SC D 1 U
1 2
C613 SCD01U50V3KX
1 2
C610 SC D 1 U
1 2
C611 SC D 1 U
1 2
C560 SC D 1 U
1 2
C557 SC1U10V3ZY
1 2
C558 SC D 1 U
1 2
C559 SC D 1 U
1 2
C565 SC D 1 U
1 2
C608 SC1U10V3ZY
1 2
C556 SC1U10V3ZY
1 2
SC
1D5V_PLL1_S0
12
SC
3D3V_DAC_S03D3V_S0
12
B
C121
SC1000P50V3KX
78.10224.2B1
C518
SC1000P50V3KX
78.10224.2B1
B
12
C122
SC1U10V3ZY
12
C517
SC1U10V3ZY
C
SC SC
1D5V_S0
Note: When use K8T800PRO, these
power circuit for GFX analog
power should be NOT STUFF.
1D5V_PLL2_S0 3D3V_S0
L5
1 2
GAP-CLOSE-PWR
12
C123
SC1000P50V3KX
78.10224.2B1
12
C124
SC1U10V3ZY
NEAR N/B ON BOT SIDE
C609 SCD01U50V3KX
1 2
C614 SCD01U50V3KX
1 2
C615 SCD01U50V3KX
1 2
C606 SCD01U50V3KX
1 2
C601 SC D 1 U
1 2
C600 SC D 1 U
1 2
C191 SC D 1 U
1 2
C174 SC D 1 U
1 2
1D2V_HT0A_S01D5V_S0
C127 SC4D7U10V5ZY
C523 SC1000P50V3KX
1 2
C574 SC1000P50V3KX
1 2
C563 SC D 1 U
1 2
C519 SC D 1 U
1 2
C567 SC D 1 U
1 2
C616 SC D 1 U
1 2
C570 SC D 1 U
1 2
C572 SCD01U50V3KX
1 2
C573 SCD01U50V3KX
1 2
C619 SCD01U50V3KX
1 2
C622 SCD01U50V3KX
1 2
C522 SCD01U50V3KX
1 2
C173 SCD01U50V3KX
1 2
C620 SCD01U50V3KX
1 2
C
78.10224.2B1
78.10224.2B1
L26
1 2
GAP-CLOSE-PWR
1D2V_HT0A_S0
1D5V_S0
3D3VA_S0
12
C575
SC1000P50V3KX
78.10224.2B1
C621 SCD22U16V3ZY
1 2
C569 SC2200P50V3JX
1 2
C649 SC1U10V3ZY
1 2
C653 SC1U10V3ZY
1 2
C655 SC1U10V3ZY
1 2
C654 SC1U10V3ZY
1 2
C657 SC1U10V3ZY
1 2
C604 SCD01U50V3KX
1 2
C605 SCD01U50V3KX
1 2
C647 SCD01U50V3KX
1 2
C652 SCD01U50V3KX
1 2
C602 SCD01U50V3KX
1 2
C176 SCD01U50V3KX
1 2
C566 SCD01U50V3KX
1 2
C603 SCD01U50V3KX
1 2
D
12
C576
SC1U10V3ZY
D
E
3D3V_S03,6,8,11,12,14,15,16,17,18,19,20,21,24,25,26,27,28,30,31,32,33,34,35,36,38,41,47,49,50
1D5V_S012,14 ,15,16,44,50
1D2V_HT0A_S04,11,39,45
3D3V_S518,19,20,21 ,2 2 ,24,28,29,33,38,43,49,50
3D3V_S5
2
VOUT
12
C190
SC1U10V3ZY
Title
Size Document Number Rev
A3
Date: Sheet of
1
NB-K8N800(3/3)_POWER
3
VIN
GND
U66
APL5308-15AC-TR
EGRET
12
C669
SC1U10V3ZY
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
13 50Friday, July 23 , 2004
E
3D3V_S0
1D5V_S0
1D2V_HT0A_S0
3D3V_S5
SC
A
2D5V_S0 2D5V_S0 2D5V_S0 VDDA1VDDA2
12
C166
DY-SCD1U
4 4
12
C164
DY-SCD1U
12
C187
DY-SCD1U
R81
1 2
GAP-CLOSE-PWR
B
SC SC
R346
12
C150
DY-SCD1U
12
C147
DY-SCD1U
12
C148
DY-SCD1U
1 2
GAP-CLOSE-PWR
12
C152
DY-SCD1U
C
12
C555
DY-SCD1U
1D5V_S0
12
C165
DY-SCD1U
3D3V_S0
12
C186
DY-SCD1U
12
C587
DY-SCD1U
D
E
2D5V_S06,12,15,16,19,20,21,38,39,50
3D3V_S03,6,8,11,12,13,15,16,17,18,19,20,21,24,25,26,27,28,30,31,32,33,34,35,36,38,41,47,49,50
1D5V_S012,13 ,15,16,44,50
2D5V_S0
3D3V_S0
1D5V_S0
3D3V_S03D3V_S0
CONF_XLT
12
R99
DY-10KR3
12
R100
DY-10KR3
U14
51
PD15
50
PD14
47
PD13
46
PD12
45
PD11
44
PD10
43
PD9
42
PD8
41
PD7
38
PD6
37
PD5
36
PD4
35
PD3
34
PD2
31
PD1
30
PD0
25
XCLK
28
P_OUT
20
SBC
21
SBD
10
DACA
12
DACB
14
DACC
16
DACD
52
ADDR
7
RSET
19
RESET
53
TE
29
DS
54
CONF_XLT
6
COMP
27
VDDQ
58
VREF
DY-VT1623M-U
Note: Only for K8N800.
When use K8T800PRO,
Please remove them.
AGP_IRDY#12,16
AGP_CBE#112,16
VSYNC
HSYNC
CSO_HSO
VDDA1
VDDA2
VDDA3
VDDA4
VDDA4
VCC25
VCC25
VCC25
VCC25
GNDA1
GNDA2
GNDA3
GNDA4
GNDA4
BCO
VSO
VCC
VCC
VCC
VSS
VSS
VSS
GND
GND
GND
GND
AGP_IRDY#
AGP_CBE#1
1623_VSYNC
22
1623_HSYNC
23
X1
2
XI
X0
3
XO
BCO
61
CSO
57
VSO
60
64
1
5
9
13
3D3V_S0
26
40
56
2D5V_S0
18
32
48
59
63
4
8
11
15
24
39
55
17
33
49
62
12
R96
DY-10KR3
ADDR
12
R125
DY-10KR3
RN8
8
7
6
DY-SRN0-1-U
RN7
8
7
6
DY-SRN0-1-U
RN6
8
7
6
DY-SRN0-1-U
RN5
8
7
6
DY-SRN0-1-U
12
C588
DY-SCD1U
TVD0
1623_HSYNC
TVD6
TVD4
TVD1
TVD2
1623_DS
1623_VSYNC
TVD11
TVD9
TVD10
TVD7
TVD8
TVD3
TVD5
1623_XCLK12
AGP_ADSTB1#12,16
PCIRST_BUF#16,19,33,35,36
R347 DY-10KR3
05/10 For VIA suggest.
VDDA2
1D5V_S0
AGP_SBA212,16
AGP_SBA312,16
AGP_AD2912,16
3 3
2 2
AGP_AD2712,16
AGP_SB_STB12,16
AGP_SB_STB#12,16
AGP_SBA112,16
AGP_SBA012,16
AGP_CBE#312,16
AGP_AD2412,16
AGP_AD2612,16
AGP_AD2812,16
AGP_AD3012,16
AGP_SBA512,16
AGP_SBA412,16
1
2
3
4 5
1
2
3
4 5
R84 DY-0R3-U
1 2
1
2
3
4 5
1
2
3
4 5
LAYOUT: Locate close the AGP connector
1D5V_S0
12
R98
DY-1KR3F
12
R97
DY-1KR3F
1 1
Config as pullup or pulldown
TVD11
TVD10
TVD9
TVD8
TVD7
TVD6
TVD5
TVD4
TVD3
TVD2
TVD1
TVD0
1623_XCLK
1 2
R83 DY-33R3
1623M_TV_COMP
1623M_TV_CRMA
1623M_TV_LUMA
1 2
R82 DY-4K64R3F
1 2
C149 DY-SCD1U
1623_PCLK
SMBC_NB
SMBD_NB
ADDR
1623_RSET
1623_TE
1623_DS
CONF_XLT
1623_COMP
12
1623_VREF1623_VREF
1D5V_S0
2 3
G
1
2 3
S
Q11
DY-FDN337N-U
VDDA1
VDDA2
G
1
D
S
Q9
DY-FDN337N-U
D
AGP_IRDY#
SMBC_NB
SMBD_NB
05/10
For VIA suggest.
Change from 2N7002 to FDN337
AGP_CBE#1
SMBC_NB
SMBD_NB
LAYOUT: Locate close the AGP connector
1 2
X2
DY-XTAL-14D318M-2
12
C151
DY-SC12P
ZZ.12034.1B1
12
C153
DY-SC12P
ZZ.12034.1B1
SC
By KDS suggested change
From 78.39034.1B1
To 78.12034.1B1
VSO
CSO
BCO
12
C167
DY-SC10P
RN10
2
1 4
DY-SRN4D7KJ
ZZ.47236.040
RN12
2
1 4
DY-SRN4D7KJ
ZZ.47236.040
SB
12
C169
DY-SC10P
1D5V_S0
3
3D3V_S0
3
12
C168
DY-SC10P
Wistron Corporation
RN79
AGP_TV_CRMA16,17
AGP_TV_LUMA16,17
AGP_TV_COMP16,17
Close to APG Slot
A
1
2
3
4 5
DY-SRN0-1-U
B
8
7
6
1623M_TV_CRMA
1623M_TV_LUMA
1623M_TV_COMP
Title
Size Document Number Rev
C
D
Date: Sheet
VT1623M-TV Encoder
A3
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
EGRET
E
14 50Friday, July 23 , 2004
SC
of
A
B
C
D
E
2D5V_S0
U6
DE
CLKINP
CLKINM
HSYNC
VSYNC
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
VREF
GND
GND
GND
GND
PLLGND
PLLGND
PLLGND
DGND
DGND
DGND
DGND
LVDSGND
LVDSGND
LVDSGND
LVDSGND
DVDD
DVDD
DVDD
LVDSVCC
LVDSVCC
LVDSVCC
DY-VT1631
12
RN89
1
8
2
7
AGP_AD1912,16
4 4
3 3
AGP_AD2112,16
AGP_DEVSEL#12,16
AGP_FRAME#12,16
AGP_WBF#12,16
AGP_AD1212,16
AGP_AD1012,16
AGP_ADSTB0#12,16
AGP_CBE#012,16
AGP_ADSTB012,16
AGP_AD712,16
AGP_AD612,16
AGP_AD512,16
AGP_AD412,16
AGP_AD312,16
AGP_AD012,16
AGP_AD112,16
AGP_ADSTB112,16
AGP_AD2212,16
AGP_AD2012,16
AGP_AD2312,16
AGP_AD1812,16
AGP_AD1712,16
AGP_AD1612,16
AGP_CBE#212,16
AGP_AD1512,16
AGP_AD1412,16
AGP_AD1312,16
AGP_AD1112,16
3
4 5
DY-SRN22-1
RN75
1
2
3
4 5
DY-SRN22-1
RN90
1
2
3
4 5
DY-SRN22-1
RN93
1
2
3
4 5
DY-SRN22-1
RN94
1
2
3
4 5
DY-SRN22-1
RN85
1
2
3
4 5
DY-SRN22-1
RN92
1
2
3
4 5
DY-SRN22-1
RN91
1
2
3
4 5
DY-SRN22-1
LAYOUT: Locate close the AGP connector
SC
2 2
R287 DY-1KR3
AGP_ST012,16
1 2
2D5V_S0
12
3
1
2
SC
AGP_ST212,16
1 1
AGP_ST112,16
1631_DE
6
1631_CLK
8
1631_VSYNC
7
1631_HSYNC
6
1631_CLK#
LD0
8
LD1
7
LD2
6
LD3
LD4
8
LD5
7
LD6
6
LD7
LD8
8
LD9
7
LD10
6
LD11
LD12
8
LD13
7
LD14
6
LD15
LD16
8
LD17
7
LD18
6
LD19
LD20
8
LD21
7
LD22
6
LD23
R527
DY-2K2R3
1631_PDB
Q48
DY-MMBT3904-U1
G
1
2 3
S
Q7
DY-FDN337N-U
1D5V_S0
G
1
2 3
S
Q8
DY-FDN337N-U
D
12
1D5V_S0
12
12
U98
1
2
3 4
DY-2N7002DW
D
05/10
For VIA suggest.
Change from 2N7002 to FDN337
1631_PDB
6
PWROK#
5
BL_ONAGP_ST2
LCDVDD_ONAGP_ST1
C95
DY-SC10P
R64
DY-10KR3F
R63
DY-10KR3F
PWROK# 18
BL_ON 16,18
LCDVDD_ON 16,18
12
12
C94
DY-SCD1U
C96
DY-SC10P
2D5V_S0
1631_DE
1631_CLK
1631_CLK#
1631_HSYNC
1631_VSYNC
LD0
LD1
LD2
LD3
LD4
LD5
LD6
LD7
LD8
LD9
LD10
LD11
LD12
LD13
LD14
LD15
LD16
LD17
LD18
LD19
LD20
LD21
LD22
LD23
1631_VREF
76
87
88
75
74
94
93
92
91
90
89
86
85
84
83
82
81
8
7
6
5
4
3
2
1
100
99
98
97
78
9
11
52
77
14
15
17
71
80
69
96
25
35
43
51
70
79
95
30
40
48
Note: Only for K8N800.
When use K8T800PRO,
Please remove them.
LAYOUT: Locate close the AGP connector
A
B
C
C57
DY-SCD1U
12
C58
DY-SCD1U
PRE
RESV1
RESV2
GPIO1-1
GPIO2-1
GPIO1-2
GPIO2-2
RESV3
RESV4
I2CSEL
I2CCLK
DSEL/I2CDAT
TST1
TST2
R_FB
PDB
DUAL
MSEN
CLK1P
CLK1M
CLK2P
CLK2M
A7M
A6M
A5M
A4M
A3M
A2M
A1M
A0M
I2CVCC
PLLVCC
PLLVCC
VCC
MODSEL
A7P
A6P
A5P
A4P
A3P
A2P
A1P
A0P
12
12
13
19
20
NC
24
NC
54
NC
58
56
57
55
62
63
A0
64
A1
65
A2
66
61
59
60
72
73
18
22
23
21
41
42
26
27
28
29
31
32
33
34
36
37
38
39
44
45
46
47
49
50
68
10
16
53
67
C92
DY-SCD1U
12
C91
DY-SCD1U
1631_PRE
1631_I2CSEL
1631_I2CDAT
1631_EDGE
1631_PDB
1631_DUAL
1631_MSEN
1631_TXACLK+
1631_TXACLK1631_TXBCLK+
1631_TXBCLK-
A7P_TEST
A7M_TEST
1631_TXBOUT2+
1631_TXBOUT2-
1631_TXBOUT1+
1631_TXBOUT1-
1631_TXBOUT0+
1631_TXBOUT0-
A3P_TEST
A3M_TEST
1631_TXAOUT2+
1631_TXAOUT2-
1631_TXAOUT1+
1631_TXAOUT1-
1631_TXAOUT0+
1631_TXAOUT0-
1631_I2CVCC
2D5V_S0
AGP_ST2
AGP_ST1
BL_ON
LCDVDD_ON
12
C93
DY-SCD1U
R38 DY-4K7R3
1 2
R76 DY-4K7R3
1 2
R77 DY-4K7R3
1 2
1 2
R75
R37 DY-4K7R3
1 2
R35 DY-1KR3
1 2
R33 DY-4K7R3
1 2
R36 DY-4K7R3
1 2
R34 DY-4K7R3
1 2
TP2
TP1
TP4
TP3
C120
DY-SCD1U
DY-4K7R3
12
Close to APG Slot
RN77
2
1 4
DY-SRN10KJ
RN2
2
1 4
DY-SRN10KJ
1D5V_S0
3
3D3V_S0
3
D
2D5V_S0
SC
R35 Change from 4K7R3 to 1KR3
1631_TXBCLK+
1631_TXBCLK1631_TXACLK+
1631_TXACLK-
1631_TXBOUT2+
1631_TXBOUT21631_TXAOUT2+
1631_TXAOUT2-
1631_TXBOUT1+
1631_TXBOUT11631_TXAOUT1+
1631_TXAOUT1-
1631_TXBOUT0+
1631_TXBOUT01631_TXAOUT0+
1631_TXAOUT0-
8
7
6
RN81
DY-SRN0-1-U
8
7
6
RN82
DY-SRN0-1-U
8
7
6
RN87
DY-SRN0-1-U
8
7
6
RN86
DY-SRN0-1-U
Title
VT1631-LVDS Transmitter
Size Document Number Rev
A3
Date: Sheet of
1
2
3
45
1
2
3
45
1
2
3
45
1
2
3
45
EGRET
1D5V_S012,13 ,14,16,44,50
2D5V_S06,12,14,16,19,20,21,38,39,50
3D3V_S03,6,8,11,12,13,14,16,17,18,19,20,21,24,25,26,27,28,30,31,32,33,34,35,36,38,41,47,49,50
AGP_TXBCLK+ 16,18
AGP_TXBCLK- 16,18
AGP_TXACLK+ 16,18
AGP_TXACLK- 16,18
AGP_TXBOUT2+ 16,18
AGP_TXBOUT2- 16,18
AGP_TXAOUT2+ 16,18
AGP_TXAOUT2- 16,18
AGP_TXBOUT1+ 16,18
AGP_TXBOUT1- 16,18
AGP_TXAOUT1+ 16,18
AGP_TXAOUT1- 16,18
AGP_TXBOUT0+ 16,18
AGP_TXBOUT0- 16,18
AGP_TXAOUT0+ 16,18
AGP_TXAOUT0- 16,18
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
15 50Friday, July 23 , 2004
E
1D5V_S0
2D5V_S0
3D3V_S0
SC
A
CN7
MH2
180
178
176
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
174
172
170
168
166
164
162
160
158
156
154
152
150
148
146
144
142
140
138
136
134
132
130
128
126
124
122
120
118
116
114
112
110
108
106
104
102
100
98
96
94
92
90
88
86
84
82
80
78
76
74
72
70
68
66
64
62
60
58
56
54
52
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
MH1
SMC-CONN180A-U
20.F0575.180
SB_GPI621
SB_GPO520
AGP_BUSY#
AGP_STP#
5V_S0
2D5V_S0
AGP_PAR
AGP_STOP#
AGP_TRDY#
AGP_FRAME#
AGP_WBF#
AGP_ST1
INT_PIRQA#
AGP_GNT#
AGP_ST0
AGP_ST2
BL_ON
LCDVDD_ON
AGP_CRT_R
AGP_CRT_B
AGP_CRT_G
AGP_TXBOUT3+
AGP_TXBOUT3-
AGP_TXBCLK+
AGP_TXBCLK-
AGP_TXBOUT2+
AGP_TXBOUT2-
AGP_TXBOUT1+
AGP_TXBOUT1-
AGP_TXBOUT0AGP_TXBOUT0+
AGP_SBA6
AGP_SBA7
AGP_SBA4
AGP_SBA5
AGP_DBIH
AGP_DBIL
AGP_AD30
AGP_AD28
AGP_AD26
AGP_AD24
AGP_ADSTB1#
AGP_ADSTB1
AGP_CBE#3
AGP_AD22
AGP_AD20
AGP_AD18
AGP_AD16
AGP_AD13
AGP_AD11
AGP_AD9
AGP_CBE#0
AGP_ADSTB0
AGP_ADSTB0#
AGP_AD2
AGP_AD0
VGA_CARD_IN#
VGA_ID1
VGA_ID0
PM_SLP_S3#
2D5V_S0
2D5V_S0
2D5V_S0
2D5V_S0
2D5V_S0
2D5V_S0
2D5V_S0
2D5V_S0
DCBATOUT
AGP_PAR12
AGP_STOP#12
AGP_TRDY#12
4 4
3 3
2 2
1 1
AGP_FRAME#12,15
AGP_WBF#12,15
INT_PIRQA#12,19 PCIRST_BUF# 14,19,33,35,36
AGP_GNT#12
BL_ON15,18
LCDVDD_ON15,18
AGP_CRT_R12,17
AGP_CRT_B12,17
AGP_CRT_G12,17
AGP_TXBCLK+15,18
AGP_TXBCLK-15,18
AGP_TXBOUT2+15,18
AGP_TXBOUT2-15,18
AGP_TXBOUT1+15,18
AGP_TXBOUT1-15,18
AGP_TXBOUT0-15,18
AGP_TXBOUT0+15,18
AGP_DBIH12
AGP_DBIL12
AGP_ADSTB1#12,14
AGP_ADSTB112,15
AGP_ADSTB012,15
AGP_ADSTB0#12,15
VGA_CARD_IN#36
VGA_ID136
VGA_ID036
PM_SLP_S3#19,33,38,39,43,44
Debug only do not stuff
A
B
179
1D25V_S01D5V_S0
177
GND
175
GND
173
GND
171
169
167
AGP_DEVSEL#
165
GND
163
PM_SUS_STAT#
161
AGP_RBF#
159
AGP_IRDY#
157
AGP_REQ#
155
A_RST#_AGP
153
AGP_MBDET#
151
GND
149
AGP_JVGA_VS
147
AGP_JVGA_HS
145
GND
143
AGP_TV_CRMA
141
AGP_TV_LUMA
139
AGP_TV_COMP
137
GND
135
AGP_DAT_DDC_3
133
AGP_CLK_DDC_3
131
GND
129
GND
127
GND
125
AGP_TXAOUT3+
123
AGP_TXAOUT3-
121
GND
119
AGP_TXACLK+
117
AGP_TXACLK-
115
113
AGP_TXAOUT2+
111
AGP_TXAOUT2-
109
107
AGP_TXAOUT0+
105
AGP_TXAOUT0-
103
101
AGP_TXAOUT1+
99
AGP_TXAOUT1-
97
95
93
AGP_SB_STB
91
AGP_SB_STB#
89
AGP_SBA1
87
AGP_SBA0
85
AGP_SBA2
83
AGP_SBA3
81
GND
79
AGP_AD31
77
AGP_AD29
75
AGP_AD27
73
AGP_AD25
71
GND
69
AGP_AD23
67
AGP_AD21
65
AGP_AD19
63
AGP_AD17
61
AGP_CBE#2
59
GND
57
AGP_AD15
55
AGP_CBE#1
53
AGP_AD14
51
AGP_AD12
49
AGP_AD10
47
AGP_AD8
45
GND
43
AGP_AD6
41
AGP_AD7
39
AGP_AD4
37
AGP_AD5
35
AGP_AD3
33
AGP_AD1
31
GND
29
CLK66_VGA
27
25
23
GND
21
GND
19
GND
17
GND
15
GND
13
GND
11
GND
9
GND
7
5
3
By ME requset for
12
Discrete CN7 P/N:
Main 20.F0575.180
Second 20.F0498.180
SC
1 2
R24 DY-0R3-U
1 2
R23 DY-0R3-U
B
AGP_BUSY#
AGP_STP#
AGP_DEVSEL# 12,15
PM_SUS_STAT# 12,20,33
AGP_RBF# 12
AGP_IRDY# 12,14
AGP_REQ# 12
AGP_MBDET# 12
AGP_JVGA_VS 12,17
AGP_JVGA_HS 12,17
AGP_TV_CRMA 14,17
AGP_TV_LUMA 14,17
AGP_TV_COMP 14,17
AGP_TXACLK+ 15,18
AGP_TXACLK- 15,18
AGP_TXAOUT2+ 15,18
AGP_TXAOUT2- 15,18
AGP_TXAOUT0+ 15,18
AGP_TXAOUT0- 15,18
AGP_TXAOUT1+ 15,18
AGP_TXAOUT1- 15,18
AGP_SB_STB 12,14
AGP_SB_STB# 12,14
CLK66_VGA 3
3D3V_S0
R39
1 2
33R3
3D3V_S0
12
C
C426
SC10U10V5ZY
78.10693.411
C
3D3V_S0
12
12
AGP_AD[31..0] 12,14,15
AGP_CBE#[3..0] 12,14,15
AGP_ST[2..0] 12,15
AGP_SBA[7..0] 12,14
12
C644
SCD1U
AGP_DAT_DDC_312
VGA_CLK_DDC_317
R270
1K62R3F
64.16215.651
AGP_1D25V_VREF
12
R271
1KR3F
64.10015.651
SC
C427
SCD1U
78.10492.4B1
D
3D3V_S0 1D5V_S0
12
C189
SCD1U
12
C591
SCD1U
DDC_CLK & DATA level shift
AGP_DAT_DDC_3
AGP_CLK_DDC_3
AGP_DAT_DDC_3
VGA_CLK_DDC_3
1
2
3 4
5V @ ext. CRT side
1D25V_S0
Iomax=1.5A
3D3V_S0
12
C460
SCD1U
U45
VIN1VOUT
3
VREF
VCNTL6NC
2
GND
9
GND
APL5331KAC-TR
SO-8-P
4
8
7
NC
5
NC
D
12
1 4
2
3D3V_S0
U48
2N7002DW
C590
SCD1U
RN4
SRN10KJ
6
5
1D25V_S0
E
DCBATOUT1 8 ,3 8 , 41 , 43,44,45,46,47,50
1D5V_S012,13 ,14,15,44,50
5V_S017,18,19,20,21,22,23,24,27,30,31,32,33,34,37,38,39,41,42,47,48,49,50
3D3V_S03,6,8,11,12,13,14,15,17,18,19,20,21,24,25,26,27,28,30,31,32,33,34,35,36,38,41,47,49,50
2D5V_S06,12,14,15,19,20,21,38,39,50
5V_S0DCBATOUT
12
C170
SCD1U
3D3V_S0
3
VGA_DAT_DDC_3
AGP_CLK_DDC_3
12
C424
SCD1U
VGA_DAT_DDC_3 17
AGP_CLK_DDC_3 12
SB
KEMET,NT:5.7, B2 size
SC
ST100U4VBM-1 (80.10716.321)
12
TC7
ST100U4VBM-1
Title
Size Document Number Rev
Date: Sheet of
Iripple=1.1A,ESR=70mohm
SANYO, NT$:6.1
Iripple=1.1A,ESR=70mohm
3.5/2.8/2.0
77.21071.031
A3
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Graphic Conn.
EGRET
16 50Friday, July 23 , 2004
E
DCBATOUT
1D5V_S0
5V_S0
3D3V_S0
2D5V_S0
SC