Wistron Calado, Aspire 2420, Aspire 2920Z Schematic
A
B
C
D
E
Project code: 91.4X401.001
Calado Block Diagram
PCB P/N : 07227
REVISION : -1
4 4
CLK GEN.
3
RTM875T-605 71.00875.C0W
(ICS 9LPRS502 71.09502.B0W)
DDR2
533/667MHz
533/667 MHz
12,13
DDR2
3 3
533/667 MHz
12,13
533/667MHz
Mobile CPU
Merom 479
Celeron M
2.0G : 71.MEROM.A0U
2.33G : 71.MEROM.B0U
HOST BUS
667/800MHz@1.05V
Intel GM965/GL960
AGTL+ CPU I/F
DDR Memory I/F
INTEGRATED GRAHPICS
LVDS, CRT I/F
71.GL960.00U, SLA5V
X4 DMI
400MHz
4, 5
6,7,8,9,10,11
C-Link0
G792
GM965 : KI.96501.008
GL960 :KI.96501.010
20
SVIDEO/COMP
LVDS
RGB CRT
TVOUT
14" WXGA
LCD
CRT
15
14
15
PCB STACKUP
TOP
VCC
S
S
GND
BOTTOM
SYSTEM DC/DC
TPS51120
INPUTS
DCBATOUT
OUTPUTS
5V_S5(6A)
3D3V_S5(6A)
SYSTEM DC/DC
TPS51124
INPUTS OUTPUTS
DCBATOUT
TPS51100(G2997)
1D8V_S3
1D05V_S0(8A)
1D8V_S3(12A)
DDR_VREF_S0
(1.5A)
DDR_VREF_S3
33
34
35
Codec
ALC268
MIC In
25
INT.MIC(Digital)
25
2 2
OP AMP
APA2031
INT.SPKR
OP AMP
G1412
Line Out
26
27
27
AZALIA
ICH8M
6 PCIe ports
PCI/PCI BRIDGE
ACPI 1.1
3 SATA
1 PATA 66/100
10 USB 2.0/1.1 ports
ETHERNET (10/100/1000MbE)
High Definition Audio
LPC I/F
Serial Peripheral I/F
Matrix Storage Technology(DO)
Active Managemnet Technology(DO)
PCIex1
LPC BUS
(No-SPDIF)
RJ11
22
MODEM
MDC Card
21
71.ICH8M.C0U, SLA5Q, B3
ICH8 : 71.80101.024
16,17,18,19
Touch
Pad
USB
3 PORT
USB
USB 5in1
21
Cardreader
SATA
1 1
HDD
21
PATA
CDROM
21
GIGA LAN
BCM5787MKMLG
Mini Card
New card
KBC
Winbond
WPC8763L
INT.
KB
29 29
abgn/bg
28
22
24
24 24
SPI I/F
PWR BD
07563
25
RTS5158
TXFM RJ45
PWR SW
P2231NFC
BIOS
W25X80-VSS
29
BT
24
LPC
DEBUG
CONN.
2323
36
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet
Date: Sheet
BLOCK DIAGRAM
BLOCK DIAGRAM
BLOCK DIAGRAM
APL5913
1D8V_S3 1D25V_S0
G909
5V_AUX_S5 3D3V_AUX_S5
APL5915
1D8V_S3 1D5V_S0
CHARGER
DCBATOUT
CPU DC/DC
INPUTS
DCBATOUT
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Calado
Calado
Calado
(1.5A)
(100mA)
(1.5A)
MAX8731
OUTPUTSINPUTS
CHG_PWR
18V 4.0A
UP+5V
5V 100mA
MAX8770
OUTPUTS
VCC_CORE_S0
0~1.3V
47A
139Thursday, September 13, 2007
139Thursday, September 13, 2007
139Thursday, September 13, 2007
35
28
35
36
32
-1
-1
of
of
-1
A
B
C
D
E
ICH8M Functional Strap Definitions
Signal
HDA_SDOUT
HDA_SYNC
4 4
GNT2#
GPIO20
GNT1#/
GPIO51
GNT3#
GNT0#/
SPI_CS1#
INTVRMEN
3 3
LAN100_SLP
SATALED#
SPKR
TP3
GPIO33/
HDA_DOCK
_EN#
Usage/When Sampled
XOR Chain Entrance/
PCIE Port Config1 bit1,
Rising Edge of PWROK
PCIE config1 bit0,
Rising Edge of PWROK.
PCIE config2 bit0,
Rising Edge of PWROK.
Reserved
ESI Strap (Server Only)
Rising Edge of PWROK
Top-Block
Swap Override.
Rising Edge of PWROK.
Boot BIOS Destination
Selection.
Rising Edge of PWROK.
Integrated VccSus1_05,
VccSus1_5 and VccCL1_5
VRM Enable/Disable.
Always sampled.
Integrated VccLAN1_05
and VccCL1_05 VRM
Enable/Disable.
Always sampled.
PCI Express Lane
Reversal. Rising Edge
of PWROK.
No Reboot.
Rising Edge of PWROK.
XOR Chain Entrance.
Rising Edge of PWROK.
Flash Descriptor
Security Override Strap
Rising Edge of PWROK
Allows entrance to XOR Chain testing when TP3
pulled low.When TP3 not pulled low at rising edge
of PWROK,sets bit1 of RPC.PC(Config Registers:
offset 224h)
This signal has a weak internal pull-down.
Sets bit0 of RPC.PC(Config Registers:Offset 224h)
This signal has a weak internal pull-up.
Sets bit2 of RPC.PC2(Config Registers:Offset 0224h)
This signal should not be pulled high.
ESI compatible mode is for server platforms only.
This signal should not be pulled low for desttop
and mobile.
Sampled low:Top-Block Swap mode(inverts A16 for
all cycles targeting FWH BIOS space).
Note: Software will not be able to clear the
Top-Swap bit until the system is rebooted
without GNT3# being pulled down.
Controllable via Boot BIOS Destination bit
(Config Registers:Offset 3410h:bit 11:10).
GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC.
Enables integrated VccSus1_05, VccSus1_5 and
VccCL1_5 VRM's when sampled high
Enables integrated VccLAN1_05 and VccCL1_05 VRM's
when sampled high
Signal has weak internal pull-up. Sets bit 27
of MPC.LR(Device 28:Function 0:Offset D8)
If sampled high, the system is strapped to the
"No Reboot" mode(ICH8 will disable the TCO Timer
system reboot feature). The status is readable
via the NO REBOOT bit.
This signal should not be pull low unless using
XOR Chain testing.
This signal has a weak internal pull-up.
Sampled low:the Flash Descriptor Security will be
overridden. If high,the security measures will be
in effect.This should only be used in manufacturing
environments.
ICH8-M EDS 21762 2.0V1
Comment
page 16
ICH8M Integrated Pull-up
and Pull-down Resistors
SIGNAL Resistor Type/Value
HDA_BIT_CLK
HDA_RST#
HDA_SDIN[3:0]
HDA_SDOUT
HDA_SYNC
GNT[3:0]
GPIO[20]
LDA[3:0]#/FHW[3:0]#
LAN_RXD[2:0]
LDRQ[0]
LDRQ[1]/GPIO23
PME#
PWRBTN#
SATALED#
SPI_CS1#
SPI_CLK
SPI_MOSI
SPI_MISO
TACH_[3:0]
SPKR
TP[3]
USB[9:0][P,N]
CL_RST#
ICH8-M EDS 21762 2.0V1
PULL-DOWN 20K
NONE
PULL-DOWN 20K
PULL-DOWN 20K
PULL-DOWN 20K
PULL-UP 20K
PULL-DOWN 20K ?
PULL-UP 20K
PULL-UP 10K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 15K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K ?
PULL-DOWN 20K
PULL-UP 20K
PULL-DOWN 15K
PULL-UP 13K
History
Crestline Strapping Signals and
Configuration
Pin Name
CFG[2:0]
CFG[4:3]
CFG5
CFG9
CFG[11:10] Reserved
CFG[13:12]
CFG[15:14]
CFG16
CFG[18:17]
CFG19
CFG20
SDVOCRTL
_DATA
All strap signals are sampled with respect to the leading
NOTE:
Strap Description
FSB Frequency Select
Reserved
DMI x2 Select
ReservedCFG[8:6]
Low Power PCI Express
PCI Express Graphics
Lane Reversal
XOR/ALL Z test
straps
Reserved
FSB Dynamic ODT
Reserved
DMI Lane Reversal
SDVO/PCIE
Concurrent
SDVO Present
edge of the Crestline GMCH PWORK in signal.
001 = FSB533
011 = FSB667
010 = FSB800
others = Reserved
0 = DMI x2
1 = DMI x4
0 = Normal mode
1 = Low Power mode
0 = Reverse Lanes,15->0,14->1 ect..
1= Normal operation(Default):Lane
Numbered in order
00 = Reserved
01 = XOR mode enabled
10 = All Z mode enabled
11 = Normal Operation
0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled
0 = Normal operation (Default):lane
Numbered in order
1 =Reverse Lane,4->0,3->1 ect...
0 = Only SDVO or PCIE x1 is
operational (Default)
1 =SDVO and PCIE x1 are operating
simultaneously via the PEG port
0 = No SDVO Card present
1= SDVO Card present
Crestline EDS 20954 1.0
Configuration
(Default)
(Default)
Reserved
page 7
(Default)
(Default)
(Default)
2 2
ICH8M IDE Integrated Series
Termination Resistors
DIOR#,DIOW#,DD[15:0],
DDACK#, IORDY,
DCS3#,
IDEIRQ
DA[2:0],
DREQ,
DCS1#,
approximately 33 ohm
USB Table
PCIE Routing
LANE1
LANE2
LANE3 NewCard WLAN
1 1
LAN Marvell
MiniCard WLAN
USB
Pair
0
1
2
3
4
5
6
7
8
9 NEW1
Device
USB1
NC
USB2
NC
USB3
BT
Cardreader
MINICARD
CCD
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet of
Date: Sheet of
Reference
Reference
Reference
Volvi2
Volvi2
Volvi2
of
239Monday, September 10, 2007
239Monday, September 10, 2007
239Monday, September 10, 2007
-1
-1
-1
3D3V_S0
0R0603-PAD
0R0603-PAD
1 2
R72
R72
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
3D3V_48MPWR_S0 3D3V_CLKPLL_S0
C223
C223
12
DY
DY
A
12
C218
C218
SC1U16V3ZY-GP
SC1U16V3ZY-GP
12
C495
C495
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C493
C493
SC4D7U10V5ZY-3GP
SC4D7U10V5ZY-3GP
B
12
C498
C498
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C492
C492
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C491
C491
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C
R71
R71
0R0603-PAD
0R0603-PAD
1 2
12
C488
C488
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
3D3V_S0
12
C507
C507
DY
DY
SC4D7U10V5ZY-3GP
SC4D7U10V5ZY-3GP
D
12
C490
C490
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C496
C496
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
3D3V_CLKGEN_S0
12
C506
C506
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
E
R339
R339
0R0603-PAD
0R0603-PAD
1 2
12
C500
C500
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
3D3V_S0
4 4
DY
R334
R334
10KR2J-3-GP
10KR2J-3-GP
PCLKCLK2
PCLKCLK3
PCLKCLK4
PCLKCLK5
3 3
1 2
DY
DY
R331
R331
10KR2J-3-GP
10KR2J-3-GP
1 2
DY
R336
R336
10KR2J-3-GP
10KR2J-3-GP
1 2
RTM
RTM
R333
R333
10KR2J-3-GP
10KR2J-3-GP
1 2
DY
DY
R325
R325
10KR2J-3-GP
10KR2J-3-GP
1 2
R322
R322
10KR2J-3-GP
10KR2J-3-GP
1 2
3D3V_S0
DY
DY
R321
R321
10KR2J-3-GP
10KR2J-3-GP
1 2
R326
R326
10KR2J-3-GP
10KR2J-3-GP
1 2
CL=20pF±0.2pF
C236
C236
SC27P50V2JN-2-GP
SC27P50V2JN-2-GP
1 2
1 2
C235
C235
SC27P50V2JN-2-GP
SC27P50V2JN-2-GP
GEN_XTAL_IN
12
X4
X4
X-14D31818M-44GP
X-14D31818M-44GP
82.30005.951
82.30005.951
GEN_XTAL_OUT_R
PCLK_KBC28
PCLK_ICH17
R91 10MR2J-L-GP
R91 10MR2J-L-GP
R90 0R0402-PADR90 0R0402-PAD
DY
DY
1 2
CLK48_ICH17
CPU_SEL04,7
CPU_SEL14,7
CPU_SEL24,7
CLK_ICH1417
12
3D3V_CLKGEN_S0
3D3V_48MPWR_S0
3D3V_CLKPLL_S0
TP142TPAD30 TP142TPAD30
TP141TPAD30 TP141TPAD30
TP169TPAD30 TP169TPAD30
R320 22R2J-2-GPR320 22R2J-2-GP
R323 22R2J-2-GPR323 22R2J-2-GP
R327 22R2J-2-GPR327 22R2J-2-GP
R324 2K2R2J-2-GPR324 2K2R2J-2-GP
R332 2K2R2J-2-GPR332 2K2R2J-2-GP
R335 22R2J-2-GPR335 22R2J-2-GP
GEN_XTAL_OUT
12
12
12
12
12
12
PCLKCLK0
PCLKCLK1
PCLKCLK2
PCLKCLK3
PCLKCLK4
PCLKCLK5
CLK48
CPU_SEL2_R
CPU_SEL2_R
U15
U15
2
VDDPCI
9
VDD48
16
VDD
53
VDDREF
31
VDDSRC
47
VDDCPU
12
VDD96I/O
20
VDDPLL3I/O
26
VDDSRCI/O
37
VDDSRCI/O
41
VDDCPUI/O
1
PCICLK0/CR#_A
3
PCICLK1/CR#_B
4
PCICLK2/LTE
5
PCICLK3
6
PCICLK4/SRC5_EN
7
PCI_F5/ITP_EN
51
X2
52
X1
10
USB_48MHZ/FSLA
49
FSLB/TEST_MODE
54
FSLC/TEST_SEL/REF0
8
GNDPCI
11
GND48
15
GND
19
GND
23
GNDSRC
34
GNDSRC
44
GNDCPU
50
GNDREF
ICS9LPRS502PGLFT-GP
ICS9LPRS502PGLFT-GP
71.09502.B0W
71.09502.B0W
SDATA
SCLK
DOTT_96/SRCCLKT0
DOTC_96/SRCCLKC0
SRCCLKT1/SE1
SRCCLKC1/SE2
SRCCLKT2/SATACLKT
SRCCLKC2/SATACLKC
SRCCLKT3/CR#_C
SRCCLKC3/CR#_D
SRCCLKT4
SRCCLKC4
PCI_STOP#/SRCCLKT5
CPU_STOP#/SRCCLKC5
SRCCLKT6
SRCCLKC6
SRCCLKT7/CR#_F
SRCCLKC7/CR#_E
CPUCLKT2_ITP/SRCCLKT8
CPUCLKC2_ITP/SRCCLKC8
CPUCLKT1
CPUCLKC1
CPUCLKT0
CPUCLKC0
CK_PWRGD/PD#
NC#40
55
56
13
14
17
18
21
22
24
25
27
28
30
29
33
32
36
35
39
38
43
42
46
45
48
40
SMBD_ICH 12,19
SMBC_ICH 12,19
R330
R330
1 2
DY
DY
10KR2J-3-GP
10KR2J-3-GP
PM_STPPCI# 17
PM_STPCPU# 17
CLK_PWRGD 17
DREFCLK 7
DREFCLK# 7
CLK_PCIE_NEW 24
CLK_PCIE_NEW# 24
CLK_PCIE_SATA 16
CLK_PCIE_SATA# 16
CLK_MCH_3GPLL 7
CLK_MCH_3GPLL# 7
CLK_PCIE_MINI1 24
CLK_PCIE_MINI1# 24
CLK_PCIE_ICH 17
CLK_PCIE_ICH# 17
DREFSSCLK 7
DREFSSCLK# 7
CLK_PCIE_LAN 22
CLK_PCIE_LAN# 22
CLK_MCH_BCLK 6
CLK_MCH_BCLK# 6
CLK_CPU_BCLK 4
CLK_CPU_BCLK# 4
3D3V_CLKGEN_S0
RTM:71.00875.C0W
PCLK_KBC
2 2
CLK48_ICH
1 2
SC22P50V3JN-GP
SC22P50V3JN-GP
DY
DY
1 2
SC22P50V3JN-GP
SC22P50V3JN-GP
DY
DY
EC105
EC105
EC106
EC106
EMI capacitor
ICS9LPR502HGLFT-GP setting table
PIN NAME DESCRIPTION
Byte 5, bit 7
0 = PCI0 enabled (default)
PCI0/CR#_A
PCI1/CR#_B
1 1
PCI2/TME
PCI4/SRC5_EN
PCI_F5/ITP_EN
1= CR#_A enabled. Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair
Byte 5, bit 6
0 = CR#_A controls SRC0 pair (default),
1= CR#_A controls SRC2 pair
Byte 5, bit 5
0 = PCI1 enabled (default)
1= CR#_B enabled. Byte 5, bit 6 controls whether CR#_B controls SRC1 or SRC4 pair
Byte 5, bit 4
0 = CR#_B controls SRC1 pair (default)
1= CR#_B controls SRC4 pair
0 = Overclocking of CPU and SRC Allowed
1 = Overclocking of CPU and SRC NOT allowed
0 = Pin29 as CPU_STOP# , pin 30 as PCI_STOP#.
1 = Pins29,30 as SRC-5 differential pair.
0 =SRC8/SRC8#
1 = ITP/ITP#
A
B
RTM875T-605 setting table
PIN NAME
PCI0/CR#_A
PCI1/CR#_B
PCI2/TME
PCI3/SRC-5_EN
PCI4/27M_SEL
PCI_F5/ITP_EN
DESCRIPTION
Byte 5, bit 7
0 = PCI0 enabled (default)
1= CR#_A enabled. Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair
Byte 5, bit 6
0 = CR#_A controls SRC0 pair (default),
1= CR#_A controls SRC2 pair
Byte 5, bit 5
0 = PCI1 enabled (default)
1= CR#_B enabled. Byte 5, bit 6 controls whether CR#_B controls SRC1 or SRC4 pair
Byte 5, bit 4
0 = CR#_B controls SRC1 pair (default)
1= CR#_B controls SRC4 pair
0 = Overclocking of CPU and SRC Allowed
1 = Overclocking of CPU and SRC NOT allowed
0 = Pin29 as CPU_STOP# , pin 30 as PCI_STOP#.
1 = Pins29,30 as SRC-5 differential pair.
0 = Pin17 as SRC-1, Pin18 as SRC-1#, Pin13 as DOT96, Pin14 as DOT96#
1 = Pin17 as 27MHz, Pin 18 as 27MHz_SS, Pin13 as SRC-0, Pin14 as SRC-0#
0 =SRC8/SRC8#
1 = ITP/ITP#
C
SEL2
FSC
SEL1
FSB
1
0
0101
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
D
Date: Sheet of
Clock Generator
Clock Generator
Clock Generator
SEL0
FSA
01
01
01
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Calado
Calado
Calado
E
CPU
100M
133M
166M
200M
339Wednesday, September 12, 2007
339Wednesday, September 12, 2007
339Wednesday, September 12, 2007
FSB
X
X
667M
800M
-1
-1
of
of
-1
A
B
C
D
E
H_A#[35..3]6
4 4
H_ADSTB#06
H_REQ#[4..0]6
3 3
H_ADSTB#16
H_A20M#16
H_FERR#16
H_IGNNE#16
H_STPCLK#16
H_INTR16
H_NMI16
H_SMI#16
2 2
H_A#[35..3]
1 OF 4
1 OF 4
U44A
U44A
H_A#3
J4
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
RSVD_CPU_B1 TEST6
TP76TPAD30 TP76TPAD30
A3#
L5
A4#
L4
A5#
K5
A6#
M3
A7#
N2
A8#
J1
A9#
N3
A10#
P5
A11#
P2
A12#
L2
A13#
P4
A14#
P1
A15#
R1
A16#
M1
ADSTB0#
K3
REQ0#
H2
REQ1#
K2
REQ2#
J3
REQ3#
L1
REQ4#
Y2
A17#
U5
A18#
R3
A19#
W6
A20#
U4
A21#
Y5
A22#
U1
A23#
R4
A24#
T5
A25#
T3
A26#
W2
A27#
W5
A28#
Y4
A29#
U2
A30#
V4
A31#
W3
A32#
AA4
A33#
AB2
A34#
AA3
A35#
V1
ADSTB1#
A6
A20M#
A5
FERR#
C4
IGNNE#
D5
STPCLK#
C6
LINT0
B4
LINT1
A3
SMI#
M4
RSVD#M4
N5
RSVD#N5
T2
RSVD#T2
V3
RSVD#V3
B2
RSVD#B2
C3
RSVD#C3
D2
RSVD#D2
D22
RSVD#D22
D3
RSVD#D3
F6
RSVD#F6
B1
KEY_NC
BGA479-SKT6-GPU3
BGA479-SKT6-GPU3
ADDR GROUP 0
ADDR GROUP 0
ADDR GROUP 1
ADDR GROUP 1
ICH
ICH
RESERVED
RESERVED
62.10079.001
62.10079.001
XDP/ITP SIGNALS CONTROL
XDP/ITP SIGNALS CONTROL
THERMAL
THERMAL
PROCHOT#
THERMTRIP#
HCLK
HCLK
ADS#
BNR#
BPRI#
DEFER#
DRDY#
DBSY#
BR0#
IERR#
INIT#
LOCK#
RESET#
RS0#
RS1#
RS2#
TRDY#
HIT#
HITM#
BPM0#
BPM1#
BPM2#
BPM3#
PRDY#
PREQ#
TCK
TDO
TMS
TRST#
DBR#
THRMDA
THRMDC
BCLK0
BCLK1
H1
E2
G5
H5
F21
E1
F1
D20
B3
H4
C1
F3
F4
G3
G2
G6
E4
AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
TDI
AB3
AB5
AB6
C20
D21
A24
B25
C7
A22
A21
H_RS#0
H_RS#1
H_RS#2
XDP_BPM#5
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
XDP_DBRESET#
PM_THRMTRIP#
should connect to
ICH8 and MCH
without T-ing
( No stub)
TP35 TPAD30TP35 TPAD30
H_ADS# 6
H_BNR# 6
H_BPRI# 6
H_DEFER# 6
H_DRDY# 6
H_DBSY# 6
H_BREQ#0 6
H_IERR#
H_INIT# 16
H_LOCK# 6
H_CPURST# 6,38
H_TRDY# 6
H_HIT# 6
H_HITM# 6
TP72 TPAD30TP72 TPAD30
TP65 TPAD30TP65 TPAD30
TP61 TPAD30TP61 TPAD30
TP70 TPAD30TP70 TPAD30
TP64 TPAD30TP64 TPAD30
TP62 TPAD30TP62 TPAD30
TP37 TPAD30TP37 TPAD30
CPU_PROCHOT#_R
H_THERMDA 20
H_THERMDC 20
CLK_CPU_BCLK 3
CLK_CPU_BCLK# 3
1D05V_S0
12
R34
R34
56R2J-4-GP
56R2J-4-GP
Place testpoint on
H_IERR# with a GND
0.1" away
H_RS#[2..0] 6
1D05V_S0
12
R33
R33
56R2J-4-GP
56R2J-4-GP
PM_THRMTRIP-A# 7,16,30
Layout Note:
"CPU_GTLREF0"
0.5" max length.
H_THERMDA
H_THERMDC
R280
R280
2KR2F-3-GP
2KR2F-3-GP
1D05V_S0
1 2
12
12
C443
C443
SC2200P50V2KX-2GP
SC2200P50V2KX-2GP
R279
R279
1KR2F-3-GP
1KR2F-3-GP
H_DSTBN#06
H_DSTBP#06
H_DINV#06
CPU_GTLREF0
2nd source: 62.10053.401
1D05V_S0
XDP_TMS
XDP_TDI
R58 39R2F-GPR58 39R2F-GP
1 2
R56 150R2F-1-GPR56 150R2F-1-GP
1 2
2 OF 4
2 OF 4
U44B
U44B
H_D#0
E22
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_DSTBN#16
H_DSTBP#16
H_DINV#16
TP24TPAD30 TP24TPAD30
TP77TPAD30 TP77TPAD30
TP23TPAD30 TP23TPAD30
CPU_SEL03,7
CPU_SEL13,7
CPU_SEL23,7
Net "TEST4" as short as possible,
make sure "TEST4" routing is
reference to GND and away other
noisy signals
H_D#31
TEST4
TEST5
D0#
F24
D1#
E26
D2#
G22
D3#
F23
D4#
G25
D5#
E25
D6#
E23
D7#
K24
D8#
G24
D9#
J24
D10#
J23
D11#
H22
D12#
F26
D13#
K22
D14#
H23
D15#
J26
DSTBN0#
H26
DSTBP0#
H25
DINV0#
N22
D16#
K25
D17#
P26
D18#
R23
D19#
L23
D20#
M24
D21#
L22
D22#
M23
D23#
P25
D24#
P23
D25#
P22
D26#
T24
D27#
R24
D28#
L25
D29#
T25
D30#
N25
D31#
L26
DSTBN1#
M26
DSTBP1#
N24
DINV1#
AD26
GTLREF
C23
TEST1
D25
TEST2
C24
TEST3
AF26
TEST4
AF1
TEST5
A26
TEST6
B22
BSEL0
B23
BSEL1
C21
BSEL2
BGA479-SKT6-GPU3
BGA479-SKT6-GPU3
DATA GRP0 DATA GRP1
DATA GRP0 DATA GRP1
MISC
MISC
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
DATA GRP2DATA GRP3
DATA GRP2DATA GRP3
D43#
D44#
D45#
D46#
D47#
DSTBN2#
DSTBP2#
DINV2#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
DSTBN3#
DSTBP3#
DINV3#
COMP0
COMP1
COMP2
COMP3
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PSI#
H_DINV#[3..0]
H_DSTBN#[3..0]
H_DSTBP#[3..0]
H_D#[63..0]
H_D#32
Y22
H_D#33
AB24
H_D#34
V24
H_D#35
V26
H_D#36
V23
H_D#37
T22
H_D#38
U25
H_D#39
U23
H_D#40
Y25
H_D#41
W22
H_D#42
Y23
H_D#43
W24
H_D#44
W25
H_D#45
AA23
H_D#46
AA24
H_D#47
AB25
Y26
AA26
U22
H_D#48
AE24
H_D#49
AD24
H_D#50
AA21
H_D#51
AB22
H_D#52
AB21
H_D#53
AC26
H_D#54
AD20
H_D#55
AE22
H_D#56
AF23
H_D#57
AC25
H_D#58
AE21
H_D#59
AD21
H_D#60
AC22
H_D#61
AD23
H_D#62
AF22
H_D#63
AC23
AE25
AF24
AC20
COMP0
R26
U26
AA1
Y1
E5
B5
D24
D6
D7
AE6
R277 27D4R2F-L1-GPR277 27D4R2F-L1-GP
COMP1
R278 54D9R2F-L1-GPR278 54D9R2F-L1-GP
COMP2
R64 27D4R2F-L1-GPR64 27D4R2F-L1-GP
COMP3
R65 54D9R2F-L1-GPR65 54D9R2F-L1-GP
Layout Note:
Comp0, 2 connect with Zo=27.4 ohm, make
trace length shorter than 0.5" .
Comp1, 3 connect with Zo=55 ohm, make
trace length shorter than 0.5" .
H_DINV#[3..0] 6
H_DSTBN#[3..0] 6
H_DSTBP#[3..0] 6
H_D#[63..0] 6
H_DSTBN#2 6
H_DSTBP#2 6
H_DINV#2 6
H_DSTBN#3 6
H_DSTBP#3 6
H_DINV#3 6
1 2
1 2
1 2
1 2
H_DPRSTP# 7,16,32
H_DPSLP# 16
H_DPWR# 6
H_PWRGD 16,30,38
H_CPUSLP# 6
PSI# 32
1 1
XDP_TCK
XDP_TRST#
R59 27D4R2F-L1-GPR59 27D4R2F-L1-GP
1 2
R57 649R2F-GPR57 649R2F-GP
1 2
All place within 2" to CPU
A
B
C
D
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
CPU (1 of 2)
CPU (1 of 2)
CPU (1 of 2)
Calado
Calado
Calado
E
439Wednesday, September 12, 2007
439Wednesday, September 12, 2007
439Wednesday, September 12, 2007
-1
-1
-1
A
VCC_CORE_S0
4 4
3 3
AA10
AA12
2 2
1 1
AA13
AA15
AA17
AA18
AA20
AC10
AB10
AB12
AB14
AB15
AB17
AB18
U44C
U44C
A7
VCC
A9
VCC
A10
VCC
A12
VCC
A13
VCC
A15
VCC
A17
VCC
A18
VCC
A20
VCC
B7
VCC
B9
VCC
B10
VCC
B12
VCC
B14
VCC
B15
VCC
B17
VCC
B18
VCC
B20
VCC
C9
VCC
C10
VCC
C12
VCC
C13
VCC
C15
VCC
C17
VCC
C18
VCC
D9
VCC
D10
VCC
D12
VCC
D14
VCC
D15
VCC
D17
VCC
D18
VCC
E7
VCC
E9
VCC
E10
VCC
E12
VCC
E13
VCC
E15
VCC
E17
VCC
E18
VCC
E20
VCC
F7
VCC
F9
VCC
F10
VCC
F12
VCC
F14
VCC
F15
VCC
F17
VCC
F18
VCC
F20
VCC
AA7
VCC
AA9
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AB9
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
BGA479-SKT6-GPU3
BGA479-SKT6-GPU3
3 OF 4
3 OF 4
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCA
VCCA
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VCCSENSE
VSSSENSE
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
B26
C26
AD6
AF5
AE5
AF4
AE3
AF3
AE2
AF7
AE7
VCC_CORE_S0
H_VID0 32
H_VID1 32
H_VID2 32
H_VID3 32
H_VID4 32
H_VID5 32
H_VID6 32
12
C197
C197
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
VCC_CORE_S0
1D05V_S0
12
C194
C194
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
layout note: "1D5V_VCCA_S0"
as short as possible
12
R52
R52
100R2F-L1-GP-U
100R2F-L1-GP-U
12
R53
R53
100R2F-L1-GP-U
100R2F-L1-GP-U
B
VCC_CORE_S0
12
C122
C122
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
960
960
VCC_CORE_S0
12
12
C163
C163
C165
C165
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
960
960
960
960
1D5V_VCCA_S0
12
C433
C433
Layout Note:
VCCSENSE and VSSSENSE lines
should be of equal length.
Layout Note:
Provide a test point (with
no stub) to connect a
differential probe
between VCCSENSE and
VSSSENSE at the location
where the two 54.9ohm
resistors terminate the
55 ohm transmission line.
12
C157
C157
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
960
960
960
960
12
C178
C178
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
960
960
960
960
12
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
VCC_SENSE 32
VSS_SENSE 32
12
12
C156
C156
C155
C155
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
DY
DY
12
12
C149
C149
C146
C146
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
960
960
960
960
1D5V_S0
L19
L19
1 2
0R3-0-U-GP
0R3-0-U-GP
C428
C428
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
C
VCC_CORE_S0
12
TC6
TC6
965
965
3 4
12
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
DY
DY
1D05V_S0
C196
C196
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C140
C140
12
C98
C98
12
C21
C21
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
DY
DY
12
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
12
12
C126
C126
C179
C179
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
DY
DY
12
ENG
ST900U2D5VM-GP
ST900U2D5VM-GP
77.E9071.001
77.E9071.001
12
C138
C138
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
DY
DY
DY
DY
12
C111
C111
C92
C92
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
12
C133
C133
12
C195
C195
12
12
C415
C415
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
DY
DY
12
C99
C99
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
12
C168
C168
C172
C172
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
DY
DY
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
DY
DY
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
D
4 OF 4
4 OF 4
U44D
U44D
A4
VSS
A8
VSS
A11
VSS
A14
VSS
A16
VSS
A19
VSS
A23
CPU_AF2
TP69TPAD30 TP69TPAD30
VSS
AF2
VSS
B6
VSS
B8
VSS
B11
VSS
B13
VSS
B16
VSS
B19
VSS
B21
VSS
B24
VSS
C5
VSS
C8
VSS
C11
VSS
C14
VSS
C16
VSS
C19
VSS
C2
VSS
C22
VSS
C25
VSS
D1
VSS
D4
VSS
D8
VSS
D11
VSS
D13
VSS
D16
VSS
D19
VSS
D23
VSS
D26
VSS
E3
VSS
E6
VSS
E8
VSS
E11
VSS
E14
VSS
E16
VSS
E19
VSS
E21
VSS
E24
VSS
F5
VSS
F8
VSS
F11
VSS
F13
VSS
F16
VSS
F19
VSS
F2
VSS
F22
VSS
F25
VSS
G4
VSS
G1
VSS
G23
VSS
G26
VSS
H3
VSS
H6
VSS
H21
VSS
H24
VSS
J2
VSS
J5
VSS
J22
VSS
J25
VSS
K1
VSS
K4
VSS
K23
VSS
K26
VSS
L3
VSS
L6
VSS
L21
VSS
L24
VSS
M2
VSS
M5
VSS
M22
VSS
M25
VSS
N1
VSS
N4
VSS
N23
VSS
N26
VSS
P3
VSS
BGA479-SKT6-GPU3
BGA479-SKT6-GPU3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25
CPU_AE1
CPU_AE26
CPU_A2
CPU_A25
CPU_AF25
E
TP78 TPAD30TP78 TPAD30
TP25 TPAD30TP25 TPAD30
TP71 TPAD30TP71 TPAD30
TP30 TPAD30TP30 TPAD30
TP29 TPAD30TP29 TPAD30
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
A
B
C
D
Date: Sheet of
CPU (2 of 2)
CPU (2 of 2)
CPU (2 of 2)
Calado
Calado
Calado
E
-1
-1
539Wednesday, September 12, 2007
539Wednesday, September 12, 2007
539Wednesday, September 12, 2007
-1
A
4 4
H_SWING routing Trace width and
Spacing use 10 / 20 mil
H_SWING Resistors and
Capacitors close MCH
500 mil ( MAX )
12
H_SCOMP and H_SCOMP# Resistors and
Capacitors close MCH 500 mil ( MAX )
3 3
1D05V_S0
54D9R2F-L1-GP
54D9R2F-L1-GP
54D9R2F-L1-GP
54D9R2F-L1-GP
1 2
H_SCOMP
H_SCOMP#
24D9R2F-L-GP
24D9R2F-L-GP
1 2
R276
R276
1D05V_S0
1 2
R275
R275
H_RCOMP routing Trace width and
Spacing use 10 / 20 mil
R282
R282
1D05V_S0
H_SWING
C437
C437
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
H_RCOMP
12
R285
R285
221R2F-2-GP
221R2F-2-GP
12
R284
R284
100R2F-L1-GP-U
100R2F-L1-GP-U
Place them near to the chip ( < 0.5")
2 2
H_REF Decoupling Crestline
close Crestline 100 mil
1D05V_S0
R287
R287
1KR2F-3-GP
1KR2F-3-GP
1 2
12
R286
R286
2KR2F-3-GP
2KR2F-3-GP
B
H_AVREF
H_D#[63..0]
H_CPURST#4,38
H_CPUSLP#4
C446
C446
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
1 2
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_SWING
H_RCOMP
H_SCOMP
H_SCOMP#
M10
N12
W10
AD12
AE3
AD9
AC9
AC7
AC14
AD11
AC11
AB2
AD7
AB1
AC6
AE2
AC5
AG3
AH8
AJ14
AE9
AE11
AH12
AH5
AE7
AE5
AH2
AH13
P13
AJ9
AJ5
AJ6
AJ7
AJ2
AJ3
E2
G2
G7
M6
H7
H3
G4
F3
N8
H2
N9
H5
K9
M2
Y8
V4
M3
J1
N5
N3
W6
W9
N2
Y7
Y9
P4
W3
N1
Y3
B3
C2
W1
W2
B6
E5
B9
A9
H_D#[63..0]4
1 OF 10
1 OF 10
U43A
U43A
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_SWING
H_RCOMP
H_SCOMP
H_SCOMP#
H_CPURST#
H_CPUSLP#
H_AVREF
H_DVREF
C
H_ADSTB#0
H_ADSTB#1
HOST
HOST
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DRDY#
H_HITM#
H_LOCK#
H_TRDY#
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADS#
H_BNR#
H_HIT#
H_RS#0
H_RS#1
H_RS#2
J13
B11
C11
M11
C15
F16
L13
G17
C14
K16
B13
L16
J17
B14
K19
P15
R17
B16
H20
L19
D17
M17
N16
J19
B18
E19
B17
B15
E17
C18
A19
B19
N19
G12
H17
G20
C8
E8
F12
D6
C10
AM5
AM7
H8
K7
E4
C6
G10
B7
K5
L2
AD13
AE13
M7
K3
AD2
AH11
L7
K2
AC2
AJ10
M14
E13
A11
H13
B12
E12
D7
D8
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
H_A#[35..3]
H_ADS# 4
H_ADSTB#0 4
H_ADSTB#1 4
H_BNR# 4
H_BPRI# 4
H_BREQ#0 4
H_DEFER# 4
H_DBSY# 4
CLK_MCH_BCLK 3
CLK_MCH_BCLK# 3
H_DPWR# 4
H_DRDY# 4
H_HIT# 4
H_HITM# 4
H_LOCK# 4
H_TRDY# 4
H_DINV#[3..0]
H_DSTBN#[3..0]
H_DSTBP#[3..0]
D
H_A#[35..3] 4
H_DINV#[3..0] 4
H_DSTBN#[3..0] 4
H_DSTBP#[3..0] 4
H_REQ#[4..0] 4
H_RS#[2..0] 4
E
1 1
A
CRB v0.9 REQUEST
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
GMCH (1 of 6)
GMCH (1 of 6)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
B
C
D
Date: Sheet of
GMCH (1 of 6)
Calado
Calado
Calado
E
-1
-1
639Wednesday, September 12, 2007
639Wednesday, September 12, 2007
639Wednesday, September 12, 2007
-1
A
AR12
AR13
AM12
AN13
AR37
PM_EXTTS#0
PM_EXTTS#1
AM36
AM37
BK22
BH20
BK18
BG23
BC23
BD24
BH39
AW20
BK20
AW49
AV20
BK51
BK50
4 4
3 3
CPU_SEL03,4
CPU_SEL13,4
CPU_SEL23,4
2 2
R35
R35
A
PM_BMBUSY#17
100R2J-2-GP
100R2J-2-GP
RSTIN#
12
H_DPRSTP#4,16,32
PWROK17,20
PLT_RST1#17,28
PM_THRMTRIP-A#4,16,30
PM_DPRSLPVR17,32
1 1
P36
P37
R35
N35
AL36
D20
H10
B51
BJ20
BF19
BJ18
BF23
B44
C44
C34
P27
N27
N24
C21
C23
F23
N23
G23
C20
R24
E23
E20
K23
M20
M24
N33
G41
N20
G36
BJ51
BL50
BL49
BL3
BL2
BK1
BJ1
C51
B50
A50
A49
BK2
J12
A35
B37
B36
B34
J20
L23
J23
L32
L35
L39
L36
J36
E1
A5
2 OF 10
2 OF 10
U43B
U43B
RSVD#P36
RSVD#P37
RSVD#R35
RSVD#N35
RSVD#AR12
RSVD#AR13
RSVD#AM12
RSVD#AN13
RSVD#J12
RSVD#AR37
RSVD#AM36
RSVD#AL36
RSVD#AM37
RSVD#D20
RSVD#H10
RSVD#B51
RSVD#BJ20
RSVD#BK22
RSVD#BF19
RSVD#BH20
RSVD#BK18
RSVD#BJ18
RSVD#BF23
RSVD#BG23
RSVD#BC23
RSVD#BD24
RSVD#BH39
RSVD#AW20
RSVD#BK20
RSVD#B44
RSVD#C44
RSVD#A35
RSVD#B37
RSVD#B36
RSVD#B34
RSVD#C34
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20
PM_BM_BUSY#
PM_DPRSTP#
PM_EXT_TS#0
PM_EXT_TS#1
PWROK
RSTIN#
THERMTRIP#
DPRSLPVR
NC#BJ51
NC#BK51
NC#BK50
NC#BL50
NC#BL49
NC#BL3
NC#BL2
NC#BK1
NC#BJ1
NC#E1
NC#A5
NC#C51
NC#B50
NC#A50
NC#A49
NC#BK2
B
RSVD
RSVD
DDR MUXING
DDR MUXING
SM_RCOMP_VOH
SM_RCOMP_VOL
SM_VREF#AR49
SM_VREF#AW4
DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
CLK
CLK
DMI
DMI
CFG PM NC
CFG PM NC
SDVO_CTRL_CLK
SDVO_CTRL_DATA
MISC ME GRAPHICS VID
MISC ME GRAPHICS VID
B
SM_CK0
SM_CK1
SM_CK3
SM_CK4
SM_CK#0
SM_CK#1
SM_CK#3
SM_CK#4
SM_CKE0
SM_CKE1
SM_CKE3
SM_CKE4
SM_CS#0
SM_CS#1
SM_CS#2
SM_CS#3
SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3
SM_RCOMP
SM_RCOMP#
PEG_CLK
PEG_CLK#
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
GFX_VID0
GFX_VID1
GFX_VID2
GFX_VID3
GFX_VR_EN
CL_CLK
CL_DATA
CL_PWROK
CL_RST#
CL_VREF
CLKREQ#
ICH_SYNC#
TEST1
TEST2
AV29
BB23
BA25
AV23
AW30
BA23
AW25
AW23
BE29
AY32
BD39
BG37
BG20
BK16
BG16
BE13
BH18
BJ15
BJ14
BE16
SM_RCOMP_VOH
BK31
SM_RCOMP_VOL
BL31
BL15
BK14
AR49
AW4
DREFCLK
B42
DREFCLK#
C42
DREFSSCLK
H48
DREFSSCLK#
H47
K44
K45
DMI_TXN0
AN47
DMI_TXN1
AJ38
DMI_TXN2
AN42
DMI_TXN3
AN46
DMI_TXP0
AM47
DMI_TXP1
AJ39
DMI_TXP2
AN41
DMI_TXP3
AN45
DMI_RXN0
AJ46
DMI_RXN1
AJ41
DMI_RXN2
AM40
DMI_RXN3
AM44
DMI_RXP0
AJ47
DMI_RXP1
AJ42
DMI_RXP2
AM39
DMI_RXP3
AM43
E35
A39
C38
B39
E36
AM49
AK50
AT43
AN49
MCH_CLVREF
AM50
H35
K36
CLK_3GPLLREQ#
G39
G40
A37
TEST2_GMCH
R32
20KR2J-L2-GP
20KR2J-L2-GP
M_CLK_DDR0 12
M_CLK_DDR1 12
M_CLK_DDR2 12
M_CLK_DDR3 12
M_CLK_DDR#0 12
M_CLK_DDR#1 12
M_CLK_DDR#2 12
M_CLK_DDR#3 12
M_CKE0 12,13
M_CKE1 12,13
M_CKE2 12,13
M_CKE3 12,13
M_CS0# 12,13
M_CS1# 12,13
M_CS2# 12,13
M_CS3# 12,13
M_ODT0 12,13
M_ODT1 12,13
M_ODT2 12,13
M_ODT3 12,13
M_RCOMPP
M_RCOMPN
DDR_VREF_S3
CLK_MCH_3GPLL 3
CLK_MCH_3GPLL# 3
MCH_ICH_SYNC# 17
12
R50
R50
1 2
DREFCLK 3
DREFCLK# 3
DREFSSCLK 3
DREFSSCLK# 3
DMI_TXN0 17
DMI_TXN1 17
DMI_TXN2 17
DMI_TXN3 17
DMI_TXP0 17
DMI_TXP1 17
DMI_TXP2 17
DMI_TXP3 17
DMI_RXN0 17
DMI_RXN1 17
DMI_RXN2 17
DMI_RXN3 17
DMI_RXP0 17
DMI_RXP1 17
DMI_RXP2 17
DMI_RXP3 17
R55
R55
10KR2J-3-GP
10KR2J-3-GP
C
C82
C82
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
CL_CLK0 17
CL_DATA0 17
PWROK 17,20
CL_RST#0 17
3D3V_S0
12
C
C480
C480
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1D25V_S0
12
M_RCOMPP
M_RCOMPN
R309
R309
1KR2F-3-GP
1KR2F-3-GP
1 2
12
R311
R311
392R2F-GP
392R2F-GP
20R2F-GP
20R2F-GP
20R2F-GP
20R2F-GP
R37
R37
150R2F-1-GP
150R2F-1-GP
12
R39
R39
150R2F-1-GP
150R2F-1-GP
12
R40
R40
150R2F-1-GP
150R2F-1-GP
12
R44
R44
150R2F-1-GP
150R2F-1-GP
12
R47
R47
150R2F-1-GP
150R2F-1-GP
12
R38
R38
150R2F-1-GP
150R2F-1-GP
12
R298 1KR2F-3-GPR298 1KR2F-3-GP
12
R295
R295
3K01R2F-3-GP
3K01R2F-3-GP
R292
R292
1KR2F-3-GP
1KR2F-3-GP
1 2
CLK_DDC_EDID14
DAT_DDC_EDID14
GMCH_LCDVDD_ON14
1D8V_S3
R289
R289
R288
R288
GMCH_BLUE
GMCH_GREEN
GMCH_RED
GMCH_BL_ON28
12
12
TV_DACA
TV_DACB
TV_DACC
12
GMCH_GREEN15
GMCH_DDCCLK15
GMCH_DDCDATA15
GMCH_VSYNC15
GMCH_HSYNC15
1D8V_S3
12
C465
C465
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
12
C462
C462
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
GMCH_BLUE15
GMCH_RED15
3D3V_S0
12
12
D
8
7
6
SM_RCOMP_VOH
SM_RCOMP_VOL
D
3D3V_S0
678
RN32
RN32
SRN10KJ-6-GP
SRN10KJ-6-GP
123
TV_DACA15
TV_DACB15
TV_DACC15
RN31
RN31
SRN10KJ-6-GP
SRN10KJ-6-GP
C466
C466
SC2D2U6D3V3MX-1-GP
SC2D2U6D3V3MX-1-GP
C461
C461
SC2D2U6D3V3MX-1-GP
SC2D2U6D3V3MX-1-GP
L_BKLTCTL14
4 5
LCTLA_CLK
LCTLB_DATA
R51
R51
12
2K4R2F-GP
2K4R2F-GP
TP63TPAD30 TP63TPAD30
GMCH_TXACLK-14
GMCH_TXACLK+14
GMCH_TXAOUT0-14
GMCH_TXAOUT1-14
GMCH_TXAOUT2-14
GMCH_TXAOUT3-
TP66TPAD30 TP66TPAD30
GMCH_TXAOUT0+14
GMCH_TXAOUT1+14
GMCH_TXAOUT2+14
GMCH_TXAOUT3+
TP67TPAD30 TP67TPAD30
PM_EXTTS#1
1
PM_EXTTS#0
2
TV_DCONSEL0
3
TV_DCONSEL1
45
GMCH_BLUE
GMCH_GREEN
GMCH_RED
GMCH_DDCCLK
GMCH_DDCDATA
1 2
R49 33R2F-3-GPR49 33R2F-3-GP
1 2
R46 33R2F-3-GPR46 33R2F-3-GP
1 2
R36 1K3R2F-1-GPR36 1K3R2F-1-GP
GMCH_VS
GMCH_HS
CRT_IREF
FOR Calero: 255 ohm
Crestline: 1.3k ohm
CRT_IREF routing Trace
width use 20 mil
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
LIBG
L_LVBG
H39
E39
E40
C37
D35
K40
N41
N40
D46
C45
D44
E42
G51
E51
F49
C48
G50
E50
F48
D47
G44
B47
B45
E44
A47
A45
E27
G27
K27
F27
M35
P33
H32
G32
K29
F29
E29
K33
G35
E33
C32
F33
U43C
U43C
J40
L41
L43
J27
L27
J29
3 OF 10
3 OF 10
L_BKLT_CTRL
L_BKLT_EN
L_CTRL_CLK
L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA
L_VDD_EN
LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK
LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3
LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
TVA_DAC
TVB_DAC
TVC_DAC
TVA_RTN
TVB_RTN
TVC_RTN
TV_DCONSEL0
TV_DCONSEL1
CRT_BLUE
CRT_BLUE#
CRT_GREEN
CRT_GREEN#
CRT_RED
CRT_RED#
CRT_DDC_CLK
CRT_DDC_DATA
CRT_VSYNC
CRT_TVO_IREF
CRT_HSYNC
GMCH (2 of 6)
GMCH (2 of 6)
GMCH (2 of 6)
Calado
Calado
Calado
E
PEG_COMPI
PEG_COMPO
PEG_RX#0
PEG_RX#1
PEG_RX#2
PEG_RX#3
PEG_RX#4
PEG_RX#5
PEG_RX#6
PEG_RX#7
PEG_RX#8
LVDS
LVDS
PEG_RX#9
PEG_RX#10
PEG_RX#11
PEG_RX#12
PEG_RX#13
PEG_RX#14
PEG_RX#15
PEG_RX0
PEG_RX1
PEG_RX2
PEG_RX3
PEG_RX4
PEG_RX5
PEG_RX6
PEG_RX7
PEG_RX8
PEG_RX9
PEG_RX10
PEG_RX11
PEG_RX12
PEG_RX13
PEG_RX14
PEG_RX15
PEG_TX#0
PEG_TX#1
PEG_TX#2
TV VGA
TV VGA
PEG_TX#3
PEG_TX#4
PEG_TX#5
PEG_TX#6
PEG_TX#7
PEG_TX#8
PEG_TX#9
PEG_TX#10
PCI_EXPRESS GRAPHICS
PCI_EXPRESS GRAPHICS
PEG_TX#11
PEG_TX#12
PEG_TX#13
PEG_TX#14
PEG_TX#15
PEG_TX0
PEG_TX1
PEG_TX2
PEG_TX3
PEG_TX4
PEG_TX5
PEG_TX6
PEG_TX7
PEG_TX8
PEG_TX9
PEG_TX10
PEG_TX11
PEG_TX12
PEG_TX13
PEG_TX14
PEG_TX15
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
739Wednesday, September 12, 2007
739Wednesday, September 12, 2007
739Wednesday, September 12, 2007
E
R54
R54
24D9R2F-L-GP
24D9R2F-L-GP
PEG_CMP
N43
M43
J51
L51
N47
T45
T50
U40
Y44
Y40
AB51
W49
AD44
AD40
AG46
AH49
AG45
AG41
J50
L50
M47
U44
T49
T41
W45
W41
AB50
Y48
AC45
AC41
AH47
AG49
AH45
AG42
N45
U39
U47
N51
R50
T42
Y43
W46
W38
AD39
AC46
AC49
AC42
AH39
AE49
AH44
M45
T38
T46
N50
R51
U43
W42
Y47
Y39
AC38
AD47
AC50
AD43
AG39
AE50
AH43
1D05V_S0
12
-1
-1
-1
A
B
C
D
E
4 4
M_A_DQ[63..0]12
3 3
2 2
M_A_DQ[63..0]
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
AR43
AW44
BA45
AY46
AR41
AR45
AT42
AW47
BB45
BG47
BB47
BG50
BH49
BE45
AW43
BE44
BG42
BE40
BH45
BG40
AR40
AW40
AT39
AW36
AW41
AY41
AV38
AT38
AV13
AT13
AW11
AV11
AU15
AT11
BA13
BA11
BE10
BD10
BG10
AN10
AN11
BF48
BJ45
BF44
BF40
BD8
AY9
AW9
BD7
BB9
BB5
AY7
AT5
AT7
AY6
BB7
AR5
AR8
AR9
AN3
AM8
AT9
AN9
AM9
U43D
U43D
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
4 OF 10
4 OF 10
BB19
SA_BS0
BK19
SA_BS1
BF29
SA_BS2
BL17
SA_CAS#
AT45
SA_DM0
BD44
SA_DM1
BD42
SA_DM2
AW38
SA_DM3
AW13
SA_DM4
BG8
SA_DM5
AY5
SA_DM6
AN6
SA_DM7
AT46
SA_DQS0
BE48
SA_DQS1
BB43
SA_DQS2
BC37
SA_DQS3
BB16
SA_DQS4
BH6
SA_DQS5
BB2
SA_DQS6
AP3
SA_DQS7
AT47
SA_DQS#0
BD47
SA_DQS#1
BC41
SA_DQS#2
BA37
SA_DQS#3
BA16
SA_DQS#4
BH7
SA_DQS#5
BC1
SA_DQS#6
AP2
SA_DQS#7
BJ19
SA_MA0
BD20
SA_MA1
BK27
SA_MA2
BH28
SA_MA3
BL24
SA_MA4
BK28
SA_MA5
BJ27
SA_MA6
BJ25
SA_MA7
BL28
SA_MA8
BA28
SA_MA9
BC19
SA_MA10
DDR SYSTEM MEMORRY A
DDR SYSTEM MEMORRY A
SA_RCVEN#
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_RAS#
SA_WE#
BE28
BG30
BJ16
BJ29
BE18
AY20
BA19
M_A_DM[7..0]
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
SA_RCVEN#
M_A_DQS[7..0]
M_A_DQS#[7..0]
M_A_A[14..0]
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
TP47 TPAD30TP47 TPAD30
Place Test PAD Near to Chip
as could as possible
M_A_BS#0 12,13
M_A_BS#1 12,13
M_A_BS#2 12,13
M_A_CAS# 12,13
M_A_DM[7..0] 12
M_A_DQS[7..0] 12
M_A_DQS#[7..0] 12
M_A_A[14..0] 12,13
M_A_RAS# 12,13
M_A_WE# 12,13
5 OF 10
5 OF 10
U43E
M_B_DQ[63..0]12
M_B_DQ[63..0]
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
AP49
AR51
AW50
AW51
AN51
AN50
AV50
AV49
BA50
BB50
BA49
BE50
BA51
AY49
BF50
BF49
BJ50
BJ44
BJ43
BL43
BK47
BK49
BK43
BK42
BJ41
BL41
BJ37
BJ36
BK41
BJ40
BL35
BK37
BK13
BE11
BK11
BC11
BC13
BE12
BC12
BG12
BJ10
BL9
BK5
BL5
BK9
BK10
BJ8
BJ6
BF4
BH5
BG1
BC2
BK3
BE4
BD3
BJ2
BA3
BB3
AR1
AT3
AY2
AY3
AU2
AT2
U43E
SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
AY17
SB_BS0
BG18
SB_BS1
BG36
SB_BS2
BE17
SB_CAS#
SB_DM0
SB_DM1
SB_DM2
SB_DM3
SB_DM4
SB_DM5
SB_DM6
SB_DM7
SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7
SB_DQS#0
SB_DQS#1
SB_DQS#2
SB_DQS#3
SB_DQS#4
SB_DQS#5
SB_DQS#6
SB_DQS#7
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
DDR SYSTEM MEMORY B
DDR SYSTEM MEMORY B
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_RAS#
SB_RCVEN#
SB_WE#
M_B_DM0
AR50
M_B_DM1
BD49
M_B_DM2
BK45
M_B_DM3
BL39
M_B_DM4
BH12
M_B_DM5
BJ7
M_B_DM6
BF3
M_B_DM7
AW2
M_B_DQS0
AT50
M_B_DQS1
BD50
M_B_DQS2
BK46
M_B_DQS3
BK39
M_B_DQS4
BJ12
M_B_DQS5
BL7
M_B_DQS6
BE2
M_B_DQS7
AV2
M_B_DQS#0
AU50
M_B_DQS#1
BC50
M_B_DQS#2
BL45
M_B_DQS#3
BK38
M_B_DQS#4
BK12
M_B_DQS#5
BK7
M_B_DQS#6
BF2
M_B_DQS#7
AV3
M_B_A0
BC18
M_B_A1
BG28
M_B_A2
BG25
M_B_A3
AW17
M_B_A4
BF25
M_B_A5
BE25
M_B_A6
BA29
M_B_A7
BC28
M_B_A8
AY28
M_B_A9
BD37
M_B_A10
BG17
M_B_A11
BE37
M_B_A12
BA39
M_B_A13
BG13
M_B_A14
BE24
AV16
SB_RCVEN#
AY18
BC17
Place Test PAD Near to Chip
ascould as possible
M_B_DM[7..0]
M_B_DQS[7..0]
M_B_DQS#[7..0]
M_B_A[14..0]
M_B_DQS[7..0] 12
M_B_DQS#[7..0] 12
M_B_A[14..0] 12,13
M_B_RAS# 12,13
TP44TPAD30TP44TPAD30
M_B_WE# 12,13
M_B_BS#0 12,13
M_B_BS#1 12,13
M_B_BS#2 12,13
M_B_CAS# 12,13
M_B_DM[7..0] 12
1 1
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
A
B
C
D
Date: Sheet of
GMCH (3 of 6)
GMCH (3 of 6)
GMCH (3 of 6)
Calado
Calado
Calado
839Wednesday, September 12, 2007
839Wednesday, September 12, 2007
839Wednesday, September 12, 2007
E
-1
-1
-1
A
1D05V_S0
FOR VCC CORE
C104
12
DY
DY
C104
C160
C160
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C184
C184
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
12
C169
C169
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
12
12
DY
DY
C185
C185
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
12
R43
DY
DY
R43
1 2
0R0402-PAD
0R0402-PAD
C186
C186
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
12
4 4
C110
C110
12
VCC_NCTF + VCC=1573mA
6 OF 10
6 OF 10
U43F
1573mA
VCC_GMCH1
AT35
AT34
AH28
AC32
AC31
AK32
AJ31
AJ28
AH32
AH31
AH29
AF32
R30
U43F
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC CORE
VCC CORE
Coupling CAP 370 mils from the Edge
POWER
1D8V_S3
3138mA
FOR VCC SM
Place CAP where
LVDS and DDR2 taps
3 3
12
12
C173
C173
C180
C180
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
DY
DY
12
C470
C470
Place on the Edge
2 2
1 1
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
12
12
1D05V_S0
A
C170
C170
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C471
C471
12
DY
DY
12
TC7
TC7
ST220U2D5VBM-5GP
ST220U2D5VBM-5GP
12
C458
C458
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
DY
DY
12
C482
C481
C481
C482
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
AU32
AU33
AU35
AV33
AW33
AW35
AY35
BA32
BA33
BA35
BB33
BC32
BC33
BC35
BD32
BD35
BE32
BE33
BE35
BF33
BF34
BG32
BG33
BG35
BH32
BH34
BH35
BJ32
BJ33
BJ34
BK32
BK33
BK34
BK35
BL33
AU30
R20
T14
W13
W14
Y12
AA20
AA23
AA26
AA28
AB21
AB24
AB29
AC20
AC21
AC23
AC24
AC26
AC28
AC29
AD20
AD23
AD24
AD28
AF21
AF26
AA31
AH20
AH21
AH23
AH24
AH26
AD31
AJ20
AN14
POWER
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC SM
VCC SM
VCC GFX
VCC GFX
B
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC GFX NCTF
VCC GFX NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC SM LF
VCC SM LF
B
T17
T18
T19
T21
T22
T23
T25
U15
U16
U17
U19
U20
U21
U23
U26
V16
V17
V19
V20
V21
V23
V24
Y15
Y16
Y17
Y19
Y20
Y21
Y23
Y24
Y26
Y28
Y29
AA16
AA17
AB16
AB19
AC16
AC17
AC19
AD15
AD16
AD17
AF16
AF19
AH15
AH16
AH17
AH19
AJ16
AJ17
AJ19
AK16
AK19
AL16
AL17
AL19
AL20
AL21
AL23
AM15
AM16
AM19
AM20
AM21
AM23
AP15
AP16
AP17
AP19
AP20
AP21
AP23
AP24
AR20
AR21
AR23
AR24
AR26
V26
V28
V29
Y31
AW45
BC39
BE39
BD17
BD4
AW8
AT6
1D05V_S0
VCC_AXG_NCTF + VCC_AXG=7700mA
12
C147
C147
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SM_LF1_GMCH
SM_LF2_GMCH
SM_LF3_GMCH
SM_LF4_GMCH
SM_LF5_GMCH
SM_LF6_GMCH
SM_LF7_GMCH
12
C131
C131
C83
C83
12
12
C187
C187
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
C79
C79
C93
C93
12
12
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C
D
E
FOR VCC CORE AND VCC NCTF
7 OF 10
7 OF 10
U43G
1D05V_S0
TC18
TC18
DY
ST220U2D5VBM-5GP
ST220U2D5VBM-5GP
DY
308 mils from
the Edge
12
12
12
C128
C128
C150
C150
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
12
12
C175
C175
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
12
C136
C136
C97
C97
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
DY
DY
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
Coupling CAP
12
12
C117
C117
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C176
C176
SC4D7U10V5ZY-3GP
SC4D7U10V5ZY-3GP
1D25V_S0
R42
R42
0R0603-PAD
0R0603-PAD
1 2
R48
R48
0R6J-3-GP
0R6J-3-GP
DY
DY
FOR VCC AXM NCTF AND VCC AXM
VCC_AXM_S01D05V_S0
C177
C177
C181
C181
C162
12
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C162
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
12
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
DY
DY
Coupling CAP
C167
C167
12
12
Place on the Edge
C154
C154
12
12
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
C174
C174
12
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
DY
DY
VCC_AXM_NCTF + VCC_AXM=540mA
C125
C125
C189
C189
C192
C192
C193
12
12
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
12
SCD47U16V3ZY-3GP
SCD47U16V3ZY-3GP
C193
12
SC1U10V3KX-3GP
SC1U10V3KX-3GP
SC1U10V3KX-3GP
SC1U10V3KX-3GP
C
D
U43G
AB33
VCC_NCTF
AB36
VCC_NCTF
AB37
VCC_NCTF
AC33
VCC_NCTF
AC35
VCC_NCTF
AC36
VCC_NCTF
AD35
VCC_NCTF
AD36
VCC_NCTF
AF33
VCC_NCTF
AF36
VCC_NCTF
AH33
VCC_NCTF
AH35
VCC_NCTF
AH36
VCC_NCTF
AH37
VCC_NCTF
AJ33
VCC_NCTF
AJ35
VCC_NCTF
AK33
VCC_NCTF
AK35
VCC_NCTF
AK36
VCC_NCTF
AK37
VCC_NCTF
AD33
VCC_NCTF
AJ36
VCC_NCTF
AM35
VCC_NCTF
AL33
VCC_NCTF
AL35
VCC_NCTF
AA33
VCC_NCTF
AA35
VCC_NCTF
AA36
VCC_NCTF
AP35
VCC_NCTF
AP36
VCC_NCTF
AR35
VCC_NCTF
AR36
VCC_NCTF
Y32
VCC_NCTF
Y33
VCC_NCTF
Y35
VCC_NCTF
Y36
VCC_NCTF
Y37
VCC_NCTF
T30
VCC_NCTF
T34
VCC_NCTF
T35
VCC_NCTF
U29
VCC_NCTF
U31
VCC_NCTF
U32
VCC_NCTF
U33
VCC_NCTF
U35
VCC_NCTF
U36
VCC_NCTF
V32
VCC_NCTF
V33
VCC_NCTF
V36
VCC_NCTF
V37
VCC_NCTF
AL24
VCC_AXM_NCTF
AL26
VCC_AXM_NCTF
AL28
VCC_AXM_NCTF
AM26
VCC_AXM_NCTF
AM28
VCC_AXM_NCTF
AM29
VCC_AXM_NCTF
AM31
VCC_AXM_NCTF
AM32
VCC_AXM_NCTF
AM33
VCC_AXM_NCTF
AP29
VCC_AXM_NCTF
AP31
VCC_AXM_NCTF
AP32
VCC_AXM_NCTF
AP33
VCC_AXM_NCTF
AL29
VCC_AXM_NCTF
AL31
VCC_AXM_NCTF
AL32
VCC_AXM_NCTF
AR31
VCC_AXM_NCTF
AR32
VCC_AXM_NCTF
AR33
VCC_AXM_NCTF
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS NCTF
VSS NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VCC NCTF
VCC NCTF
POWER
POWER
VSS SCBVSS AXM
VSS SCBVSS AXM
VSS AXM NCTF
VSS AXM NCTF
GMCH (4 of 6)
GMCH (4 of 6)
GMCH (4 of 6)
Calado
Calado
Calado
T27
T37
U24
U28
V31
V35
AA19
AB17
AB35
AD19
AD37
AF17
AF35
AK17
AM17
AM24
AP26
AP28
AR15
AR19
AR28
NB_A3
A3
VSS_SCB
B2
VSS_SCB
C1
VSS_SCB
BL1
VSS_SCB
BL51
VSS_SCB
A51
VSS_SCB
AT33
VCC_AXM
AT31
VCC_AXM
AK29
VCC_AXM
AK24
VCC_AXM
AK23
VCC_AXM
AJ26
VCC_AXM
AJ23
VCC_AXM
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
939Monday, September 10, 2007
939Monday, September 10, 2007
939Monday, September 10, 2007
E
NB_B2
NB_C1
NB_BL1
NB_BL51
NB_A51
1D05V_S0
TP136TPAD30TP136TPAD30
TP135TPAD30TP135TPAD30
TP134TPAD30TP134TPAD30
TP20 TPAD30TP20 TPAD30
TP74 TPAD30TP74 TPAD30
TP75 TPAD30TP75 TPAD30
-1
-1
-1
A
1D25V_S0
R308
R308
0R0603-PAD
0R0603-PAD
1 2
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
R312
4 4
R312
0R0603-PAD
0R0603-PAD
1 2
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
1D25V_S0
L17
L17
FCM1608KF-121-GP
FCM1608KF-121-GP
1 2
120ohm 100MHz
C424
C424
DY
DY
C475
C475
C485
C485
12
12
12
M_VCCA_DPLLA
12
C200
C200
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
M_VCCA_DPLLB
12
C484
C484
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
2nd source:68.00206.021
M_VCCA_HPLL
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
12
12
C423
C423
C431
C431
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
3D3VTVDAC
120ohm 100MHz
3 3
2 2
1 1
1 2
L18
L18
FCM1608KF-121-GP
FCM1608KF-121-GP
2nd source:68.00206.021
1D25V_S0
1 2
3D3VTVDAC
L23
L23
0R0603-PAD
0R0603-PAD
220ohm 100MHz
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
180ohm 100MHz
L22
L22
1 2
FCM1608CF-1-GP
FCM1608CF-1-GP
2nd source:68.00206.041
R291
R291
12
0R0402-PAD
0R0402-PAD
R293
R293
12
0R0402-PAD
0R0402-PAD
R294
R294
12
0R0402-PAD
0R0402-PAD
12
C142
C142
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1D5V_S0
180ohm 100MHz
A
M_VCCA_MPLL
1D25V_RUN_PEGPLL
12
C199
C199
M_VCCA_TVDACA
12
C457
C457
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
M_VCCA_TVDACB
12
C460
C460
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
M_VCCA_TVDACC
12
C464
C464
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1D5V_S0
R41
R41
0R0603-PAD
0R0603-PAD
1 2
12
C152
C152
DY
DY
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
L6
L6
1 2
FCM1608CF-1-GP
FCM1608CF-1-GP
12
3D3V_S0
R417
R417
0R3-0-U-GP
0R3-0-U-GP
1 2
12
C456
C456
SC2D2U6D3V3MX-1-GP
SC2D2U6D3V3MX-1-GP
12
C459
C459
SC2D2U6D3V3MX-1-GP
SC2D2U6D3V3MX-1-GP
12
C463
C463
SC2D2U6D3V3MX-1-GP
SC2D2U6D3V3MX-1-GP
12
C148
C148
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C430
C430
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
3D3V_S0_DIS_LDO
R416
R416
0R3-0-U-GP
0R3-0-U-GP
DY
DY
1 2
1 2
DY
DY
VCCD_CRT
12
C164
C164
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1D5VRUN_QDAC
TC5
TC5
ST330U6D3VDM-21GP
ST330U6D3VDM-21GP
B
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
180ohm 100MHz
R296R296
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
1D25V_S0
1D25V_S0
C73
C73
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
B
3D3V_S0
10mA
1 2
12
C171
C171
SC2D2U6D3V3MX-1-GP
SC2D2U6D3V3MX-1-GP
M_VCCA_DAC_BG
12
12
C115
C115
C467
C467
SC2D2U6D3V3MX-1-GP
SC2D2U6D3V3MX-1-GP
1D8V_TXLVDS_S3
C472
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
C472
400uA
1D25V_S0
C135
C135
12
DY
DY
12
12
C161
C161
C145
C145
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
60mA
12
1D8V_S3
0R0603-PAD
0R0603-PAD
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
80mA
180ohm 100MHz
R300
R300
BLM18HG102SN-1GP
BLM18HG102SN-1GP
R45
R45
0R0603-PAD
0R0603-PAD
3D3V_SYNC_S0
C468
C468
5mA
12
80mA
80mA
50mA
150mA
1 2
12
0R0402-PAD
0R0402-PAD
12
C190
C190
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1D25V_RUN_PEGPLL
C109
C109
C425
C425
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
12
SC1U10V3KX-3GP
SC1U10V3KX-3GP
12
12
C159
C159
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
DY
DY
40mA
40mA
40mA
1D5V_S0
60mA
1D5VRUN_QDAC
1D25V_RUN_PEGPLL
12
C483
C483
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
R60
R60
1D8V_SUS_DLVDS
12
12
C198
C198
12
DY
DY
12
M_VCCA_DAC_BG
M_VCCA_DPLLA
M_VCCA_DPLLB
M_VCCA_HPLL
M_VCCA_MPLL
1D8V_TXLVDS
R301
R301
3D3V_S0
C429
C429
SC1U10V3KX-3GP
SC1U10V3KX-3GP
12
M_VCCA_TVDACA
M_VCCA_TVDACB
M_VCCA_TVDACC
VCCD_CRT
5mA
250mA
150mA
3D3VTVDAC
10mA
SC1U10V3KX-3GP
SC1U10V3KX-3GP
100mA
12
C
8 OF 10
8 OF 10
U43H
U43H
J32
VCC_SYNC
A33
VCCA_CRT_DAC
B33
VCCA_CRT_DAC
A30
VCCA_DAC_BG
B32
VSSA_DAC_BG
B49
VCCA_DPLLA
H49
VCCA_DPLLB
AL2
VCCA_HPLL
AM2
VCCA_MPLL
A41
VCCA_LVDS
B41
VSSA_LVDS
K50
VCCA_PEG_BG
K49
VSSA_PEG_BG
U51
VCCA_PEG_PLL
AW18
VCCA_SM
AV19
VCCA_SM
AU19
VCCA_SM
AU18
VCCA_SM
AU17
VCCA_SM
AT22
VCCA_SM
AT21
VCCA_SM
AT19
VCCA_SM
AT18
VCCA_SM
AT17
VCCA_SM
AR17
VCCA_SM_NCTF
AR16
VCCA_SM_NCTF
BC29
VCCA_SM_CK
BB29
VCCA_SM_CK
C25
VCCA_TVA_DAC
B25
VCCA_TVA_DAC
C27
VCCA_TVB_DAC
B27
VCCA_TVB_DAC
B28
VCCA_TVC_DAC
A28
VCCA_TVC_DAC
M32
VCCD_CRT
L29
VCCD_TVDAC
N28
VCCD_QDAC
AN2
VCCD_HPLL
U48
VCCD_PEG_PLL
J41
VCCD_LVDS
H42
VCCD_LVDS
C191
C191
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
C
C449
C449
5V_S0
SC1U16V3ZY-GP
SC1U16V3ZY-GP
POWER
POWER
A LVDS PLL CRT
A LVDS PLL CRT
AXD
AXD
VCC_AXD_NCTF
A PEG
A PEG
SM CK
SM CK
TV A CK A SM
TV A CK A SM
DMI
DMI
LVDS TV/CRT
LVDS TV/CRT
12
DY
DY
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VCC_AXD
VCC_AXD
VCC_AXD
VCC_AXD
VCC_AXD
VCC_AXD
VCC_AXF
VCC_AXF
AXF
AXF
VCC_AXF
VCC_DMI
VCC_SM_CK
VCC_SM_CK
VCC_SM_CK
VCC_SM_CK
VCC_TX_LVDS
VCC_HV
HV
HV
VCC_HV
VCC_PEG
VCC_PEG
VCC_PEG
PEG
PEG
VCC_PEG
VCC_PEG
VCC_RXR_DMI
VCC_RXR_DMI
VTTLF
VTTLF
VTTLF
VTTLF
VTTLF
ENG
U42
U42
3
IN
2
GND
1
SHDN#
G913CF-GP
G913CF-GP
74.00913.A3F
74.00913.A3F
I max = 300 mA
DY
DY
U13
U12
U11
U9
U8
U7
U5
U3
U2
U1
T13
T11
T10
T9
T7
T6
T5
T3
T2
R3
R2
R1
AT23
AU28
AU24
AT29
AT25
AT30
AR29
B23
B21
A21
AJ50
BK24
BK23
BJ24
BJ23
A43
C40
B40
AD51
W50
W51
V49
V50
AH50
AH51
A7
F2
AH1
Tahoe
OUT
SET
Place on the edge
12
C112
C112
200mA
350mA
1D8V_TXLVDS_S3
3D3V_S0
100mA
1200mA
250mA
VTTLF1
VTTLF2
VTTLF3
12
C69
C69
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
4
5
DY
DY
DY
DY
D
12
12
C114
C114
C427
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
C427
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
1D25V_S0
C141
C141
SC1U10V3KX-3GP
SC1U10V3KX-3GP
12
100mA
12
C166
C166
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
C151
12
C432
C432
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
R418
R418
16K5R2F-1-GP
16K5R2F-1-GP
R419
R419
10KR2F-2-GP
10KR2F-2-GP
C151
C444
C444
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
DY
DY
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
12
3D3V_S0_DIS_LDO
12
12
D
E
1D05V_S0
12
12
12
12
C108
C108
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC2D2U6D3V3MX-1-GP
SC2D2U6D3V3MX-1-GP
C123
C123
12
SC1U10V3KX-3GP
SC1U10V3KX-3GP
12
C139
C139
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
1D25V_S0
C119
C119
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
DY
DY
12
C106
C106
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
12
C158
C158
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C188
C188
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
DY
DY
1D25V_S0
850mA
C143
C143
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1D8V_S3
200mA
12
C182
C182
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
100mA
12
C473
C473
1D05V_S0
12
12
C132
C132
DY
DY
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
12
C426
C426
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
1D05V_S0
12
C455
C455
SC1U16V3ZY-GP
SC1U16V3ZY-GP
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
D22
D22
1
BAS16-1-GP
BAS16-1-GP
83.00016.B11
83.00016.B11
2
1D8V_S3
R304
R304
12
0R0603-PAD
0R0603-PAD
1D05V_S0
12
C75
C75
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
1D05V_HV_S0
3
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
GMCH (5 of 6)
GMCH (5 of 6)
GMCH (5 of 6)
Calado
Calado
Calado
R310
R310
10R3J-3-GP
10R3J-3-GP
E
3D3V_S0
12
10 39Monday, September 10, 2007
10 39Monday, September 10, 2007
10 39Monday, September 10, 2007
-1
-1
-1
5
AA21
AA24
AA29
AB20
AB23
AB26
D D
C C
B B
A A
5
AB28
AB31
AC10
AC13
AC39
AC43
AC47
AD21
AD26
AD29
AD41
AD45
AD49
AD50
AE10
AE14
AG38
AG43
AG47
AG50
AH40
AH41
AK20
AK21
AK26
AK28
AK31
AK51
AM11
AM13
AM41
AM45
AN38
AN39
AN43
AP48
AP50
AR11
AR39
AR44
AR47
AT10
AT14
AT41
AT49
AU23
AU29
AU36
AU49
AU51
AV39
AV48
AW12
AW16
A13
A15
A17
A24
AC3
AD1
AD3
AD5
AD8
AE6
AF20
AF23
AF24
AF31
AG2
AH3
AH7
AH9
AJ11
AJ13
AJ21
AJ24
AJ29
AJ32
AJ43
AJ45
AJ49
AL1
AM3
AM4
AN1
AN5
AN7
AP4
AR2
AR7
AU1
AU3
AW1
U43I
U43I
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
9 OF 10
9 OF 10
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AW24
AW29
AW32
AW5
AW7
AY10
AY24
AY37
AY42
AY43
AY45
AY47
AY50
B10
B20
B24
B29
B30
B35
B38
B43
B46
B5
B8
BA1
BA17
BA18
BA2
BA24
BB12
BB25
BB40
BB44
BB49
BB8
BC16
BC24
BC25
BC36
BC40
BC51
BD13
BD2
BD28
BD45
BD48
BD5
BE1
BE19
BE23
BE30
BE42
BE51
BE8
BF12
BF16
BF36
BG19
BG2
BG24
BG29
BG39
BG48
BG5
BG51
BH17
BH30
BH44
BH46
BH8
BJ11
BJ13
BJ38
BJ4
BJ42
BJ46
BK15
BK17
BK25
BK29
BK36
BK40
BK44
BK6
BK8
BL11
BL13
BL19
BL22
BL37
BL47
C12
C16
C19
C28
C29
C33
C36
C41
4
4
3
10 OF 10
10 OF 10
U43J
U43J
C46
VSS
C50
VSS
C7
VSS
D13
VSS
D24
VSS
D3
VSS
D32
VSS
D39
VSS
D45
VSS
D49
VSS
E10
VSS
E16
VSS
E24
VSS
E28
VSS
E32
VSS
E47
VSS
F19
VSS
F36
VSS
F4
VSS
F40
VSS
F50
VSS
G1
VSS
G13
VSS
G16
VSS
G19
VSS
G24
VSS
G28
VSS
G29
VSS
G33
VSS
G42
VSS
G45
VSS
G48
VSS
G8
VSS
H24
VSS
H28
VSS
H4
VSS
H45
VSS
J11
VSS
VSS
VSS
J16
VSS
J2
VSS
J24
VSS
J28
VSS
J33
VSS
J35
VSS
J39
VSS
K12
VSS
K47
VSS
K8
VSS
L1
VSS
L17
VSS
L20
VSS
L24
VSS
L28
VSS
L3
VSS
L33
VSS
L49
VSS
M28
VSS
M42
VSS
M46
VSS
M49
VSS
M5
VSS
M50
VSS
M9
VSS
N11
VSS
N14
VSS
N17
VSS
N29
VSS
N32
VSS
N36
VSS
N39
VSS
N44
VSS
N49
VSS
N7
VSS
P19
VSS
P2
VSS
P23
VSS
P3
VSS
P50
VSS
R49
VSS
T39
VSS
T43
VSS
T47
VSS
U41
VSS
U45
VSS
U50
VSS
V2
VSS
V3
VSS
3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
W11
W39
W43
W47
W5
W7
Y13
Y2
Y41
Y45
Y49
Y5
Y50
Y11
P29
T29
T31
T33
R28
AA32
AB32
AD32
AF28
AF29
AT27
AV25
H50
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
GMCH (6 of 6)
GMCH (6 of 6)
GMCH (6 of 6)
Calado
Calado
Calado
1
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
11 39Monday, September 10, 2007
11 39Monday, September 10, 2007
11 39Monday, September 10, 2007
1
-1
-1
-1
A
M_B_A[14..0]8,13
4 4
TPAD30
TPAD30
M_B_BS#28,13
M_B_BS#08,13
M_B_BS#18,13
M_B_DQ[63..0]8
3 3
2 2
M_B_DQS#[7..0]8
M_B_DQS[7..0]8
DDR_VREF_S3
1 1
C208
C208
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
TP42
TP42
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_ODT27,13
M_ODT37,13
12
12
C212
C212
SCD1U16V2ZY-2GP
DY
DY
SCD1U16V2ZY-2GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
MH1
102
101
100
99
98
97
94
92
93
91
105
90
89
116
86
84
85
107
106
5
7
17
19
4
6
14
16
23
25
35
37
20
22
36
38
43
45
55
57
44
46
56
58
61
63
73
75
62
64
74
76
123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194
11
29
49
68
129
146
167
186
13
31
51
70
131
148
169
188
114
119
1
2
202
DM1
DM1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16/BA2
BA0
BA1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
OTD0
OTD1
VREF
VSS
GND
MH1
DDR2-200P-23-GP-U1
DDR2-200P-23-GP-U1
62.10017.A71
62.10017.A71
RAS#
WE#
CAS#
CS0#
CS1#
CKE0
CKE1
CK0
CK0#
CK1
CK1#
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
SDA
SCL
VDDSPD
SA0
SA1
NC#50
NC#69
NC#83
NC#120
NC#163/TEST
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
REVERSE TYPE
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
GND
MH2
High 9.2mm High 5.2mm
A
108
109
113
110
115
79
80
30
32
164
166
10
26
52
67
130
147
170
185
195
197
199
198
200
50
69
83
120
163
81
82
87
88
95
96
103
104
111
112
117
118
3
8
9
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54
59
60
65
66
71
72
77
78
121
122
127
128
132
133
138
139
144
145
149
150
155
156
161
162
165
168
171
172
177
178
183
184
187
190
193
196
201
MH2
B
M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7
DDRB_SA0
10KR2J-3-GP
10KR2J-3-GP
B
R245
R245
M_B_RAS# 8,13
M_B_WE# 8,13
M_B_CAS# 8,13
M_CS2# 7,13
M_CS3# 7,13
M_CKE2 7,13
M_CKE3 7,13
M_CLK_DDR2 7
M_CLK_DDR#2 7
M_CLK_DDR3 7
M_CLK_DDR#3 7
SMBD_ICH 3,19
SMBC_ICH 3,19
12
12
1D8V_S3
M_B_DM[7..0] 8
C397
C397
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
3D3V_S0
C
C
M_A_A[14..0]8,13
M_A_BS#28,13
M_A_BS#08,13
M_A_BS#18,13
M_A_DQ[63..0]8
M_CS0#7,13
M_CS1#7,13
M_CKE07,13
M_CKE17,13
M_A_RAS#8,13
M_A_CAS#8,13
M_A_WE#8,13
DDR_VREF_S3
DY
DY
C207
C207
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
12
TPAD30
TPAD30
DM2
DM2
MH1
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
TP43
TP43
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
SMBC_ICH
SMBD_ICH
M_ODT07,13
M_ODT17,13
12
C211
C211
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
MH1
102
A0
101
A1
100
A2
99
A3
98
A4
97
A5
94
A6
92
A7
93
A8
91
A9
105
A10/AP
90
A11
89
A12
116
A13
86
A14
84
A15
85
A16_BA2
107
BA0
106
BA1
5
DQ0
7
DQ1
17
DQ2
19
DQ3
4
DQ4
6
DQ5
14
DQ6
16
DQ7
23
DQ8
25
DQ9
35
DQ10
37
DQ11
20
DQ12
22
DQ13
36
DQ14
38
DQ15
43
DQ16
45
DQ17
55
DQ18
57
DQ19
44
DQ20
46
DQ21
56
DQ22
58
DQ23
61
DQ24
63
DQ25
73
DQ26
75
DQ27
62
DQ28
64
DQ29
74
DQ30
76
DQ31
123
DQ32
125
DQ33
135
DQ34
137
DQ35
124
DQ36
126
DQ37
134
DQ38
136
DQ39
141
DQ40
143
DQ41
151
DQ42
153
DQ43
140
DQ44
142
DQ45
152
DQ46
154
DQ47
157
DQ48
159
DQ49
173
DQ50
175
DQ51
158
DQ52
160
DQ53
174
DQ54
176
DQ55
179
DQ56
181
DQ57
189
DQ58
191
DQ59
180
DQ60
182
DQ61
192
DQ62
194
DQ63
50
NC#50
69
NC#69
83
NC#83
120
NC#120
163
NC#163/TEST
110
CS0#
115
CS1#
79
CKE0
80
CKE1
108
RAS#
113
CAS#
109
WE#
197
SCL
195
SDA
114
ODT0
119
ODT1
1
VREF
201
GND
SKT-SODIMM20022U2GP
SKT-SODIMM20022U2GP
62.10017.691
62.10017.691
D
MH2
MH2
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
CK0
CK0#
CK1
CK1#
SA0
SA1
VDD_SPD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
REVERSE TYPE
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
GND
D
M_A_DQS0
13
M_A_DQS1
31
M_A_DQS2
51
M_A_DQS3
70
M_A_DQS4
131
M_A_DQS5
148
M_A_DQS6
169
M_A_DQS7
188
M_A_DQS#0
11
M_A_DQS#1
29
M_A_DQS#2
49
M_A_DQS#3
68
M_A_DQS#4
129
M_A_DQS#5
146
M_A_DQS#6
167
M_A_DQS#7
186
M_A_DM0
10
M_A_DM1
26
M_A_DM2
52
M_A_DM3
67
M_A_DM4
130
M_A_DM5
147
M_A_DM6
170
M_A_DM7
185
30
32
164
166
198
200
199
81
82
87
88
95
96
103
104
111
112
117
118
2
3
8
9
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54
59
60
65
66
71
72
77
78
121
122
127
128
132
133
138
139
144
145
149
150
155
156
161
162
165
168
171
172
177
178
183
184
187
190
193
196
202
M_A_DQS[7..0] 8
M_A_DQS#[7..0] 8
M_A_DM[7..0] 8
M_CLK_DDR0 7
M_CLK_DDR#0 7
M_CLK_DDR1 7
M_CLK_DDR#1 7
3D3V_S0
12
C23
C23
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
1D8V_S3
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
E
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
DDR2 Socket
DDR2 Socket
DDR2 Socket
Calado
Calado
Calado
12 39Wednesday, September 12, 2007
12 39Wednesday, September 12, 2007
12 39Wednesday, September 12, 2007
E
-1
-1
of
of
of
-1
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