Winbond Electronics W29C011AS-15, W29C011AP-15 Datasheet

Preliminary W29C011A

128K × 8 CMOS FLASH MEMORY

GENERAL DESCRIPTION

The W29C011A is a 1-megabit, 5-volt only CMOS flash memory organized as 128K × 8 bits. The
device can be programmed and erased in-system with a standard 5V power supply. A 12-volt VPP is
not required. The unique cell architecture of the W29C011A results in fast program/erase operations
with extremely low current consumption (compared to other comparable 5-volt flash memory
products). The device can also be programmed and erased using standard EPROM programmers.

FEATURES

• Single 5-volt program and erase operations

• Fast page-write operations

− 128 bytes per page

− Page program cycle: 10 mS (max.)

− Effective byte-program cycle time: 39 µS

− Software-protected data write

• Fast chip-erase operation: 50 mS

• Read access time: 150 nS

• Page program/erase cycles: 1,000

• Ten-year data retention

• Software and hardware data protection

• Low power consumption

− Active current: 25 mA (typ.)

− Standby current: 20 µA (typ.)

• Automatic program timing with internal VPP

generation

• End of program detection

− Toggle bit

− Data polling

• Latched address and data

• TTL compatible I/O

• JEDEC standard byte-wide pinouts

• Available packages: 32-pin 600 mil DIP, 450

mil SOP and PLCC

Publication Release Date: December 1997

- 1 - Revision A1

Preliminary W29C011A

1

111213

14

16

A3A2A1A0NC

A4

V

A13

DD

DQ7

CE

OE

WE

PIN CONFIGURATIONS BLOCK DIAGRAM

V

DD

V

SS

CE
OE

CONTROL

WE

A0

.

DECODER

.

A16

SYMBOL PIN NAME

A0−A16

DQ0−DQ7

Address Inputs
Data Inputs/Outputs
Chip Enable
Output Enable
Write Enable

VDD Power Supply

GND Ground

DQ0

2

A16

3

A15

4

A12

5

A7

6

A6

7

A5

DQ0
DQ1
DQ2
GND

A7
A6
A5
A4
A3

10

A2

11

A1

12

A0

13

32-pin

8

DIP

9

10

15

A

A

A

1

1

1

2

6NC

5

5
6
7
8

32-pin

9

PLCC

14

15

1716

D

D

G

Q

Q

N

1

2

D

32
31

WE

30

NC

29

A14

28
27

A8

26

A9

25

A11

24

OE

23

A10

22

CE

21

DQ7

20

DQ6

19

DQ5

18

DQ4

17

DQ3

V

/

D

N

W

C

D

E

3031

1234

32

A14

29

A13

28
27

A8

26

A9

25

A11

24

OE
A10

23
22

CE

21

18

2019

D

D

D

D

Q

Q

Q

Q

4

3

5

6

PIN DESCRIPTION

OUTPUT
BUFFER

CORE

ARRAY

DQ0

.
.

DQ7

NC No Connection

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Preliminary W29C011A

FUNCTIONAL DESCRIPTION

Read Mode

The read operation of the W29C011A is controlled by CE and OE, both of which have to be low for
the host to obtain data from the outputs. CE is used for device selection. When CE is high, the chip
is de-selected and only standby power will be consumed. OE is the output control and is used to gate
data from the output pins. The data bus is in high impedance state when either CE or OE is high.

Refer to the timing waveforms for further details.

Page Write Mode

The W29C011A is programmed on a page basis. Every page contains 128 bytes of data. If a byte of
data within a page is to be changed, data for the entire page must be loaded into the device. Any byte
that is not loaded will be erased to "FFh" during programming of the page.

The write operation is initiated by forcing CE and WE low and OE high. The write procedure consists
of two steps. Step 1 is the byte-load cycle, in which the host writes to the page buffer of the device.
Step 2 is an internal programming cycle, during which the data in the page buffers are simultaneously
written into the memory array for non-volatile storage.

During the byte-load cycle, the addresses are latched by the falling edge of either CE or WE,
whichever occurs last. The data are latched by the rising edge of either CE or WE, whichever occurs

first. If the host loads a second byte into the page buffer within a byte-load cycle time (TBLC) of 200
µS, after the initial byte-load cycle, the W29C011A will stay in the page load cycle. Additional bytes
can then be loaded consecutively. The page load cycle will be terminated and the internal
programming cycle will start if no additional byte is loaded into the page buffer within 300 µS (TBLCO)

from the last byte-load cycle, i.e., there is no subsequent WE high-to-low transition after the last
rising edge of WE. A7 to A16 specify the page address. All bytes that are loaded into the page buffer

must have the same page address. A0 to A6 specify the byte address within the page. The bytes may
be loaded in any order; sequential loading is not required.

In the internal programming cycle, all data in the page buffers, i.e., 128 bytes of data, are written
simultaneously into the memory array. Before the completion of the internal programming cycle, the
host is free to perform other tasks such as fetching data from other locations in the system to prepare
to write the next page.

Software-protected Data Write

The device provides a JEDEC-approved software-protected data write. Once this scheme is enabled,
any write operation requires a series of three-byte program commands (with specific data to a specific
address) to be performed before the data load operation. The three-byte load command sequence
begins the page load cycle, without which the write operation will not be activated. This write scheme
provides optimal protection against inadvertent write cycles, such as cycles triggered by noise during
system power-up and power-down.

The W29C011A is shipped with the software data protection enabled. To enable the software data
protection scheme, perform the three-byte command cycle at the beginning of a page load cycle. The
device will then enter the software data protection mode, and any subsequent write operation must be
preceded by the three-byte program command cycle.

Publication Release Date: December 1997

- 3 - Revision A1

Preliminary W29C011A

WE

Hardware Data Protection

The integrity of the data stored in the W29C011A is also hardware protected in the following ways:
(1) Noise/Glitch Protection: A WE pulse of less than 15 nS in duration will not initiate a write cycle.

(2) VDD Power Up/Down Detection: The programming operation is inhibited when VDD is less than

3.8V.

(3) Write Inhibit Mode: Forcing OE low, CE high, or WE high will inhibit the write operation. This

prevents inadvertent writes during power-up or power-down periods.

Data Polling (DQ7)-Write Status Detection

The W29C011A includes a data polling feature to indicate the end of a programming cycle. When
the W29C011A is in the internal programming cycle, any attempt to read DQ7 of the last byte loaded
during the page/byte-load cycle will receive the complement of the true data. Once the programming
cycle is completed. DQ7 will show the true data.

Toggle Bit (DQ6)-Write Status Detection

In addition to data polling, the W29C011A provides another method for determining the end of a
program cycle. During the internal programming cycle, any consecutive attempts to read DQ6 will
produce alternating 0's and 1's. When the programming cycle is completed, this toggling between 0's
and 1's will stop. The device is then ready for the next operation.

5-Volt-Only Software Chip Erase

The chip-erase mode can be initiated by a six-byte command sequence. After the command loading
cycles, the device enters the internal chip erase mode, which is automatically timed and will be
completed in 50 mS. The host system is not required to provide any control or timing during this
operation.

Product Identification

The product ID operation outputs the manufacturer code and device code. Programming equipment
automatically matches the device with its proper erase and programming algorithms.

The manufacturer and device codes can be accessed by software or hardware operation. In the
software access mode, a six-byte command sequence can be used to access the product ID. A read
from address 0000H outputs the manufacturer code (DAh). A read from address 0001H outputs the
device code (C1h). The product ID operation can be terminated by a three-byte command sequence.

In the hardware access mode, access to the product ID is activated by forcing CE and OE low,
high, and raising A9 to 12 volts.

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Preliminary W29C011A

CEOEWE

TABLE OF OPERATING MODES

Operating Mode Selection

Operating Range = 0 to 70°C (Ambient Temperature), VDD = 5V ±10%, VSS = 0V, VHH = 12V

MODE PINS

ADDRESS DQ.

Read VIL VIL VIH AIN Dout
Write VIL VIH VIL AIN Din
Standby VIH X X X High Z
Write Inhibit X VIL X X High Z/DOUT

X X VIH X High Z/DOUT
Output Disable X VIH X X High Z
5-Volt Software Chip Erase VIL VIH VIL AIN DIN
Product ID VIL VIL VIH A0 = VIL; A1-A16 = VIL;

A9 = VHH

VIL VIL VIH A0 = VIH; A1-A16 = VIL;

A9 = VHH

Manufacturer Code
DA (Hex)

Device Code
C1 (Hex)

Publication Release Date: December 1997

- 5 - Revision A1

Preliminary W29C011A

Command Codes for Software Data Protection Write

BYTE SEQUENCE ADDRESS DATA

0 Write 5555H AAH
1 Write 2AAAH 55H
2 Write 5555H A0H

Software Data Protection Acquisition Flow

Software Data Protection
Write Flow

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Notes for software program code:
Data Format: DQ7−DQ0 (Hex)
Address Format: A14−A0 (Hex)

Load data A0

to

address 5555

Load 0 to

128 bytes of

page data

Pause 10 mS

Exit

- 6 -