Winbond Electronics W27E257P-15, W27E257P-12, W27E257P-10, W27E257-12, W27E257-10 Datasheet
W27E257
BUFFER
CE
OE
32K × 8 ELECTRICALLY ERASABLE EPROM
GENERAL DESCRIPTION
The W27E257 is a high-speed, low-power Electrically Erasable and Programmable Read Only
Memory organized as 32768 × 8 bits that operates on a single 5 volt power supply. The W27E257
provides an electrical chip erase function. This part was the same EPROM Writer's utilities as the
W27E256.
FEATURES
• High speed access time:
100/120/150 nS (max.)
• Read operating current: 15 mA (typ.)
• Erase/Programming operating current
1 mA (typ.)
• Standby current: 5 µA (typ.)
• Single 5V power supply
• +14V erase/+12V programming voltage
• Fully static operation
• All inputs and outputs directly TTL/CMOS
compatible
• Three-state outputs
• Available packages: 28-pin 600 mil DIP and
32-pin PLCC
PIN CONFIGURATIONS
1
V
PP
2
A12
3
A7
4
A6
5
A5
6
A6
A5
A4
A3
A2
A1
A0
NC
Q0
A4
A3
A2
A1
A0
Q0
Q1
Q2
GND
5
6
7
8
9
10
11
12
1
13
4
28-pin
DIP
7
8
9
10
11
12
13
14
A
V
A
1
P
7
2
P
4 3 2 1
32-pin
151
6
Q
G
1Q2
N
D
N
C
PLCC
1
7
N
C
A
V
1
C
4
C
3
231
18192
Q3Q4Q
BLOCK DIAGRAM
V
28
CC
A14
27
A13
26
A8
25
A9
24
A11
23
22
OE
A10
21
20
CE
Q7
19
18
Q6
17
Q5
16
Q4
15
Q3
A
1
3
3
29
A8
0
A9
28
27
A11
NC
26
25
OE
A10
24
23
CE
22
Q7
21
Q6
0
5
PIN DESCRIPTION
A14
V
CC
GND
V
PP
CE
OE
A0
.
.
CONTROL
DECODER
OUTPUT
CORE
ARRAY
SYMBOL DESCRIPTION
A0−A14
Q0−Q7
Address Inputs
Data Inputs/Outputs
Chip Enable
Output Enable
VPP Program/Erase Supply Voltage
VCC Power Supply
GND Ground
NC No Connection
Q0
.
.
Q7
Publication Release Date: January 1997
- 1 - Revision A3
W27E257
CE
CE
FUNCTIONAL DESCRIPTION
Read Mode
Like conventional UVEPROMs, the W27E257 has two control functions, both of which produce data
at the outputs.
is for power control and chip select. OE controls the output buffer to gate data to the output pins.
When addresses are stable, the address access time (TACC) is equal to the delay from CE to output
(TCE), and data are available at the outputs TOE after the falling edge of OE, if TACC and TCE timings
are met.
Erase Mode
The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs,
which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half
an hour), the W27E257 uses electrical erasure. Generally, the chip can be erased within 100 mS by
using an EPROM writer with a special erase algorithm.
Erase mode is entered when VPP is raised to VPE (14V), VCC = VCE (5V), OE = VIH (2V or above but
lower than VCC), A9 = VHH (14V), A0 = VIL (0.8V or below but higher than GND), and all other
address pins equal VIL and data input pins equal VIH. Pulsing CE low starts the erase operation.
Erase Verify Mode
After an erase operation, all of the bytes in the chip must be verified to check whether they have been
successfully erased to "1" or not. The erase verify mode automatically ensures a substantial erase
margin. This mode will be entered after the erase operation if VPP = VPE (14V), CE = VIH, and OE =
VIL.
Program Mode
Programming is performed exactly as it is in conventional UVEPROMs, and programming is the only
way to change cell data from "1" to "0." The program mode is entered when VPP is raised to VPP
(12V), VCC = VCP (5V), OE = VIH, the address pins equal the desired address, and the input pins
equal the desired inputs. Pulsing CE low starts the programming operation.
Program Verify Mode
All of the bytes in the chip must be verified to check whether or not they have been successfully
programmed with the desired data. Hence, after each byte is programmed, a program verify
operation should be performed. The program verify mode automatically ensures a substantial
program margin. This mode will be entered after the program operation if VPP = VPP (12V), CE = VIH,
and OE = VIL.
Erase/Program Inhibit
Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different
data. When CE = VIH, erasing or programming of non-target chips is inhibited, so that except for the
and OE pins, the W27E257 may have common inputs.
- 2 -
W27E257
Standby Mode
The standby mode significantly reduces VCC current. This mode is entered when CE = VIH. In
standby mode, all outputs are in a high impedance state, independent of OE.
Two-line Output Control
Since EPROMs are often used in large memory arrays, the W27E257 provides two control inputs for
multiple memory connections. Two-line control provides for lowest possible memory power
dissipation and ensures that data bus contention will not occur.
System Considerations
EPROM power switching characteristics require careful device decoupling. System designers are
interested in three supply current issues: standby current levels (ISB), active current levels (ICC), and
transient current peaks produced by the falling and rising edges of CE. Transient current magnitudes
depend on the device output's capacitive and inductive loading. Two-line control and proper
decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 µ
F ceramic capacitor connected between its VCC and GND. This high frequency, low inherentinductance capacitor should be placed as close as possible to the device. Additionally, for every eight
devices, a 4.7 µF electrolytic capacitor should be placed at the array's power supply connection
between VCC and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace
inductances.
TABLE OF OPERATING MODES
(VPP = 12V, VPE = 14V, VHH = 12V, VCP = 5V, X = VIH or VIL)
MODE PINS
CE OE A0 A9 VCC VPP OUTPUTS
Read VIL VIL X X VCC VCC DOUT
Output Disable VIL VIH X X VCC VCC High Z
Standby (TTL) VIH X X X VCC VCC High Z
Standby (CMOS)
Program VIL VIH X X VCP VPP DIN
Program Verify VIH VIL X X VCP VPP DOUT
Program Inhibit VIH VIH X X VCP VPP High Z
Erase VIL VIH VIL VPE VCC VPE DIH
Erase Verify VIH VIL X X VCC VPE DOUT
Erase Inhibit VIH VIH X X VCP VPP High Z
Product Identifier-manufacturer VIL VIL VIL VHH VCC VCC DA (Hex)
Product Identifier-device VIL VIL VIH VHH VCC VCC 02 (Hex)
VCC ±0.3V
X X X VCC VCC High Z
Publication Release Date: January 1997
- 3 - Revision A3
DC CHARACTERISTICS
CE
CE
Absolute Maximum Ratings
PARAMETER RATING UNIT
W27E257
Ambient Temperature with Power Applied -55 to +125
Storage Temperature -65 to +125
Voltage on all pins with Respect to Ground Except VPP, A9
and VCC pins
Voltage on VPP Pin with Respect to Ground -0.5 to +14.5 V
Voltage on A9 Pin with Respect to Ground -0.5 to +14.5 V
Voltage on VCC Pin with Respect to Ground -0.5 to +7 V
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.
-0.5 to VCC +0.5 V
°C
°C
DC Erase Characteristics
(TA = 25° C ±5° C, VCC = 5.0V ±10%)
PARAMETER SYM. CONDITIONS LIMITS UNIT
MIN. TYP. MAX.
Input Load Current ILI VIN = VIL or VIH -10 - 10
VCC Erase Current ICP
VPP Erase Current IPP
Input Low Voltage VIL - -0.3 - 0.8 V
= VIL
= VIL
- - 30 mA
- - 30 mA
µA
Input High Voltage VIH - 2.4 - 5.5 V
Output Low Voltage (Verify) VOL IOL = 2.1 mA - - 0.45 V
Output High Voltage (Verify) VOH IOH = -0.4 mA 2.4 - - A9 Erase Voltage VID - 13.75 14 14.25 V
VPP Erase Voltage VPE - 13.75 14 14.25 V
VCC Supply Voltage (Erase) VCE - 4.5 5.0 5.5 V
Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.
CAPACITANCE
(VCC = 5V, TA = 25° C, f = 1 MHz)
PARAMETER SYMBOL CONDITIONS MAX. UNIT
Input Capacitance CIN VIN = 0V 6 pF
Output Capacitance COUT VOUT = 0V 12 pF
- 4 -
W27E257
AC CHARACTERISTICS
AC Test Conditions
PARAMETER CONDITIONS
Input Pulse Levels 0.45V to 2.4V
Input Rise and Fall Times 10 nS
Input and Output Timing Reference Level 0.8V/2.0V
Output Load CL = 100 pF, IOH/IOL = -0.4 mA/2.1 mA
AC Test Load and Waveform
+1.3V
(IN914)
D
OUT
Input
2.4V
0.45V
3.3K ohm
100 pF (Including Jig and Scope)
Output
Test Points Test Points
2.0V
0.8V
2.0V
0.8V
Publication Release Date: January 1997
- 5 - Revision A3
Loading...