Winbond Electronics W25P243AD-6, W25P243AD-5, W25P243AD-4A, W25P243AF-6, W25P243AF-5 Datasheet

W25P243A

LBO

ZZ

64K × 64 BURST PIPELINED HIGH-SPEED

CMOS STATIC RAM

GENERAL DESCRIPTION

The W25P243A is a high-speed, low-power, synchronous-burst pipelined, CMOS static RAM
organized as 65,536 × 64 bits that operates on a single 3.3-volt power supply. A built-in two-bit burst
address counter supports both Pentium burst mode and linear burst mode. The mode to be

executed is controlled by the
the FT pin. A snooze mode can reduce power dissipation.

W25P243A supports 2T/1T mode, while disable data output within one cycle in a burst read when the
device is deselected by CE2/CE3 .

This device supports 3-1-1-1-2-1-1-1 in a two-bank, back-to-back burst read cycle.

FEATURES

pin. Pipelining or non-pipelining of the data outputs is controlled by

•

Synchronous operation

•

High-speed access time: 4.5/5/6 nS (max.)

•

Single +3.3V power supply

•

Individual byte write capability

•

3.3V LVTTL compatible I/O

•

Clock-controlled and registered input

•

Asynchronous output enable

BLOCK DIAGRAM

A(15:0)

CLK

CE(3:1)

GW

BWE

BW(8:1)

OE

ADSC

ADSP

ADV
LBO

INPUT

REGISTER

CONTROL

REGISTER

LOGIC

•

Pipelined data output capability

•

Supports snooze mode (low-power state)

•

Internal burst counter supports Intel burst

(Interleaved) mode & linear burst mode

•

Support 2T/1T mode

•

Packaged in 128-pin QFP and TQFP

64K X 64

CORE

ARRAY

DATA I/O

REGISTER

I/O(64:1)

Publication Release Date: August 1999

- 1 - Revision A3

PIN CONFIGURATION

S

V
D
D
Q

C

NCN

E
2

W25P243A

/

/
/
C
E

C

3

/

/
B
W
5

/
/
O
E

/

B

/

C

B

W

G

L

W

E

W

K

4

V

S

D

S

D

B

B

C

W

W

W

E

8

6

7

/

/

/

B

V

/
B
W
3

/

/

B

V

B

V

W

S

W

D

2

1

D

V

/

A

A

S

A

D

D

S

D

S

S

Q

V

C

P

VSSQ
I/O33
I/O34
I/O35
I/O36
I/O37
I/O38
I/O39
I/O40
I/O41
I/O42
I/O43
VDDQ
VSSQ
I/O44
I/O45
I/O46
I/O47
I/O48
I/O49
I/O50
I/O51
I/O52
I/O53
VDDQ
VSSQ
I/O54
I/O55
I/O56
I/O57
I/O58
I/O59
I/O60
I/O61
I/O62
I/O63
I/O64

VDDQ

1

1

1

1

1

1

1

1

1

1

1

1

2

2

2

2

2

2

7

8

6

5

3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38

3
9

4

4

424

4

0

3

1

2

2

3

2

44454

1

2

1

1

1

2

1

9

8

7

0

48495

4

6

0

7

1

1

1

1

1

1

1
6

5
1

1

1

1

2

3

4

5

5

5

5

455

3

2

1

1

1

1

1

0

1

1

0

0

575

0

9

8

7

5

606

9

8

1

5
6

1

1

1

1

102

0

0

0

0

3

6

4

5

6

6

2

1

3

VDDQ

101

I/O32

100

I/O31

99

I/O30

98

I/O29

97

I/O28

96

I/O27

95

I/O26

94

I/O25

93

I/O24

92

I/O23

91

I/O22

90

VSSQ

89

VDDQ

88

I/O21

87

I/O20

86

I/O19

85

I/O18

84

I/O17

83

I/O16

82

I/O15

81

I/O14

80

I/O13

79

I/O12

78

VSSQ

77

VDDQ

76

I/O11

75

I/O10

74

I/O9

73

I/O8

72

I/O7

71

I/O6

70

I/O5

69

I/O4

68

I/O3

67

I/O2

66

I/O1

65

VSSQ

6
4

A

R

A

V

A

N

/

S

1

C

L

S

5

B

Q

O

V

A

V
1
4

A

S

1

D

1

3

D

S

2

A

A

A

1

8

1

9

0

1

A5A4A

A

A

S

7

6

V

A2A

V

V

3

D

S

D

S

Z

V

A

1

Z

D

0

D
Q

- 2 -

PIN DESCRIPTION

CE1

GW

BWE

BW1

BWE

OE

ADV

ADSC

ADSP

LBO

SYMBOL TYPE DESCRIPTION

W25P243A

A0−A15

I/O1−I/O64

CLK Input, Clock Processor host bus clock

, CE2, CE3

−

BW8

ZZ Input, Asynchronous Snooze pin for low-power state, internal pull low

DDQ

V

I/O power supply

SSQ

V

I/O ground

VDD Power supply

VSS Ground

RSV Reserved pin, don't use these pins

NC No connection

Input, Synchronous Host address
I/O, Synchronous Data Inputs/Outputs

Input, Synchronous Chip enables
Input, Synchronous Global write
Input, Synchronous Byte write enable from cache controller
Input, Synchronous
Input, Asynchronous Output enable input
Input, Synchronous Internal burst address counter advance
Input, Synchronous Address status from Chip Set

Input, Synchronous Address status from CPU

Input, Static Lower address burst order

Host bus byte enables used with

Connected to VSS: Device is in linear mode.
Connected to VDD or unconnected: Device is in non-

linear mode.

Publication Release Date: August 1999

- 3 - Revision A3

W25P243A

LBO

ADSP

ADSC

ADV

LBO

LBO

BWE

GW

FUNCTIONAL DESCRIPTION

The W25P243A is a synchronous-burst pipelined SRAM designed for use in high-end personal
computers. It supports two burst address sequences for Intel systems (Interleaved mode) and linear

mode, which can be controlled by the
and the burst counter is incremented whenever

BURST ADDRESS SEQUENCE

pin. The burst cycles are initiated by

is sampled low.

or

INTEL SYSTEM (

= VDD) LINEAR MODE (

= VSS)

A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0]
External Start Address 00 01 10 11 00 01 10 11
Second Address 01 00 11 10 01 10 11 00
Third Address 10 11 00 01 10 11 00 01
Fourth Address 11 10 01 00 11 00 01 10

The device supports several types of write mode operations.
byte writes. The BE[7:0] signals can be directly connected to the SRAM BW[8:1]. The

and BW[8:1] support individual

signal is
used to override the byte enable signals and allows the cache controller to write all bytes to the
SRAM, no matter what the byte write enable signals are. The various write modes are indicated in the
Write Table below. Note that in pipelined mode, the byte write enable signals are not latched by the
SRAM with addresses but with data. In pipelined mode, the cache controller must ensure the SRAM
latches both data and valid byte enable signals from the processor.

TRUTH TABLE

CYCLE

Unselected No 1 X X X 0 X X Hi-Z X
Unselected No 0 X 1 0 X X X Hi-Z X
Unselected No 0 0 X 0 X X X Hi-Z X
Unselected No 0 X 1 1 0 X X Hi-Z X
Unselected No 0 0 X 1 0 X X Hi-Z X
Begin Read External 0 1 0 0 X X X Hi-Z X
Begin Read External 0 1 0 1 0 X X Hi-Z Read
Continue Read Next X X X 1 1 0 1 Hi-Z Read
Continue Read Next X X X 1 1 0 0 D-Out Read
Continue Read Next 1 X X X 1 0 1 Hi-Z Read
Continue Read Next 1 X X X 1 0 0 D-Out Read
Suspend Read Current X X X 1 1 1 1 Hi-Z Read
Suspend Read Current X X X 1 1 1 0 D-Out Read
Suspend Read Current 1 X X X 1 1 1 Hi-Z Read
Suspend Read Current 1 X X X 1 1 0 D-Out Read

ADDRESS

USED

CE1

CE2

CE3 ADSP ADSC ADV

OE

DATA WRITE*

- 4 -

W25P243A

Truth Table, continued

CYCLE

Begin Write Current X X X 1 1 1 X Hi-Z Write
Begin Write Current 1 X X X 1 1 X Hi-Z Write
Begin Write External 0 1 0 1 0 X X Hi-Z Write
Continue Write Next X X X 1 1 0 X Hi-Z Write
Continue Write Next 1 X X X 1 0 X Hi-Z Write
Suspend Write Current X X X 1 1 1 X Hi-Z Write
Suspend Write Current 1 X X X 1 1 X Hi-Z Write

Notes:

1. For a detailed definition of read/write, see the Write Table below.

2. An "X" means don't care, "1" means logic high, and "0" means logic low.

3. TheOE pin enables the data output and is not sampled with the clock. All signals of the SRAM are sampled synchronously
with the bus clock except for theOE pin.

4. On a write cycle that follows a read cycle, OE must be inactive prior to the start of write cycle to allow write data to setup to
the SRAM. OE must also disable the output buffer prior to the finish of a write cycle to ensure the SRAM data hold timings

are met.

ADDRESS

USED

CE1

CE2

CE3 ADSP ADSC ADV

OE

DATA WRITE*

WRITE TABLE

READ/WRITE FUNCTION

Read 1 1 X X X X X X X X
Read 1 0 1 1 1 1 1 1 1 1
Write byte 1 I/O1−I/O8
Write byte 2 I/O9−I/O16
Write byte 2, byte 1 1 0 1 1 1 1 1 1 0 0
Write byte 3 I/O17−I/O24
Write byte 3, byte 1 1 0 1 1 1 1 1 0 1 0
Write byte 3, byte 2 1 0 1 1 1 1 1 0 0 1
Write byte 3, byte 2, byte 1 1 0 1 1 1 1 1 0 0 0
Write byte 4, I/O25−I/O32
Write byte 4, byte 1 1 0 1 1 1 1 0 1 1 0
Write byte 4, byte 2 1 0 1 1 1 1 0 1 0 1
Write byte 4, byte 2, byte 1 1 0 1 1 1 1 0 1 0 0
Write byte 4, byte 3 1 0 1 1 1 1 0 0 1 1
Write byte 4, byte 3, byte 1 1 0 1 1 1 1 0 0 1 0
Write byte 4, byte 3, byte 2 1 0 1 1 1 1 0 0 0 1
Write byte 4, byte 3, byte 2, byte 1 1 0 1 1 1 1 0 0 0 0
Write byte 5, I/O33−I/O40
Write byte 5, byte 1 1 0 1 1 1 0 1 1 1 0

GW

BW8 BW7 BW6 BW5 BW4 BW3 BW2 BW1

BWE

1 0 1 1 1 1 1 1 1 0
1 0 1 1 1 1 1 1 0 1

1 0 1 1 1 1 1 0 1 1

1 0 1 1 1 1 0 1 1 1

1 0 1 1 1 0 1 1 1 1

Publication Release Date: August 1999

- 5 - Revision A3

W25P243A

Write Table, continued

READ/WRITE FUNCTION

Write byte 5, byte 2 1 0 1 1 1 0 1 1 0 1
Write byte 5, byte 2, byte 1 1 0 1 1 1 0 1 1 0 0
Write byte 5, byte 3 1 0 1 1 1 0 1 0 1 1
Write byte 5, byte 3, byte 1 1 0 1 1 1 0 1 0 1 0
Write byte 5, byte 3, byte 2 1 0 1 1 1 0 1 0 0 1
Write byte 5, byte 3, byte 2, byte 1 1 0 1 1 1 0 1 0 0 0
Write byte 5, byte 4 1 0 1 1 1 0 0 1 1 1
Write byte 5, byte 4, byte 1 1 0 1 1 1 0 0 1 1 0
Write byte 5, byte 4, byte 2 1 0 1 1 1 0 0 1 0 1
Write byte 5, byte 4, byte 2, byte 1 1 0 1 1 1 0 0 1 0 0
Write byte 5, byte 4, byte 3 1 0 1 1 1 0 0 0 1 1
Write byte 5, byte 4, byte 3, byte 1 1 0 1 1 1 0 0 0 1 0
Write byte 5, byte 4, byte 3, byte 2 1 0 1 1 1 0 0 0 0 1
Write byte 5, byte 4, byte 3, byte 2,

byte 1
Write byte 6 1 0 1 1 0 1 1 1 1 1
Write byte 6, byte 1 1 0 1 1 0 1 1 1 1 0
Write byte 6, byte 2 1 0 1 1 0 1 1 1 0 1
Write byte 6, byte 2, byte 1 1 0 1 1 0 1 1 1 0 0

..... and so on ..... ... ... ... ... ... ... ... ... ... ...

Write byte 8, byte 7, byte 6, byte 5,
byte 4, byte 2, byte 1

Write byte 8, byte 7, byte 6, byte 5,
byte 4, byte 3

Write byte 8, byte 7, byte 6, byte 5,
byte 4, byte 3, byte 1

Write byte 8, byte 7, byte 6, byte 5,
byte 4, byte 3, byte 2

Write all bytes 1 0 0 0 0 0 0 0 0 0
Write all bytes 0 x x x x x x x x x

GW

1 0 1 1 1 0 0 0 0 0

1 0 0 0 0 0 0 1 0 0

1 0 0 0 0 0 0 0 1 1

1 0 0 0 0 0 0 0 1 0

1 0 0 0 0 0 0 0 0 1

BW8 BW7 BW6 BW5 BW4 BW3 BW2 BW1

BWE

Power Down Mode

The ZZ state is a low-power state in which the device consumes less power than in the unselected
mode. Enabling the ZZ pin for a fixed period of time will force the SRAM into the ZZ state. Pulling the
ZZ pin low for a set period of time will wake up the SRAM again. While the SRAM is in ZZ mode, data
retention is guaranteed, but the chip will not monitor any input signals except for the ZZ pin. In the
unselected mode, on the other hand, all the input signals are monitored.

- 6 -

W25P243A

DC CHARACTERISTICS

Absolute Maximum Ratings

PARAMETER RATING UNIT

Core Supply Voltage to Vss -0.5 to 4.6 V
I/O Supply Voltage to Vss -0.5 to 4.6 V
Input/Output to V

SSQ

Potential V
Allowable Power Dissipation 1.0 W
Storage Temperature -65 to 150
Operating Temperature 0 to +70

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.

Operating Characteristics

(VDD/V

DDQ

= 3.15V to 3.6V, VSS/V

SSQ

= 0V, TA = 0 to 70° C)

SSQ

-0.5 to V

DDQ

+0.5 V

°

C

°

C

PARAMETER SYM.

Input Low Voltage VIL - -0.5 - +0.8 V
Input High Voltage VIH - +2.0 - VDD

TEST CONDITIONS MIN. TYP. MAX. UNIT

V

+0.3
Input Leakage Current ILI VIN = V
Output Leakage

Current

ILO V

I/O

= V

I/O pins in high-Z state defined

SSQ

SSQ

to V
to V

DDQ

-10 - +10

DDQ,

and data

-10 - + 10

µ

A

µA

in truth table
Output Low Voltage VOL IOL = +8.0 mA - - 0.4 V
Output High Voltage VOH IOH = -4.0 mA 2.4 - - V
Operating Current IDD

T

CYC

≥

min. , I/O = 0 mA

Standby Current ISB Unselected mode defined in

- - 350 mA

- - 80 mA

truth table,

≥

min.

IH

(min.) /VIL (max.)

CYC

≥

min.

- - 5 mA

VIN, VIO = V

CYC

T
ZZ Mode Current IZZ

Note: Typical characteristics are measured at VDD = 3.3V, TA = 25° C.

ZZ mode, T

CAPACITANCE

DD

(V

= 3.3V, TA = 25° C, f = 1 MHz)

PARAMETER SYM. CONDITIONS MAX. UNIT

Input Capacitance CIN VIN = 0V 6 pF
Input/Output Capacitance C

Note: These parameters are sampled but not 100% tested.

I/O

V

OUT

= 0V 8 pF

Publication Release Date: August 1999

- 7 - Revision A3

W25P243A

AC CHARACTERISTICS

AC Test Conditions

PARAMETER CONDITIONS

Input Pulse Levels 0V to 3V
Input Rise and Fall Times 2 nS
Input and Output Timing Reference Level 1.5V
Output Load CL = 30 pF, IOH/IOL = -4 mA/8 mA

AC Test Loads and Waveform

R1 320 ohm

Including
Jig and
Scope

T

OHZ,TOLZ,

5 pF

measurement)

R2
350 ohm

VL = 1.5V

OUTPUT

RL = 50 ohm

Zo = 50 ohm

3.0V

0V

30 pF

Including
Jig and
Scope

2 nS

90%

10%

(For T

10%

3.3V

OUTPUT

KHZ,

90%

2 nS

T

KLZ,

AC Timing Characteristics

(VDD/VDDQ = 3.15V to 3.6V, VSS/VSSQ = 0V, TA = 0 to 70° C, all timings measured in pipelined mode)

PARAMETER SYM. W25P243A-4A W25P243A-5 W25P243A-6 UNIT NOTE

MIN. MAX. MIN. MAX. MIN. MAX.

Address Setup Time T
Address Hold Time T
Write Data Setup Time T
Write Data Hold Time T

ADV

Setup Time

ADV

Hold Time

AS
AH
DS
DH
ADVS

T

ADVH

T

2.0 - 2.0 - 2.0 -

1.0 - 1.0 - 1.0 -

2.0 - 2.0 - 2.0 -

1.0 - 1.0 - 1.0 -

2.0 - 2.0 - 2.0 -

1.0 - 1.0 - 1.0 -

nS
nS
nS
nS
nS
nS

nS

- 8 -

AC Timing Characteristics, continued

PARAMETER SYM. W25P243A-4A W25P243A-5 W25P243A-6 UNIT

MIN. MAX. MIN. MAX. MIN. MAX.

ADSP

Setup Time

ADSP

Hold Time

ADSC

Setup Time

ADSC

Hold Time
CE1
CE1
GW, BWE, BWEx

, CE2,
, CE2,

CE3

Setup Time

CE3

Hold Time

Setup

Time

GW, BWE, BWEx

Hold Time
Clock Cycle Time T
Clock High Pulse Width T
Clock Low Pulse Width T
Clock Access Time T
Clock High to Output High-Z
Clock High to Output Low-Z T
Output Hold from Clock High T
Output Enable to Output Valid T
Output Disable to Output High-Z T
Output Enable to Output Low-Z T
ZZ Standby Time T
ZZ Recover Time T

ADSS

T

ADSH

T

ADCS

T

ADCH

T

CES

T

CEH

T

WS

T

WH

T

CYC
KH
KL
KQ
KHZ

T

KLZ
KX
OE
OHZ
OLZ
ZZS
ZZR

W25P243A

2.0 - 2.0 - 2.0 - nS

1.0 - 1.0 - 1.0 - nS

2.0 - 2.0 - 2.0 - nS

1.0 - 1.0 - 1.0 - nS

2.0 - 2.0 - 2.0 - nS

1.0 - 1.0 - 1.0 - nS

2.0 - 2.0 - 2.0 - nS

1.0 - 1.0 - 1.0 - nS
10 - 12 - 13.3

4 - 5 - 6
4 - 5 - 6

- 4.5 - 5 - 6

1.5 10 1.5 12

0 - 0 - 0 1

1.5 - 1.5 - 1.5 -

- 4.5 - 5 - 6

- 4.5 - 5 - 6

0 - 0 - 0 -

- 100 - 100 - 100

100 - 100 - 100 -

1.5 13.3

- nS

- nS

- nS
nS
nS
nS
nS
nS
nS
nS
nS
nS

NOTE

1
1
1

1
1
2
3

Notes:

1. These parameters are sampled but not 100% tested

2. In the ZZ mode, the SRAM will enter a low-power state. In this mode, data retention is guaranteed and the clock is active.

3.

4. Configuration signals

ADSC

and

should not be accessed for at least 100 nS after chip leaves ZZ mode.

ADSP

and FT are static and should not be changed during operation.

LBO

Publication Release Date: August 1999

- 9 - Revision A3

TIMING WAVEFORMS

Read Cycle Timing

W25P243A

CLK

ADSP

ADSC

ADV

A[15:0]

GW

BWE

BW[8:1]

CE1

CE2

Single Read Burst Read

T

ADSS

T

ADSH

T

T

ADVSTADVH

TAST

AH

RD1

TWST

WH

TWST

WH

T

CESTCEH

T

T

CES

CEH

CE2 / CE3 only sampled with ADSP or ADSC

ADCS

RD2

T

T

T

KH

ADCH

CYC

T

Pipelined Read

Unselected

KL

ADSP is blocked by CE1 inactive

ADSC initiated read

Suspend Burst

RD3

CE1 masks ADSP

Unselected with CE2

T

CESTCEH

CE3

T

T

OHZ

OE

OE

T

KX

2a

T

KQ

Data-Out

Data-In

High-Z

High-Z

T

OLZ

1a

T

KLZ

T

KQ

DON'T CARE
UNDEFINED

- 10 -

3a

2b

2c

2d

T

KHZ

Timing Waveforms, continued

Write Cycle Timing

W25P243A

CLK

ADSP

ADSC

ADV

A[15:0]

GW

BWE

BW[8:1]

CE1

CE2

CE3

Single Write

TADSS TADSH

T

ADCS

T

ADVSTADVH

T

AS TAH

WR1

TWS

TWS TWH

TWSTWH

T

TCEH

CES

T

CES TCEH

T

CES TCEH

Burst Write

TCYC

T

KH

T

KL

T

ADCH

ADV must be inactive for ADSP write

WR2

T

WH

WR1

CE2 / CE3 only sampled with ADSP or ADSC

GWE allows processor address (and BE=BW)

to be pipelined during a writeback

WR2

ADSP is blocked by CE1 inactive

CE1 masks ADSP

Write

Unselected

ADSC initiated write

WR3

WR3

Unselected with CE2

OE

Data-Out

Data-In

High-Z

High-Z

TDS TDH

1a

DON'T CARE

UNDEFINED

BW[4:1] are applied only to first cycle of WR2
2a 2b 2c

2d 3a

Publication Release Date: August 1999

- 11 - Revision A3

Timing Waveforms, continued

Read/Write Cycle Timing

W25P243A

CLK

ADSP

ADSC

ADV

A[15:0]

GW

BWE

BW[8:1]

CE1

CE2

T

ADSS

TAST

T

CESTCEH

T

CESTCEH

Single Read

T

ADSH

T

ADVSTADVH

AH

RD1

T

WS

T

WSTWH

Single Write

T

CYC

T

KH

T

KL

T

T

ADCH

ADCS

ADSC initiated read

Suspend Burst

WR1

T

WH

T

T

WS

WH

WR1

CE2 / CE3 only sampled with ADSP or ADSC

Burst Read Unselected

ADSP is blocked by CE1 inactive

RD2

CE1 masks ADSP

T

CESTCEH

CE3

T

T

OE

OHZ

OE

T

OH

1a

TDST

DH

1a

Data-Out

Data-In

High-Z

High-Z

T

OLZ

T

KLZ

T

KQ

DON'T CARE

UNDEFINED

- 12 -

Unselected with CE3

T

KX

2a

2b

2c

2d

T

KHZ

Timing Waveforms, continued

ZZ and RD Timing

W25P243A

CLK

ADSP

ADSC

ADV

A[15:0]

GW

BWE

BW[8:1]

CE1

CE2

CE3

OE

Data-Out

Data-In

Single Read Snooze -with Data Retention

T

ADSS

T

AS

T

ADSH

T

ADVSTADVH

T

AH

T

CYC

T

KH

T

KL

RD1

TWST

WH

TWST

WH

T

T

WS

WH

RD RD

T

CESTCEH

T

CESTCEH

T

T

CES

CEH

T

OETOHZ

T

OLZ

High-Z

High-Z

T

KLZ

1a

T

KX

T

KHZ

T

KQ

Read

RD2

RD

T

ZZS

T

ZZR

ZZ

DON'T CARE
UNDEFINED

Publication Release Date: August 1999

- 13 - Revision A3

Timing Waveforms, continued

Dual Bank Burst Read Cycle

CLK

Select Bank 0

ADSP

ADSC

ADV

Select Bank 1

W25P243A

Select Bank 0

A[31:3]

GW

BWE

BW[8:1]

CE1

CE[3:2]
Bank 0

CE[3:2]
Bank 1

OE

D[63:0]
Bank 0

D[63:0]
Bank 1

Active

Non­Active

Read 1

Read 2

Non-

Active

Activ

1a

1b

1d1c

2a

2b

Read 3

Active

Non­Active

2d2c

DON'T CARE

UNDEFINED

- 14 -

ORDERING INFORMATION

W25P243A

PART NO. ACCESS

TIME (nS)

W25P243AF-4A 4.5 350 80 128-pin QFP
W25P243AF-5 5 350 80 128-pin QFP
W25P243AF-6 6 350 80 128-pin QFP
W25P243AD-4A 4.5 350 80 128-pin TQFP
W25P243AD-5 5 350 80 128-pin TQFP
W25P243AD-6 6 350 80 128-pin TQFP

Notes

1. Winbond reserves the right to make changes to its products without prior notice.

2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications
where personal injury might occur as a consequence of product failure.

OPERATING

CURRENT

MAX. (mA)

STANDBY
CURRENT

MAX. (mA)

PACKAGE

Publication Release Date: August 1999

- 15 - Revision A3

PACKAGE DIMENSIONS

128-pin QFP

128

W25P243A

H

D

D

103

1

38

39

Seating Plane

e

See Detail F

b

Symbol

A
A

1
2

A
b
c
D
E

e

D

H

E

H
L

1

L
y

θ

102

65

64

A

A

y

Dimension in inches

Nom.

Min.

0.004

0.101

0.006

0.004

0.547

0.783 0.787 0.791

0.669

0.905

0.023

0.055

Max. Max.

0.134

0.113

0.107

0.010

0.008

0.006 0.15

0.010

0.555

0.551

0.020

0.685

0.677

0.921

0.913

0.039

0.031

0.071

0.063

0.004

E

H

E

A

2

1

13.90

19.90

17.00

23.00

Dimension in mm

Nom.

Min.

0.10

2.57

2.72

0.15

0.20

0.10

14.00

20.00

0.50

17.20

23.20 23.40

0.80

0.60

1.60

1.40

0120

c

L

3.40

2.87

0.25

0.25

14.10

20.10

17.40

1.00

1.80

0.10
12

θ

L

1

Detail F

- 16 -

Package Dimensions, continued

128-pin TQFP

128

W25P243A

H

D

D

103

1

38

39

Seating Plane

e

See Detail F

b

Symbol

A
A

1

A

2

b
c

D
E

e
HD

H

E

L

1

L
y

θ

102

65

64

2

A

A

y

Dimension in inches

Nom.

Min.

0.002

0.053

0.006

0.004

0.547

0.783 0.787 0.791

0.626

0.862

0.018

Max. Max.

0.063

0.057

0.055

0.011

0.008

0.006 0.15

0.010

0.555

0.551

0.020

0.634

0.630

0.870

0.866

0.030

0.024

0.039

0.004

E

HE

A

1

0.05

1.35

0.15

0.10

13.90

19.90

15.90

21.90

0.45

Dimension in mm

Nom.

Min.

1.40

0.20

14.00

20.00

0.50

16.00

22.00 22.10

0.60

1.00

0120

c

L

1.60

1.45

0.27

0.25

14.10

20.10

16.10

0.75

0.10
12

θ

L

1

Detail F

Publication Release Date: August 1999

- 17 - Revision A3

VERSION HISTORY

VERSION DATE PAGE DESCRIPTION

A1 Nov. 1997 Initial Issued
A2 Feb. 1998 1 to 5, 8 to 12, 14

A3 Aug. 1999 1, 8, 9, 15 Support 83, 75 MHz

9 T

Eliminate the CE2 and CE3 functionality

OHZ

: Change from "Output Enable" to "

Output Disable"

W25P243A

Headquarters

No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: [phone]
FAX: [phone]
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-7197006

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: [phone]
FAX: [phone]

Note: All data and specifications are subject to change without notice.

Winbond Electronics (H.K.) Ltd.

Rm. 803, World Trade Square, Tower II,
123 Hoi Bun Rd., Kwun Tong,
Kowloon, Hong Kong
TEL: [phone]
FAX: [phone]

- 18 -

Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.

2727 N. First Street, San Jose,
CA 95134, U.S.A.
TEL: [phone]

FAX: [phone]