Winbond Electronics W27C520W-90, W27C520W-70, W27C520S-90, W27C520S-70 Datasheet

Preliminary W27C520

64K × 8 ELECTRICALLY ERASABLE EPROM

GENERAL DESCRIPTION

The W27C520 is a high speed, low power Electrically Erasable and Programmable Read Only Memory organized as 65,536 × 8 bits. It includes latches for the lower 8 address lines to multiplex with the 8 data lines. To cooperate with the MCU, this device could save the external TTL component, also cost and space. It requires only one supply in the range of 3.0V to 3.6V or 4.5V to 5.5V in normal read mode. The W27C520 provides an electrical chip erase function. It will be a great convenient when you need to change/update the contents in the device.

FEATURES

• High speed access time: 70/90 nS (max.)

• Read operating current: 8/20 mA (max.)

• Erase/Programming operating current

30 mA (max.)

• Standby current: 20/100 µA (max.)

• Unregulated battery power supply range,

3.0V to 3.6V and 4.5V to 5.5V

• +13V erase and programming voltage

• High Reliability CMOS Technology

− 2K V ESD Protection

− 200 mA Latchup Immunity

• Fully static operation

• All inputs and outputs directly LVTTL/CMOS

compatible

• Three-state outputs

• Available packages: 20-pin TSSOP and 20-pin

SOP

PIN CONFIGURATIONS

A10

A12

A14

ALE

OE/VPP

A15 A13 A11

OE/VPP

A15

A13

A11

AD0

AD2 AD4 AD6

GND

6 7 8 9 10

1 2 3 4 5 6 7 8 9 10

TSSOP

Top View

SOP

Top View

BLOCK DIAGRAM

A8 AD1

AD3

AD5

AD7

GND

15 14

AD6

AD4

AD2 AD0

VDD

ALE

A14

A12

A10

AD1

14 13

AD3 AD5

AD7

PIN DESCRIPTION

SYMBOL DESCRIPTION

AD0−AD7

A8−A15

ALE Address Latch Enable

VDD Power Supply

GND Ground

OE / V

AD7 - AD0

A15 - A8

/VPP

ALE

GND

CONTROL

L A T C H E S

DECODER

OUTPUT BUFFER

MEMORY

ARRAY

Address/Data Inputs/Outputs Address Inputs

Output Enable, Program/Erase Supply Voltage

Publication Release Date: October 2000

- 1 - Revision A1

Preliminary W27C520

FUNCTIONAL DESCRIPTION

Read Mode

Unlike conventional UVEPROMs, which has CE and OE two control functions, the W27C520 has one OE/VPP and one ALE (address_latch_enable) control functions. The ALE makes lower

address A[7:0] to be latched in the chip when it goes from high to low, so that the same bus can be used to output data during read mode. i.e. lower address A[7:0] and data bus DQ[7:0] are multiplexed.

/VPP controls the output buffer to gate data to the output pins. When addresses are stable, the

address access time (TACC) is equal to the delay from ALE to output (TCE), and data are available at the outputs TOE after the falling edge of OE/VPP, if TACC and TCE timings are met.

Erase Mode

The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs, which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half an hour), the W27C520 uses electrical erasure. Generally, the chip can be erased within 100 mS by using an EPROM writer with a special erase algorithm.

There are two ways to enter Erase mode. One is to raise OE/VPP to VPE (13V), VDD = VDE (6.5V), A9 = VHH (13V), A10 = high A8&A11 = low, and all other address pins include AD[7:0] keep at fixed low or high. Pulsing ALE high starts the erase operation. The other way is somewhat like flash, by programming two consecutive commands into the device and then enter Erase mode. The two commands are loading Data = AA(hex) to Addr. = 5555(hex) and Data = 10(hex) to Addr. = 2AAA(hex). Be careful to note that the ALE pulse widths of these two commands are different: One is 50 µS, while the other is 100 mS. Please refer to the Smart Erase Algorithm 1 & 2.

Erase Verify Mode

The device will enter the Erase Verify Mode automatically after Erase Mode. Only power down the device can force the device enter Normal Read Mode again.

Program Mode

Programming is the only way to change cell data from "1" to "0." The program mode is entered when

/VPP is raised to VPP (13V), VDD = VDP (6.5V), the address pins equal the desired addresses, and

the input pins equal the desired inputs. Pulsing ALE high starts the programming operation.

Program Verify Mode

The device will enter the Program Verify Mode automatically after Program Mode. Only power down the device can force the device enter Normal Read Mode again.

Erase/Program Inhibit

Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different data. When ALE low, erasing or programming of non-target chips is inhibited, so that except for the

ALE and OE/VPP pins, the W27C520 may have common inputs.

Standby Mode

The standby mode significantly reduces VDD current. This mode is entered when ALE and OE/VPP keep high. In standby mode, all outputs are in a high impedance state.

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Preliminary W27C520

System Considerations

An EPROM's power switching characteristics require careful device decoupling. System designers are interested in three supply current issues: standby current levels (ISB), active current levels (IDD), and transient current peaks produced by the falling and rising edges of ALE Transient current magnitudes depend on the device output's capacitive and inductive loading. Proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a

0.1 µF ceramic capacitor connected between its VDD and GND. This high frequency, low inherentinductance capacitor should be placed as close as possible to the device. Additionally, for every eight devices, a 4.7 µF electrolytic capacitor should be placed at the array's power supply connection between VDD and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductances.

TABLE OF OPERATING MODES

(VPP = 13V, VPE = 13V, VHH = 12V, VDP = 6.5V, VDE = 6.5V, VDD = 3.3V or 5.0V, VDI = 5.0V, X = VIH or VIL)

MODE PIN

Address Latch Enable VIH VIH AIN VDD A[7:0] Read VIL VIL AIN VDD DOUT Output Disable VIL/

Standby VIH VIH X VDD A[7:0] Program VIH VPP AIN VDP DIN Erase 1 VIH VPE A8&A11 = VIL, A9 = VPE,

Erase 2 VIH VPE First command:

Second command:

Product Identifiermanufacturer

Product Identifier-device VIL VIL A8 = VIH, A9 = VHH, Others = X VDI 1F(Hex)

ALE

VIH

VIL VIL A8 = VIL, A9 = VHH, Others = X VDI DA(Hex)

/VPP

VIH X VDD High Z

OTHER ADDRESS VDD AD[7:0]

VDE X

A10 = VIH, Others = X

VDE AA(hex)

Addr. = 5555 (hex)

VDE 10(hex)

Addr. = 2AAA (hex)

Publication Release Date: October 2000

- 3 - Revision A1

Preliminary W27C520

DC CHARACTERISTICS

Absolute Maximum Ratings

PARAMETER RATING UNIT

Ambient Temperature with Power Applied -55 to +125 Storage Temperature -65 to +150 Voltage on all Pins with Respect to Ground Except

/VPP, A9 and VDD Pins

Voltage on OE/VPP Pin with Respect to Ground Voltage on A9 Pin with Respect to Ground -2.0 to +7.0 V Voltage VDD Pin with Respect to Ground -2.0 to +14.0 V

Notes:

1. Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.

2. Minimum voltage is -0.6V DC which may undershoot to -2.0V for pulses of less than 20 nS. Maximum output pin voltage is VDD +0.75V DC which may overshoot to +7.0V for pulses of less than 20 nS.

-2.0 to +7.0 V

DC Erase Characteristics

(TA = 25° C ±5° C, VDD = 6.5V ±0.25V)

°C °C

PARAMETER SYM.

Input Load Current ILI VIN = VIL or VIH -10 - 10 VDD Erase Current ICP

VPP Erase Current IPP

Input Low Voltage VIL - -0.3 - 0.8 V Input High Voltage VIH - 2.4 - VDD+0.3 Output Low Voltage

(Verify) Output High Voltage

(Verify) A9 SID Voltage

A9 Erase Voltage VPE - 12.75 13 13.25 V VPP Erase Voltage VPE - 12.75 13 13.25 V VDD Supply Voltage

(Erase & Erase Verify)

Note: VDD must be applied simultaneously or before VPP and removed simultaneously or after VPP.

VOL IOL = 2.1 mA - - 0.45 V

VOH

VHH

VDE - 6.25 6.5 6.75 V

CONDITIONS LIMITS UNIT

ALE = VIH, OE/VPP = VPE A8 & A11 = VIL, A9 = VPE, A10 = VIH, Others = X

IOH = -0.4 mA 2.4 - - -

VDD = 5V ±10%

MIN. TYP. MAX.

- - 30 mA

11.5 12 12.5 V

µA

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Preliminary W27C520

Input

CAPACITANCE

(VDD = 3.0V to 3.6V or 4.5V to 5.5V, TA = 25° C, f = 1 MHz)

PARAMETER SYMBOL MAX. UNIT

Input Capacitance CIN VIN = 0V 6 pF Output Capacitance COUT VOUT = 0V 12 pF

AC CHARACTERISTICS

AC Test Conditions

PARAMETER CONDITIONS

Input Pulse Levels 0V/3V Input Rise and Fall Times 10 nS Input and Output Timing Reference Level 1.5V/1.5V Output Load CL = 100 pF, IOH/IOL = -0.4 mA/2.1 mA

AC Test Load and Waveforms

OUT

+1.3V

(IN914)

3.3K ohm

100 pF (Including Jig and Scope)

Output

Test Points Test Points

1.5V

Publication Release Date: October 2000

- 5 - Revision A1

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