Winbond Electronics W27C512-70, W27C512-12, W27C512-45, W27C512P-90, W27C512P-45 Datasheet
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W27C512
0
3
CE
OE
64K × 8 ELECTRICALLY ERASABLE EPROM
GENERAL DESCRIPTION
The W27C512 is a high speed, low power Electrically Erasable and Programmable Read Only
Memory organized as 65536 × 8 bits that operates on a single 5 volt power supply. The W27C512
provides an electrical chip erase function.
FEATURES
• High speed access time:
45/70/90/120 nS (max.)
• Read operating current: 30 mA (max.)
• Erase/Programming operating current
30 mA (max.)
• Standby current: 1 mA (max.)
• Single 5V power supply
• +14V erase/+12V programming voltage
• Fully static operation
• All inputs and outputs directly TTL/CMOS
compatible
• Three-state outputs
• Available packages: 28-pin 600 mil DIP, 330 mil
32-pin PLCC
PIN CONFIGURATIONS
1
A6
A5
A4
A3
A2
A1
A0
NC
Q0
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
GND
A7N
4 3 2 1
5
6
7
8
9
10
11
12
1
13
4
Q1Q
2
3
4
5
6
7
8
9
10
11
12
13
14
A
1
2
151
2
28-pin
A
1
5
32-pin
PLCC
6
G
N
D
DIP
C
1
7
N
C
A
V
1
C
4
C
323
1
18192
Q
Q
4
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A
1
3
3
0
Q
5
29
28
27
26
25
24
23
22
21
V
CC
A14
A13
A8
A9
A11
OE/Vpp
A10
CE
Q7
Q6
Q5
Q4
Q3
A8
A9
A11
NC
OE/Vpp
A10
CE
Q7
Q6
BLOCK DIAGRAM
Q0
.
.
Q7
OE/V
CE
PP
A0
.
.
A15
V
CC
GND
CONTROL
DECODER
OUTPUT
BUFFER
CORE
ARRAY
PIN DESCRIPTION
SYMBOL DESCRIPTION
A0−A15
Q0−Q7
/VPP
VCC Power Supply
GND Ground
NC No Connection
Address Inputs
Data Inputs/Outputs
Chip Enable
Output Enable, Program/Erase
Supply Voltage
Publication Release Date: November 1999
- 1 - Revision A4
W27C512
CE
FUNCTIONAL DESCRIPTION
Read Mode
Like conventional UVEPROMs, the W27C512 has two control functions, both of which produce data
at the outputs. CE is for power control and chip select. OE/VPP controls the output buffer to gate data
to the output pins. When addresses are stable, the address access time (T
from CE to output (TCE), and data are available at the outputs TOE after the falling edge of OE/VPP,
ACC
if T
and TCE timings are met.
Erase Mode
The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs,
which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half
an hour), the W27C512 uses electrical erasure. Generally, the chip can be erased within 100 mS by
using an EPROM writer with a special erase algorithm.
Erase mode is entered when OE/VPP is raised to VPE (14V), VCC = VCE (5V), A9 = VPE (14V), A0
low, and all other address pins low and data input pins high. Pulsing CE low starts the erase
operation.
Erase Verify Mode
After an erase operation, all of the bytes in the chip must be verified to check whether they have been
successfully erased to "1" or not. The erase verify mode ensures a substantial erase margin if VCC =
VCE (3.75V), CE low, and OE/VPP low.
ACC
) is equal to the delay
Program Mode
Programming is performed exactly as it is in conventional UVEPROMs, and programming is the only
way to change cell data from "1" to "0." The program mode is entered when OE/VPP is raised to VPP
(12V), VCC = VCP (5V), the address pins equal the desired addresses, and the input pins equal the
desired inputs. Pulsing CE low starts the programming operation.
Program Verify Mode
All of the bytes in the chip must be verified to check whether they have been successfully
programmed with the desired data or not. Hence, after each byte is programmed, a program verify
operation should be performed. The program verify mode automatically ensures a substantial
program margin. This mode will be entered after the program operation if OE/VPP low and CE low.
Erase/Program Inhibit
Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different
data. When CE high, erasing or programming of non-target chips is inhibited, so that except for the
and OE/VPP pins, the W27C512 may have common inputs.
- 2 -
W27C512
CE OE
Standby Mode
The standby mode significantly reduces VCC current. This mode is entered when CE high. In standby
mode, all outputs are in a high impedance state, independent of OE/VPP.
Two-line Output Control
Since EPROMs are often used in large memory arrays, the W27C512 provides two control inputs for
multiple memory connections. Two-line control provides for lowest possible memory power
dissipation and ensures that data bus contention will not occur.
System Considerations
An EPROM's power switching characteristics require careful device decoupling. System designers are
interested in three supply current issues: standby current levels (ISB), active current levels (ICC), and
transient current peaks produced by the falling and rising edges of CE. Transient current magnitudes
depend on the device output's capacitive and inductive loading. Two-line control and proper
decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 µ
F ceramic capacitor connected between its VCC and GND. This high frequency, low inherentinductance capacitor should be placed as close as possible to the device. Additionally, for every eight
devices, a 4.7 µF electrolytic capacitor should be placed at the array's power supply connection
between VCC and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace
inductances.
TABLE OF OPERATING MODES
(VPP = 12V, VPE = 14V, VHH = 12V, VCP = 5V, VCE = 5V, X = VIH or VIL)
MODE PINS
Read VIL VIL X X VCC D
Output Disable VIL VIH X X VCC High Z
Standby (TTL) VIH X X X VCC High Z
Standby (CMOS)
Program VIL VPP X X VCP DIN
Program Verify VIL VIL X X VCC D
Program Inhibit VIH VPP X X VCP High Z
Erase VIL VPE VIL VPE VCE DIH
Erase Verify VIL VIL X X 3.75 D
Erase Inhibit VIH VPE X X VCE High Z
Product Identifier-manufacturer VIL VIL VIL VHH VCC DA (Hex)
Product Identifier-device VIL VIL VIH VHH VCC 08 (Hex)
VCC ±0.3V
/VPP
X X X VCC High Z
A0 A9 VCC OUTPUTS
OUT
OUT
OUT
Publication Release Date: November 1999
- 3 - Revision A4
DC CHARACTERISTICS
CE
CE
OE
Absolute Maximum Ratings
PARAMETER RATING UNIT
W27C512
Operation Temperature 0 to +70
Storage Temperature -65 to +125
Voltage on all Pins with Respect to Ground Except OE/V
A9 and VCC Pins
Voltage on OE/VPP Pin with Respect to Ground
Voltage on A9 Pin with Respect to Ground -0.5 to +14.5 V
Voltage VCC Pin with Respect to Ground -0.5 to +7 V
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
PP,
-0.5 to VCC +0.5 V
-0.5 to +14.5 V
°
C
°
C
DC Erase Characteristics
(TA = 25° C ±5° C, VCC = 5.0V ±5%)
PARAMETER SYM.
Input Load Current ILI VIN = VIL or VIH -10 - 10
VCC Erase Current ICP
VPP Erase Current IPP
Input Low Voltage VIL - -0.3 - 0.8 V
Input High Voltage VIH - 2.4 - 5.5 V
Output Low Voltage (Verify) VOL IOL = 2.1 mA - - 0.45 V
Output High Voltage (Verify) VOH IOH = -0.4 mA 2.4 - - A9 Erase Voltage VID - 13.75 14 14.25 V
VPP Erase Voltage VPE - 13.75 14 14.25 V
VCC Supply Voltage (Erase) VCE - 4.75 5.0 5.25 V
VCC Supply Voltage
(Erase Verify)
Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.
VCE - 3.5 3.75 4.0 V
CONDITIONS LIMITS UNIT
MIN. TYP. MAX.
µ
IL,
= V
OE/VPP = VPE
IL,
= V
/VPP = VPE
- - 30 mA
- - 30 mA
A
- 4 -
W27C512
100 pF for 90/120 nS (Including Jig and Scope)
CAPACITANCE
(VCC = 5V, TA = 25° C, f = 1 MHz)
PARAMETER SYMBOL CONDITIONS MAX. UNIT
Input Capacitance CIN VIN = 0V 6 pF
Output Capacitance C
OUT
V
AC CHARACTERISTICS
AC Test Conditions
PARAMETER CONDITIONS
45/70 nS 90/120 nS
Input Pulse Levels 0 to 3.0V 0.45V to 2.4V
Input Rise and Fall Times 5 nS 10 nS
Input and Output Timing Reference Level 1.5V/1.5V 0.8V/2.0V
Output Load CL = 30 pF,
OUT
= 0V 12 pF
IOH/IOL = -0.4 mA/2.1 mA
CL = 100 pF,
IOH/IOL = -0.4 mA/2.1 mA
AC Test Load and Waveforms
D
OUT
For 90/120 nS
For 45/70 nS
2.4V
0.45V
3.0V
0V
Input
Input
+1.3V
(IN914)
3.3K ohm
30 pF for 45/70 nS (Including Jig and Scope)
Output
Test Points Test Points
2.0V
2.0V
0.8V
0.8V
Output
Test Point Test Point
1.5V
1.5V
- 5 - Revision A4
Publication Release Date: November 1999
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