Winbond Electronics W27C4096T-15, W27C4096T-12, W27C4096P-12, W27C4096P-15, W27C4096-15 Datasheet

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Preliminary W27C4096

256K × 16 ELECTRICALLY ERASABLE EPROM

GENERAL DESCRIPTION

The W27C4096 is a high speed, low power Electrically Erasable and Programmable Read Only Memory organized as 262144 × 16 bits that operates on a single 5 volt power supply. The W27C4096 provides an electrical chip erase function.

FEATURES

• High speed access time:

120/150 nS (max.)

• Read operating current: 30 mA (max.)

• Erase/Programming operating current

30 mA (max.)

• Standby current: 100 µA (max.)

• Single 5V power supply

• +14V erase/+12V programming voltage

• Fully static operation

• All inputs and outputs directly TTL/CMOS

compatible

• Three-state outputs

• Available packages: 40-pin 600 mil DIP, TSOP

and 44-pin PLCC

PIN CONFIGURATIONS

Q15

Q14

Q13

Q12

Q11

Q10

40-pin

DIP

GND

1 4

Q2Q

456

44123 4041

44-pin PLCC

232221201918

NCA

Q0/

40-pin TSOP

1 3

Q12

Q11

Q10

GND

Q5 Q4

Q 3

A10

A11

A12

A13

A14 A15

A16

8 9

A17

Q15

Q14

Q13

Q12

Q11

Q10

BLOCK DIAGRAM

A17

A16

A15

A14

A13

A12

A11

A10

GND

4243

A13

A12

A11

A10

GND

2827262524

A2A

GND A8

37 36

A5 A4

31 30

OE Q0

29 28

PIN DESCRIPTION

SYMBOL DESCRIPTION

A0−A17

Q0−Q15

CONTROL

OUTPUT BUFFER

DECODER

CORE

ARRAY

A17

GND

Address Inputs Data Inputs/Outputs Chip Enable

Output Enable VPP Program/Erase Supply Voltage VCC Power Supply

GND Ground

NC No Connection

. .

Q15

Publication Release Date: March 1999

- 1 - Revision A1

Preliminary W27C4096

FUNCTIONAL DESCRIPTION

Read Mode

Like conventional UVEPROMs, the W27C4096 has two control functions, both of which produce data at the outputs. CE is for power control and chip select. OE controls the output buffer to gate data to

the output pins. When addresses are stable, the address access time (TACC) is equal to the delay from CE to output (TCE), and data are available at the outputs TOE after the falling edge of OE, if

TACC and TCE timings are met.

Erase Mode

The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs, which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half an hour), the W27C4096 uses electrical erasure. Generally, the chip can be erased within 100 mS by using an EPROM writer with a special erase algorithm.

Erase mode is entered when VPP is raised to VPE (14V), VCC = VCE (5V), CE low, OE high, A9 = VPE (14V), A0 low, and all other address pins low and data input pins high.

Erase Verify Mode

After an erase operation, all of the words in the chip must be verified to check whether they have been successfully erased to "1" or not. The erase verify mode automatically ensures a substantial

erase margin. This mode will be entered after the erase operation if VPP = VPE (14V), CE high, and

low.

Program Mode

Programming is performed exactly as it is in conventional UVEPROMs, and programming is the only way to change cell data from "1" to "0." The program mode is entered when VPP is raised to VPP

(12V), VCC = VCP (5V), CE low, OE high, the address pins equal the desired address, and the input pins equal the desired inputs.

Program Verify Mode

All of the words in the chip must be verified to check whether they have been successfully programmed with the desired data or not. Hence, after each word is programmed, a program verify operation should be performed. The program verify mode automatically ensures a substantial

program margin. This mode will be entered after the program operation if VPP = VPP (12V), CE high,

low and VCC = VCP (5V).

Erase/Program Inhibit

Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different data. When CE high , VPP = VPP/VPE (12V/14V), and VCC = 5V, erasing or programming of nontarget chips is inhibited, so that except for the CE and VPP, and VCC, the W27C4096 may have

common inputs.

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Preliminary W27C4096

Standby Mode

The standby mode significantly reduces VCC current. This mode is entered when CE high , VPP = 5V, and VCC = 5V. In standby mode, all outputs are in a high impedance state, independent of OE.

Two-line Output Control

Since EPROMs are often used in large memory arrays, the W27C4096 provides two control inputs for multiple memory connections. Two-line control provides for lowest possible memory power dissipation and ensures that data bus contention will not occur.

System Considerations

EPROM power switching characteristics require careful device decoupling. System designers are interested in three supply current issues: standby current levels (ISB), active current levels (ICC), and

transient current peaks produced by the falling and rising edges of CE. Transient current magnitudes depend on the device output's capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 µ F ceramic capacitor connected between its VCC and GND. This high frequency, low inherentinductance capacitor should be placed as close as possible to the device. Additionally, for every eight devices, a 4.7 µF electrolytic capacitor should be placed at the array's power supply connection between VCC and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductances.

TABLE OF OPERATING MODES

(VPP = 12V, VPE = 14V, VHH = 12V, VCP = 5V, X = VIH or VIL)

MODE PINS

A0 A9 VCC VPP OUTPUTS

Read VIL VIL X X VCC VCC DOUT Output Disable VIL VIH X X VCC VCC High Z Standby (TTL) VIH X X X VCC VCC High Z Standby (CMOS) Program VIL VIH X X VCP VPP DIN Program Verify VIH VIL X X VCP VPP DOUT Program Inhibit VIH X X X VCP VPP High Z Erase VIL VIH VIL VPE VCE VPE DIH Erase Verify VIH VIL X X VCE VPE DOUT Erase Inhibit VIH X X X VCE VPE High Z Product Identifier-manufacturer VIL VIL VIL VHH VCC VCC 00DA (Hex) Product Identifier-device VIL VIL VIH VHH VCC VCC 000D (Hex)

VCC ±0.3V

X X X VCC VCC High Z

Publication Release Date: March 1999

- 3 - Revision A1

DC CHARACTERISTICS

Absolute Maximum Ratings

PARAMETER RATING UNIT

Preliminary W27C4096

Ambient Temperature with Power Applied -55 to +125 Storage Temperature -65 to +125 Voltage on all pins with Respect to Ground Except VPP, A9

and VCC pins Voltage on VPP Pin with Respect to Ground -0.5 to +14.5 V Voltage on A9 Pin with Respect to Ground -0.5 to +14.5 V Voltage on VCC Pin with Respect to Ground -0.5 to +7 V

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the

device.

-0.5 to VCC +0.5 V

°C °C

DC Erase Characteristics

(TA = 25° C ±5° C, VCC = 5.0V ± 5%, VHH = 14V)

PARAMETER SYM. CONDITIONS LIMITS UNIT

MIN. TYP. MAX.

Input Load Current ILI VIN = VIL or VIH -10 - 10 VCC Erase Current ICP VPP Erase Current IPP Input Low Voltage VIL - -0.3 - 0.8 V

= VIL = VIL

- - 30 mA

µA

Input High Voltage VIH - 2.4 - 5.5 V Output Low Voltage (Verify) VOL IOL = 2.1 mA - - 0.45 V Output High Voltage (Verify) VOH IOH = -0.4 mA 2.4 - - A9 Erase Voltage VID - 13.75 14 14.25 V VPP Erase Voltage VPE - 13.75 14 14.25 V VCC Supply Voltage (Erase) VCE - 4.5 5.0 5.5 V

Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.

CAPACITANCE

(VCC = 5V, TA = 25° C, f = 1 MHz)

PARAMETER SYMBOL CONDITIONS MAX. UNIT

Input Capacitance CIN VIN = 0V 6 pF Output Capacitance COUT VOUT = 0V 12 pF

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Preliminary W27C4096

100 pF (Including Jig and Scope)

AC CHARACTERISTICS

AC Test Conditions

PARAMETER CONDITIONS

Input Pulse Levels 0.45V to 2.4V Input Rise and Fall Times 10 nS Input and Output Timing Reference Level 0.8V/2.0V Output Load CL = 100 pF, IOH/IOL = -0.4 mA/2.1 mA

AC Test Load and Waveform

+1.3V

(IN914)

OUT

Input

2.4V

0.45V

3.3K ohm

Output

Test Points Test Points

2.0V

0.8V

2.0V

0.8V

Publication Release Date: March 1999

- 5 - Revision A1

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