Preliminary W24256
32K × 8 CMOS STATIC RAM
GENERAL DESCRIPTION
The W24256 is a normal speed, very low power CMOS static RAM organized as 32768 × 8 bits that
operates on a single 5-volt power supply. This device is manufactured using Winbond's high
performance CMOS technology.
FEATURES
•
Low power consumption:
•
Access time: 70 nS (max.)
•
Active :300 mW
Standby :250 µW
•
Single 5V power supply
•
Fully static operation
•
All inputs and outputs directly TTL compatible
•
Three-state outputs
•
Battery back-up operation capability
•
Data retention voltage: 2V (min.)
•
Packaged in 28-pin 600 mil DIP, 330 mil SOP
and standard type one TSOP (8 mm × 13.4
mm)
PIN CONFIGURATIONS
1
A14
A12
2
A7
3
A6
4
A5
5
A4
6
28-pin
7
DIP
8
9
10
11
12
13
14
28-pin
TSOP
A11
A13
WE
V
A14
A12
A3
A2
A1
A0
I/O1
I/O2
I/O3
V
SS
OE
1
2
A9
3
A8
4
5
6
7
DD
8
9
A7
10
A6
11
A5
12
A4
13
A3
BLOCK DIAGRAM
CLK GEN.
A12
A14
A2
WE
CS
OE
A3
A4
A5
A6
A7
A13
I/O1
I/O8
DATA
CNTRL.
28
V
DD
27
WE
26
A13
25
A8
24
A9
23
A11
22
OE
21
A10
20
CS
I/O8
19
I/O7
18
I/O6
17
I/O5
16
I/O4
CLK
GEN.
R
O
W
D
E
C
O
D
E
PRECHARGE CKT.
CORE CELL ARRAY
512 ROWS
64 X 8 COLUMNS
I/O CKT.
COLUMN DECODER
A10 A1 A0A8A9
A11
PIN DESCRIPTION
A10
28
27
CS
26
I/O8
25
I/O7
24
I/O6
23
I/O5
22
I/O4
21
VSS
20
I/O3
19
I/O2
18
I/O1
17
A0
A1
16
A2
15
SYMBOL DESCRIPTION
A0−A14
I/O1−I/O8
Address Inputs
Data Inputs/Outputs
Chip Select Input
Write Enable Input
Output Enable Input
VDD Power Supply
VSS Ground
Publication Release Date: October 1999
- 1 - Revision A1
TRUTH TABLE
Preliminary W24256
MODE
I/O1−I/O8
VDD CURRENT
H X X Not Selected High Z ISB, ISB1
L H H Output Disable High Z IDD
L L H Read Data Out IDD
L X L Write Data In IDD
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER RATING UNIT
Supply Voltage to VSS Potential -0.5 to +7.0 V
Input/Output to V
Allowable Power Dissipation 1.0 W
Storage Temperature -65 to +150
Operating Temperature 0 to 70
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
Operating Characteristics
(VDD = 5V ±10%; VSS = 0V; TA = 0° C to 70° C)
SS
Potential -0.5 to VDD +0.5 V
°
C
°C
PARAMETER SYM.
Input Low Voltage V
Input High Voltage V
Input Leakage Current I
Output Leakage Current I
IL
IH
LI
LO
TEST CONDITIONS MIN. TYP.* MAX. UNIT
- -0.5 - +0.8 V
- +2.2 - VDD +1 V
VIN = VSS to VDD -5 - +5
VI/O = VSS to VDD, CS = VIH
-5 - +5
µ
A
µ
A
(min.) or OE = VIH (min.) or
= VIL (max.)
Output Low Voltage V
Output High Voltage V
Operating Power
Supply Current
Standby Power Supply
Current
I
LL - - 50
Note: Typical parameter is measured under ambient temperature TA = 25° C and VDD = 5V.
OL IOL
OH IOH
DD
I
= +2.1 mA - - 0.4 V
= -1.0 mA 2.4 - - V
= VIL (max.), I/O = 0 mA ,
Cycle = min , Duty = 100 %
SB
I
= VIH (min.), Cycle = min.
Duty = 100%
SB1
≥ VDD -0.2V
- - 60 mA
- - 3 mA
L - - 100
µ
A
µ
A
- 2 -
Preliminary W24256
CAPACITANCE
(VDD = 5V, TA = 25° C, f = 1 MHz)
PARAMETER SYM. CONDITIONS MAX. UNIT
Input Capacitance CIN VIN = 0V 6 pF
Input/Output Capacitance C
Note: These parameters are sampled but not 100% tested.
I/O
V
OUT
= 0V 8 pF
AC CHARACTERISTICS
AC Test Conditions
PARAMETER CONDITIONS
Input Pulse Levels 0V to 3.0V
Input Rise and Fall Times 5 nS
Input and Output Timing Reference Level 1.5V
Output Load See the drawing below
AC TEST LOADS AND WAVEFORM
1 TTL
OUTPUT
100 pF
Including
Jig and
Scope
OUTPUT
(For T T T T T T )
CLZ, OLZ,
OHZ, WHZ, OW
CHZ,
1 TTL
5 pF
Including
Jig and
Scope
3.0V
0V
90%
10%
5 nS
90%
10%
5 nS
Publication Release Date: October 1999
- 3 - Revision A1