Winbond Electronics BM29F040 Datasheet

BRIGHT Preliminary BM29F040

Microelectronics Inc.

4 MEGABIT (512K × 8)

5 VOLT SECTOR ERASE CMOS FLASH MEMORY

GENERAL DESCRIPTION

The BM29F040 is a 4 Megabit, 5.0 Volts only Flash memory device organized as 512K × 8 bits each. The BM29F040 is offered in an Industry standard 32-pin package which is backward compatible to 1 Megabit and also pin compatible to EEPROMs. The device is offered in PDIP, PLCC and TSOP packages. The device is designed to be programmed and erased in system with the standard system 5 Volt Vcc supply. An external 12.0 Volts Vpp is not required for program and erase operation. The device can also be reprogrammed in standard EPROM programmers.

The BM29F040 offers access times between 70 to 150 nS. The device has separate chip enable (CE), write enable (WE) and output enable (OE ) controls to eliminate bus contention.

BMI flash memory technology reliably stores memory information even after 100,000 erase and program cycles. The BMI proprietary cell technology enhances the programming speeds and eliminates over erase problems seen in the classical ETOX™ type of Flash cell technologies. The combination of cell technology and internal circuit design techniques give reduced internal electrical fields and this provides improved reliability and endurance. The BM29F040 is entirely pin and command set compatible to the JEDEC standard 4 Megabit EEPROM. The commands are written to the Command State machine using standard microprocessor write timings. The internal Programming and Erase Algorithms are automatically implemented based on the input commands.

The BM29F040 is programmed by executing the program command sequence. This will start the internal automatic program Algorithm that times the program pulse width and also verifies the proper cell margin. Erase is accomplished by executing the erase command sequence. The internal Power Switching State Machine automatically executes the algorithms and generates the necessary voltages and timings for the erase operation. The program and erase verify is also done internally and proper margin testing is automatically performed. This scheme unburdens the microprocessor or microcontroller from generating the program and erase algorithms by controlling all the necessary timings and voltages. The entire memory is typically erased in 1.5 seconds. No preprogramming is necessary in this technology.

The BM29F040 also features a sector erase architecture. It is divided into 8 sectors of 64K bytes each. Each sector can be erased individually without affecting the data in other sectors or they can be erased in a random combination of groups. This multiple sector erase capability or full chip erase makes it very flexible to alter the data in BM29F040. To protect the data from accidental program or erase the device also has a sector protect or multiple sector protect function.

The device features a single 5 Volt power supply for read, program and erase operation. Internally generated and well regulated voltages are provided for the program and erase operation. A low Vcc detector inhibits write operations during power transitions. The end of program or erase is detected by Data polling of DQ7 or by the Toggle Bit feature on DQ6. Once the program or erase cycle has been successfully completed, the device internally resets to Read mode.

A Winbond Company Publication Release Date: June 1999

- 1 - Revision A1

BRIGHT Preliminary BM29F040

Microelectronics Inc.

FEATURES

• 5.0 V +/- 10% Program and Erase

− Minimizes system power consumption

− Simplifies the system design

• Compatible with JEDEC standard commands

− Uses same software commands as

EEPROMs

• Compatible with JEDEC-standard byte wide

pinout

− 32 pin PLCC/TSOP

− 32 pin DIP

• Automated sector/chip Erase Algorithms

− No programming before Erase needed

− Internal program and Erase Margin Check

• Data Polling and Toggle Bit

− useful for detection of Program and Erase

cycle completion

Product Selection Guide

FAMILY PART NO. -75* -90 -120 -150

• Sector Erase architecture

− 8 Equal sectors of 64K bytes each

− Any combination of multiple Sector Erase

− Full Chip Erase

• Sector Protection

− Any number of sectors can be protected from

Program and Erase operation

• Low Power Consumption

• Typically 100,000 Program/Erase cycles

• Erase Suspend and Resume

− Suspend the Sector Erase Operation to

allow a READ in another sector

• Low Vcc Write inhibit < 3.2 volts

• Single Cycle reset command

Maximum Access Time (nS) 70 90 120 150

CE (E) Access time (nS) OE (G) Access time (nS)

70 90 120 150 30 35 50 60

Table 1

*This speed is available with Vcc = 5V +/- 5% variation

- 2 -

BRIGHT Preliminary BM29F040

Microelectronics Inc.

PIN CONFIGURATIONS

DIP Top View

A18 A16 A15 A12

A7 A6 A5 A4 A3 A2 A1

A0 DQ0 DQ1 DQ2

GND

PLCC Top View

A12 A16 Vcc A17

A15 A18 WE

Vcc WE A17 A14 A13 A8 A9 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3

A11 A9 A8 A13 A14 A17 WE Vcc A18 A16 A15 A12 A7 A6 A5 A4

DQ0

14 15 16 17 18 19 20

I/O's 1 2 3 4 5 6

TSOP Top View

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

GND

TYPE 1

3031

A14

A13

A11

A10

DQ7

A10

DQ7

DQ6

DQ5

DQ4

DQ3

GND

DQ2

DQ1

DQ0

A Winbond Company Publication Release Date: June 1999

- 3 - Revision A1

BRIGHT Preliminary BM29F040

Microelectronics Inc.

Flexible Sector-erase Architecture:

64K bytes per sector Individual sector, multiple sector or bulk erase capability. Individual or multiple-sector protection is user definable.

Table 2. Sector Definition

64K byte sector 70000H-7FFFFH 64K byte sector 60000H-6FFFFH 64K byte sector 50000H-5FFFFH 64K byte sector 40000H-4FFFFH 64K byte sector 30000H-3FFFFH 64K byte sector 20000H-2FFFFH 64K byte sector 10000H-1FFFFH 64K byte sector 00000H-0FFFFH

PIN DESCRIPTION

SYMBOL TYPE NAME AND FUNCTION

A0 - A18 I

A9 I

DQ0-DQ7 I/O

Vcc

GND

ADDRESS INPUTS: for memory addresses. Addresses are internally latched during a write cycle.

ADDRESS INPUT: When A9 is at 12 Volts the ID mode is accessed. During this mode A0 decodes between the manufacturer and device ID′s.

DATA INPUTS / OUTPUTS: Inputs array data on the fourth CE and WE cycle during a program command. Inputs commands WE to the Command register when CE and WE are active. Data is internally latched during the

program cycles. Outputs are from Array and Intelligent Identifier information. The output pins float to tri-state when the chip is deselected or the outputs are disabled.

CHIP ENABLE: Activates the device's control logic, input buffers, decoders and sense amplifiers. CE is active low control; CE high deselects the memory device and reduces power consumption to standby levels.

OUTPUT ENABLE: OE is active low control signal. This pin gates the device’s outputs through the data buffers during a read cycle. When CE is low and OE is high the outputs are tri-state.

WRITE ENABLE: Controls writes to the Command state Machine and memory array. WE is active low signal. Addresses and Data are latched during the rising edge of the WE pulse.

DEVICE POWER SUPPLY: Main power source to the device. It′s value is 5V ± 10% or 5V ± 5%.

GROUND: The device ground for the internal circuitry.

Table 3

- 4 -

BRIGHT Preliminary BM29F040

Microelectronics Inc.

BLOCK DIAGRAM

Vcc

GND

State

Control

Command

Program Voltage

Generator

Erase Voltage

Generator

DQ0 - DQ

Input / output

Buffers

A0 - A 18

Vcc Detect

Timer

Chip Enable

Output Enable

Logic

Y-Decode

d d

r e s

X-decode

s L a

t c h

Data

latch

Y-MUX / SENSING

ARRAY

Figure 1

BUS OPERATION

Operation

CE OE

Auto select Manufacturers ID (1) L L H L L L VID Code Auto select Device ID (1) L L H H L L VID Code Read L L H A0 A1 A6 A9 Dout Standby H X X X X X X High Z Output Disable L H H X X X X High Z Write L H L A0 A1 A6 A9 Din (2) Enable Sector Protect L VID L X X X VID X Verify Sector Protect (3) L L H L H L VID Code

A0 A1 A6 A9 I/O

Table 4

Notes:

1. LEGENDS: L = VIL, H = VIH, X = don't care, VID = +12V.

2. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to table 6 for Command definitions.

3. Refer to Table 4 for valid Din during a write operation.

4. Refer to the section on sector protection.

A Winbond Company Publication Release Date: June 1999

- 5 - Revision A1

BRIGHT Preliminary BM29F040

Code

(Hex)

Microelectronics Inc.

Autoselect Codes

TYPE

Manufacturer Code BM29F040 Device code

Sector Protection (1)

A18A

Sector Addresses

XXX

Vil Vil Vil

Vil

Vih

Vil

Vih

Vil

Table 5

DQ7DQ6DQ5DQ4DQ

ADH

1 0 01 0 1 0 0 0

40H 01H

00 1

DQ2DQ1DQ

0000

0 1

000

PRODUCT FAMILY PRINCIPLES OF OPERATION

Flash memory devices are electrically alterable non-volatile memory products. The BM29F040 augments this feature by not requiring an additional Vpp power supply. The 4 Megabit flash family uses a Command register and internally generated voltages and timing algorithms to make program and erase operations simple. The user need not worry about generating tightly controlled high voltages on board or tying up the microcontroller to generate program and erase algorithms.

The Command register allows for 100% TTL-level control inputs, and maximum compatibility with the Flash memory functions.

The device provides standard EPROM read, standby and output disable operations. Manufacturer Identification and Device Identification data can be accessed through the Command register or through the standard EPROM ″A9″ high voltage access (VID) for PROM programming equipment.

A Command register and Power Switching State Machine are built inside the device. Their purpose is to completely automate the program and erase operation. The command register receives the commands given by the user and internally controls the power switching state machine.

Read Mode

The BM29F040 has three control pins and they should all be logically active to obtain valid data at the outputs. Chip-Enable (CE) is the device selection control. Output Enable (OE ) is the data

input/output control. This pin when high (VIH) brings the output drivers to the tristate and allows data into the device. Data input is then controlled by

. When the OE pin is low (VIL) it enables the

output buffers and valid array data becomes available at the output pins. The Write Enable (WE) pin has to be high during the READ mode.

Standby Mode

The BM29F040 has two standby modes: a CMOS standby mode ( CE input = Vcc +0.5V) when the current consumed is less than 100 µA; and a TTL standby mode (CE is held at VIH) when the current

consumed is approximately 1 mA. In the standby mode the outputs are in a high impedance state independent of the OE input.

If the device is deselected during erasure or programming, the device will draw active current until the erase or programming operation is complete.

- 6 -

BRIGHT Preliminary BM29F040

Microelectronics Inc.

Autoselect Mode

The Autoselect mode allows access to the manufacturers and the device code. This mode can be enabled by either taking the address pin A9 to VID (11.5 to 12.5 volts) or by giving the Autoselect Command sequence as shown in Table 5. Once the Autoselect mode is enabled two identifier bytes can be read on the device outputs by toggling A0 from VIL to VIH. Byte 0 (A0 = VIL) represents the manufacturers code (ADH for BMI). Byte 1 (A0 = VIH) represents the device identifier and this is 40H for the BM29F040. A READ command must be written to the Command register to return to the Read mode after the Autoselect mode.

Write Operations

The on-chip state machines control the Chip Erase, Sector Erase and byte Write operations. This frees the system processor to do other tasks. All the Programming and Erase voltages are generated internally. The Write and Erase timings and algorithms are also built into the device. The byte write/ sector erase or Chip Erase Command Interface provides additional data protection to avoid accidental Write or Erase.

Commands are written to the Command register using standard microprocessor write timings. The Command register recognizes Read mode, Autoselect mode, Chip Erase, Sector Erase (64K bytes per sector) and Program commands. The Command register does not occupy an addressable memory location. The interface register is a latch used to store the command and address and data information needed to execute the command.

Command Definitions

Device operations are selected by writing specific address and data sequences into the Command register. Table 6 defines these Command sequences.

Read/ Reset Command

The read or reset operation is initiated by writing the read/reset command sequence to the command register. Processor read cycles retrieve the data from the memory. The device remains enabled for reads until the command register contents are changed.

The device will automatically power-up in the read/reset mode. In this case, a command sequence is not needed to read the memory data. This default power up to read mode ensures that no spurious changes of the data can take place during power-up. As shown in this data sheet, the timing parameters and A.C. read waveforms should be referenced.

A single cycle reset is also available as shown in table.

A Winbond Company Publication Release Date: June 1999

- 7 - Revision A1

BRIGHT Preliminary BM29F040

Bus

Write

cycles

Microelectronics Inc.

Table 6. Command Definitions

Command

Sequence

Read /Reset Read /Reset Auto Select

Auto Select

required

1 4 4

First Bus

Write cycle

Address Data Address Data Address Data Address Data Address Data Address Data

XXXXH F0H

5555H AAH 2AAAH 55H 5555H F0H RA RD 5555H AAH 2AAAH 55H 5555H 90H 00H ADH

5555H AAH 2AAAH 55H 5555H 90H SA 00

Second

Bus Write

cycle

Third Bus

Write cycle

Fourth Bus

Write cycle

01H 40H

Fifth Bus

Write

cycle

Sector Protect

X02 01

Verify

5555H AAH 2AAAH 55H 5555H A0H PA PD

Byte

Program

5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H

Chip Erase Sector Erase Sector Erase

5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SA 30H

XXXXH B0H

Suspend

XXXXH 30H

Sector Erase

Resume

Notes:

1. Address bit A15, A16, A17 and A18 = X = don′t care for all address commands except for Program address (PA) and sector address (SA).

2. Bus operations are defined in Table 4.

3. RA = Address of the memory location to be read. PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of WE. SA = Address of the sector to be erased. The combination of A16, A17 and A18 will uniquely select the sector.

4. RD = Data from the selected address location (RA) during read operation. PD = Data to be programmed at the selected memory location (PA). Data is latched at the falling edge of /WE.

5. Auto select command can be used to evaluate whether a block is protected or not by using at the fourth address 02H. This is similar to placing A9 to High Voltage.

Sixth Bus

Write

cycle

Auto Select Command

The BM29F040 contains two different procedures for the autoselect mode. One is the traditional PROM programmer methodology (by taking Address pin A9 to VID) and the other is by writing the Auto Select command sequence into the command register. Following the third bus cycle write command, a read cycle from Address 00H retrieves the BMI manufacturer code ADH, and a read cycle at 01H retrieves the device code of 40H. Scanning the sector addresses (A16, A17, A18) while (A6, A1, A0) = (0, 1, 0) will produce a logical at device output DQ0 for a protected sector. See table 5 for more details.

To terminate this operation, it is necessary to write the read/ reset command to the command register.

- 8 -

BRIGHT Preliminary BM29F040

Microelectronics Inc.

Byte Write or Byte program

The BM29F040 is programmed one byte at a time. Programming is a four bus cycle operation. There are two "unlock" write cycles which are followed by a program set-up command and data write cycles.

Addresses are latched on the falling edge of rising edge of WE begins programming. During the execution of the embedded program algorithm

the host system is not required to provide any other controls or timings. The device also provides adequate program margin and all the necessary voltages and timings. When completed, the automatic programming will provide the equivalent of the written data on DQ7. After a successful programming operation the device returns back to read mode. Data polling must be performed at the memory location which is being programmed.

Figure 3 illustrates the Embedded Programming Algorithm and the waverforms are shown in figures 9 and 10.

Chip Erase

Chip erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the ″setup″ command. Two more "unlock" write cycles are then followed by the chip erase command.

Chip erase does not require the user to program the device prior to erase. BM29F040's technology is immune to overerase and it does not need any internal programming algorithm before erase. This can save erase time in many applications.

and data is latched on the rising edge of WE. The

The automatic Chip erase begins on the rising edge of the last and terminates when the data on DQ7 is "1", and which time the device returns back to the read mode.

Figure 4 illustrates the Auto Erase Algorithm and the Erase Waveforms are shown in Figure 11.

pulse in the command sequence

Sector Erase

Sector erase is a six bus cycle operation. There are two "unlock" write cycles followed by writing the sector erase setup command. Two more "unlock" write cycles are then followed by the sector erase

confirm command. The sector address is latched on the failing edge of WE, and the command data is latched on the rising edge of WE. An 80 µS time-out from the rising edge of WE of the last sector erase command is initiated. The actual sector erase starts 100 uS after the last rising edge of WE.

Multiple sectors can be erased simultaneously. After writing the six bus cycle command for sector erase additional sector address and sector erase command can be inserted within the 80 uS time-out period. The timer is reset every time and additional sector erase command is inserted. The sectors can be added to be erased in any random sequence. Any command other than the sector erase command or Erase Suspend command during the time-out period will reset the device to the read mode and ignoring the previous command string. During the execution of the Sector Erase command, only the Erase Suspend and Erase Resume commands are allowed. All other commands will reset the device to the Read mode. Once the device resets to the Read mode due to command error during Sector Erase, the data in this sector has lost its integrity. The sector should be properly erased again.

Sector erase does not require the user to program the sector before erase. When erasing a sector or multiple sectors the data in the unselected sectors remains unchanged. After the sector erase

A Winbond Company Publication Release Date: June 1999

- 9 - Revision A1

+ 20 hidden pages