Winbond Electronics BM29F400T, BM29F400B Datasheet

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4MEGABIT (512K × 8/ 256K × 16)

5VOLT SECTOR ERASE CMOS FLASH MEMORY

GENERAL DESCRIPTION

The BM29F400 is an 4 Megabit, 5.0 volt-only CMOS Flash memory device organized as a 512 Kbytes of 8-bits each, or 256 Kbytes of 16 bits each. The device is offered in standard 48-pin TSOP package. It is designed to be programmed and erased in-system with a 5.0 volt power-supply and can also be reprogrammed in standard EPROM programmers.

With access times of 90 nS, 120 nS, and 150 nS, the BM29F400 has separate chip enable CE, write enable WE, and output enable OE controls. BMI's memory devices reliably store memory data even

after 100,000 program and erase cycles. The BM29F400 is entirely pin and command set compatible with the JEDEC standard for 4 Megabit

Flash memory devices. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations.

The BM29F400 is programmed by executing the program command sequence. This will start the internal byte/word programming algorithm that automatically times the program pulse width and also verifies the proper cell margin. Erase is accomplished by executing either the sector erase or chip erase command sequence. This will start the internal erasing algorithm that automatically times the erase pulse width and also verifies the proper cell margin. No preprogramming is required prior to execution of the internal erase algorithm. Sectors of the BM29F400 Flash memory array are electrically erased via Fowler-Nordheim tunneling. Bytes/words are programmed one byte/word at a time using a hot electron injection mechanism.

The BM29F400 features a sector erase architecture. The device memory array is divided into one 16 Kbytes, two 8 Kbytes, one 32 Kbytes, and seven 64 Kbytes. Sectors can be erased individually or in groups without affecting the data in other sectors. Multiple sector erase and full chip erase capabilities add flexibility to altering the data in the device. To protect this data from accidental program and erase, the device also has a sector protect function. This function hardware write protects the selected sector(s). The sector protect and sector unprotect features can be enabled in a PROM programmer.

For read, program and erase operation, the BM29F400 needs a single 5.0 volt power-supply. Internally generated and well regulated voltages are provided for the program and erase operation. A low Vcc detector inhibits write operations on loss of power. End of program or erase is detected by the Ready/Busy status pin, Data Polling of DQ7, or by the Toggle Bit I feature on DQ6. Once the program or erase cycle has been successfully completed, the device internally resets to the Read mode.

The BM29F400 also has a hardware Internal Programming or Erase command will terminate the operation and reset the device to the

Read mode. The access to boot code upon completion of system reset, even if the Flash device is in the process of an

Internal Programming or Erase operation. If the device is reset using the Internal Programming or Erase operation, data in the address locations on which the internal state

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pin may be tied to the system reset circuitry, so that the system will have

pin. Driving the

pin low during execution of an

pin during an

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machine is operating will be erroneous. Thus, these address locations will need rewriting after the device is reset.

FEATURES

•

5.0V +/- 10% Program and Erase

− Minimizes system-level power requirements High performance

− 90 nS access time

•

Compatible with JEDEC-standard Commands

− Uses software commands, pinouts, and packages following industry standards for single power supply Flash memory

•

Typically 100,000 Program/Erase Cycles

•

Sector Erase Architecture

− One 16 Kbytes, two 8 Kbytes, one 32 Kbytes, and seven 64 Kbytes

−

Any combination of sectors can be erased

concurrently; also supports full chip erase

•

Erase Suspend/Resume

− Suspend a sector erase operation to allow a data read in a sector not being erased within the same device

•

Ready/Busy

− RY/BY output pin for detection of programming or erase cycle completion

•

− Hardware pin resets the internal state machine to the read mode

•

Internal Erase Algorithms

− Automatically erases a sector, any combination of sectors, or the entire chip

•

Internal Programming Algorithms

− Automatically programs and verifies data at a specified address

•

Low Power Consumption

− 20 mA typical active read current for Byte Mode

− 28 mA typical active read current for Word Mode

− 30 mA typical write/erase current

•

Sector Protection

− Hardware method disables any combination of sectors from a program or erase operation

•

Boot Code Sector Architecture

FAMILY PART NO.

-90 -120 -150

Maximum Access Time (nS) 90 120 150

(E) Access time (nS) (G) Access time (nS)

90 120 150 35 50 60

*This speed is available with Vcc = 5V +/- 5% variation

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PIN CONFIGURATIONS

A15

A14

A13

A12

A11

A10

RESET

RY/BY

A17

Standard TSOP

BLOCK DIAGRAM

Vcc Vss

/WE

/BYTE

/RESET

RY/BY Buffer

State

Control

Command

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

PGM Voltage

Generator

A16 BYTE Vss DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 Vcc DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE Vss CE A0

Erase Boltage

Generator

PIN DESCRIPTION

A0−A17 DQ0−DQ14 DQ15/A-1 Data Input/Output, Address

VSS Device Ground

RY/BY Ready/Busy Status Output VCC Device Power Supply

NC Not Internally Connected

Address Inputs Data Input/Output

Max. Chip Enable

Output Enable Write Enable

Hardware

Active Low

Selects 8-bit or 16-bit Mode

DQ0-DQ15

Input/Output

Buffers

Pin,

/CE /OE

Chip Enable Output Enable

Logic

STB

Data Latch

STB

Y-Gating

Cell Matrix

A0-A16

Vcc Detector

Timer

Address

Latch

Y-Decodor

X-Decoder

A-1

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BUS OPERATION

(1)

A0 A1 A6 A9 DQ0-DQ15

(1)

A0 A1 A6 A9 DQ0-DQ7 DQ8-DQ15

(4)

High Z H

OUT

(4)

RESET

Table 1. Bus Operations

OPERATION

Electronic ID Manufacturer Electronic ID Device

(3)

Read

L L H A0 A1 A6 A9 D Standby H X X X X X X High Z H Hardware Reset X X X X X X X High Z L Output Disable L H H X X X X High Z X Write L H L A0 A1 A6 A9 DIN Verify Sector Protect Temporary Sector Unprotect X X X X X X X X VID

Notes:

1. L = VIL, H = VIH, X = Don't Care. See DC Characteristics for voltage levels.

2. Manufacturer and device codes may also be accessed via a command register sequence. Refer to Table 6.

3. WE can be V

4. Refer to Table 6 for valid DIN during a write operation.

if CE is VIL, OE at VIH initiates the write operations.

(2)

L L H H L L VID Code H

(2)

L L H L H L VID Code H

Table 2. Bus Operations

OPERATION

Electronic ID Manufacturer Electronic ID Device

(3)

Read

L L H A0 A1 A6 A9 DOUT High Z H Standby H X X X X X X High Z High Z H Hardware Reset X X X X X X X High Z High Z L Output Disable L H H X X X X High Z High Z H Write L H L A0 A1 A6 A9 D Verify Sector Protect Temporary Sector Unprotect X X X X X X X X High Z VID

Notes:

1. L = VIL, H = VIH, X = Don't Care. See DC Characteristics for voltage levels.

2. Manufacturer and device codes may also be accessed via a command register sequence. Refer to Table 6.

3. WEcan be VIL if CE is VIL, OE at VIH initiates the write operations.

4. Refer to Table 6 for valid DIN during a write operation.

(2)

L L H H L L VID Code High Z H

(2)

L L H L H L VID Code High Z H

(

L L H L L L VID Code H

(

L L H L L L VID Code High Z H

= VIH)

= VIL)

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Table 3. Sector Protection Verify Electronic ID Codes

TYPE A17-A12 A6 A1 A0 Code (Hex)

Manufacturer Code

29F400T Byte X VIL VIL VIH 23H

29F400 Word 22,23H

29F400B Byte X VIL VIL VIH ABH Word 22 ABH

Sector Protection Sector Address VIL VIH VIL 01H(1)

Note: Outputs 01H at protected sector addresses, and outputs 00H at unprotected addresses.

Table 4. Sector Address Tables (BM29F400T)

A17 A16 A15 A14 A13 A12 (x8) Address Range (x16) Address Range

SA0 0 0 0 X X X 00000H-0FFFFH 00000H-07FFFH SA1 0 0 1 X X X 10000H-1FFFFH 08000H-0FFFFH SA2 0 1 0 X X X 20000H-2FFFFH 10000H-17FFFH SA3 0 1 1 X X X 30000H-3FFFFH 18000H-1FFFFH SA4 1 0 0 X X X 40000H-4FFFFH 20000H-27FFFH SA5 1 0 1 X X X 50000H-5FFFFH 28000H-2FFFFH SA6 1 1 0 X X X 60000H-6FFFFH 30000H-37FFFH SA7 1 1 1 0 X X 70000H-77FFFH 38000H-3BFFFH SA8 1 1 1 1 0 0 78000H -79FFFH 3C000H-3CFFFH SA9 1 1 1 1 0 1 7A000H -7BFFFH 3D000H-3DFFFH SA10 1 1 1 1 1 X 7C000H-7FFFFH 3E000H-3FFFFH

Notes:

1. The address range is A17:A-1 if in byte mode (

2. The address range is A17:A0, if in word mode (

X VIL VIL VIL ADH

= VIL).

BYTE

= VIH).

BYTE

Table 5. Sector Address Tables (BM29F400B)

A17 A16 A15 A14 A13

SA0 0 0 0 0 0 X 00000H-03FFFH 00000H-01FFFH SA1 0 0 0 0 1 0 04000H-05FFFH 02000H-02FFFH SA2 0 0 0 0 1 1 06000H-07FFFH 03000H-03FFFH SA3 0 0 0 1 X X 08000H-0FFFFH 04000H-07FFFH SA4 0 0 1 X X X 10000H-1FFFFH 08000H-0FFFFH SA5 0 1 0 X X X 20000H-2FFFFH 10000H-17FFFH SA6 0 1 1 X X X 30000H-3FFFFH 18000H-1FFFFH SA7 1 0 0 X X X 40000H-4FFFFH 20000H-27FFFH SA8 1 0 1 X X X 50000H-5FFFFH 28000H-2FFFFH SA9 1 1 0 X X X 60000H-6FFFFH 30000H-37FFFH SA10 1 1 1 X X X 70000H-7FFFFH 38000H-3FFFFH

Notes:

1. The address range is A17:A-1 if in byte mode (

2. The address range is A17:A0, if in word mode (

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BYTE

A12

= VIL).

= VIH).

(x8) Address Range

x16) Address Range

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Electronic ID Mode

The Electronic ID mode allows the reading out of a binary code from the device and will identify its manufacturer and device type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional over the entire temperature range of the device.

To activate this mode, the programming equipment must force VID (11.5V to 12.5V) on address pin A9. Two identifier bytes may then be sequenced from the device outputs by toggling address A0 from VIL to VIH. All addresses are don't cares except A0, A1, and A6 (see Table 3).

Manufacturer and device codes may also be read via the command register; for instance, when the BM29F400 is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in Table 6 (refer to Electronic ID Command section).

Byte 0 (A0 = VIL) represents the manufacturer's code (Bright Microelectronics = ADH) and byte 1 (A0 = VIH) the device identifier code (BM29F400T = 23H and BM29F400B = ABH for 8-bit mode; BM29F400T = 2223H and BM29F400B = 22ABH for 16-bit mode). These two byte words are given in Table 3. To read the proper device codes when executing the Electronic ID, all identifiers for manufacturer and device will exhibit odd parity with the MSB (DQ7) defined as the parity bit. A1 must be VIL (see Table 3).

Read Mode

The BM29F400 has three control functions which must be satisfied in order to obtain data at the outputs. CE is the power control and should be used for device selection. OE is the output control and should be used to gate data to the output pins if a device is selected. As shown in Table 1, WE

should be held at VIH, except in Write mode and Enable Sector Protect mode. Address access time (t

enable access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. Output enable access time is the delay from the falling edge of OE to valid data at the output

pins (assuming the addresses have been stable for at least t

Standby Mode and Hardware

The BM29F400 has two methods for implementing standby mode. The first method requires use of both the CE pin and the

When using both pins, a CMOS standby mode is achieved when both CE and Vcc ±0.5V. In this condition, the current consumed is typically less than 100 µA. A TTL standby mode

is achieved with both CE and reduced to 200 µA. The device can be read with standard access time (tCE) from either of these two standby modes.

When using the

0.5V. In this condition, the current consumed is typically less than 100 µA. A TTL standby mode is

achieved with Once the

valid for a read access.

pin is taken high, the device requires 500 nS of wake-up time before outputs are

) is equal to the delay from stable addresses to valid output data. Chip

ACC

−

tOE time).

ACC

Standby Mode

pin. The second method only requires use of the

held at VIH. In this condition, the typical current required is

pin only, a CMOS standby mode is achieved with

held at VIL. In this condition, the typical current required is reduced to 1 mA.

pin.

are held at

held at VSS

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If the device is deselected during programming or erase, the device will draw active current until the programming or erase operation is completed. In the standby mode the outputs are in a high

impedance state, independent of the OE input.

Output Disable Mode

With the OE input at a logic high level (VIH), output from the device is disabled. This will cause the output pins to be in a high impedance state. It is shown in Table 1 that CE = VIL and WE = VIH for

Output Disable. This is to differentiate Output Disable mode from Write mode and to prevent inadvertent writes during Output Disable.

Program and Erase Modes

Device programming and erase are accomplished via the command register. Contents of the register serve as inputs to the internal state machine. Outputs of the state machine dictate the function of the device.

The command register itself does not occupy any addressable memory locations. The register is a latch used to store the commands along with the addresses and data information needed to execute

the command. The command register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the falling edge of WE or CE, whichever happens later, while data is latched on the rising edge of WE or CE, whichever happens first. Standard microprocessor write

timings are used. Refer to AC Characteristics for Programming/Erase and their respective Timing Waveforms for specific timing parameters.

Enable Sector Protect and Verify Sector Protect Modes

The BM29F400 has a hardware Sector Protect mode that disables both Programming and Erase operation to the protected sector(s). There are total of 11 sectors in this device. The sector protect feature is enabled using the programming equipment at the user's site. The device is shipped from the BMI factory with all sectors unprotected.

To verify programming of the protection circuitry, the programming equipment must force VID on the address pin A9 with CE and OE at VIL and WE at VIH. As shown in Table 2, scanning the sector

addresses while (A6, A1 and A0) = (0, 1, 0) will produce a 01H code at the device output pins for a protected sector. In the Verify Sector Protect mode, the device will read 00H for an unprotected sector. In this mode, the lower order addresses, except for A0, A1 and A6, are don't care. Address locations with A1 = VIL are reserved for Electronic ID manufacturer and device codes. It is also possible to determine if a sector is protected in-system by writing the Electronic ID command (described in the Electronic ID command section below.)

Temporary Sector Unprotect Mode

The BM29F400 has a Temporary Sector Unprotect feature that allows the protect feature to be temporarily suspended to change data in a protected sector in-system. The Temporary Sector

Unprotect mode is activated by setting the In this mode, protected sectors can be programmed or erased by selecting the sector addresses.

Once VID is removed from the the Temporary Sector Unprotect algorithm and timing waveforms.

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pin, all previously protected sectors will be protected. Refer to

pin to VID (11.5V−12.5V).

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Read

The read or command register. Microprocessor read cycles retrieve the data from the memory. The device remains enable for reads until the command register contents are changed.

The device will automatically power-up in the Read/Reset mode. In this case, a command sequence is not needed to read the memory data. This default power-up to Read mode ensures that no spurious changes of the data can take place during the power transitions. Refer to the AC Characteristics for Read-Only Operation and the respective Timing Waveforms for the specific timing parameters.

Electronic ID Command

The BM29F400 contains an Electronic ID command to supplement the traditional PROM programming method described in the Electronic ID Mode section. The operation is initiated by writing the Electronic ID command sequence into the command register. Following command write, a read cycle from address XX00H retrieves manufacturer code of ADH. A read cycle from address XX01H returns the device code (BM29F400T = 23H and BM29F400B = ABH for 8-bit mode; BM29F400T = 2223H and BM29F400B = 22ABH for 16-bit mode) (see Table 3). All manufacturer and device codes exhibit odd parity with the MSB (DQ7) defined as the parity bit.

The Electronic ID command can also be used to identify protected sectors. After writing the Electronic ID command sequence, the CPU can scan the sector addresses (see Table 4 and Table 5) while (A6, A1, A0) = (0, 1, 0). Protected sectors will return 01H on the data outputs and unprotected sectors will return 00H. To terminate the operation, it is necessary to write the Read/Reset command sequence into the command register.

Byte/Word Programming Command

Command

operation is initiated by writing the Read/Reset command sequence in to the

The device is programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle operation (see Table 6). There are two "unlock" write cycles. These are followed by the program

set-up command and data write cycles. Addresses are latched on the falling edge of CE or WE, whichever happens later, and program data (PD) is latched on the rising edge of CE or WE, whichever happens first. The rising edge of CE or WE, whichever happens first, begins

programming using the Embedded Program Algorithm. Upon executing the algorithm, the system is not required to provide further controls or timings. The

device will automatically provide adequate internally generated program pulses and verify the programmed cell margin.

The automatic programming operation is completed when the data on DQ7 (also used as Data Polling) is equivalent to the data written to this bit at which time the device returns to the read mode and addresses are no longer latched (see Table 7, Write Operation Status Flags). Therefore, the

device requires that a valid address to the device be supplied by the system at this particular instance of time for

being programmed. Any commands written to the chip during the Internal Program Algorithm will be ignored. If a

hardware be corrupted.

Data

Polling operations.

Data

Polling must be performed at the memory location which is

occurs during the programming operation, the data at that particular location will

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Byte/Word programming is allowed in any sequence, and across sector boundaries. However, remember that a data "0" cannot be programmed to a data "1". Only erase operations can convert a logical "0" to a logical "1". Attempting to program data from "0" to "1" may cause the device to exceed

time limits, or even worse, result in an apparent success according to the Data Polling algorithm. In the later case, however, a subsequent read of this bit will show that the data is still a logical "0".

Figure 1 illustrates the Byte/Word Programming Algorithm using typical command strings and bus operations.

The device will ignore any commands written to the chip during execution of the internal Byte/Word Programming Algorithm. If a hardware

the data at that particular address location will be corrupted.

Chip Erase Command

Chip erase is a six bus cycle operation (see Table 6). The chip erase begins on the rising edge of the last WE pulse in the command sequence.

Upon executing the Chip Erase command sequence, the device's internal state machine executes an internal erase algorithm. The system is not required to provide further controls or timings. The device will automatically provide adequate internally generated erase pulses and verify chip erase within the proper cell margins. During chip erase, all sectors of the device are erased except protected sectors.

occurs during the Byte/Word Programming operation,

During Chip Erase, data bit DQ7 shows a logical "0". This operation is known as erase operation is completed when the data on DQ7 is a logical "1" (see Write Operation Status section). Upon completion of the Chip Erase operation, the device returns to read mode. At this time,

the address pins are no longer latched. Note that Data Polling must be performed at a sector address within any of the sectors being erased and not a protected sector to ensure that DQ7 returns a logical "1" upon completion of the Chip Erase operation.

Figure 2 illustrates the Chip Erase Algorithm using typical command strings and bus operations. The device will ignore any commands written to the chip during execution of the internal Chip Erase

algorithm. If a hardware be corrupted.

Sector Erase Command

Sector erase is a six bus cycle operation (see Table 6). The sector address (any address location within the desired sector) is latched on the falling edge of WE, while the command data is latched on the rising edge of WE. An internal device timer will initiate the Sector Erase operation 100 µS ±20% (80 µS to 120 µS) from the rising edge of the WE pulse for the last Sector Erase command entered

on the device. Upon executing the Sector Erase command sequence, the device's internal state machine executes

an internal erase algorithm. The system is not required to provide further controls or timings. The device automatically provides adequate internally generated erase pulses and verify sector erase within the proper cell margins. Protected sectors of the device will not be erased, even if they are selected with the Sector Erase command.

occurs during the Chip Erase operation, the data in the device will

Data

Polling. The

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Multiple sectors can be erased simultaneously by writing the sixth bus cycle command of the Sector Erase command for each sector to be erased. The time between initiation of the next Sector Erase command must be less than 80 µS to guarantee acceptance of the command by the internal state machine. The time-out window can be monitored via the write operation status pin DQ3 (refer to the Write Operation Status section for Sector Erase Timer operation). It is recommended that CPU interrupts be disabled during this time to ensure that the subsequent Sector Erase commands can be initiated within the 100 µS window. The interrupts can be re-enabled after the last Sector Erase command is written. As mentioned above, an internal device timer will initiate the Sector Erase

operation 100 µS ±20% (80 µS to 120 µS) from the rising edge of the last WE pulse. Sector Erase Timer Write Operation Status pin (DQ3) can be used to monitor time out window. If another falling

edge of the WE occurs within the 100 mS time-out window, the internal device timer is reset. Loading the sector erase buffer may be done in any sequence and with any number of sectors.

Any command other than Sector Erase or Erase Suspend during this period and afterwards will

the device to read mode, ignoring the previous command string. Resetting the device with a

hardware the operated sectors being undefined and may be unrecoverable. In this case, restart the Sector Erase operation on those sectors and attempt to allow them to complete the Erase operation.

Command Definitions

after it has begun execution of a Sector Erase operation will result in the data in

Device operations are selected by writing specific address and data sequences in to the Command register. Writing incorrect addresses and data values or writing them in the improper sequence will

the device to Read mode. Table 5 defines the valid register command sequences. Either of

the two Read/Reset commands will During Sector Erase operation, data bit DQ7 shows a logical "0". This operation is known as

Polling. Sector Erase operation is complete when data on DQ7 is a logical "1" (see Write Operation Status section) at which time the device returns to read mode. At this time, the address pins are no

longer latched. Note that Data Polling must be performed at a sector address within any of the sectors being erased and not a protected sector to ensure that DQ7 returns a logical "1" upon completion of the Sector Erase operation.

Figure 2 illustrates the Sector Erase Algorithm using typical command strings and bus operations. During execution of the Sector Erase command, only the Erase Suspend and Erase Resume

commands are allowed. All other commands will

Note: Do not attempt to write an invalid command sequence during the sector erase operation. Doing so will terminate the sector erase operation and the device will /RESET to the read mode.

the device (when applicable).

Data

the device to read mode.

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Table 6. Command Definitions

Command Sequence

Reset/Read Required Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data

Reset/Read 1 XXXXH F0H Reset Word 4 5555H AAH 2AAAH 55H 5555H F0H RA RD /Read Byte AAAAH 5555H AAAAH

ID Byte AAAAH 5555H AAAAH 23H

Program Word 4 5555H AAH 2AAAH 55H 5555H A0H PA PD

Byte AAAAH 5555H AAAAH

Chip Word 6 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H Erase Byte AAAAH 5555H AAAAH AAAAH 5555H AAAAH Sector Word 6 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SA 30H Erase Byte AAAAH 5555H AAAAH AAAAH 5555H Erase Word 1 XXXXH B0H

Suspend Byte

Erase Word 1 XXXXH 30H

Resume Byte

Notes:

Bus Write

Cycles

Word 4 5555H AAH 2AAAH 55H 5555H 90H 01H

First Bus Write

Cycle

Second Bus

Write Cycle

Third Bus

Write Cycle

Fourth Bus Write

Cycle

(7)

2223H

(T Device ID)

22ABH

(T Device ID)

ABH

Fifth Bus Write

Cycle

Sixth Bus Write

Cycle

1. Bus operations are defined in Tables 1 and 2.

2. For a Command Sequence, address bit A15 = X = Don't Care for all address commands except for Program Address (PA) and Sector Address (SA).

3. RA = Address of the memory location to be read. RD = Data read from location RA during read operation.

PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE pulse. PD = Data to be programmed at location PA. Data is latched on the rising edge of WE.

SA = Address of sector to be erased. (See Table 4 for top boot and Table 5 for bottom boot.)

4. The Erase Suspend (B0H) and Erase Resume (30H) commands are valid only while the Sector Erase operation is in progress.

5. Reading from, and programming to, non-erasing sectors is allowed in the Erase Suspend mode.

6. The System should generate the following address patterns: Word Mode: 5555H or 2AAAH to addresses A0−A14. Byte Mode: AAAAH or 5555H to addresses A-1−A14.

7. Address 00H returns the manufacturer's ID code (Bright Microelectronics - ADH), address 01H returns the device ID code.

Erase Suspend/Erase Resume Commands

The Erase Suspend command allows the user to interrupt a Sector Erase operation and read data from or to a sector that is not being erased. The Erase Suspend command is applicable only during Sector Erase operation, including, but not limited to, sector erase time-out period after any Sector Erase commands (30H) have been initiated.

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Writing the Erase Suspend command during the time-out will result in immediate termination of the time-out period. Any subsequent writes of the Sector Erase command will be taken as the Erase

Resume command (30H). Note that any other commands during the time-out will to the Read mode. The address pins are "don't cares" when writing the Erase Suspend or Erase Resume commands.

When the Erase Suspend command is written during a Sector Erase operation, the chip will take between 1 µS and 230 µS to suspend the erase operation and go into Erase Suspended mode.

During this time, the system can monitor the Data Polling or Toggle Bit write operation status flags to determine when the device has entered erase suspend mode (see Write Operation Status section.)

The system must use an address of an erasing sector to monitor Data Polling or Toggle Bit to determine if the Sector Erase operation has been suspended.

In Erase Suspend mode, the system can read data from any sector that is not being erased. A read from a sector being erased will result in write operation status data. After the system writes the Erase Suspend command and waits until the Toggle Bit stops toggling, data reads from the device may then be performed (see Write Operation Status section). Any further writes of the Erase Suspend command at this time will be ignored.

To resume operation of Sector Erase, the Erase Resume command (30H) should be written. Any further writes of the Erase Resume command at this point will be ignored. Another Erase Suspend command can be written after the chip has resumed Sector Erase operation.

DQ7

the device

Polling

Data

The BM29F400 device features Byte/Word Programming, Chip Erase, and Sector Erase operations. When the Byte/Word

Programming operation is in progress, an attempt to read the device will produce the compliment of the data last written to DQ7. Upon completion of the Byte/Word Programming operation, an attempt to read the device will produce the true data last written to DQ7. When the Chip Erase or Sector Erase operation is in progress, an attempt to read the device will produce a logical "0" at the DQ7 output. Upon completion of the Chip Erase or Sector Erase operation, an attempt to read the device will produce a logical "1" at the DQ7 output. The flowchart for Data Polling (DQ7) is shown in Figure

3. For Chip Erase, the

pulse sequence. For Sector Erase, the Data Polling is valid after the last rising edge of the sector erase WE pulse. For both Chip Erase and Sector Erase, Data Polling must be performed at sector address within any of the sectors being erased and not a protected sector. Otherwise, the

Polling status may not be valid. Once the Internal Algorithm operation is close to being completed, the BM29F400 data pins (DQ7) may change asynchronously while the output enable (OE) is

asserted low. This means that the device is driving status information on DQ7 at one instant and valid data at the next instant of time. Depending on when the system samples the DQ7 output, it may read status or valid data. Even if the device has completed the Internal Algorithm operation and DQ7 has a valid data, data outputs on DQ0-DQ6 may be still invalid. Valid data on DQ0-DQ7 will be read on the successive read attempts.

Data

Polling is valid after the rising edge of the sixth WE pulse in the six write

Data

Polling as a method to indicate to the host the status of the

Data

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