Winbond Electronics W24100S-70LL, W24100S-70L, W24100Q-70L, W24100Q-70LL, W24100-70LL Datasheet
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Preliminary W24100
1
2
3
5
6
789
10
121314
16
OE
CS1
I/O7
I/O6
I/O5
I/O4
28
V
CS2
DD
A9
I/O3
I/O1
CS1
WE
OE
128K × 8 CMOS STATIC RAM
GENERAL DESCRIPTION
The W24100 is a normal-speed, very low-power CMOS static RAM organized as 131072 × 8 bits that
operates on a single 5-volt power supply. This device is manufactured using Winbond's high
performance CMOS technology.
FEATURES
•
Low power consumption:
− Active: 385 mW (max.)
•
Access time: 70 nS
•
Single 5V power supply
•
Fully static operation
•
All inputs and outputs directly TTL compatible
•
Three-state outputs
•
Battery back-up operation capability
•
Data retention voltage: 2V (min.)
•
Packaged in 32-pin 600 mil DIP, 450 mil SOP,
standard type one TSOP (8 mm × 20 mm) and
small type one TSOP (8 mm × 13.4 mm)
PIN CONFIGURATIONS
32-pin
SOP
32-pin
TSOP
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
NC
A16
2
A14
3
4
A12
A7
5
A6
6
A5
7
A4
8
A3
9
A2
10
A1
11
A0
12
I/O1
13
I/O2
14
I/O3
15
V
SS
16
A11
A8
A13
4
WE
A15
NC
A16
11
A14
A12
A7
A6
15
A5
A4
BLOCK DIAGRAM
CLK GEN.
A16
V
DD
A15
CS2
WE
A13
A8
A9
A11
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
PIN DESCRIPTION
A14
A12
I/O1
I/O8
WE
CS1
CS2
A4
A3
A2
A7
A6
A5
A9
:
OE
SYMBOL DESCRIPTION
32
A10
31
30
I/O8
29
27
26
25
VSS
24
23
I/O2
22
21
A0
20
A1
19
A2
18
A3
17
A0−A16
I/O1−I/O8
, CS2
VDD Power Supply
VSS Ground
Address Inputs
Data Inputs/Outputs
Chip Select Input
Write Enable Input
Output Enable Input
NC No Connection
W
D
C
O
D
DATA
CNTRL.
CLK
GEN.
R
O
E
E
R
A15
PRECHARGE CKT.
CORE CELL ARRAY
1024 ROWS
128 X 8 COLUMNS
I/O CKT.
COLUMN DECODER
A0 A11
A13A8A1
A10
Publication Release Date: October 1999
- 1 - Revision A1
TRUTH TABLE
CS1
OE WE
CS1
CS1
CS
CS1
Preliminary W24100
CS2
MODE
I/O1−I/O8
VDD CURRENT
H X X X Not Selected High Z ISB, ISB1
X L X X Not Selected High Z ISB, ISB1
L H H H Output Disable High Z IDD
L H L H Read Data Out IDD
L H X L Write Data In IDD
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER RATING UNIT
Supply Voltage to VSS Potential -0.5 to +7.0 V
Input/Output to V
SS
Potential -0.5 to VDD +0.5 V
Allowable Power Dissipation 1.0 W
Storage Temperature -65 to +150
Operating Temperature 0 to 70
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.
°
C
°
C
Operating Characteristics
(VDD = 5V ±10%; VSS = 0V; TA = 0° C to 70° C)
PARAMETER
Input Low Voltage
Input High Voltage
Input Leakage Current
Output Leakage
Current
Output Low Voltage
Output High Voltage
Operating Power
Supply Current
Standby Power Supply
Current
Note: Typical parameter is measured under ambient temperature TA = 25° C and VDD = 5V.
SYM. TEST CONDITIONS MIN. TYP.* MAX. UNIT
VIL - -0.5 - +0.8 V
VIH - +2.2 - V
ILI VIN = V
ILO
V
(min.) or OE = V
or WE = V
VOL I
VOH I
IDD
SS
to VDD -1 - +1
I/O
= VSS to V
OL
= +2.1 mA - - 0.4 V
OH
= -1.0 mA 2.4 - - V
DD,
IL
(max.)
IH
(min.)
= V
IH
= VIL (max.) and
-1 - +1
- - 70 mA
DD
+0.5 V
µ
A
µ
A
CS2 = VIH (min.), I/O = 0 mA
Cycle = min., Duty = 100%
ISB
= VIH (min.), Cycle = min.
- - 3 mA
Duty = 100%
ISB1
≥ VDD -0.2V or
CS2 ≤ 0.2V
LL -
L -
-
50
-
100
µ
A
- 2 -
Preliminary W24100
CAPACITANCE
(VDD = 5 V, TA = 25° C, f = 1 MHz)
PARAMETER SYM. CONDITIONS MAX. UNIT
Input Capacitance CIN VIN = 0V 6 pF
Input/Output Capacitance C
Note: These parameters are sampled but not 100% tested.
I/O
V
AC CHARACTERISTICS
AC Test Conditions
PARAMETER CONDITIONS
Input Pulse Levels 0V to 3.0V
Input Rise and Fall Times 5 nS
Input and Output Timing Reference Level 1.5V
Output Load See the drawing below
OUT
= 0V 8 pF
AC Test Loads and Waveform
OUTPUT
1 TTL
100 pF
Including
Jig and
Scope
3.0V
0V
5 nS
1 TTL
OUTPUT
5 pF
Including
Jig and
Scope
(For T T T T T T )
CLZ, OLZ, CHZ, OHZ, WHZ, OW
90%
10%
90%
10%
5 nS
Publication Release Date: October 1999
- 3 - Revision A1
Preliminary W24100
CS1
AC Characteristics, continued
(VDD = 5V ±10%; VSS = 0V; TA = 0° C to 70° C)
Read Cycle
PARAMETER SYM. W24100-70L W24100-70LL UNIT
MIN. MAX. MIN. MAX.
Read Cycle Time TRC 70 - 70 - nS
Address Access Time TAA - 70 - 70 nS
Chip Select Access Time T
Output Enable to Output Valid T
Chip Selection to Output in Low Z T
Output Enable to Output in Low Z T
Chip Deselection to Output in High Z T
Output Disable to Output in High Z T
Output Hold from Address Change TOH 10 - 10 - nS
These parameters are sampled but not 100% tested
∗
ACS
- 70 - 70 nS
AOE
- 35 - 35 nS
CLZ
* 10 - 10 - nS
OLZ
* 5 - 5 - nS
CHZ
* - 30 - 30 nS
OHZ
* - 30 - 30 nS
Write Cycle
PARAMETER SYM. W24100-70L W24100-70LL UNIT
MIN. MAX. MIN. MAX.
Write Cycle Time TWC 70 - 70 - nS
Chip Selection to End of Write TCW 50 - 50 - nS
Address Valid to End of Write TAW 50 - 50 - nS
Address Setup Time TAS 0 - 0 - nS
Write Pulse Width TWP 50 - 50 - nS
Write Recovery Time
, CS2, WE
TWR 0 - 0 - nS
Data Valid to End of Write TDW 30 - 30 - nS
Data Hold from End of Write TDH 0 - 0 - nS
Write to Output in High Z T
Output Disable to Output in High Z T
WHZ
* - 25 - 25 nS
OHZ
* - 25 - 25 nS
Output Active from End of Write TOW 5 - 5 - nS
These parameters are sampled but not 100% tested
∗
- 4 -
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