Vizio VM60P Service Manual

Service Manual

Model #: VIZIO VM60P HDTV10A

V, Inc

320A Kalmus Drive Costa Mesa, CA 92626

TEL : [phone] FAX :[phone]

Top Confidential

Table of Contents

CONTENTS PAGE

Sections

1. Features 1-1

2. Specifications 2-1

3. On Screen Display

3-1

4. Factory Preset Timings 4-1

5. Pin Assignment 5-1

6. Main Board I/O Connections

6-1

7. Theory of Circuit Operation 7-1

8. Waveforms 8-1

9. Trouble Shooting

9-1

10. Block Diagram 10-1

11. Spare parts list 11-1

12. Complete Parts List 12-1

Appendix

1. Main Board Circuit Diagram

2. Main Board PCB Layout

3. Assembly Explosion Drawing

Block Diagram

VIZIO VM60P HDTV10A HDTV Service Manual

VINC Service Manual

VIZIO VM60P HDTV10A

COPYRIGHT © 2000 V, INC. ALL RIGHTS RESERVED.

IBM and IBM products are registered trademarks of International Business Machines
Corporation.

Macintosh and Power Macintosh are registered trademarks of Apple Computer, Inc.

VINC and VINC products are registered trademarks of V, Inc.

VESA, EDID, DPMS and DDC are registered trademarks of Video Electronics Standards
Association (VESA).

Energy Star is a registered trademark of the US Environmental Protection Agency (EPA).

No part of this document may be copied, reproduced or transmitted by any means for any
purpose without prior written permission from VINC.

FCC INFORMATION
This equipment has been tested and found to comply with the limits of a Class B digital device,
pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable
protection against harmful interference in a residential installation. This equipment generates,
uses and can radiate radio frequency energy, and if not installed and used in accordance with
the instructions, may cause harmful interference to radio communications. However, there is
no guarantee that the interference will not occur in a particular installation. If this equipment
does cause unacceptable interference to radio or television reception, which can be
determined by turning the equipment off and on, the user is encouraged to try to correct the
interference by one or more of the following measures -- reorient or relocate the receiving
antenna; increase the separation between equipment and receiver; or connect the into an
outlet on a circuit different from that to which the receiver is connected.

FCC WARNING
To assure continued FCC compliance, the user must use a grounded power supply cord and
the provided shielded video interface cable with bonded ferrite cores. Also, any unauthorized
changes or modifications to Amtrak products will void the user’s authority to operate this
device. Thus VINC Will not be held responsible for the product and its safety.

CE CERTIFICATION
This device complies with the requirements of the EEC directive 89/336/EEC with regard to
“Electromagnetic compatibility.”

SAFETY CAUTION
Use a power cable that is properly grounded. Always use the AC cords as follows – USA (UL);
Canada (CSA); Germany (VDE); Switzerland (SEV); Britain (BASEC/BS); Japan (Electric
Appliance Control Act); or an AC cord that meets the local safety standards.

VIZIO VM60P HDTV10A HDTV Service Manual

Chapter 1 Features

y Wall-mountable

y New WIDE HD Plasma Panel:1366 x 768 (H x V)

y TruSurround XT sound system and DCDi by Faroujia video image

y High definition digital interface – HDMI

y HDCP supportive

y Multiple-screen display (picture-on-picture/picture-in-picture)

y Selectable picture mode

y 3-language On Screen Display

y 2 S-video and Composite video inputs

y 2 Component video inputs

y 4 HDMI inputs

y Supporting DVI converted to HDMI

y Closed caption

y Copper metal front bezel

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File No. SG-0214

Chapter 2 Specification

1. Optical Characteristics

Item Specification Note

Display Pixels 1366 (H) x 768 (V) pixels

Display Cells 1319.6 (H) x 741.9 (V) cells

Pixel Pitch 0.966 mm (H) X 0.966 mm (V)

Pixel Type RGB Closed type

Color Depth 256 (R) x 256 (G) x 256 (B) colors

Active Display Area 1319.6 mm (H) x 741.9 mm ±0.5 (V)

Brightness (panel spec) 1200 cd/m2 (Typical)

w/Glass Filter Min.250 cd/m2 1

Min. 40 cd/m2 Full white

Contrast ratio (panel spec) 7000:1 (Typical, dark room)

Color Coordinates (typical)

White (w/Glass Filter) x=0.250±0.03, y=0.270±0.03

White (wo/Glass Filter) x=0.280±0.03, y=0.290±0.03

80% White (w/glass filter) Warm (5400K)

Standard (6500K)

Cool (9300K)

Viewing Angle Free

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2. INPUT SOURCE

RF Connector

RGB Connector

a. Type: Analog

b. Frequency: H: 30-80KHz V: 60-85Hz

c. Signal level: 0.7Vp-p

d. Impedance: 75ȍ

e. Synchronization H/V separate sync: TTL

H/V composite sync: Sync on Green TTL

f. Video bandwidth: 135MHz

g. Connector type: 15-pin D-Sub, female

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Pin Pin Assignment Pin Pin Assignment

1 Red video input 9 +5V

2 Green video input 10 Ground

3 Blue video input 11 No connection

4 Ground 12 (SDA)

5 Ground 13 Horizontal sync (Composite sync)

6 Red video ground 14 Vertical sync

7 Green video ground 15 (SCL)

8 Blue video ground

HDMI Connector

ˈ

˄˃

˄ˈ

ˈ

˄ˈ

˄

ˉ˄˃

˄˄

˄

ˉ

˄˄

a. Frequency: H: 15.734KHz V: 60Hz

H: 31KHz V: 60Hz

H: 45KHz V: 60Hz

H: 33KHz V: 60Hz

H: 67.5KHz V: 60Hz

b. Polarity: Positive or Negative

c. Type: Type A

d. Pin Assignment: Please see below

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Pin 2

Pin Signal Assignment Pin Signal Assignment

1 TMDS Data2+ 2 TMDS Data2 Shield

3 TMDS Data2- 4 TMDS Data1+

5 TMDS Data1 Shield 6 TMDS Data1-

7 TMDS Data0+ 8 TMDS Data0 Shield

9 TMDS Data0- 10 TMDS Clock+

11 TMDS Clock Shield 12 TMDS Clock-

13 CEC 14 Reserved (N.C. on device)

15 SCL 16 SDA

17 EDID/CEC Ground 18 +5V Power

19 Hot Plug Detect

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RCA-type (Yellow) Composite Video Connector

a. Frequency: H: 15.734KHz RCA jack (NTSC)

b. Signal level: 1Vp-p V: 60Hz 0.3V below Video (Y+C)

c. Impedance: 75ȍ Sync (H+V):

d. Connector type: RCA jack

S-Video Connector

443

2

1

1, 2 = GND

3 = Luminance (Y)

4 = Chrominance(C)

a. Frequency: H: 15.734KHz V: 60Hz (NTSC)

b. Signal level: Y: 1Vp-p C: 0.286Vp-p

c. Impedance: 75ȍ

d. Connector type: 4-pin mini DIN

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File No. SG-0214

Y-Cb/Pb-Cr/Pr Component video signal

a. Frequency: H: 15.734KHz V: 60Hz (NTSC-480i)

H: 31KHz V: 60Hz (NTSC-480p)

H: 45KHz V: 60Hz (NTSC-720p)

H: 33KHz V: 60Hz (NTSC-1080i)

H: 67.50KHz V: 60Hz (NTSC-1080p)

b. Signal level: Y: 1Vp-p Pb: r0.350Vp-p Pr:

r0.350Vp-p

c. Impedance: 75ȍ

d. Connector type: RCA jack

PC audio in

a. Signal level: 1Vrms

Video audio in

b. Impedance: 47Kȍ

c. Connector type: 3.5 I mini jack

a. Signal level: 0.7Vrms

b. Impedance: 47Kȍ

c. Frequency Response: 20Hz-20KHz

d. Connector type: RCA L/R:

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3. INPUT CONNECTORS

A

A

Inputs I/Os

V1 (1x Composite Video (1x RCA) + 1x

ʳ

ʳ

ʳ

ʳ

ʳ

ʳ

ʳ

ʳ

Service
interface

S-Video (1x 6-Pin DIN)+ 1x Stereo
Audio (RCA L/R) )

V2 (1x Composite Video (1x RCA) +1x
S-Video (1x 6-Pin DIN) + 1x Stereo Audio
(RCA L/R) )
Component1 (1x Component (3x RCA,
YPbPr Video) (1080p) + 1x Stereo
Audio (RCA L/R) )
Component2 (1x Component (3x RCA,
YPbPr Video) (1080p) + 1x Stereo
Audio (RCA L/R) ) COMPONENT 2 COMPONENT 2
HDMI (4x HDMI + 1x Stereo Audio (RCA
L/R) , HDCP & DVI support )

TV (Combo RF tuner, for internal
NTSC/ATSC/QAM)

VGA (1x Analog RGB (1x 15-Pin
D-Sub) ) + 1x Stereo Mini Jack) )

2x RJ11 (one for analog, one for DTV)

Wording on

the input OSD Wording on the rear

AV1 (S-VIDEO)/AV1

(VIDEO) AV1

AV2 (S-VIDEO)/AV2

(VIDEO)

COMPONENT 1 COMPONENT 1

HDMI HDMI

DTV

TV

RGB RGB PC

ʳ

DTV/TV - CABLE /

SERVICE 2 (MTK)

AV2

ANTENNA

SERVICE 1

(GNSS & 8051)

4. OUTPUT CONNECTORS

a. SPDIF Digital Audio Out (Optical)

b. Audio output

5. POWER SUPPLY

Consumption: 650W MAX Power OFF: less than 3W

6. SPEAKER

Output 20W (max) X2

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7. ENVIRONMENT

Operating

a. Temperature: 0~40к

b. Relative humidity: 20%~80% RH

c. Altitude: 0~6,560 ft

Non-operating

a. Temperature: -20~60к

b. Relative humidity: 10%~90% RH

c. Altitude: 0~9,840 ft

8. DIMENSIONS

Display Module (A)

Height 877mm 907.1mm 904.1mm

Width 1429mm 1429mm 1429mm

Depth 124mm 124mm 330mm

Display Module(A) +

Audio Deflector (B)

9. WEIGHT

a. Net 185 +/- 1.5 lbs

b. Gross 218 +/- 2.2 lbs

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Display Module(A) +

Audio Deflector (B) +

Base (C)

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Chapter 3 On Screen Display

Main unit button

Buttons 1 2 3 4 5 6 7

Name MENU CH+/Ÿ CH-/ź VOL+/Ź VOL-/Ż INPUT

OSD Adjustment

Main OSD Tree

Mode ʳʳʳʳ

Video Settings

ҲҥҠҡҫ

ҲҥҠҡҫ

ҲҥҠҡҫ

ҲҥҠҡҫ Saturation(OД100)

ҲҥҠҡҫ

ҲҥҠҡҫ

ҲҥҠҡҫ

ҲҥҠҡҫ

ҲҥҠҡҫ

Picture Mode(Custom, Vivid,

Movie, Game, Sport)

Brightness(O~100) ʳʳʳ

Contrast(O~100) ʳʳʳ

Hue(-50~50) ʳʳʳ

Sharpness(O~24) ʳʳʳ

Advanced ʳʳʳ

ʳ Noise Reduction ʳʳ

ʳʳ

ʳʳʳ

ʳʳʳ

Motion(High,

Medium, Low,

OFF, Adaptive)

ʳ

ҲҥҠҡҫ

ҲҥҠҡҫ

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ʳʳ Digital(O~64) ʳ

ʳ Fleshtone (Off, Low, ʳʳ

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File No. SG-0214

Mode ʳʳʳʳ

Medium, High)

ҲҥҠҡҫ

ҲҥҠҡҫ

ҲҥҠҡҫ

ҲҥҠҡҫ

ҲҥҠҡҫ

ҲҥҠҡҫ

ҲҥҠҡҫ

ҲҥҠҡҫ

ҲҥҠҡҫ

ҲҥҠҡҫ

Ҭҟ

Dynamic Contrast(0, 1,

ʳ

ʳʳ

2, 3, 4)

ʳ Color Temp ʳ

ʳ

ʳʳ Warm ʳ

ʳʳ Standard ʳ

ʳʳ Cool ʳ

ʳʳ Custom ʳ

ʳʳʳ Red(0~100)

ʳʳʳ

Green(0Д100)

ʳʳʳ Blue(0~100)

ʳʳʳʳ

ʳ Auto Adjustment ʳʳ

Ҭҟ

ʳ

Ҭҟ

Ҭҟ

Ҭҟ

Ҭҟ

Ҭҟ

Ҭҟ

ʳ Phase (0~100) ʳʳ

ʳ Clocks / Line(0~100) ʳʳ

ʳ ColorTemp ʳʳ

ʳʳ Warm ʳ

ʳʳ Standard ʳ

ʳʳ Cool ʳ

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Image

Position(-100~+100hor

ʳʳ

izontal,

-31~+31vertical)

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Mode ʳʳʳʳ

Ҭҟ

Ҭҟ

Ҭҟ

Ҭҟ

Ҭҟ

ʳʳ User ʳ

ʳʳʳ Red(0~100)

ʳʳʳ

Green(0Д100)

ʳʳʳ Blue(0~100)

Power

ʳ

ʳʳ

saving(ON/OFF)

ʳ Reset ʳʳʳ

Audio Settings

ʳ Bass(O~20) ʳʳʳ

ʳ Treble(O~20) ʳʳʳ

ʳ Balance(-10~10) ʳʳʳ

ʳ SRSTSXT(On,Off) ʳʳʳ

ʳ Auto Volume(On,Off) ʳʳʳ

ʳ

Audio Out(Fixed VolumeΡ

ʳʳʳ

Variable Volume)

ʳ

Speakers(OnΡOff)

ʳʳʳ

ʳ Reset ʳʳʳ

Parental Controls

ҲҥҠҡҫ

Parental Lock Enable (No,

ʳʳʳ

Yes)

ҲҥҠҡҫ

ҲҥҠҡҫ

ҲҥҠҡҫ

TV Rating ʳʳʳ

ʳ TV Youth ʳʳ

ʳ TV Youth 7 ʳʳ

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Mode ʳʳʳʳ

ҲҥҠҡҫ

ҲҥҠҡҫ

ҲҥҠҡҫ

ҲҥҠҡҫ

ҲҥҠҡҫ

ҲҥҠҡҫ

ҲҥҠҡҫ

ҲҥҠҡҫ

ҲҥҠҡҫ

ҲҥҠҡҫ

ҲҥҠҡҫ

ҲҥҠҡҫ

ʳ TV G ʳʳ

ʳ TV PG ʳʳ

ʳ TV 14 ʳʳ

ʳ TV MA ʳʳ

Movie Rating ʳʳʳ

ʳ Movie G ʳʳ

ʳ Movie PG ʳʳ

ʳ Movie PG-13 ʳʳ

ʳ Movie R ʳʳ

ʳ Movie NC-17 ʳʳ

ʳ Movie X ʳʳ

Blocked Unrated(Yes,No) ʳʳʳ

ҲҥҠҡҫ

ҲҥҠҡҫ

Change Password ʳʳʳ

Please enter new

ʳ

ʳʳ

password

ҲҥҠҡҫ

ʳ

Please re-enter new

ʳʳ

password

ҲҥҠҡҫ

ʳʳʳʳ

Tuner Settings

ATV Cable/Air(Cable, Air) ʳʳʳ

ATV Scan ʳʳʳ

ATV Channel Skip ʳʳʳ

ATV MTS(Mono, Stereo, SAP) ʳʳʳ

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Mode ʳʳʳʳ

DTV DTV Menu ʳʳʳ

ʳʳ ʳ ʳ ʳ

ʳʳ ʳ ʳ ʳ

ʳʳ ʳ ʳ ʳ

Setup

ʳ Language(English, Français,

ʳʳʳ

Español)

VIDEO Aspect Ratio(16:9, Zoom,

ʳʳʳ

4:3, Panoramic)

PC Aspect Ratio(16:9, 4:3) ʳʳʳ

ʳ PIP ʳ ʳʳ

ʳ

ʳ

PIP Mode(Off, Large

ʳʳ

PIP, Small PIP, POP)

ʳ

PIP Position(Top-Left,

Top-Right,

ʳ

ʳʳ

Bottom-Left,

Bottom-Right)

ʳʳ PIP Input ʳʳ

AV/ATV

AV/ATV

Closed Caption ʳʳʳ

Display(Off, CC1, CC2,

CC3, CC4, TEXT1,

ʳ

ʳʳ

TEXT2, TEXT3,

TEXT4)

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Mode ʳʳʳʳ

PDP Image Cleaner ʳʳʳ

ʳ ʳ ʳʳ

Ҙǵ DTV Menu

LEVEL 1 LEVEL 2 LEVEL 3 LEVEL 4 LEVEL 5

DTV Tuner

Setup ʳʳʳʳ

ʳ Time Zone ʳʳʳ

ʳʳ Hawaii ʳʳ

Eastern

ʳʳ

Time ʳʳ

ʳʳ Indiana ʳʳ

ʳʳ Central Time ʳʳ

Mountain

ʳʳ

Time ʳʳ

ʳʳ Arizona ʳʳ

ʳʳ Pacific Time ʳʳ

ʳʳ Alaska ʳʳ

ʳ Cable/Air/Auto ʳ ʳʳ

ʳʳ Cable ʳʳ

ʳʳ Air ʳʳ

ʳʳ Auto ʳʳ

ʳ Scan ʳ ʳʳ

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LEVEL 1 LEVEL 2 LEVEL 3 LEVEL 4 LEVEL 5

ʳ Manual Scan ʳʳ

ʳʳ Scan Mode ʳʳ

Add-on

ʳʳ ʳ

Mode ʳ

Range

ʳʳ ʳ

Mode ʳ

ʳʳ ʳ ʳ From Channel

ʳʳ ʳ ʳ To Channel

ʳ Channel Skip ʳʳʳ

Digital Audio

ʳ

Out ʳʳʳ

ʳʳ PCM ʳʳ

ʳʳ OFF ʳʳ

ʳʳ Dolby Digital ʳʳ

ʳʳ ʳ ʳ ʳ

Closed

Caption ʳʳʳʳ

Analog Closed

ʳ

Caption

CC1~CC4Ε

OFF ʳʳ

Service

Digital Closed

ʳ

Caption

1~Service

6ΕOFF

ʳʳ

ʳ Digital Caption ʳʳʳ

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LEVEL 1 LEVEL 2 LEVEL 3 LEVEL 4 LEVEL 5

Style

ʳʳAsBroadcaster ʳʳ

ʳʳ Custom ʳʳ

ʳʳ ʳ Font Size ʳ

ʳʳ ʳ ʳ Lagrge

ʳʳ ʳ ʳ Small

ʳʳ ʳ ʳ Medium

ʳʳ ʳ Font Color ʳ

ʳʳ ʳ ʳ Black

ʳʳ ʳ ʳ White

ʳʳ ʳ ʳ Green

ʳʳ ʳ ʳ Blue

ʳʳ ʳ ʳ Red

ʳʳ ʳ ʳ Cyan

ʳʳ ʳ ʳ Yellow

ʳʳ ʳ ʳ Magenta

Font

ʳʳ ʳ

Opacity ʳ

ʳʳ ʳ ʳ Solid

ʳʳ ʳ ʳ Translucent

ʳʳ ʳ ʳ Transparent

ʳʳ ʳ Background ʳ

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LEVEL 1 LEVEL 2 LEVEL 3 LEVEL 4 LEVEL 5

Color

ʳʳ ʳ ʳ Black

ʳʳ ʳ ʳ White

ʳʳ ʳ ʳ Green

ʳʳ ʳ ʳ Blue

ʳʳ ʳ ʳ Red

ʳʳ ʳ ʳ Cyan

ʳʳ ʳ ʳ Yellow

ʳʳ ʳ ʳ Magenta

Background

ʳʳ ʳ

Opacity ʳ

ʳʳ ʳ ʳ Solid

ʳʳ ʳ ʳ Translucent

ʳʳ ʳ ʳ Transparent

Window

ʳʳ ʳ

Color ʳ

ʳʳ ʳ ʳ Black

ʳʳ ʳ ʳ White

ʳʳ ʳ ʳ Green

ʳʳ ʳ ʳ Blue

ʳʳ ʳ ʳ Red

ʳʳ ʳ ʳ Cyan

ʳʳ ʳ ʳ Yellow

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LEVEL 1 LEVEL 2 LEVEL 3 LEVEL 4 LEVEL 5

ʳʳ ʳ ʳ Magenta

Window

ʳʳ ʳ

Opacity ʳ

ʳʳ ʳ ʳ Solid

ʳʳ ʳ ʳ Translucent

ʳʳ ʳ ʳ Transparent

* HDMI and Component 720p/1080i/1080p inputs do not support Panoramic.

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DTV Menu

A

.DTV Tuner

Setup ʳʳʳʳ

ʳ a.Time Zone ʳʳ ʳ

ʳʳ 1.Hawall ʳʳ

ʳʳ 2.Eastern Time ʳʳ

ʳʳ 3.Indiana ʳʳ

ʳʳ 4.Central Time ʳʳ

ʳʳ 5.Mountain Time ʳʳ

ʳʳ 6.Arizona ʳʳ

ʳʳ 7.Pacific Time ʳʳ

DTV Menu

ʳʳ 8.Alaska ʳʳ

ʳ b.Cable/Air/Auto ʳʳ ʳ

ʳ c.Scan**** ʳʳ ʳ

ʳ d.Manual Scan**** ʳʳ

ʳʳ Scan mode ʳʳ

ʳʳ ʳ Add-on Mode ʳ

ʳʳ ʳ Range Mode ʳ

ʳʳ ʳ ʳ From Channel

ʳʳ ʳ ʳ To Channel

ʳ e.Channel Skip ʳʳ ʳ

ʳ f.Digital Audio Out ʳʳ ʳ

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DTV Menu

ʳʳ 1.PCM ʳʳ

ʳʳ 2.OFF ʳʳ

ʳʳ 3.Dolby Digital ʳʳ

B.Closed

Caption ʳʳʳʳ

a.Analog Closed

ʳ

ʳ

Caption

b.Digital Closed

CAPTION

CC1~CC4ޔOFF

Service1~Servic

e6ޔOFF

ʳʳ

ʳʳ

c.Digital Closed

ʳ

Style ʳʳ ʳ

ʳʳ 1.As Broadcaster ʳʳ

ʳʳ 2.Custom ʳʳ

ʳʳ ʳ (1)Font Size ʳ

ʳʳ ʳ ʳ Large

ʳʳ ʳ ʳ Small

ʳʳ ʳ ʳ Medium

ʳʳ ʳ (2)Font Color ʳ

ʳʳ ʳ ʳ Black

ʳʳ ʳ ʳ White

ʳʳ ʳ ʳ Green

ʳʳ ʳ ʳ Blue

ʳʳ ʳ ʳ Red

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DTV Menu

ʳʳ ʳ ʳ Cyan

ʳʳ ʳ ʳ Yellow

ʳʳ ʳ ʳ Magenta

ʳʳ ʳ (3)Font Opacity ʳ

ʳʳ ʳ ʳ Solid

ʳʳ ʳ ʳ Translucent

ʳʳ ʳ ʳ Transparent

(4)Background

ʳʳ ʳ

Color ʳ

ʳʳ ʳ ʳ Black

ʳʳ ʳ ʳ White

ʳʳ ʳ ʳ Green

ʳʳ ʳ ʳ Blue

ʳʳ ʳ ʳ Red

ʳʳ ʳ ʳ Cyan

ʳʳ ʳ ʳ Yellow

ʳʳ ʳ ʳ Magenta

(5)Background

ʳʳ ʳ

Opacity ʳ

ʳʳ ʳ ʳ Solid

ʳʳ ʳ ʳ Translucent

ʳʳ ʳ ʳ Transparent

ʳʳ ʳ (6)Window Color ʳ

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DTV Menu

ʳʳ ʳ ʳ Black

ʳʳ ʳ ʳ White

ʳʳ ʳ ʳ Green

ʳʳ ʳ ʳ Blue

ʳʳ ʳ ʳ Red

ʳʳ ʳ ʳ Cyan

ʳʳ ʳ ʳ Yellow

ʳʳ ʳ ʳ Magenta

(7)Window

ʳʳ ʳ

Opacity ʳ

ʳʳ ʳ ʳ Solid

ʳʳ ʳ ʳ Translucent

ʳʳ ʳ ʳ Transparent

Parental

control ʳʳʳʳ

ʳ C. Password ʳʳ ʳ

ʳʳ Channel Block ʳʳ

* HDMI and Component 720P/1080i inputs do not support Panoramic.

**See below for detailed information regarding the PIP sources.

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SUB

MAIN DTV

TV AV1 AV 2 Component 1 Component 2

RG

HDMI 1 HDMI 2

B

DTV

TV

AV1 9 9

AV2 9 9

Component 1

9

9

Component 2 9 9

RGB

9 9 9 9 9 9 9 9

HDMI 1 9 9

HDMI 2 9 9

9 9 9 9

9 9 9 9

9 9 9

9 9 9

9 9 9

9 9 9

9 9 9 9

9 9 9 9

9

9

9

9

9

9

9

9

9 9

9 9

9 9

9 9

9 9

9 9

9

9

RemarkΚ

(1) “9” – Indicates which inputs are available for PIP and POP modes.

(2) For AV1 and AV2, S-Video has priority. If a signal is connected to AV1 S-Video by itself or

signals are connected to AV1 S-Video and AV1 Video simultaneously, then S-Video will be

the only choice for AV1. If a signal is connected to AV1 Video only, then Video will be the

only choice for AV1. The same input priority scheme applies to AV2.

*** When Speakers off

**** Do Scan or Manual Scan function, it maybe spend several minutes is normal. It

depends on channels and area.

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Page 3-15

Chapter 4 Factory preset timings

This timing chart is already preset for this plasma monitor.

PC analog preset modes

Horizonta

Refresh

Mode

Resolution

No.

1 640x480 60 31.5 59.94 N N 25.175 Windows

2 640x480 75 37.5 75.00 N N 31.500 Windows

3 800x600 60 37.9 60.317 P P 40.000 Windows

4 800x600 75 46.9 75 P P 49.500 Windows

5 800x600 85 53.7 85.06 P P 56.250 Windows

6 1024x768 60 48.4 60.01 N N 65.000 Windows

7 1024x768 70 56.5 70.07 N N 75.000 Windows

8 1024x768 75 60.0 75.03 P P 78.750 Windows

Rate

(Hz)

Horizontal

Frequency

(KHz)

Vertical

l Sync

Frequency

Polarity

(Hz)

(TTL)

Vertical

Sync

Polarity

(TTL)

Pixel

Rate

(MHz)

Remark

9 1366X768 60 47.7 60.00 P N 85.500 Windows

10 1280X1024 60 63.98 60.02 P P 108.000 Windows

Remark: P: positive, N: negative 1366x768 @60 Hz: Primary

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HD video digital preset modes at HDMI

Mode No. Resolution

1 480i

2 480p

3 720p

4 1080i

5 1080p

HDMI digital preset modes at DVI

through HDMI interface by an optional interface cable below video input.

Video input

Mode No. Resolution

1 480i

2 480p

3 720p

4 1080i

5 1080p

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Chapter 5 Pin Assignment

(1) RF Connector

(2) RGB Connector

a. Type: Analog

b. Frequency: H: 30-80KHz V: 60-85Hz

c. Signal level: 0.7Vp-p

d. Impedance: 75ȍ

e. Synchronization H/V separate sync: TTL

H/V composite sync: Sync on Green TTL

f. Video bandwidth: 135MHz

g. Connector type: 15-pin D-Sub, female

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Pin Pin Assignment Pin Pin Assignment

1 Red video input 9 +5V

2 Green video input 10 Ground

3 Blue video input 11 No connection

4 Ground 12 (SDA)

5 Ground 13 Horizontal sync (Composite sync)

6 Red video ground 14 Vertical sync

7 Green video ground 15 (SCL)

8 Blue video ground

(3) HDMI Connector

ˈ

˄˃

˄ˈ

ˈ

˄ˈ

˄

ˉ˄˃

˄˄

˄

ˉ

˄˄

a. Frequency: H: 15.734KHz V: 60Hz

H: 31KHz V: 60Hz

H: 45KHz V: 60Hz

H: 33KHz V: 60Hz

H: 67.5KHz V: 60Hz

b. Polarity: Positive or Negative

c. Type: Type A

d. Pin Assignment: Please see below .

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Pin 2

Pin Signal Assignment Pin Signal Assignment

1 TMDS Data2+ 2 TMDS Data2 Shield

3 TMDS Data2- 4 TMDS Data1+

5 TMDS Data1 Shield 6 TMDS Data1-

7 TMDS Data0+ 8 TMDS Data0 Shield

9 TMDS Data0- 10 TMDS Clock+

11 TMDS Clock Shield 12 TMDS Clock-

13 CEC 14 Reserved (N.C. on device)

15 SCL 16 SDA

17 EDID/CEC Ground 18 +5V Power

19 Hot Plug Detect

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(4) RCA-type (Yellow) Composite Video Connector

a. Frequency: H: 15.734KHz RCA jack (NTSC)

b. Signal level: 1Vp-p V: 60Hz 0.3V below Video

(Y+C)

c. Impedance: 75ȍ Sync (H+V):

d. Connector type: RCA jack

(5) S-Video Connector

443

2

1

1, 2 = GND

3 = Luminance (Y)

4 = Chrominance(C)

a. Frequency: H: 15.734KHz V: 60Hz (NTSC)

b. Signal level: Y: 1Vp-p C: 0.286Vp-p

c. Impedance: 75ȍ

d. Connector type: 4-pin mini DIN

(6) Y-Cb/Pb-Cr/Pr Component video signal

a. Frequency: H: 15.734KHz V: 60Hz (NTSC-480i)

H: 31KHz V: 60Hz (NTSC-480p)

H: 45KHz V: 60Hz (NTSC-720p)

H: 33KHz V: 60Hz (NTSC-1080i)

H: 67.50KHz V: 60Hz (NTSC-1080p)

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(7) PC audio in

(8) Video audio in

b. Signal level: Y: 1Vp-p Pb: r0.350Vp-p Pr: r0.350Vp-p

c. Impedance: 75ȍ

d. Connector type: RCA jack

a. Signal level: 1Vrms

b. Impedance: 47Kȍ

c. Connector type: 3.5 I mini jack

a. Signal level: 0.7Vrms

b. Impedance: 47Kȍ

c. Frequency Response: 20Hz-20KHz

d. Connector type: RCA L/R:

(9) SPDIF Digital Audio Out (Optical)

a. Peak emission wave length: 630 – 690 μm

b. Transmission Speed: 13.2M pbs

c. Connector type: Optical fiber transmitter

(10) Audio output

a. Signal level: 0.7Vrms

b. Impedance: 100ȍ

c. Frequency Response: 20Hz-20KHz

d. Connector type: RCA L/R:

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File No. SG-0214

Chapter 6 Block Diagram

System Block Diagram

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CONFIDENTIAL

File No. SG-0214

The TV system block diagram is powered by power board that transforms AC source of 100V~240V AC +/- 10% @ 50/60 HZ

into DC 5Vsb, 5V & 12V source. The main board receives different types of video signal into the FLI8668 IC. Afterward, the FLI8668

IC process the signals control the various functions of the monitor and outputs control signal, video signal and power to the 60” LGE

panel to be displayed.

The analog video signals are processed in the panel and the outcome determines the brightness, pixel on/off and the color

displayed on the panel. The signals of S-video, YPbPr, TV, PC and A/V all video signals are translated from analog signals into

FLI8668 generates the vertical and horizontal timing signals for display device.

The analog audio of s-video, YPbPr, TV, PC and A/V is transmitting to the BBE MSP4450 processed. The purpose is process

the input audio signal to control volume, bass, treble, surround, and balance. The HDMI video and audio is must transmitting to

Sil9025 processed then TMDS signal to the FLI8668 generates the vertical and horizontal timing signals for display device.

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CONFIDENTIAL

File No. SG-0214

Video Block Diagram

DO NOT COPYʳ Page 6ˀˆ

Ω

CONFIDENTIAL

+12V_SW

U28/ NC

+15V_SW

U41

IDTQS3253QG

TDA8946AJ

+5V_AU2

FB33

80ohm_100MHz

U27

MSP4440G

+5V_AUDL8

50uH_1A

U22

+5V_AU1

U33

CS4344-CZZ

FB15

+5V_SW1

PI5C3257QE

U23

U15

MM74HC4052MX

80ohm_100MHz

U18

U21

MC7805CTG

PI5C3257QE

FB17

80ohm_100MHz

AV15_HDMI1

FB29

IDTQS3253QG

AV15

U29

HDMI

RECEIVER

SiI9025CTU

U31

PI3HDMI412FTZHE

AV15_HDMI2

AV33_HDMI1

80ohm_100MHz

FB31

80ohm_100MHz

FB28

U30

AMC1117-ADJ

U32

AV33_HDMI2

80ohm_100MHz

FB30

80ohm_100MHz

PI3HDMI412FTZHE

+1.8V_HDMI

U45

U6

AP1117E18LA

+3.3V

U9

CONTROLLER

MX29LV320

+1.8V

FLI8668

+2.5V_DDR

U13

HY5DU561622ETP-4

U12

HY5DU561622ETP-4

File No. SG-0214

+5V

U1

FDS4935

+15V_AUD

U2/ NC

F2

1.5A/125V

PDP_AUDIO

N2576SG-ADJ

+12V

Main BD Power Block Diagram

+8V

U3

MC7805CTG

F3

U25

KIA7808API

4A/125V

PDP_+12V

+3.3VSB

+5VSB

U10

74HCT14D

U35, U38

PI5C3257QE

F4

1A/125V

PDP_+5Vsb

U4

AP1084D33LA

U42

MCU

SM5964C40JP

+6.3V

F1

U5

AP1084D33LA

4A/125V

PDP_+6.3V

U7

AP1084D18LA

U8

AP1117E25LA

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Ω

CONFIDENTIAL

Chapter7 Main Board I/o Connections

CN3 Connection (Power)

Pin Description

1 “PDP_+5V”

2 “PDP_+5V”

3 “PDP_+5V”

4 “GND”

5 “GND”

6 “GND”

7 “PDP_+12V”

8 “PDP_+12V”

9 “GND”

10 “GND”

CN5 Connection (Standby Power)

Pin Description

1 “PDP_+5Vsb”

2 “GND”

3 “VS_ON”

4 “PS_ON”

5 “BRIGHT”

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CN2 Connection (ATSC Power)

Pin Description

1 “GND”

2 “GND”

3 “GND”

4 “+12V_SW”

5 “+12V_SW”

CN10 Connection (LED Power)

Pin Description

1 “+5VSB”

2 “WHITE”

3 “AMBER”

CN22, CN23 Connection (FAN Power)

Pin Description

1 “GND”

2 NC

3 “FAN_VCC”

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CN9 Connection (Side Jack)

Pin Description

1 “CVBS1”

2 “+5V”

3 “AudioAV1_R”

4 “+5V”

5 “AudioAV1_L”

6 “GND”

7 “CVBS2”

8 “GND”

9 “AudioAV2_R”

10 “GND”

11 “AudioAV2_L”

12 “GND”

13 “LUMA1”

14 “LUMA2”

15 “CHROMA1”

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16 “CHROMA2”

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CN21 Connection (Audio)

Pin Description

1 “AUDIO_AMP_R”

2 “GND”

3 “AUDIO_AMP_L”

4 “MUTE_AMP”

5 “AUDIO_SUB”

6 “AUDIO_ON”

7 “SPDIF_OUT_AU”

8 “GND”

9 “AUDIO_TX”

10 “AUDIO_RX”

11 ”+12V”

12 “+5V”

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CN18 Connection (LVDS)

Pin Description Pin Description

1 “GND” 16 “GND”

2 “TXA3+“ 17 “PS_ON”

3 “TXA3-“ 18 “GND”

4 “GND” 19 “VS_ON”

5 “TXAC+“ 20 “GND”

6 “TXAC-“ 21 I2C_READY

7 “GND” 22 “GND”

8 “TXA2+“ 23 “MSTR0_SCL”

9 “TXA2-“ 24 “MSTR0_SDA”

10 “TXA1+“ 25 “GND”

11 “TXA1-“ 26 NC

12 “TXA0+“ 27 “LVDSVDD”

13 “TXA0-“ 28 “LVDSVDD”

14 “TXB3+“ 29 “LVDSVDD”

15 “TXB3-“ 30 “LVDSVDD”

31 “LVDSVDD”

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CN20 Connection (ATSC Signal)

Pin Description Pin Description

1 “GND” 29 “BDATA13”

2 “ATSC_SPDIF” 30 “BDATA12”

3 “SIF_Tuner” 31 “GND”

4 “NTSC_Tuner” 32 “BDATA11”

5 “Tuner_SW” 33 “BDATA10”

6 “GND” 34 “BDATA9”

7 “SDA_5V” 35 “BDATA8”

8 “SCL_5V” 36 “GND”

9 “ATSC_RDY” 37 “BDATA7”

10 “ATSC_RST” 38 “BDATA6”

11 “GND” 39 “BDATA5”

12 “IPCLK1” 40 “BDATA4”

13 “BDE” 41 “GND”

14 “BVS” 42 “BDATA3”

15 “BHS” 43 “BDATA2”

16 “GND” 44 “BDATA1”

17 “BDATA23” 45 “BDATA0”

18 “BDATA22” 46 “GND”

19 “BDATA21” 47 “A_SDATA0”

20 “BDATA20” 48 “A_LRCK”

21 “GND” 49 “A_BCK”

22 “BDATA19” 50 “A_MCLK”

23 “BDATA18” 51 “GND”

24 “BDATA17” 52 “ATSC_RX”

25 “BDATA16” 53 “ATSC_TX”

26 “GND” 54 NC

27 “BDATA15” 55 NC

28 “BDATA14”

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CN7 Connection (Keypad)

Pin Description

1 “LED2_KEYPAD”

2 “+5VSB”

3 “IR”

4 “ADC_IN2”

5 “GND”

6 “+3.3V_LBADC”

7 “LBADC_RETURN”

8 “ADC_IN1”

9 “LED1_KEYPAD”

10 “GND”

11 “PWR_KEY”

12 “+5V”

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Chapter 8 Theory of Circuit Operation

The operation of user interface

The following diagram provides a brief overview of the user-interactive components of the

firmware.

Figure 8-1 User Interface Block Diagram

The operation of keypad

There are 7 keys to control and select the function. They are “Power, MENU, SET+, SET-,

VOL+, VOL-, INPUT” keys.

1.The power key controls video processor FLI8668, FLI8668 will receive a low/ high

signal to turn on/ off system while press the power key.

2.The other six keys are on high state because the pull up resistor but will transit to low

state dependent on which key pressed, and the state will be reader by FLI8668

through internalADC to act corresponding function.

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The operation of video processor FLI8668

The Genesis Microchip FLI8668 offers high integration for advanced, dual-channel

applications of Picture-in-Picture (PiP) and Picture-by-Picture (PBP). Two video decoders

with 3D comb filters and two channels of DCDi processing provide the highest quality picture

for a two-channel application.

The integrated VBI dataslicer and decoder remove the need for external counterparts

resulting in significant cost reduction. The FLI8668 supports many worldwide VBI standards

for applications of Teletext, Closed Captioning, V-Chip, and other VBI services.

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Figure 8-2 FLI8668 Block Diagram

Page 8-2

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Clock Generation

The FLI8668 features six clock inputs. All additional clocks are internal clocks derived from

one or more of these:

1.Crystal Input Clock (TCLK and XTAL). This is the input pair to an internal crystal oscillator

and corresponding logic. A 19.6608MHz TV crystal is recommended for best noise immunity

with the 3D decoder. Alternatively, a single-ended TTL/CMOS clock oscillator can be driven

into the TCLK pin (leave XTAL as N/C in this case). If an external crystal is being used,

connect a 10KӨ pull-up to OCMADDR_19. See Figure 8-3 Resetn Ball Behavior.

2.Digital Input Video/Graphics Clocks (IPCLK0, IPCLK1, IPCLK2 and IPCLK3)

3.Audio Delay Clock (AVS_CLK)

The FLI8668 TCLK oscillator circuitry is a custom-designed circuit to support the use of an

external oscillator or a crystal resonator to generate a reference frequency source for the

FLI8668 device.

Figure 8-3 Resetn Ball Behavior

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Analog Front End (AFE)

The FLI8668 chip has a flexible Analog Front End (AFE) with 13 configurable inputs. These

13 inputs can be shared across two configurable paths: V1 and V2. Either of these paths can

be used as Main or PIP channels. The 13 configurable inputs can be routed through an

analog multiplexer before the Analog to Digital Converters (ADCs) and decoders in V1 and V2.

These integrated features eliminate the need for any device between the input connector and

the Analog input pin of the FLI8668 beyond de-coupling capacitors.

Figure 8-4 Analog Front End

The figure above depicts the data path for the AFE and decoder blocks on V1 and V2 paths in

FLI8668. The data path selects whether the data follows the Main Video Channel or PIP video

channel.

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Page 8-4

Digital input port

The Digital Input Port is a 48-bit data input with flexible configuration to support a wide range

of digital sources. It consists of two 24-bit ports (PORTA and PORTB), two sets of control

signals (VS, HS, ODD, etc.), and 4 input clocks. Up to 4 different inputs are supported as long

as at least 2 of these inputs are 8-bit CCIR656. The digital input port can also be configured to

support one 30-bit input with a second 16-bit input port.

PORTA also includes optional signals (DIP_EXT_CLAMP, DIP_EXT_COAST,

DIP_CLEAN_HS_OUT) for interfacing to external ADC/PLL devices. These signals are not

present on PORTB. Bits 7 to 0 of PORTA can be configured as a bidirectional interface for

media card applications.

Inputs to the digital input port are TTL compatible with a maximum clock speed of 165MHz.

Sync and clock polarity are programmable.

Due to pin sharing, PORTB is not available when using 48-bit double-wide TTL output to the

panel.

The following digital video formats are supported by the FLI8668 digital video graphic port:

• ITU-BT-656

• 8-bit 4:2:2 YCbCr or YPbPr

• 16-bit 4:2:2 YCbCr or YPbPr

• 20-bit 4:2:2 YCbCr or YPbPr

• 24-bit 4:4:4 YCbCr or YPbPr

• 30-bit 4:4:4 YCbCr or YPbPr

• 24-bit RGB

• 30-bit RGB

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Digital input port configuration

The Digital Input Port offers flexible mapping of the input busses for PORTA and PORTB and

allows individual Bus Flipping (MSB to LSB) for each group of 8- or 10-bit inputs. The purpose

of this flexible mapping is to ease the circuit board design when interfacing to other devices.

Figure 8-5 Input DATA bus assignment

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LVDS Transmitter

Two LVDS channels (A and B) are available on the output of the FLI8668 to transmit data and

timing information to the display device.

FLI8668 directly drives the standard LVDS interface panels, supporting all standard data

formats—single and dual bus, 18- or 24-bit data output. The 24-bit data may be mapped as

either standard receiver formats. The following diagrams illustrate the RGB, HSync, VSync

and Data Enable signal mapping in a single bus output configuration. For dual bus output, the

only difference is that the even bus contains only the "even" pixels and the odd bus contains

only the "odd" pixels with the data clock at DCLK/2.

The following diagram shows the available LVDS mapping for 8-bit LVDS output which is

applying to PDP panel spec:

8-bit LVDS Output

Figure 8-6 Data Mapping For LVDS Output In 8-BIT Configuration With EIGHT_BIT_MODE_SEL=0

Figure 8-7 Data Mapping For LVDS Output In 8-BIT Configuration With EIGHT_BIT_MODE_SEL=1

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Page 8-7

On Chip Microcontroller (OCM)

The FLI8668 on-chip microcontroller (OCM) serves as the system microcontroller. It programs

the FLI8668 and manages other devices in the system such as the keypad and non-volatile

RAM (NVRAM) using general-purpose input/output (GPIO) pins. The OCM can address a

22-bit address space to utilize 4 MB external ROM.

Figure 8-8 OCM External Master

The OCM executes a firmware program running from external ROM, as well as driver-level (or

Application Programming Interface – API) functions residing in internal ROM. This is

illustrated above. A parallel port with separate address and data busses is available for this

purpose. This port connects directly to standard, commercially available ROM or

programmable Flash ROM devices in either 8 or 16-bit configurations. External Flash-ROM

memory requirements range from 512Kbytes to 4Mbytes depending on the application.

Both firmware and OSD content must be compiled into a HEX file and then loaded onto the

external ROM. The OSD content is generated using Genesis Workbench. Genesis

Workbench is a GUI-based tool for defining OSD menus, navigation, and functionality; this is

illustrated in Figure 8-9 Programming the OCM shown below.

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Figure 8-9 Programming The OCM

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Two-Wire master serial protocol

The two-wire protocol consists of a serial clock MSTR_SCL and bi-directional serial data line

MSTR_SDA. The FLI8668 acts as bus master and drives MSTR_SCL and either the master

or slave can drive the MSTR_SDA line (open drain) depending on whether a read or write

operation is being performed.

There are three isolated Master Serial busses, all driven by a common Master Serial

Controller.

These busses can be independently taken “off-line” or pulled up to different voltages without

affecting the other busses.

The two-wire protocol requires each slave device to be addressable by a 7-bit identification

number.

A two-wire data transfer consists of a stream of serially transmitted bytes formatted as shown

in the figure below. A transfer is initiated (START) by a high-to-low transition on MSTR_SDA

while MSTR_SCL is held high. A transfer is terminated by a STOP (a low-to- high transition on

MSTR_SDA while MSTR_SCL is held high) or by a START (to begin another transfer).

Figure 8-10 Two-Wire Protocol Data Transfer

Each transaction on the MSTR_SDA is in integer multiples of 8 bits (i.e. bytes). The number of

bytes that can be transmitted per transfer is unrestricted. Each byte is transmitted with the

most significant bit (MSB) first. After the 8 data bits, the master releases the MSTR_SDA line

and the receiver asserts the MSTR_SDA line low to acknowledge receipt of the data. The

master device generates the MSTR_SCL pulse during the acknowledge cycle. The addressed

receiver is obliged to acknowledge each byte that has been received.

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ADC capture window

In the horizontal direction, the capture window is defined in IP_CLKs (equivalent to a pixel

count). In the vertical direction, it is defined in lines.

All the parameters beginning with “Source” are programmed FLI8668 registers values. Note

that the Input Vertical Total is determined solely by the input and is not a programmable

parameter.

Figure 8-11 ADC Capture Window

The Reference Point marks the leading edge of the first internal HSYNC following the leading

edge of an internal VSYNC. Both the internal HSYNC and the internal VSYNC are derived

from external HSYNC and VSYNC inputs.

Horizontal parameters are defined in terms of single-pixel increments relative to the internal

horizontal sync. Vertical parameters are defined in terms of single-line increments relative to

the internal vertical sync.

For interlaced inputs, the FLI8668 may be programmed to automatically determine the field

type (even or odd) from the VSYNC/HSYNC relative timing. See Input Format Measurement,

Section Input Format Measurement (IFM).

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Page 8-11

DCDI by faroudja video processing

The FLI8668 dual zoom/shrink scalers use an advanced scaling technique proprietary to

Genesis Microchip Inc. They provide simultaneous high-quality scaling of real-time video and

graphics images on both channels. An input field/frame is scalable arbitrarily in both the

vertical and horizontal dimensions.

The input image is separated into three zones horizontally; left, center, and right. The center

zone is scaled at a programmable fixed ratio. The left and right zones have a programmable

changing scale factor that changes from left to right: see Figure 8-12 Non-linear Scaling of a

4:3 to 16:9 aspect ratio conversion. The scale ratio change can either be linear or parabolic.

Figure 8-12 Non-linear Scaling of a 4:3 to 16:9 aspect ratio conversion

A conversion for 16:9 to 4:3 aspect ratio would use the same method with an inverse

parabolic ratio for the scale factor of the left and right zones.

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Page 8-12

Display output interface

The Display Output Port provides data and control signals that permit the FLI8668 to connect

to a variety of display devices using a TTL or LVDS interface. The output interface is

configurable for single wide LVDS in 18, 24, or 30-bit RGB pixel format in single or

double-wide formats. TTL output is available in 18 or 24-bit RGB pixel formats as well as 20

and 24 4:2:2 YUV single wide formats. All display data and timing signals are synchronous

with the DCLK output clock. The integrated LVDS transmitter is programmable to allow the

data and control signals to be remapped to support all common LVDS receiver formats. DC

balanced operation is supported as described in the Open LDI standard.

Note: If the output is 4:4:4, the width can be 30 bits (10 bit per channel) or 24 bits (8 bits per

channel) and YUV is re-mappable through the 3x3 matrix. If the output is 4:2:2, the 3x3 matix

can only be used for color space conversion and there are three fixed options:

a. 4:2:2, 8 bits per channel, outputs allocation – G = Y, B = UV

b. 4:2:2, 10 bits per channel, outputs allocation – G = Y, B = UV

c. 4:2:2, 12 bits per channel, outputs allocation – G [7:0] = Y [11:4], B [7:0] = UV [11:4], R [3:0]

= UV [3:0], R [7:4] = Y [3:0]

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Display timing programming

Display timing signals provide timing information so the Display Port can be connected to an

external display device via a TTL or LVDS interface. Based on values programmed in

registers, the Display Timing Generator produces the horizontal sync (DHS), vertical sync

(DVS), and data enable (DEN) control signals. The figure below provides the registers that

define the output display timing.

Horizontal values are in single-pixel increments except for the display horizontal sync end

position which is in 4-DCLK increments. When the display is in double-wide mode, horizontal

settings should use even numbers. Vertical values are programmed in line increments relative

to the leading edge of the vertical sync signal.

Figure 8-13 Display Windows and Timing

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The operation of HDMI Sil9025

The SiI9025 provides a complete solution for receiving HDMI compliant digital audio and

video. Specialized audio and video processing is available within the SiI9025 to easily and

cost effectively add HDMI capability to consumer electronics devices such as Digital TVs,

plasma displays, LCD TVs and projectors.

Figure 8-14 Functional Block Diagram

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TMDS digital core

The two TMDS cores perform 10-to-8-bit TMDS decoding on the audio and video data

received from the three TMDS differential data lines along with a TMDS differential clock. The

TMDS cores can sense a stopped clock or stopped video and put the receiver into

power-down mode.

Active Port Detection and Selection

Only one port may be active at a time, under control of the receiver’s firmware. Active TMDS

signaling may arrive at both ports, but only one will have its TMDS clock pair termination

active and only one port will have its internal circuitry enabled. These states are controlled

with register settings by the firmware in the display.

Other control signals are associated with the TMDS signals on each HDMI port. The +5V

supply from each attached host can be monitored by the SiI9025. The microcontroller can poll

registers to check on which ports are connected. The firmware also controls functional

connection to one of the two E-DDC buses, enabling one while disabling the other. An

attached host determines the active status of an attached HDMI device by polling the E-DDC

bus to the receiver.

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Data Input and Conversion

Mode control logic

The mode control logic determines if the decrypted data is video, audio or auxiliary

information, and directs it to the appropriate logic block.

Video data conversion and video output

The SiI9025 can output video in many different formats (see examples in Table 1). The

receiver can also process the video data before it is output, as shown in Figure 8-15 Each of

the processing blocks may be bypassed by setting the appropriate register bits.

Table 1. Digital Video Output Formats

Figure 8-15 Default Video Processing Path

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Chapter 9 Waveforms

1. Voltage Measurement

(1) 12V (+12V, U3-1)

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(2) 5V (+5V, U3-3)

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(3) 5V (+5VSB, U4-3)

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(4) 3.3V (+3.3VSB, U4-2)

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(5) 3.3V (+3.3, U5-2)

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(6) 2.5V (+2.5V_DDR, FB9-2)

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(7) 1.8V (+1.8V, U7-2)

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(8) 1.8V (+1.8V_HDMI, U6-2)

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2. Clock Timing

(1) FLI8668 Clock (1.U9-B26, XTAL / 2.U9-C26, TCLK)

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(2) Memory Clock (1.U12-45, CLK / 2.U13-45, CLK)

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(3) Sil 9025 Clock (1.U29-97, XTLI / 2.U29-96, XTLO)

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(4) SM5964 Clock (1.U42-21, X1 / 2.U42-20, X2)

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3. H-sync & V-sync Timing

PC Mode (1024 x 768 60Hz)

(1) H-sync (U17-1, HS_VGA)

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(2) V-sync (U17-5, VS_VGA)

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Chapter 10 Trouble shooting

g

r

PDP display nothing (Component/ AC on/ off default)

START

LED backlight

?

is ambe

YES

LED backlight

is white?

YES

Is picture on

screen?

YES

N0

Check AC power cord

Check internal CN3 cable

N0 YES

N0 YES

Check internal CN18
LVDS cable connect
correctly between
panel and M/B?

Pin 1,2,3 Ш +5V
Pin 7,8 Ш +12V

Check internal CN5 cable

Pin 3 Ш PS_ON (high)

Check internal CN5 cable
Pin 2 Ш VS_ON (high)

YES NO NO

YES

Check internal CN5 cable
Pin 1 Ш PDP_+5Vsb

N0 YES

Check fuse open?

F1 Ш +5V
F3 Ш +12V

N0

YES

Press Menu or Info.
Is there any OSD logo

N0

Check CN18 pin 21
(I2C_READY) is high?

YES

NO

Check U5.2Ш3.3V

Check U7.2Ш1.8V

Check U8.2Ш2.5V

Remove R97
Check U9 (FLI8668) pin
AD14 is high?

Check fuse open?
F4 Ш PDP_+5Vsb

Panel power fail

Fuse fail

N0

N0

N0

Check input source

U5 fail

U7 fail

U8 fail

U9
FAIL

Block 1

PDP display nothing (Component1, 2 without Y signal)

N0 N0

Is YPbPr

nal on?

si

Check component (Y signal)
Ш C163,C170
Is there sync?

Yes

Use GProbe connect from main to PC
Does scaler detect the signal?

ONFIDENTIAL – DO NOT COPY

Trace component from input to U9 circuit
1Ш Check R574, C391, R213
2Ш Check R581, C394, R234

N0

U9 fail

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PDP display nothing (Component1, 2 without Pb signal)

g

g

Block1

Is YPbPr

nal on ?

si

N0

Check component (Pb signal)
Ш C165,C171
Is there sync?

Use GProbe connect from main to PC
Does scaler detect the signal?

YES

N0

PDP display nothing (Component1, 2 without Pr signal)

Block1

I Is YPbPr

si

nal on?

N0

Check component (Pr signal)
Ш C167,C172
Is there sync?

Use GProbe connect from main to PC
Does scaler detect the signal?

YES

N0

PDP display nothing (RGB)

Trace component from input to U9 circuit
1Ш Check R575, C392, R217
2Ш Check R582, C395, R235

N0

U9 fail

Trace component from input to U9 circuit
1Ш Check R576, C393, R226
2Ш Check R583, C396, R237

N0

U9 fail

Block1

Is RGB signal

on?

N0

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Check U17
H sync outputШ pin 4, R198
V sync outputШ pin 8, R202

N0 YES

Check U17
H sync inputШpin 1, R195
V sync inputШpin 5, R199

No YES

Check input source

Check U17
pin 14Ш +3.3V

U17 fail

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PDP display nothing (AV1<CVBS1> without screen)

g

g

Block1

N0 YES

Is composite

nal on?

si

Check internal cable?
Connect (CN9) cable

Check U18 pin 6 (CVBS1)
is there signal?

Check:

1.C3 (signal AC coupled)

YES No

2.R1

3.R4 (75ohm impedance)
Is there signal?

PDP display nothing (AV2<CVBS2> without screen)

No No

Check Connect Board

Check Q1 base is there signal?
Check collector voltage +5V

Check input source

Q1 fail

Block1

Is composite

si

nal on?

N0 YES

Check internal cable?
Connect (CN9) cable

Check U18 pin 4 (CVBS2)
is there signal?

No No

Check Connect Board

Check Q2 base is there signal?
Check collector voltage +5V

Check:

1.C7 (signal AC coupled)

YES No

2.R8

3.R9 (75ohm impedance)
Is there signal?

Q2 fail

Check input source

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PDP display nothing (AV1<S-Video1> without screen)

g

Block1

N0 YES

Is composite

nal on?

si

YES

Check U18 pin 11 (CHROMA1)
is there signal?

Check internal cable?
Connect (CN9) cable

Check U18 pin 5 (LUMA1)
is there signal?

No No

Check:

1.C12 (signal AC coupled)

YES No

2.R19

3.R21 (75ohm impedance)
Is there signal?

Check Connect Board

Check Q3 base is there signal?
Check collector voltage +5V

Q3 fail

Check input source

No No

Check Connect Board

Check Q4 base is there signal?
Check collector voltage +5V

Check:

1.C18 (signal AC coupled)

YES No

2.R18

3.R20 (75ohm impedance)
Is there signal?

Q4 fail

Check input source

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PDP display nothing (AV2<S-Video2> without screen)

g

Block1

N0 YES

Is composite

nal on?

si

YES

Check U18 pin 13 (CHROMA2)
is there signal?

Check internal cable?
Connect (CN9) cable

Check U18 pin 3 (LUMA2)
is there signal?

No No

Check:

1.C24 (signal AC coupled)

YES No

2.R25

3.R28 (75ohm impedance)
Is there signal?

Check Connect Board

Check Q6 base is there signal?
Check collector voltage +5V

Q6 fail

Check input source

No No

Check Connect Board

Check Q5 base is there signal?
Check collector voltage +5V

Check:

1.C20 (signal AC coupled)

YES No

2.R24

3.R27 (75ohm impedance)
Is there signal?

Q5 fail

Check input source

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PDP display nothing (HDMI1, 2, 3, 4)

Block1

Is HDMI signal

on?

Is picture on

screen?

N0

Check input source

YES

Check I2C bus
U34, U36, U37, U39
SCLШ pin 6

SDAШ pin 5

Check
U29(SiI9025) pin 103Шhigh

N0 No No

V syncШ R366
H syncШ R367
ClockШ R368

Check Source
Q28, Q31, Q34, Q37
Ш high(3.3V)

YES

Check U29 I2C bus
CSDAШ pin 27
CSCLШ pin 28

No No

Check power
U34, U36, U37, U39
5VШ pin 8

Check +3.3VSBШ
FB23, FB24, FB25, FB26, FB27
+1.8V_HDMIШU6 pin 2

YES

No No

Check Gata
Q28, Q31, Q34, Q37
Ш high(5V)

No No

I2C add.Ш R371

Q28 or Q31 or Q34 or Q37 fail

Check Block 2

Check schottky diode

1.D30, D31

2.D33, D34

3.D36, D37

4.D39, D40

No

1.D30 or D31 fail

2.D33 or D34 fail

3.D36 or D37 fail

4.D39 or D40 fail

Check crystalШ
Y2=28.322MHz

Check U29 RGB data bus
BШ RP1, RP2

Is picture on

screen?

N0

GШ RP3, RP4
RШ RP5, RP6

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YES

Yes

U29 fail Check U29 all power

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Block 2

(

Start

HDMI’s chip

communicate with U42

SM5964) is ok?

N0

Check U42 power
Ш pin 44, 35

Check crystalШ
Y3=11.0592MHz

Check U42 UART
TXDШ pin 13
RXDШ pin 11

Yes

Yes

No No

Check U15
pin 16Ш +5V
pin 10Ш output select=high

Check R86, R87

U15 fail

Yes

No

U9 fail

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PDP display nothing (TV, DTV)

g

Block1

Check internal CN20 FFC
cable connect correctly

Is picture on

screen?

Is TV, DTV

nal on?

si

N0

between J1 (ATSC Board)
and M/B?

N0 N0

If power off, U1-2 Ш high
U1-2 low Ш ON
Check pin 7,8 Ш +12V_SW

U1 fail

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Chapter 11 Spare Parts List

PART NO DESCRIPTION LOC QTY REMARK

0111-3104-5115 C/M MULTI 0.1UF 50V X7R 0805

0320-4000-0142 POWER CORD 110V UL/CSA 1800mm BLK N.M. (VINC) ʳ 1 ʳ

0321-0000-0411 AV CABLE RCA(Y/W/R) 1800mm BLK (VINC) ʳ 1 ʳ

0360-1000-0410 POWER INDUCTOR L:15uH 4.7A 12x12mm SMD LF L2, L3, L4, L5 4 ʳ

0400-0681-2713 ZENER 6.46V-7.14V MMSZ5235B 1/2W SOD-123 L-F

0420-1004-9621 MOSFET N-CH 2N7002E-T1-E3 SMD (SOT-23) L-F Q4 1 ʳ

0430-1008-6088 IC NJM4558M-TE2_PB SO8(DMP8) L-F U1, U6 2 ʳ

0430-7043-3620 IC 50W AUDIO AMP MP7782DF-LF-Z 20PIN TSSOP LF U7,U8 2 ʳ

0390-5004-2343 GEN. DIODE LL4148WP SMD 1206 L-F

1801-1932-8011 LOGO-LENS ASS'Y (VM60P HDTV10A) ʳ 1 ʳ

1812-0101-1100 MAIN-BEAM(SGCC T=2.0mm)(VM60P HDTV10A) ASS'Y ʳ 1 ʳ

1925-1000-3700 CUSHION-TOP-LEFT(VM60P HDTV10A) ʳ 1 ʳ

1925-1000-3710 CUSHION-TOP-RIGHT(VM60P HDTV10A) ʳ 1 ʳ

1925-1000-3720 CUSHION-BOTTOM-LEFT(VM60P HDTV10A) ʳ 1 ʳ

1925-1000-3730 CUSHION-BOTTOM-RIGHT(VM60P HDTV10A) ʳ 1 ʳ

1925-1000-3740 CUSHION-TOP-MIDDLE(VM60P HDTV10A) ʳ 1 ʳ

1925-1100-0230 PE BAG 320*230*0.04T ʳ 1 ʳ

1925-1100-0280 PE BAG (180W*290L*0.04t)(PE-LD)(ACC.-1) ʳ 1 ʳ

1925-1100-0430 PE BAG (70.0*100.0*0.04t) (No,#3) ʳ 1 ʳ

1925-1100-0670 PE BAG (120.0*170.0*0.04t)(No.#6) ʳ 1 ʳ

1925-1100-2360

1925-1200-7080 ACCESSARY BOX (330W*230D*50H) ʳ 1 ʳ

1925-1200-9240 BOTTOM-CARTON (VM60P HDTV10A) ʳ 1 ʳ

1925-1200-9250 INSIDE-SUPPORT (VM60P HDTV10A) ʳ 2 ʳ

1925-1200-9471 CARTON VIZIO VM60P HDTV10A ʳ 1 ʳ

1925-1200-9521 CARTON TOP TRAY VIZIO(VM60P HDTV10A) ʳ 1 ʳ

1925-1300-7080 Brochure VIZIO Series ʳ 1 ʳ

1925-1300-8100 QSG VIZIO VM60P HDTV10A ʳ 1 ʳ

1925-1300-8110 MANUAL VIZIO VM60P HDTV10A ʳ 1 ʳ

1925-1400-2710 Register CARD/VIZIO L15 ʳ 1 ʳ

1925-1900-0610 CARTON JOINT (TM-32V) ʳ 14 ʳ

1925-2000-0030 Polishing Cloth VIZIO P42 HDTV10A ʳ 1 ʳ

PE BAG (1600W*1100L*1.0T) Λ (VM60P HDTV10A)

C193,C194,C200,

6 ʳ

C202,C206,C209

ZD2, ZD3,

4 ʳ

ZD4,ZD5

D10,D11,D12,

ʳʳ

D2,D3, D4,D5

ʳ 1 ʳ

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Page 11-1

PART NO DESCRIPTION LOC QTY REMARK

1936-1100-8980 B/C LBL VIZIO VM60P HDTV10A ʳ 1 ʳ

1936-1300-1550 SERIAL NO.LBL byd:sign ʳ 1 ʳ

1936-1600-1250 Technology Logo LBL VIZIO VM60P HDTV10A ʳ 1 ʳ

1947-1200-0310

1947-1200-0400

1947-1200-0730

1947-1200-3020

1947-1500-1360 PANEL-CUSHION-H(8*8*1364,PORON)(VM60P HDTV10A) ʳ 2 ʳ

1947-1500-1370 PANEL-CUSHION-V(8*8*777,PORON)(VM60P HDTV10A) ʳ 2 ʳ

1947-1500-3200 SPEAKER BKT SPONGE(40*15*1.5)(VM60P HDTV10A) ʳ 12 ʳ

1947-1500-3210 LOGO SPONGE(40*20*2.5)(VM60P HDTV10A) ʳ 3 ʳ

1947-1500-3240 FAN-SPONGE(VM60P HDTV10A) ʳ 2 ʳ

1947-1500-3260 FAN-SPONGE-A(PORON MO-48)(VM60P) ʳ 4 ʳ

1947-1800-0050 GASKET BLOCK (20*3*12mm) (850GT) ʳ 1 ʳ

1947-1800-0290 GASKET BLOCK (12L*10W*1.5Hmm) HOLE 6 ij ʳ 1 ʳ

1947-1800-1230 Conductive Fabric Tape_T (1382.0L*29.0W)(VM60P HDTV1 ʳ 1 ʳ

1947-1800-1240 Conductive Fabric Tape_L (777.0L*35.5W)(VM60P HDTV10 ʳ 1 ʳ

1947-1800-1250 Conductive Fabric Tape_R (777.0L*35.5W)(VM60P HDTV10 ʳ 1 ʳ

1947-1800-1290 Conductive Fabric Tape-B(1382L*48W)(VM60P HDTV10A) ʳ 1 ʳ

1947-2000-1230 FOOT(PINGOO GL-6-B)(VM60P HDTV10A) ʳ 6 ʳ

1947-2600-0020 BASE-ACRYLIC(T=4.0Cm)(VM60P HDTV10A) ʳ 1 ʳ

1947-9900-0660 Glue, 94 Primer (for Face Plate) (M16) ʳ 0.02 ʳ

1947-9900-0770 Teflon Tape (110.0L*10.0W) ʳ 0.11 ʳ

3860-0012-0137 PDP AUDIO BD ASS'Y VM60P HDTV10A) ʳ 1 ʳ

3860-0012-0146 CONNECTOR BD ASS'Y (VM60P HDTV10A) ʳ 1 ʳ

3860-0012-0187 VIDEO BOX BD ASS'Y (VM60P HDTV10A) ʳ 1 ʳ

3860-0012-0189 IR BD ASS'Y (VM60P HDTV10A) ʳ 1 ʳ

3860-0022-0395 REFLECTOR BOX ASS'Y (VM60P HDTV10A) ʳ 1 ʳ

3860-0032-0150 MAIN BD ASS'Y (VM60P HDTV10A) ʳ 1 ʳ

3860-0042-0156 DISPLAY BD ASS'Y (VM60P HDTV10A) ʳ 1 ʳ

ACETATE CLOTH TAPE ( ᔩᎨؒᓄ൅ ) 27*75mm

ACETATE CLOTH TAPE ( ᔩᎨؒᓄ൅ ) 20*45mm

ACETATE CLOTH TAPE ( ᔩᎨؒᓄ൅ ) 25*50mm

ACETATE CLOTH TAPE ( ᔩᎨؒᓄ൅ ) 100x35mm

ʳ 2 ʳ

ʳ 6 ʳ

ʳ 2 ʳ

ʳ 3 ʳ

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Chapter 12 Complete Parts List

2860-8500-1053 60'' PDP VM60P HDTV10A(LG,BLACK) Vinc

ITEM M/S LOCATION PART NO. DESCRPTION

1 3860-0022-0301 PDP BASE ASS'Y VM60P HDTV10A 1

2 3860-0022-0303 PDP CHASSIS ASS'Y VM60P HDTV10A (LG) Black 1

3 3860-0022-0312 PDP PACKING ASS'Y VM60P HDTV10A 1

QTY

REMARK

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ʳ