Vizio L30WGU, LCD-TFTL30WGU Schematic
Service Manual
Model #: VIZIO L30WGU
V, Inc
320A Kalmus Drive Costa Mesa, CA 92626
TEL : +714-668-0588 FAX :+714-668-9099
Top Confidential
Table of Contents
CONTENTS PAGE
Sections
1. Features 1-1
2. Specifications 2-1
3. On Screen Display 3-1
4. Factory Preset Timings
5. Pin Assignment
4-1
5-1
6. BLOCK DIAGRAM 6-1
7. Main Board I/O Connections 7-1
8. Theory of Circuit Operation 8-1
9. Waveforms 9-1
10. Trouble Shooting 10-1
11. Spare Parts List 11-1
12. Complete Parts List 12-1
Appendix
1. Main Board Circuit Diagram
2. Main Board PCB Layout
3. Assembly Explosion Drawing
Block Diagram
VIZIO L30WGU Service Manual
VINC Service Manual
VIZIO L30WGU
COPYRIGHT © 2000 V, INC. ALL RIGHTS RESERVED.
IBM and IBM products are registered trademarks of International Business Machines
Corporation.
Macintosh and Power Macintosh are registered trademarks of Apple Computer, Inc.
VINC and VINC products are registered trademarks of V, Inc.
VESA, EDID, DPMS and DDC are registered trademarks of Video Electronics Standards
Association (VESA).
Energy Star is a registered trademark of the US Environmental Protection Agency (EPA).
No part of this document may be copied, reproduced or transmitted by any means for any
purpose without prior written permission from VINC.
FCC INFORMATION
This equipment has been tested and found to comply with the limits of a Class B digital device,
pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable
protection against harmful interference in a residential installation. This equipment generates,
uses and can radiate radio frequency energy, and if not installed and used in accordance with
the instructions, may cause harmful interference to radio communications. However, there is
no guarantee that the interference will not occur in a particular installation. If this equipment
does cause unacceptable interference to radio or television reception, which can be
determined by turning the equipment off and on, the user is encouraged to try to correct the
interference by one or more of the following measures -- reorient or relocate the receiving
antenna; increase the separation between equipment and receiver; or connect the into an
outlet on a circuit different from that to which the receiver is connected.
FCC WARNING
To assure continued FCC compliance, the user must use a grounded power supply cord and
the provided shielded video interface cable with bonded ferrite cores. Also, any unauthorized
changes or modifications to Amtrak products will void the user’s authority to operate this
device. Thus VINC Will not be held responsible for the product and its safety.
CE CERTIFICATION
This device complies with the requirements of the EEC directive 89/336/EEC with regard to
“Electromagnetic compatibility.”
SAFETY CAUTION
Use a power cable that is properly grounded. Always use the AC cords as follows – USA (UL);
Canada (CSA); Germany (VDE); Switzerland (SEV); Britain (BASEC/BS); Japan (Electric
Appliance Control Act); or an AC cord that meets the local safety standards.
VIZIO L30WGU Service Manual
Chapter 1 Features
1. Built in TV channel selector for TV viewing
2. Simulatnueous display of PC and TV images
3. Connectable to PC’s analog RGB port and digital port
4. Connectable to digital port HDCP
4. Built in s-video, HDTV, composite video and TV out
5. Built in auto adjust function for automatic adjument of screen display
6. Smoothing function enables display of smooth texts and graphics even if image
withresolution lower than 1280x768 is magnified
7. Picture In Picture (PIP) funtion to show TV or VCR images
8. Power saving to reduce consumption power too less than 3W
9. On Screen Display: user can define display mode (ie color, brightness, contrast,
sharpness), sound setting, PIP, TV channel program, aspect and gamma or
reset to factory setting.
CONFIDENTIAL – DO NOT COPY
Page 1-1
File No. SG-0156
Chapter 2 Specification
1. LCD CHARACTERISTICS
Type: WXGA TFT LCD
Size: 30 inch
Active Screen Size: 29.53 inches
Outline Dimension: 683.6(H) x 431.8(V) x 41.6(D)
Display Area: 643.20 (H) x 385.92(V)
Pixel Format: 1280 horiz. By 768 vert. Pixels RGB strip arrangement
Display Color: 16.7M colors
Luminance, White: 600 cd/m
2 (Typ)
Power Consumption: 6.6Watt (Typ.)
Weight 5000 g (Typ.)
Display Operating Mode: Transmissive mode, normally Black
Surface Treatment: Hard coating (2H), Anti-glare treatment of the front polarizer,
2. OPTICAL CHARACTERISTICS
2-1. Viewing Angle by Contrast Ratio °Ÿ 10
Left: 85°typ.
Right: 85°typ.
Top: 85°typ.
Bottom: 85°typ.
3. SIGNAL (Refer to the Timing Chart)
3-1. Sync Signal
(1) Type: TMDS
(2) Input Voltage Level: 90~240 Vac, 50/ 60 Hz
(3) Input Impedance: 50£[/ Signal line
3-2. Operating Frequency
RGB Signal: H: support to 30K~70KHz
V: support to 50~85Hz
Pixel Clock: support to 110MHz
DVI Signal: H: support to 30K~80KHz
V: support to 50~85Hz
Pixel Clock: support to 110MHz
CONFIDENTIAL – DO NOT COPY
Page 2-1
File No. SG-0156
S-Video Video (Y): Analog 0.1Vp-p/75Ω
Video (C): Analog 0.286p-p/75Ω
Component signal: YCbCr
H: 15.734KHz V: 60Hz (NTSC-interlace)
H: 31KHz V: 60Hz (NTSC-progressive)
YPbPr
H: 15.734KHz V: 60Hz (NTSC-480i)
H: 31KHz V: 60Hz(NTSC-480p)
H: 45KHz V: 60Hz(NTSC-720p)
H: 33KHz V: 60Hz(NTSC-1080i)
Composite Video signal: H: 15.734KHz V: 60Hz (NTSC)
F-Type TV RF signal: H: 15.734KHz V: 60Hz (NTSC)
Audio Signal: Frequency Response: 250 Hz-20KHz
4.Input Connectors
a. RJ11 (For RS232 Controls)
b. 24-pin DVI (For DVI/HDCP input)
c. RCA x2 ((For DVI/HDCP input)
d. D-sub 15pin x 1 (For Analog RGB)
e.Mini Jack (L,R) x 1 (For PC analog Audio input)
f. YPbPr RCA x 3 (For HDTV input)
g. YCbCr RCA x 3 (For DVD input)
h. S-Video 4pin DIN x 1
i. RCA x3 (For CVBS A/V input#1)
j. RCA x 3(For CVBS A/V input#2)
k. F-terminal RF
l. CVBS RCA x 3 (For CVBS A/V output)
5. POWER SUPPLY
Consumption: 170W MAX
DPM Mode Not Active OFF: less than 3 W Low (20%)
Power OFF: to less than 3W
CONFIDENTIAL – DO NOT COPY
Page 2-2
File No. SG-0156
6.Speaker
Output 8Ω/5W (max) X2
7. ENVIRONMENT
Operating
a. Temperature: 5~35℃
b. Relative humidity: 10~90%
c. Altitude: 0~10,000ft
Non-operating
a. Temperature: -20~50℃
b. Relative humidity: 10~90%
c. Altitude: 0~40,0000ft
8. DIMENSIONS (with TILT/SWIVEL)
GATEWAY VERSION
a. Height: 601.1mm
b. Width: 740.0mm
c. Depth: 198.0mm
Wynn version
a. Height: 522.0mm
b. Width: 740.0mm
c. Depth: 100.5mm
9. WEIGHT (with TILT/SWIVEL)
GATEWAY version
a. Net: 19.1kgs
b. Gross: 25.8kgs
Wynn version
a. Net: 14.1kgs
b. Gross: 20.8kgs
CONFIDENTIAL – DO NOT COPY
Page 2-3
File No. SG-0156
Chapter 3 On Screen Display
Main unit button
Power
Source
MENU
PROG ▲
PROG ▼
Sound +
Sound -
Auto
OSD Adjustment
1. PC Analog
A. Picture:
a. Brightness
b. Contrast
c. Auto picture
d. Manual picture:
e. Sharpness: 1~5
f. Color Temp (User, 9300k, 6500k, 5000k)
B. Audio:
a. Volume
1. V position
2. H size
3. H position
4. Fine tune
1. R (Red setting) (0~100)
2. G (Green setting) (0~100)
3. B (Blue setting) (0~100)
b. Treble
c. Bass
d. Balance
e. Spatial
CONFIDENTIAL – DO NOT COPY
Page 3-1
File No. SG-0156
C. Setup:
a. Language (English, France, Spain)
b. Gamma (Linear, Vivid1, Vivid2, Vivid3)
c. Wide (Panoramic, Widescreen, Zoom, Standard)
d. PiP:
1. Switch (On/Off)
2. Style (Off, Small, Large)
3. Pos (Upper left, Upper center, Upper right
Middle left, Middle right, lower left, lower center, lower left)
4. Source (TV, DVD, AV2/S, AV1)
5. PiP TV Channel
e. OSD style (Translucent, Opaque)
f. IR Command Set (A, B, C)
2. PC digital
A. Picture:
a. Brightness
b. Contrast
c. Sharpness
d. Color Temp
B. Audio:
a. Volume
b. Treble
c. Bass
d. Balance
e. Spatial
C. Setup:
User, 5000k, 6500k, 9300k
R (Red setting)
G (Green setting)
B (Blue setting)
a. Language (English, France, Spain)
b. Gamma (Linear, Vivid1, Vivid2, Vivid3)
c. Wide (Panoramic, Widescreen, Zoom, Standard)
d. PiP:
CONFIDENTIAL – DO NOT COPY
Page 3-2
File No. SG-0156
1. Switch (On/Off)
2. Style (Off, Small, Large)
3. Pos (Upper left, Upper center, Upper right
Middle left, Middle right, lower left, lower center, lower left)
4. Source (TV, DVD, AV2/S, AV1,)
5. PiP TV Channel
e. OSD style (Translucent, Opaque)
f . IR Command Set (A, B, C)
3.AV2/S, AV1, DVD, HDTV Mode
A. Video:
a. Brightness
b. Contrast
c. Color
d. Tint
e. Sharpness (1~5)
f. Color Temp (normal, Warm, Cool)
g. Noise Reduct
B. Audio:
a. Volume
b. Treble
c. Bass
d. Balance
e. Spatial
C. Setup:
a. Language (English, France, Spain)
b. Gamma (Linear, Vivid1, Vivid2, Vivid3)
c. Wide (Panoramic, Widescreen, Zoom, Standard)
d. PiP:
1. Switch (On/Off)
2. Style (Off, Small, Large)
3. Pos (Upper left, Upper center, Upper right
Middle left, Middle right, lower left, lower center, lower left)
4. Source (TV, DVD, AV2/S, AV1)
5. PiP TV Channel
e. OSD style (Translucent, Opaque)
f . IR Command Set (A, B, C)
CONFIDENTIAL – DO NOT COPY
Page 3-3
File No. SG-0156
4. TV
A. Video:
a. Brightness
b. Contrast
c. Color
d. Tint
e. Sharpness
f. Color Temp (normal, Warm, Cool)
g. Noise Reduct
B. Audio:
a. Volume
b. Treble
c. Bass
d. Balance
e. Spatial
f. MTS (Mono, Stereo, SAP)
C. TV:
a. Source (Antenna, Cable)
b. Cable mode (auto, std, Hrc, irc)
c. Channel scan
d. CC Mode (CC1, CC2 Text1, Text2)
e. Parental Control
1. Change password (New password, Confirm password)
2. Setup TV Blocking
3. Setup Movie Blocking
4. Blocking Enable (On/Off)
5. Key Lockout (On, Off, All, All but power)
6. IR Lockout (On/Off)
7. Factory reset (Yes/No)
D. Setup:
a. Language (English, France, Spain)
b. Gamma (Vivid1, Vivid2, Vivid3 and liner)
c. Wide (Panoramic, Widescreen, Zoom and Standard)
d. PiP
1. Switch (On/Off)
2. Style (Off, Small, Large)
3. Pos (Upper left, Upper center, Upper right
CONFIDENTIAL – DO NOT COPY
Page 3-4
File No. SG-0156
Middle left, Middle right, lower left, lower center, lower left)
4. Source (TV, DVD, AV2/S, AV1)
5. PiP TV Channel
e. OSD style (Translucent, Opaque)
f . IR Command Set (A, B, C)
CONFIDENTIAL – DO NOT COPY
Page 3-5
File No. SG-0156
Chapter 4 Factory preset timings
This timing chart is already preset for the TFT LCD analog & digital display monitors.
Resolution Refresh rate
Horizontal
Frequency
640x480 60Hz 31.5kHz 59.94Hz N N 25.175
640x480 75Hz 37.5kHz 75.00Hz N N 31.500
800X600 60Hz 37.9kHz 60.317Hz P P 40.000
800x600 75Hz 46.9kHz 75.00Hz P P 49.500
800X600 85Hz 53.7kHz 85.06Hz P P 56.250
1024x768 60Hz 48.4kHz 60.01Hz N N 65.000
1024X768 75Hz 60.0kHz 75.03Hz P P 78.750
720x400 70Hz 31.46kHz 70.08Hz N P 28.320
1280x768 60Hz 47.98kHz 59.83Hz P N 81.000
1280x768 75Hz 60.15kHz 75.00Hz P N 102.977
Remark: P: positive N: negative
Vertical
Frequency
Horizontal
Polarity
Vertical
Polarity
Pixel
Rate
Native Resolution
Mode No Resolution
Refresh
Rate
(Hz) (K Hz) (Hz) (TTL) (TTL) (MHz)
9 1280x768 60 47.98 59.83 - + 81MHz
10 1280x768 75 60.15 75.00 - + 102.977MHz
Horizontal
Frequency
Vertical
Frequency
Vertical
Sync
Polarity
Horizontal
Sync
Polarity
Dot rate
CONFIDENTIAL – DO NOT COPY
File No. SG-0156
Page 4-1
Chapter 5 Pin Assignment
The TFT LCD analog display monitors use a 15 Pin Mini D-Sub connector as
video input source.
Pin Description
1 Red
2 Green
3 Blue
4 Ground
5 Ground
6 R-Ground
7 G-Ground
8 B-Ground
9 +5V for DDC
10 Ground
11 No Connection
12 (SDA)
13 H-Sync (Composite Sync)
14 V-Sync
15 (SCL)
1
5
106
CONFIDENTIAL – DO NOT COPY
11
15
Page 5-1
File No. SG-0156
The TFT LCD digital display monitors use a 24 Pin DVI_D connector as video
input source.
Pin Description
1 TMDS negative differential input, channel 2
2 TMDS positive differential input, channel 2
3 Logic Ground
4 Reserved. No connection
5 Reserved. No connection
6 DDC2B Clock
7 DDC2B Data
8 Reserved. No connection
9 TMDS negative differential input, channel 1
10 TMDS positive differential input, channel 1
11 Logic Ground
12 Reserved. No connection
13 Reserved. No connection
14 Power
15 Logic Ground
16 SENSE Pin, Pull High
17 TMDS negative differential input, channel 0
18 TMDS positive differential input, channel 0
19 Logic Ground
20 Reserved. No connection
21 Reserved. No connection
22 Logic Ground
23 TMDS positive differential input, reference clock
24 TMDS negative differential input, reference clock
CONFIDENTIAL – DO NOT COPY
Page 5-2
File No. SG-0145
Four-Pin mini DIN S-Video Connector
Signal Level Video (Y) : Analog 0.1Vp-p/75Ω
Video (C) : Analog 0.286p-p/75
Sync (H+V) : 0.3V below Video (Y)
Frequency H: 15.734Khz V: 60HZ (NTSC)
Video Output Connector
Signal Level Video (Y+C) : Analog 0.7Vp-p/75Ω
Sync (H+V): 0.3V below Video (Y+C)
RGB Signal
a. Sync Type TTL (Separate / Composite) or Sync. On Green
b. Sync polarity Positive or Negative
c. Video Amplitude RGB: 0.7 Vp-p
d. Frequency H: support to 30k~70kHZ
V: support to 50~85MHZ
Audio Signal:
a. Signal Level 1Vrms
b. Frequency Response 250HZ – 20kHZ
CONFIDENTIAL – DO NOT COPY
Page 5-3
File No. SG-0145
Component Signal
Ycbcr
a. Frequency H: 15.734kHZ V: 60HZ (NTSC-interlace)
H: 31kHZ V: 60HZ (NTSC-progressive)
b. Signal level Y: 1Vp-p Cb: ±0.350Vp-p Cr: ±0.350Vp-p
c. Impedance 75Ω
Ypbpr
a. Frequency H: 15.764kHZ V: 60HZ (NTSC-480i)
H: 31kHZ V: 60HZ (NTSC-480p)
H: 45kHZ V: 60HZ(NTSC-720p)
H: 33kHZ V: 60HZ(NTSC-1080i)
b. Signal level Y: 1Vp-p pb±0.350Vp-p pr: ±0.350Vp-p
c. Impedance 75Ω
CONFIDENTIAL – DO NOT COPY
Page 5-4
File No. SG-0145
Chapter 6 Block Diagram
System Block Diagram
30” WXGA panel
Digital
AC IN Video bus
Power Board
DC 12V Speakers
□□□□□
W6 W5 JT2
W3 Main Board
W4
W9 W1 JT3 JT11 JT10 JT8 JT5
Keypad/IR
Board DVI D-Sub Audio YPbPr YCbCr S-Video AV1/AV2 RF
The monitor’s system block diagram is powered by power board that transforms AC source of
100V~240V AC +/- 10% @ 50/60 HZ into DC 12V & 24Vsource. The DC source supplies three
important parts of the system block diagram. They are the main board, and 30” WXGA panel unit.
The main board receives different types of video signal. Afterward, the main board process the signals
control the various functions of the monitor and outputs control signal, video signal and power to the
30” WXGA panel to be displayed.
The inverter first processes the power send to the panel. The function of the inverter is to step up the
voltage supplied by the main board to the power that is needed to light up the lamps in the panel.
Simultaneously, the digital video signals are processed in the panel and the outcome determines the
brightness, pixel on/off and the color displayed on the panel.
CONFIDENTIAL – DO NOT COPY
File No. SG-0156
Page 6-1
CONFIDENTIAL – DO NOT COPY
Page 6-2
File No. SG-0145
The function of the Main board is to receive different types of video and audio signal in to
compatible digital video and audio format.
The FQ1236-MK3 tuner processes the TV antenna and the cable into analog signal.
The audio signal exiting from FQ1236-MK3 is further processed by MSP3440G. The purpose
is to process the input IF signal into AF signal and control TV sound signal features like
volume, bass, treble and balance. The processing procedure conforms to standard
recommend for Broadcast Television System Committee (BTSC).
The analog video signals of S-video, YPbPr, TV and A/V signals travel directly to video
decoder. At the decoder, all signals are translated from analog signals into compatible digital
signal which will be ultimately be processed by theVP3230 & SAA7118.
After the video signal has been converted into digital signals, the digital video signal is
de-interlaced by FLI3210. The de-interlace processor automatically determines and
de-interlace the incoming video content – static or motion and applies different algorithm to
each of the content type. An external SDRAM is used to help store the video fields and
motion video data processed in FLI3210. More over, the internal memory controller in
FLI3210 controls the external SDRAM. What’s more, FLI3210 offer programmable functions
like video enhancement and PIP (picture in picture). PIP functions by activating the primary
and secondary port simultaneously. In short, FLI3210 output (display port) digital signals up
to 74 Mpixel/sec to the PW166B generate the vertical and horizontal timing signals for
display device.
All functions are controllable by the main board. Plus, all functions in the IC boards are
programmable using I2C Bus.
CONFIDENTIAL – DO NOT COPY
Page 6-3
File No. SG-0145
Chapter 7 Main Board I/o Connections
W3 CONNECTION (TOP→BOTTOM) "OSD CONTROL
Pin Description
1 “Auto”
2 “Left”
3 “Right”
4 “Down”
5 “Gnd”
6 “Up”
7 “Menu”
8 “Source”
W4 CONNECTION (TOP→BOTTOM)
Pin Description
1 “Power”
2 “U17”
3 “V50”
4 “Gnd”
5 “Vpcon”
W6 CONNECTION (TOP→BOTTOM)
Pin Description
1 “V120dc”
2 “V120dc”
3 “V120dc”
4 “Gnd”
5 “Gnd”
6 “Gnd”
7 “Bk_Light”
8 “Pwm_p”
CONFIDENTIAL – DO NOT COPY
Page 7-1
File No. SG-0156
Chapter 8 Theory of Circuit Operation
The operation of D-SUB 15pin route
The D-SUB 15pin is input analog signal into the video switch M61323fp. Then, the signal is process
to the A/D converter (ADC9883) and output to the pw166B; the pw166B generates the vertical and
horizontal timing signals for display device.
The operation of DVI & HDCP CON route
The DVI & HDCP CON is input digital signal the signal is process to the sil169. Then transfer to the
pw166B, the pw166B generates the vertical and horizontal timing signals for display device.
The operation of HDTV & DVD route
HDTV & DVD signal is transfer to video switch M61323fp, the M61323fp can to determine signal
witch one signal is to the VP3230 (decoder) and witch one is to ADC9883. When signal transfer for
the VP3230 (decoder) and output to FLI2310 (de-interlace) then transfer the pw166B generates the
vertical and horizontal timing signals for display device. When signal to the ADC9883 then output to
pw166B generates the vertical and horizontal timing signals for display device. The pip mode is
signal to saa7118 (decoder) then transfer to the pw166B generates the vertical and horizontal timing
signals for display device.
The operation of S-Video route
The S-Video signal is input to TA1218N (switch) then transfer signal to VP3230 (decoder) and output
to FLI2310 (de-interlace) then use graphic port transfer signal to pw166B generates the vertical and
horizontal timing signals for display device. The pip mode is signal to saa7118 (decoder) then
transfer to the pw166B generates the vertical and horizontal timing signals for display device.
The operation of Video 1,2 route
Video 1,2 signal input to TA1218N (switch) and transfer signal to VP3230 (decoder) and output to
FLI2310 (de-interlace), then transfer to the pw166B generates the vertical and horizontal timing
signals for display device. The pip mode is transfer to saa7118 (decoder) then transfer to the
pw166B generates the vertical and horizontal timing signals for display device.
The operation of TV route
TV signal is processes to the tuner and output to TA1218N (switch) then transfer to VP3230
(decoder) and output toFLI2310 (de-interlace) then transfer to pw166B generates the vertical and
horizontal timing signals for display device. The pip mode is signal to saa7118 (decoder) then
transfer to the pw166B generates the vertical and horizontal timing signals for display device.
CONFIDENTIAL – DO NOT COPY
File No. SG-0156
Page 8-1
The operation of keypad
There are 8 keys to control and select the function of SHD-3010 and also have two LED to indicate
the status of operation. They are “power, Source, MENU, ▼▲, + -, Auto” keys and LED.
1. The power key through POW and GND to control PW166B, PW166B will receive a low signal to
turn on or off system while press the power key.
2. The other seven keys are on high state because the pull up resistor but will transit to low state
dependent on which key pressed, and the state will be reader by PW166B through D0 to D6 to act
corresponding function.
3. The LED is constructed with two separate LED which color is blue and Green. The PW166B direct
control the LED’s when PW166B (VPCON) is low the LED is Green (Close power) when PW166B
(VPCON) is high the LED is Orange (Open power).
The operation of Analog port
The analog port are consisted with 15 pins mini D-Sub connector which receiving video signal from
host device, EEPROM which compliance with DDC1/DDC2B protocol, H-sync and V-sync detecting
circuit which regenerate synchronous signal for PW166B detecting, video signal matching circuit and
AD9883A which capturing RGB graphics signal and digitize each pixel.
The pin assignment of 15 pins connector are as follows：
Pin No. Pin Name Description
1 GRAI Red signal
2 GGAI Green signal
3 GBAI Blue signal
4 GND Ground
5 GND Ground
6 GND R-Ground
7 GND G-Ground
8 GND B-Ground
9 +5V For DDC
10 GND Ground
11 X No connection
12 RGSA SDA
13 GHSI H-Sync
14 RVSI V-Sync
15 RGSL SCL
CONFIDENTIAL – DO NOT COPY
Page 8-2
File No. SG-0156
RGB graphics signal of host device transmits to the analog port through pin 1 to 3. The video signal
should be coupled to RIN, GIN, BIN and SOGIN of AD9883A through C78, C75, C74 and C76. The
EDID data is stored in EEPROM (24LC21) which compliance with DDC1/DDC2B protocol that
performs a plug and play function. When in DDC1 protocol the host device access the EDID data
through RVSI (pin14) and RGSA (pin12) while RGSL (pin15) is held high. But in DDC2B protocol the
host device access EDID data through RGSA (pin12) and RGSL (pin15). The SCL, SDA should be
pull up through R28 R27 and are voltage limitation through D9, D8, and D5, which will limit to 5 volts.
The PW166B let PORTA3 (ADCEN) to low state that will let FST3125 (U8C) to output GHS signal
which are derived from AD9883A pin65 SOGOUT. When PW166B detects exact GHS and GVS
timing it will configure the registers of AD9883A to satisfy the operation through SCL and SDA of IIC
bus. Oppositely while PW166B let PORTB3 (DVI_ON) to high state it means that the analog port is
disable, and should be in digital interface mode. While PW166B let PORTA6 (INSEL) PORTB4
(COMP_SEL) to High state it means that the YPbPr is disable, and DVD is enable. AD9883A is 8-bit
140 Msps monolithic analog interface for capturing RGB graphics signals from personal computers
and workstations. It includes +1.25V reference, PLL to generate a pixel clock from Hsync, and
programmable gain, offset, and clamp circuits.
The function block of AD9883A is as follows:
CONFIDENTIAL – DO NOT COPY
Page 8-3
File No. SG-0156
If user changes to analog mode or analog port is resignaled from host device then PW166B will let
PORTA6 (INSEL) to Low state that enables H-Sync, V-Sync, from AD9883A. The PW166B will
changes the power mode PLL divide ratio, clock phase VCO range and charge pump current etc.
that depends on the timing of GHS and GVS. The action should be fulfilled through SDA and SCL of
IIC bus to change the data of control registers of AD9883A. The PLL derives a master clock from an
incoming H-Sync signal. The master clock frequency is then divided by an integer value, and the
divider’s output is phase-locked to H-Sync. The PLL characteristics are determined by the loop filter
design, which controlled by PLL charge pump current (CURRENT) and VCO range setting
(VCORNGE).
The value of VCO range and charge pump current is as follows:
PV1 PV0
Pixel Clock
Range (MHz)
0 0 12–36 150
KVCO Gain
(MHz/V)
Mode
Inputs
Power-
Down1
Sync
Powered On or
Detect2
Comments
0 1 36–72 150
0 0 72–110 150
Ip2 Ip1 Ip0 Current (µA)
0 0 0 50
0 0 1 100
0 1 0 150
0 1 1 250
1 0 0 350
1 0 1 500
1 1 0 750
1 1 1 1500
Full-Power 1 1 Everything
Serial Bus, Sync
Seek Mode 1 0
Power-Down 0 X
Activity Detect, SOG,
Band gap Reference
Serial Bus, Sync
Activity Detect, SOG,
Band gap Reference
If we adjust contrast or brightness of analog port then the input gain or input offset should be
modified through IIC bus.
The power of AD9883A is supplied 3-3V. We can management the power of AD9883A through the
register of itself. The H-Sync input is used as a reference to generate the pixel-sampling clock. A
5-bit value (PHASE) adjust the sampling phase in 32 steps across one pixel time, so it generate a
stable timing relationship between HSOUT and DATACK to digitize the captured analog RGB data.
The output data is aligned to the leading edge of HSOUT. If the signal of sync on green is detected
by SOGIN then the SOGOUT will produce a digital composite sync.
CONFIDENTIAL – DO NOT COPY
File No. SG-0156
Page 8-4
DVI_D Interface
The SiI169 Receiver uses Panel Link Digital technology to support HDTV and high-resolution digital
displays for DTV and PC applications. It features High-bandwidth Digital Content Protection
(HDCP) for secure delivery of high-definition video in consumer electronics products.
The SiI 169 is a DVI 1.0 compliant digital-output receiver with built-in High-bandwidth Digital Content
Protection (HDCP). It provides a simple, cost effective solution for DTVs implementing DVI-HDCP.
Pre-programmed HDCP keys simplify manufacturing while providing the highest level of security.
There is no need to use encrypted keys, program EPROM’s, or cure epoxy coating.
the functional blocks of the chip .
Panel Link TMDS Core
The Panel Link TMDS core accepts as inputs the three TMDS differential data lines and the
differential clock. The core senses the signals on the link and properly decodes them providing
accurate pixel data. The core outputs the necessary sync signals (HSYNC, VSYNC), clock (ODCK),
and a display enable (DE) signal that drives high when video pixel data is present. The SCDT signal
is output when there is active video on the DVI link and the PLL has locked on to the video. SCDT
can be used to trigger external circuitry, indicating that an active video signal is present; or used to
place the device outputs in power down when no signal is present (by tying SCDT to PDO#). A
resistor tied to the EXT_RES pin is used for impedance matching.
CONFIDENTIAL – DO NOT COPY
File No. SG-0156
Page 8-5
HDCP Keys EEPROM
The SiI 169 comes pre-programmed with a production set of HDCP keys in its internal EEPROM. In
this way the keys are provided the highest level of protection as required by the HDCP specification.
Silicon Image manages all aspects of the key purchasing and programming. There is no need for the
customer to purchase HDCP keys from the licensing authority. For security reasons, the keys cannot
be read out of the device.
Samples of the SiI 169 are available with the B1 public keys as listed in the back of the HDCP
specification. These are marked with a -PUB part number as noted in the Ordering Information
section. Make sure to request either “Public” or “Production” keys when requesting samples. Before
receiving samples of the SiI 169 with production keys a customer must have signed the HDCP
license agreement.
HDCP Operation
The SiI 169 supports High-bandwidth Digital Content Protection (HDCP) by decrypting the pixel data
stream received from an HDCP transmitter in the video host system. HDCP provides a secure
method of delivering high definition content between a host (such as a set-top box, DVD player, or
D-VHS player) and display (such as an HDTV, projector, or A/V receiver).
The authentication process involves exchanging calculated values based on the keys and KSV. A
software driver running on the host controls the exchange of these values between the host
transmitter (SiI 170B) and the receiver (SiI 169) in the display device. The KSV and two other values,
An and Ri, are exchanged over the DDC channel (I2C bus) of DVI. The receiver is a slave on this
I2C bus. Figure 14 shows a typical HDCP system configuration.
CONFIDENTIAL – DO NOT COPY
Page 8-6
File No. SG-0156
Loading...