VISHAY TFDU6102 Operation Manual

VISHAY

18102

Vishay Semiconductors

Fast Infrared Transceiver Module (FIR, 4 Mbit/s)
for 2.7 V to 5.5 V Operation

Description

The TFDU6102 is a low-power infrared transceiver
module compliant to the latest IrDA physical layer
standard for fast infrared data communication, sup­porting IrDA speeds up to 4.0 Mbit/s (FIR), and carrier
based remote control modes up to 2 MHz. Integrated
within the transceiver module are a PIN photodiode,
an infrared emitter (IRED), and a low-power CMOS
control IC to provide a total front-end solution in a sin­gle package.

Vishay FIR transceivers are available in different
package options, including this BabyFace package
(TFDU6102). This wide selection provides flexibility
for a variety of applications and space constraints.

The transceivers are capable of directly interfacing
with a wide variety of I/O devices which perform the
modulation/ demodulation function, including
National Semiconductor’s PC87338, PC87108 and
PC87109, SMC’s FDC37C669, FDC37N769 and
CAM35C44, and Hitachi’s SH3. At a minimum, a VCC
bypass capacitor are the only external components
required implementing a complete solution.
TFDU6102 has a tri-state output and is floating in
shut-down mode with a weak pull-up.

Features

• Supply voltage 2.7 V to 5.5 V, Operating idle
current (receive mode) < 3 mA, Shutdown current
< 5 µA over full temperature range

• Surface Mount Package, top and side view,

9.7 mm x 4.7 mm x 4.0 mm

• Operating Temperature - 25 °C to 85 °C

• Storage Temperature - 40 °C to 100 °C

• Transmitter Wavelength typ. 886 nm, supporting

•IrDA

• Remote Control Range > 8 m, typ. 22 m

®

IrDA

and Remote Control

®

compliant, link distance > 1 m, ± 15 °, win­dow losses are allowed to still be inside the IrDA
spec.

• ESD > 4000 V (HBM), Latchup > 200 mA

• EMI immunity > 550 V/m for GSM frequency and
other mobile telephone bands /
(700 MHz to 2000 MHz, no external shield)

• Split power supply, LED can be driven by a
separate power supply not loading the regulated
supply. U.S. Pat. No. 6,157,476

• Tri-state-Receiver Output, floating in shut down
with a weak pull-up

• Eye safety class 1 (IEC60825-1, ed. 2001), limited
LED on-time, LED current is controlled, no single
fault to be considered

Applications

• Notebook Computers, Desktop PCs, Palmtop

Computers (Win CE, Palm PC), PDAs

• Digital Still and Video Cameras

• Printers, Fax Machines, Photocopiers,

Screen Projectors

• Telecommunication Products

(Cellular Phones, Pagers)

• Internet TV Boxes, Video Conferencing Systems

®

• External Infrared Adapters (Dongles)

• Medical and Industrial Data Collection

TFDU6102

Document Number 82550

Rev. 1.3, 16-Oct-03

www.vishay.com

1

TFDU6102

Vishay Semiconductors

Parts Table

Part Description Qty / Reel

TFDU6102-TR3 Oriented in carrier tape for side view surface mounting 1000 pcs

TFDU6102-TT3 Oriented in carrier tape for top view surface mounting 1000 pcs

Functional Block Diagram

Vcc1

Tri-State

Amplifier

Driver

Comparator

Rxd

Vcc2

VISHAY

18468

Pinout

TFDU6102
weight 200 mg

17087

Mode

SD

Txd

"U" Option BabyFace

(Universal)

IRED Detector

12345678

Logic
&

Control

GND

Controlled
Driver

IRED C

Definitions:

In the Vishay transceiver data sheets the following nomenclature is

used for defining the IrDA operating modes:

SIR: 2.4 kbit/s to 115.2 kbit/s, equivalent to the basic serial infrared

standard with the physical layer version IrPhy 1.0

MIR: 576 kbit/s to 1152 kbit/s

FIR: 4 Mbit/s

VFIR: 16 Mbit/s

MIR and FIR were implemented with IrPhy 1.1, followed by IrPhy

1.2, adding the SIR Low Power Standard. IrPhy 1.3 extended the

Low Power Option to MIR and FIR and VFIR was added with IrPhy

1.4.A new version of the standard in any case obsoletes the former

version.

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2

Document Number 82550

Rev. 1.3, 16-Oct-03

VISHAY

Pin Description

Pin Number

"U"

1 V

2 IRED

3 Txd This input is used to transmit serial data when SD is low. An on-chip

4 Rxd Received Data Output, push-pull CMOS driver output capable of driving a

5 SD Shutdown, also used for dynamic mode switching. Setting this pin active

6 V

7 Mode HIGH: High speed mode, MIR and FIR; LOW: Low speed mode, SIR only

7 Mode The mode pin can also be used to indicate the dynamically programmed

8 GND Ground

Function Description I/O Active

CC2

IRED Anode

Cathode

CC1

Connect IRED anode directly to V

external resistor might be necessary for reducing the internal power

An unregulated separate power supply can be used at this pin.

IRED cathode, internally connected to driver transistor

protection circuit disables the LED driver if the Txd pin is asserted for longer
than 80 µs. When used in conjunction with the SD pin, this pin is also used

to receiver speed mode.

standard CMOS or TTL load. No external pull-up or pull-down resistor is

required. Floating with a weak pull-up of 500 kΩ (typ.) in shutdown

places the module into shutdown mode. On the falling edge of this signal,

the state of the Txd pin is sampled and used to set receiver low bandwidth

(Txd = Low, SIR) or high bandwidth

(Txd = High, MIR and FIR) mode. Will be overwritten by the mode pin input,

which must float, when dynamic programming is used.

Supply Voltage

(see chapter "Mode Switching"). Must float, when dynamic programming is

mode. The maximum load is limited to 50 pF. High indicates FIR/MIR-, low

indicates SIR-mode

. For voltages higher than 3.6 V an

CC2

dissipation.

mode.

used.

TFDU6102

Vishay Semiconductors

I HIGH

O LOW

I HIGH

I

O

Document Number 82550

Rev. 1.3, 16-Oct-03

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3

TFDU6102

VISHAY

Vishay Semiconductors

Absolute Maximum Ratings

Reference point Ground Pin 8, unless otherwise noted.
Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.

Parameter Test Conditions Symbol Min Ty p. Max Unit

Supply voltage range,
transceiver

Supply voltage range,
transmitter

Input currents for all pins, except IRED anode

Output sinking current 25 mA

Power dissipation see derating curve, figure 5 P

Junction temperature T

Ambient temperature range
(operating)

Storage temperature range T

Soldering temperature see recommended solder profile

Average output current I

Repetitive pulse output current < 90 µs, ton < 20 % I

IRED anode voltage V

Voltage at all inputs and outputs Vin > V

Load at mode pin when used as
mode indicator

0 V < V

CC2

0 V < V

CC1

pin

(see figure 4)

is allowed V

CC1

< 6 V V

< 6 V V

IRED

IRED

CC1

CC2

D

J

T

amb

stg

(DC) 125 mA

(RP) 600 mA

IREDA

IN

- 0.5 + 6 V

- 0.5 + 6.5 V

10 mA

500 mW

125 °C

- 25 + 85 °C

- 25 + 85 °C

240 °C

- 0.5 + 6.5 V

5.5 V

50 pF

Eye safety information

Reference point Pin: GND unless otherwise noted.
Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.

Parameter Test Conditions Symbol Min Ty p. Max Unit

Virtual source size Method: (1 - 1/e) encircled

Maximum Intensity for Class 1 IEC60825-1 or

*)

Due to the internal limitation measures the device is a "class1" device

**)

IrDA specifies the max. intensity with 500 mW/sr

energy

EN60825-1,
edition Jan. 2001

d 2.5 2.8 mm

I

e

*)

(500)

mW/sr

**)

www.vishay.com

4

Document Number 82550

Rev. 1.3, 16-Oct-03

VISHAY

Vishay Semiconductors

Electrical Characteristics

Transceiver

T

= 25 °C, VCC = 2.7 V to 5.5 V unless otherwise noted.

amb

Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.

Parameter Test Conditions Symbol Min Ty p. Max Unit

Supply voltage V

Supply current (Idle)

Supply current (Idle)

1)

1)

SD = Low, Ee = 0 klx I

SD = Low, Ee = 1 klx

2)

Shutdown supply current SD = High, Mode = Floating

E

= 0 klx

e

SD = High, Mode = Floating

= 1 klx

e

2)

E

SD = High, T = 85 °C,

CC

CC

I

CC

I

SD

I

SD

I

SD

Mode = Floating, not ambient
light sensitive

Operating temperature range T

Output voltage low IOL = 1 mA, C

Output voltage high IOH = 500 µA, C

IOH = 250 µA, C

Output Rxd current limitation

Short to Ground 20 mA

= 15 pF V

load

= 15 pF V

load

= 15 pF V

load

A

OL

OH

OH

high state

Output Rxd current limitation
low state

Rxd to V

impedance SD = High R

CC1

Input voltage low

Short to V

CC1

V

Rxd

IL

(Txd, SD, Mode)

Input voltage high
(Txd, SD, Mode)

Input leakage current

CMOS level

TTL level, V

3)

= 4.5 V V

CC1

V

IH

IH

I

L

(Txd, SD)

Input leakage current
Mode

Input capacitance

I

ICH

C

I

(Txd, SD, Mode)

1)

Receive mode only.

In transmit mode, add additional 85 mA (typ) for IRED current. Add Rxd output current depending on Rxd load.

2)

Standard Illuminant A

3)

The typical threshold level is between 0.5 x V

(VCC = 3 V) and 0.4 x VCC (VCC = 5.5 V) . It is recommended to use the specified

CC2

min/ max values to avoid increased operating current.

2.7 5.5 V

2 3 mA

2 3 mA

- 25 + 85 °C

0.8 x V

CC

0.9 x V

CC

400 500 600 kΩ

- 0.5 0.5 V

VCC - 0.5 VCC + 0.5 V

2.4 V

- 10 + 10 µA

- 2 + 2 µA

TFDU6102

2.0 µA

2.5 µA

5 µA

0.4 V

V

V

20 mA

5 pF

Document Number 82550

Rev. 1.3, 16-Oct-03

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5

TFDU6102

VISHAY

Vishay Semiconductors

Optoelectronic Characteristics

Receiver

T

= 25 °C, VCC = 2.7 V to 5.5 V unless otherwise noted.

amb

Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.

Parameter Test Conditions Symbol Min Ty p. Max Unit

Minimum detection threshold
irradiance, SIR mode

Minimum detection threshold
irradiance, MIR mode

Minimum detection threshold
irradiance, FIR mode

Maximum detection threshold
irradiance

No detection receiver input
irradiance

Rise time of output signal 10 % to 90 %, 15 pF t

Fall time of output signal 90 % to 10 %, 15 pF t

Rxd pulse width of output signal,
50 % SIR mode

Rxd pulse width of output signal,
50 % MIR mode

Rxd pulse width of output signal,
50 % FIR mode

Stochastic jitter, leading edge

Receiver start up time after completion of shutdown

Latency t

Note: All timing data measured with 4 Mbit/s are measured using the IrDA
The data given here are valid 5 µs after starting the preamble.

*)

This parameter reflects the backlight test of the IrDA physical layer specification to guarantee immunity against light from fluorescent

lamps

9.6 kbit/s to 115.2 kbit/s
λ = 850 nm to 900 nm

1.152 Mbit/s
λ = 850 nm to 900 nm

4.0 Mbit/s
λ = 850 nm to 900 nm

λ = 850 nm to 900 nm E

*)

r (Rxd)

f (Rxd)

input pulse length

1.4 µs < P

Wopt

< 25 µs

input pulse length

= 217 ns,

P

Wopt

1.152 Mbit/s

input pulse length

= 125 ns,

P

Wopt

4.0 Mbit/s

input pulse length

= 250 ns,

P

Wopt

4.0 Mbit/s

input irradiance = 100 mW/m2,

4.0 Mbit/s

input irradiance = 100 mW/m2,

1.152 Mbit/s

input irradiance = 100 mW/m2,
576 kbit/s

input irradiance = 100 mW/m2,
≤ 115.2 kbit/s

programming sequence
Power on delay

®

E

e

E

e

E

e

e

E

e

4

(0.4)

10 40 ns

10 40 ns

t

t

t

t

PW

PW

PW

PW

L

1.5 1.8 2.1 µs

110 250 270 ns

100 140 ns

225 275 ns

FIR transmission header.

25

(2.5)

65

(6.5)

80

(8.0)

5

(500)

35

(3.5)

90

(9.0)

mW/m2

(µW/cm

mW/m2

(µW/cm

mW/m2

(µW/cm

kW/m2

(mW/cm

mW/m2

(µW/cm

20 ns

40 ns

80 ns

350 ns

500 µs

170 300 µs

2

)

2

)

2

)

2

)

2

)

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6

Document Number 82550

Rev. 1.3, 16-Oct-03

VISHAY

TFDU6102

Vishay Semiconductors

Transmitter

T

= 25 °C, VCC = 2.7 V to 5.5 V unless otherwise noted.

amb

Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.

Parameter Test Conditions Symbol Min Ty p. Max Unit

IRED operating current,
switched current limiter

Output leakage IRED current I

Output radiant intensity
recommended application
circuit

Output radiant intensity V

Output radiant intensity, angle of
half intensity

Peak - emission wavelength λ

Spectral bandwidth ∆λ 40 nm

Optical rise time, fall time t

Optical output pulse duration input pulse width 217 ns,

Optical overshoot 25 %

*)

Typically the output pulse duration will follow the input pulse duration t and will be identical in length t.

However, at pulse duration larger than 80 µs the optical output pulse duration is limited to 85 µs. This pulse duration limitation can already
start at 20 µs

See derating curve (fig. 5). For

3.3 V operations no external
resistor needed. For 5 V
application that might be
necessary depending on
operating temperature range.

α = 0 °, 15 °
Txd = High, SD = Low,
V

= V

CC2

= 3.3 V

CC1

Internally current-controlled, no
external resistor

= 5.0 V, α = 0 °, 15 °

CC1

Txd = Low or SD = High,
(Receiver is inactive as long as
SD = High)

1.152 Mbit/s

input pulse width 125 ns,

4.0 Mbit/s

input pulse width 250 ns,

4.0 Mbit/s

input pulse width

0.1 µs < t

< 80 µs

Txd

input pulse width t

*)

≥ 80 µs

Txd

I

D

IRED

I

e

I

e

500 550 600 mA

- 1 1 µA

120 170 350 mW/sr

0.04 mW/sr

α ± 24 °

P

, t

ropt

fopt

t

opt

t

opt

t

opt

t

opt

*)

t

opt

880 900 nm

10 40 ns

207 217 227 ns

117 125 133 ns

242 250 258 ns

t

Txd

µs

20 85 µs

Document Number 82550

Rev. 1.3, 16-Oct-03

www.vishay.com

7

TFDU6102

Vishay Semiconductors

VISHAY

Recommended Circuit Diagram

Vishay Semiconductors transceivers integrate a sen­sitive receiver and a built-in power driver. The combi­nation of both needs a careful circuit board layout.
The use of thin, long, resistive and inductive wiring
should be avoided. The inputs (Txd, SD, Mode) and
the output Rxd should be directly (DC) coupled to the
I/O circuit.

V

cc2

V

cc1

GND

Mode

SD

Txd

Rxd

18469

Figure 1. Recommended Application Circuit

The capacitor C1 is buffering the supply voltage and
reduces the influence of the inductance of the power
supply line. This one should be a Tantalum or other
fast capacitor to guarantee the fast rise time of the
IRED current. The resistor R1 is only necessary for

C1

R2

R1

C3

C2

IRED Anode

V

cc

Ground

Mode

SD

Txd

Rxd

IRED C athode

higher operating voltages and elevated temperatures,
see derating curve in figure 5, to avoid too high inter­nal power dissipation.

The capacitors C2 and C3 combined with the resistor
R2 (as the low pass filter) is smoothing the supply
voltage V
dependent on the quality of the supply voltages V
and V

CC2

. R2, C1, C2, and C3 are optional and

CC1

CC1

and injected noise. An unstable power sup­ply with dropping voltage during transmission may
reduce sensitivity (and transmission range) of the
transceiver.The placement of these parts is critical. It
is strongly recommended to position C2 and C3 as
close as possible to the transceiver power supply
pins. An Tantalum capacitor should be used for C1
and C3 while a ceramic capacitor is used for C2.

In addition, when connecting the described circuit to
the power supply, low impedance wiring should be
used.

When extended wiring is used the inductance of the
power supply can cause dynamically a voltage drop
at V

. Often some power supplies are not apply to

CC2

follow the fast current is rise time. In that case another

4.7 µF (type, see table under C1) at V

will be help-

CC2

ful.
Keep in mind that basic RF-design rules for circuit

design should be taken into account. Especially
longer signal lines should not be used without termi­nation. See e.g. "The Art of Electronics" Paul Horow­itz, Wienfield Hill, 1989, Cambridge University Press,
ISBN: 0521370957.

Table 1.
Recommended Application Circuit Components

Component Recommended Value Vishay Part Number

C1, C3 4.7 µF, 16 V 293D 475X9 016B

C2 0.1 µF, Ceramic VJ 1206 Y 104 J XXMT

R1 5 V supply voltage: 2 Ω , 0.25 W ( recommended using

two 1 Ω, 0.125 W resistor in series)

3.3 V supply voltage: no resistors necessary, the internal
controller is able to control the current

R2 47 Ω, 0.125 W CRCW-1206-47R0-F-RT1

www.vishay.com

8

e.g. 2 x CRCW-1206-1R0-F-RT1

Document Number 82550

Rev. 1.3, 16-Oct-03

VISHAY

TFDU6102

Vishay Semiconductors

I/O and Software

In the description, already different I/Os are men­tioned. Different combinations are tested and the
function verified with the special drivers available
from the I/O suppliers. In special cases refer to the I/
O manual, the Vishay application notes, or contact
directly Vishay Sales, Marketing or Application.

Mode Switching

The TFDU6102 is in the SIR mode after power on as
a default mode, therefore the FIR data transfer rate
has to be set by a programming sequence using the
Txd and SD inputs as described below or selected by
setting the Mode Pin. The Mode Pin can be used to
statically set the mode (Mode Pin: LOW: SIR, HIGH:

0.576 Mbit/s to 4.0 Mbit/s). If not used or in standby
mode, the mode input should float or should not be
loaded with more than 50 pF. The low frequency
mode covers speeds up to 115.2 kbit/s. Signals with
higher data rates should be detected in the high fre­quency mode. Lower frequency data can also be
received in the high frequency mode but with reduced
sensitivity.
To switch the transceivers from low frequency mode
to the high frequency mode and vice versa, the pro­gramming sequences described below are required.

Setting to the High Bandwidth Mode (0.576 Mbit/s to 4.0 Mbit/s)

1. Set SD input to logic "HIGH".

2. Set Txd input to logic "HIGH". Wait t

3. Set SD to logic "LOW" (this negative edge latches
state of Txd, which determines speed setting).

≥ 200 ns.

s

4. After waiting t

≥ 200 ns Txd can be set to logic

h

"LOW". The hold time of Txd is limited by the maxi­mum allowed pulse length.

After that Txd is enabled as normal Txd input and the
transceiver is set for the high bandwidth (576 kbit/s to
4 Mbit/s) mode.

Setting to the Lower Bandwidth Mode (2.4 kbit/s to 115.2 kbit/s)

1. Set SD input to logic "HIGH".

2. Set Txd input to logic "LOW". Wait t

3. Set SD to logic "LOW" (this negative edge latches
state of Txd, which determines speed setting).

4. Txd must be held for t

≥ 200 ns.

h

After that Txd is enabled as normal Txd input and the
transceiver is set for the lower bandwidth (9.6 kbit/s to

115.2 kbit/s) mode.

SD/Mode

Txd

50%

Figure 2. Mode Switching Timing Diagram

50%

t

t

s

h

50%

≥ 200 ns.

s

High : FIR

Low : SIR

14873

Table 2.
Truth table

Inputs Outputs

SD Txd

high x x weakly pulled

low high x high I

low high > 80 µs x high 0

low low < 4 high 0

low low > Min. Detection Threshold Irradiance

low low > Max. Detection Threshold Irradiance x 0

Document Number 82550

Rev. 1.3, 16-Oct-03

Optical input Irradiance mW/m

< Max. Detection Threshold Irradiance

2

Rxd Transmitter

(500 kΩ to V

low (active) 0

CC1

)

0

e

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9

TFDU6102

Vishay Semiconductors

Recommended Solder Profile Current Derating Diagram

Figure 4 shows the maximum operating temperature
when the device is operated without external current
limiting resistor. A power dissipating resistor of 2 Ω is
recommended from the cathode of the IRED to
Ground for supply voltages above 4 V. In that case
the device can be operated up to 85 °C, too.

90

85

80

75

70

65

60

Ambient Temperature ( °C)

55

50

2.0 2.5 3.0 3.5 4.0

18097

Operating Voltage [V] @ duty cycle 20%

4.5

°

Temperature ( C )

14874

240

220

200

180

160

140

120

100

80

60

40

20

0

2°C-4°C/s

0 50 100 150 200 250 300 350

2°C-4°C/s

90 s max120 s - 180 s

Time(s)

Figure 3. Recommended Solder Profile

10 s m ax .

@230°C

VISHAY

5.0 5.5 6.0

Figure 4. Temperature Derating Diagram

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10

Document Number 82550

Rev. 1.3, 16-Oct-03

VISHAY

Package Dimensions in mm

TFDU6102

Vishay Semiconductors

2.5

Document Number 82550

Rev. 1.3, 16-Oct-03

7x1=7

0.6

81

1

18470

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11

TFDU6102

Vishay Semiconductors

Reel Dimensions

VISHAY

W

1

Reel Hub

W

2

Tape Width A max. N W1 min. W2 max. W3 min. W3 max.

mm mm mm mm mm mm mm

24 330 60 24.4 30.4 23.9 27.4

14017

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12

Document Number 82550

Rev. 1.3, 16-Oct-03

VISHAY

Tape Dimensions in mm

TFDU6102

Vishay Semiconductors

Document Number 82550

Rev. 1.3, 16-Oct-03

18269

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13

TFDU6102

Vishay Semiconductors

VISHAY

www.vishay.com

14

18283

Document Number 82550

Rev. 1.3, 16-Oct-03

VISHAY

TFDU6102

Vishay Semiconductors

Ozone Depleting Substances Policy Statement

It is the policy of Vishay Semiconductor GmbH to

1. Meet all present and future national and international statutory requirements.

2. Regularly and continuously improve the performance of our products, processes, distribution and
operatingsystems with respect to their impact on the health and safety of our employees and the public, as
well as their impact on the environment.

It is particular concern to control or eliminate releases of those substances into the atmosphere which are
known as ozone depleting substances (ODSs).

The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs
and forbid their use within the next ten years. Various national and international initiatives are pressing for an
earlier ban on these substances.

Vishay Semiconductor GmbH has been able to use its policy of continuous improvements to eliminate the
use of ODSs listed in the following documents.

1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments
respectively

2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental
Protection Agency (EPA) in the USA

3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively.

Vishay Semiconductor GmbH can certify that our semiconductors are not manufactured with ozone depleting
substances and do not contain such substances.

We reserve the right to make changes to improve technical design

and may do so without further notice.

Parameters can vary in different applications. All operating parameters must be validated for each

customer application by the customer. Should the buyer use Vishay Semiconductors products for any

unintended or unauthorized application, the buyer shall indemnify Vishay Semiconductors against all

claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal

damage, injury or death associated with such unintended or unauthorized use.

Vishay Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany

Telephone: [phone], Fax number: 49 (0)7131 67 2423

Document Number 82550

Rev. 1.3, 16-Oct-03

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15