VISHAY SIHP22N60EF-GE3 Datasheet

Page 1
SiHP22N60EF
TO-220AB
G
D
S
www.vishay.com
Vishay Siliconix
EF Series Power MOSFET With Fast Body Diode
G
N-Channel MOSFET
PRODUCT SUMMARY
VDS (V) at TJ max. 650
R
typ. () at 25 °C VGS = 10 V 0.158
DS(on)
Q
max. (nC) 96
g
Q
(nC) 9
gs
Q
(nC) 21
gd
Configuration Single
D
FEATURES
• Low figure-of-merit (FOM) Ron x Q
• Low input capacitance (C
iss
)
g
• Reduced switching and conduction losses
• Ultra low gate charge (Q
)
g
• Avalanche energy rated (UIS)
• Material categorization: for definitions of compliance
S
please see www.vishay.com/doc?99912
APPLICATIONS
• Server and telecom power supplies
• Switch mode power supplies (SMPS)
• Power factor correction power supplies (PFC)
• Lighting
- High-intensity discharge (HID)
- Fluorescent ballast lighting
• Industrial
- Welding
- Induction heating
- Motor drives
- Battery chargers
- Renewable energy
- Solar (PV inverters)
ORDERING INFORMATION
Package TO-220AB
Lead (Pb)-free and halogen-free SiHP22N60EF-GE3
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER SYMBOL LIMIT UNIT
Drain-source voltage V
Gate-source voltage V
T
= 25 °C
Continuous drain current (T
Pulsed drain current
a
= 150 °C) VGS at 10 V
J
C
= 100 °C 12
C
DS
GS
I
D
I
DM
Linear derating factor 1.4 W/°C
Single pulse avalanche energy
Maximum power dissipation P
Operating junction and storage temperature range T
Drain-source voltage slope T
Reverse diode dv/dt
d
Soldering recommendations (peak temperature)
b
= 125 °C
J
c
For 10 s 260 °C
E
AS
D
, T
J
dv/dt
stg
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature b. V
= 140 V, starting TJ = 25 °C, L = 28.2 mH, Rg = 25 , IAS = 3.2 A
DD
c. 1.6 mm from case d. I
ID, di/dt = 400 A/μs, starting TJ = 25 °C
SD
600
± 30
19
46
144 mJ
179 W
-55 to +150 °C
70
50
V
AT
V/ns
S19-0120-Rev. A, 04-Feb-2019
1
Document Number: 92244
For technical questions, contact: hvm@vishay.com
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Page 2
SiHP22N60EF
S
D
G
www.vishay.com
THERMAL RESISTANCE RATINGS
PARAMETER SYMBOL TYP. MAX. UNIT
Maximum junction-to-ambient R
Maximum junction-to-case (drain) R
thJA
thJC
-62
-0.7
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Static
Drain-source breakdown voltage V
V
temperature coefficient VDS/T
DS
Gate-source threshold voltage (N) V
Gate-source leakage I
Zero gate voltage drain current I
Drain-source on-state resistance R
Forward transconductance
a
Dynamic
Input capacitance C
Output capacitance C
Reverse transfer capacitance C
Effective output capacitance, energy
a
related
Effective output capacitance, time
b
related
C
C
Total gate charge Q
Gate-drain charge Q
Turn-on delay time t
Rise time t
Turn-off delay time t
Fall time t
Gate input resistance R
Drain-Source Body Diode Characteristics
Continuous source-drain diode current I
Pulsed diode forward current I
DS
GS(th)
GSS
DSS
DS(on)
g
fs
iss
oss
rss
o(er)
o(tr)
g
gs
gd
d(on)
r
d(off)
f
g
S
SM
J
MOSFET symbol showing the integral reverse p - n junction diode
VGS = 0 V, ID = 250 μA 600 - - V
Reference to 25 °C, ID = 1 mA - 0.68 - V/°C
VDS = VGS, ID = 250 μA 2.0 - 4.0 V
VGS = ± 20 V - - ± 100 nA
V
= ± 30 V - - ± 1 μA
GS
VDS = 480 V, VGS = 0 V - - 1
= 480 V, VGS = 0 V, TJ = 125 °C - - 500
V
DS
VGS = 10 V ID = 11 A - 0.158 0.182
VDS = 30 V, ID = 11 A - 5.8 - S
VGS = 0 V,
V
= 100 V,
DS
f = 1 MHz
VDS = 0 V to 480 V, VGS = 0 V
VGS = 10 V ID = 11 A, VDS = 480 V
VDD = 480 V, ID = 11 A, V
= 10 V, Rg = 9.1
GS
f = 1 MHz, open drain 0.3 0.6 1.2
Vishay Siliconix
°C/W
μA
- 1423 -
-73-
-5-
-48-
- 240 -
-4896
-9-
-21-
-1530
-2142
-5887
-2550
--19
--46
pF
nC Gate-source charge Q
ns
A
Diode forward voltage V
Reverse recovery time t
Reverse recovery charge Q
Reverse recovery current I
SD
rr
rr
RRM
TJ = 25 °C, IS = 11 A, VGS = 0 V - - 1.2 V
TJ = 25 °C, IF = IS = 11 A,
di/dt = 100 A/μs, V
= 400 V
R
- 113 226 ns
-0.71.C
-11-A
Notes
a. C b. C
is a fixed capacitance that gives the same energy as C
oss(er)
is a fixed capacitance that gives the same charging time as C
oss(tr)
S19-0120-Rev. A, 04-Feb-2019
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
For technical questions, contact: hvm@vishay.com
while VDS is rising from 0 % to 80 % V
oss
while V
oss
is rising from 0 % to 80 % V
DS
2
DSS
DSS
Document Number: 92244
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10
100
1000
10000
0
10
20
30
40
50
0 5 10 15 20
Axis Title
2nd line
I
D
- Drain-to-Source Current (A)
VDS- Drain-to-Source Voltage (V)
TJ= 25 °C
8 V
7 V
6 V
5 V
15 V 14 V 13 V 12 V 11 V 10 V
9 V
10
100
1000
10000
0
8
16
24
32
0 5 10 15 20
Axis Title
2nd line
I
D
- Drain-to-Source Current (A)
VDS- Drain-to-Source Voltage (V)
15 V 14 V 13 V 12 V 11 V 10 V
9 V
TJ= 150 °C
7 V
6 V
5 V
8 V
10
100
1000
10000
0
15
30
45
60
0 5 10 15 20
Axis Title
2nd line
I
D
- Drain-to-Source Current (A)
VGS- Gate-to-Source Voltage (V)
TJ= 25 °C
VDS= 28.4 V
10
100
1000
10000
0
0.5
1.0
1.5
2.0
2.5
3.0
-60 -40 -20 0 20 40 60 80 100 120 140 160
Axis Title
1st line
R
DS(on)
- Drain-to-Source On-Resistance
(Normalized)
TJ- Junction Temperature (°C)
VGS= 10 V
10
100
1000
10000
0.1
1
10
100
1000
10 000
100 000
0 100 200 300 400 500 600
Axis Title
1st line
2nd line
2nd line
C - Capacitance (pF)
VDS- Drain-to-Source Voltage (V)
iss
C
rss
C
oss
VGS= 0 V, f = 1 MHz C
iss
= Cgs+ Cgd, Cdsshorted
C
rss
= C
gd
C
oss
= Cds+ C
gd
0
2
4
6
8
10
12
14
10
100
1000
10 000
0 100 200 300 400 500 600
Axis Title
E
oss
- Output Capacitance Stored Energy (µJ)
2nd line
2nd line
C
oss
- Output Capacitance (pF)
VDS- Drain-to-Source Voltage (V)
E
oss
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
I
D
SiHP22N60EF
Vishay Siliconix
= 11 A
Fig. 1 - Typical Output Characteristics
Fig. 2 - Typical Output Characteristics
Fig. 4 - Normalized On-Resistance vs. Temperature
C
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
S19-0120-Rev. A, 04-Feb-2019
Fig. 3 - Typical Transfer Characteristics
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TJ= 150 °C
3
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C
oss
Fig. 6 - C
oss
and E
vs. V
oss
DS
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10
100
1000
10000
0
3
6
9
12
0 15304560
Axis Title
2nd line
V
GS
- Gate-to-Source Voltage (V)
Qg- Total Gate Charge (nC)
VDS= 480 V V
DS
= 300 V
V
DS
= 120 V
10
100
1000
10000
0.1
1
10
100
0.2 0.4 0.6 0.8 1.0 1.2 1.4
Axis Title
2nd line
I
SD
- Reverse Drain Current (A)
VSD- Source-Drain Voltage (V)
TJ= 25 °C
TJ= 150 °C
VGS= 0 V
10
100
1000
10000
0.01
0.1
1
10
100
1101001000
Axis Title
1st line
2nd line
I
D
- Drain Current (A)
VDS- Drain-to-Source Voltage (V)
I
limited
TC= 25 °C, T
J
= 150 °C,
single pulse
Limited by R
DS(on)
a
BVDSS limited
10 ms
1 ms
100 µs
Operation in this area limited by R
DS(on)
10
100
1000
10000
0
5
10
15
20
25 50 75 100 125 150
Axis Title
2nd line
I
D
- Drain Current (A)
TC- Case Temperature (°C)
10
100
1000
10000
600
625
650
675
700
725
750
775
-60 -40 -20 0 20 40 60 80 100 120 140 160
Axis Title
2nd line
V
DS
- Drain-to-Source Breakdown Voltage (V)
TJ- Junction Temperature (°C)
SiHP22N60EF
Vishay Siliconix
Fig. 7 - Typical Gate Charge vs. Gate-to-Source Voltage
Fig. 8 - Typical Source-Drain Diode Forward Voltage
Fig. 10 - Maximum Drain Current vs. Case Temperature
ID= 1 mA
Fig. 11 - Temperature vs. Drain-to-Source Voltage
Note
a. V
GS
S19-0120-Rev. A, 04-Feb-2019
DS(on)
is specified
4
For technical questions, contact: hvm@vishay.com
Document Number: 92244
Fig. 9 - Maximum Safe Operating Area
> minimum VGS at which R
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10
100
1000
10000
0.01
0.1
1
0.0001 0.001 0.01 0.1 1
Axis Title
1st line
2nd line
Normalized Effective Transient
Thermal Impedance
Pulse Time (s)
0.2
0.02
0.05
0.1
Single pulse
V
DS
90 %
10 %
V
GS
t
d(on)
t
r
t
d(off)
t
f
R
g
I
AS
0.01 Ω
t
p
D.U.T.
L
V
DS
+
-
V
DD
10 V
Vary t
p
to obtain
required I
AS
I
AS
V
DS
V
DD
V
DS
t
p
Duty cycle = 0.5
V
DS
V
GS
R
g
Fig. 12 - Normalized Transient Thermal Impedance, Junction-to-Case
R
D
D.U.T.
+
V
-
DD
SiHP22N60EF
Vishay Siliconix
10 V
Pulse width ≤ 1 μs Duty factor ≤ 0.1 %
Fig. 13 - Switching Time Test Circuit
Fig. 16 - Unclamped Inductive Waveforms
Q
10 V
V
Q
gs
G
g
Q
gd
Charge
Fig. 14 - Switching Time Waveforms
Fig. 17 - Basic Gate Charge Waveform
Current regulator
Same type as D.U.T.
50 kΩ
0.2 μF
12 V
0.3 μF
D.U.T.
+
V
DS
-
V
S19-0120-Rev. A, 04-Feb-2019
Fig. 15 - Unclamped Inductive Test Circuit
5
For technical questions, contact: hvm@vishay.com
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
GS
3 mA
Current sampling resistors
Fig. 18 - Gate Charge Test Circuit
I
G
I
D
Document Number: 92244
Page 6
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P.W.
Period
di/dt
Diode recovery
dv/dt
Ripple ≤ 5 %
Body diode forward drop
Re-applied voltage
Reverse recovery current
Body diode forward
current
VGS = 10 V a
V
DD
I
SD
Driver gate drive
D.U.T. I
SD
waveform
D.U.T. V
DS
waveform
Inductor current
D =
P.W.
Period
+
-
+
+
+
-
-
-
Note
a. V
GS
= 5 V for logic level devices
Peak Diode Recovery dv/dt Test Circuit
V
DD
• dv/dt controlled by R
g
• Driver same type as D.U.T.
• I
SD
controlled by duty factor “D”
• D.U.T. - device under test
D.U.T.
Circuit layout considerations
• Low stray inductance
Ground plane
• Low leakage inductance current transformer
R
g
2
1
2
1
3
4
4
3
SiHP22N60EF
Vishay Siliconix
Fig. 19 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?92244
S19-0120-Rev. A, 04-Feb-2019
.
6
For technical questions, contact: hvm@vishay.com
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Document Number: 92244
Page 7
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M
*
3
2
1
L
L(1)
D
H(1)
Q
Ø P
A
F
J(1)
b(1)
e(1)
e
E
b
C
Package Information
Vishay Siliconix
TO-220-1
DIM.
A 4.24 4.65 0.167 0.183
b 0.69 1.02 0.027 0.040
b(1) 1.14 1.78 0.045 0.070
c 0.36 0.61 0.014 0.024
D 14.33 15.85 0.564 0.624
E 9.96 10.52 0.392 0.414
e 2.41 2.67 0.095 0.105
e(1) 4.88 5.28 0.192 0.208
F 1.14 1.40 0.045 0.055
H(1) 6.10 6.71 0.240 0.264
J(1) 2.41 2.92 0.095 0.115
L 13.36 14.40 0.526 0.567
L(1) 3.33 4.04 0.131 0.159
Ø P 3.53 3.94 0.139 0.155
Q 2.54 3.00 0.100 0.118
ECN: X15-0364-Rev. C, 14-Dec-15 DWG: 6031
Note
• M* = 0.052 inches to 0.064 inches (dimension including protrusion), heatsink hole for HVM
MILLIMETERS INCHES
MIN. MAX. MIN. MAX.
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Revison: 14-Dec-15
ASE Xi’an
For technical questions, contact: hvm@vishay.com
Package Picture
1
Document Number: 66542
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Disclaimer
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Revision: 01-Jan-2019
1
Document Number: 91000
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