VISHAY SI7149ADP-GE3 Datasheet

PRODUCT SUMMARY

S

G

D

P-Channel MOSFET

VDS (V) R

0.0052 at V

- 30

0.0095 at V

() Max. ID (A) Qg (Typ.)

DS(on)

= - 10 V

GS

= - 4.5 V

GS

PowerPAK SO-8

P-Channel 30 V (D-S) MOSFET

FEATURES

• TrenchFET® Power MOSFET

• Low On-Resistance for Low Voltage Drop

- 50

- 50

d

43.1 nC

d

• Extended V

• 100 % R

• Material categorization: For definitions of compliance

please see www.vishay.com/doc?99912

max. Rating: 25 V

GS

and UIS Tested

g

Si7149ADP

Vishay Siliconix

APPLICATIONS

• Battery, Load and Adaptor Switches

- Notebook Computers

- Notebook Battery Packs

D

S

1

S

2

Bottom View

S

3

5.15 mm

G

4

6.15 mm

D

8

D

7

D

6

5

Ordering Information:

Si7149ADP-T1-GE3 (Lead (Pb)-free and Halogen-free)

ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)

Parameter Symbol Limit Unit

Drain-Source Voltage

Gate-Source Voltage

Continuous Drain Current (T

= 150 °C)

J

Pulsed Drain Current (t = 100 µs)

Continuous Source-Drain Diode Current

Avalanche Current

Single-Pulse Avalanche Energy

Maximum Power Dissipation

Operating Junction and Storage Temperature Range

Soldering Recommendations (Peak Temperature)

e, f

T

= 25 °C

C

= 70 °C

T

C

TA = 25 °C

TA = 70 °C

T

= 25 °C

C

TA = 25 °C

L = 0.1 mH

T

= 25 °C

C

T

= 70 °C 31

C

T

= 25 °C

A

TA = 70 °C

V

DS

V

GS

I

D

I

DM

I

S

I

AS

E

AS

- 30

± 25

d

- 50

d

- 50

a, b

- 23.1

a, b

- 18.4

- 300

d

- 50

a, b

- 4.1

- 25

31.2 mJ

V

A

48

P

D

, T

T

J

stg

a, b

5

a, b

3.2

- 55 to 150

260

W

°C

THERMAL RESISTANCE RATINGS

Parameter Symbol Typical Maximum Unit

Maximum Junction-to-Ambient

Maximum Junction-to-Case

Notes:
a. Surface mounted on 1" x 1" FR4 board.
b. t = 10 s.
c. Maximum under steady state conditions is 70 °C/W.
d. Package limited.
e. See solder profile (www.vishay.com/doc?73257

(not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not
required to ensure adequate bottom side solder interconnection.

f. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components.

Document Number: 62839
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a, c

t 10 s

Steady State

R

thJA

R

thJC

). The PowerPAK SO-8 is a leadless package. The end of the lead terminal is exposed copper

For technical questions, contact: [e-mail]

This document is subject to change without notice.

21 25

2.1 2.6

°C/W

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1

Si7149ADP

Vishay Siliconix

SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)

Parameter Symbol Test Conditions Min. Typ. Max. Unit

Static

V

Drain-Source Breakdown Voltage

V

Temperature Coefficient VDS/T

DS

V

Temperature Coefficient V

GS(th)

Gate-Source Threshold Voltage

Gate-Source Leakage

Zero Gate Voltage Drain Current

On-State Drain Current

Drain-Source On-State Resistance

Forward Transconductance

Dynamic

b

a

a

a

Input Capacitance

Reverse Transfer Capacitance

Total Gate Charge

Gate-Source Charge

Gate-Drain Charge

Gate Resistance

Tur n -O n De l ay T i m e

Rise Time

Turn-Off DelayTime

Fall Time

Tur n -O n De l ay T i m e

Rise Time

Turn-Off DelayTime

Fall Time

V

DS

GS(th)/TJ

V

GS(th)

I

GSS

I

DSS

I

D(on)

R

DS(on)

g

fs

C

iss

C

oss

C

rss

Q

g

Q

gs

Q

gd

R

g

t

d(on)

t

r

t

d(off)

t

f

t

d(on)

t

r

t

d(off)

t

f

J

Drain-Source Body Diode Characteristics

Continous Source-Drain Diode Current I

Pulse Diode Forward Current (100 µs) I

Body Diode Voltage V

Body Diode Reverse Recovery Time t

Body Diode Reverse Recovery Charge Q

Reverse Recovery Fall Time t

Reverse Recovery Rise Time t

S

SM

SD

rr

rr

a

b

Notes:
a. Pulse test; pulse width  300 µs, duty cycle  2 %.
b. Guaranteed by design, not subject to production testing.

V

DS

V

DS

V

DS

V

= - 15 V, V

DS

 - 10 A, V

I

D

 - 10 A, V

I

D

IF = - 10 A, dI/dt = 100 A/µs, TJ = 25 °C

= 0, ID = - 250 µA

GS

ID = - 250 µA

V

= VGS, ID = - 250 µA

DS

VDS = 0 V, VGS = ± 25 V

V

= - 30 V, VGS = 0 V

DS

= - 30 V, V

V

 - 10 V, V

DS

V

GS

V

GS

V

DS

= - 15 V, V

= - 15 V, V

= 0 V, TJ = 55 °C

GS

= - 10 V - 30 A

GS

= - 10 V, ID = - 15 A

= - 4.5 V, ID = - 10 A

= - 10 V, ID = - 15 A

= 0 V, f = 1 MHz

GS

= - 10 V, ID = - 10 A

GS

= - 4.5 V, ID = - 10 A

GS

f = 1 MHz 0.5 2.4 4.8 

V

= - 15 V, RL = 1.5 

DD

V

DD

= - 10 V, Rg = 1 

GEN

= - 15 V, RL = 1.5 

= - 4.5 V, Rg = 1 

GEN

TC = 25 °C - 50

IS = - 3 A, V

GS

- 30 V

- 22

4.1

mV/°C

- 1.2 - 2.5 V

± 100 nA

- 1

- 5

0.0042 0.0052

0.0076 0.0095

60 S

5125

615

554

90 135

43.1 65

13.6

28.8

15 30

12 24

58 110

12 24

60 120

60 120

52 100

26 52

- 300

= 0 - 0.74 - 1.20 V

23 46 ns

12 24 nC

9

14

µA



pFOutput Capacitance

nC

ns

A

ns

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the de vice. These are stress rating s only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.

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This document is subject to change without notice.

Document Number: 62839

S13-1158-Rev. A, 13-May-13

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

0

30

60

90

120

150

0.0 1.0 2.0 3.0 4.0 5.0

I

D

- Drain Current (A)

VDS - Drain-to-Source Voltage (V)

V

GS

= 3 V

VGS = 4 V

V

GS

= 2 V

0

2

4

6

8

10

0 20 40 60 80 100

V

GS

- Gate-to-Source Voltage (V)

Qg - Total Gate Charge (nC)

VDS = 15 V

VDS = 20 V

VDS = 10 V

0.6

0.8

1.0

1.2

1.4

1.6

- 50 - 25 0 25 50 75 100 125 150

R

DS(on)

- On-Resistance (Normalized)

TJ - Junction Temperature (°C)

ID = 15 A

VGS = 4.5 V

150

VGS = 10 V thru 5 V

120

90

Si7149ADP

Vishay Siliconix

Output Characteristics

0.0150

0.0120

0.0090

0.0060

- On-Resistance (Ω)

DS(on)

R

0.0030

0.0000
0 20 40 60 80 100

VGS = 4.5 V

VGS = 10 V

ID - Drain Current (A)

On-Resistance vs. Drain Current

60

- Drain Current (A)

D

I

30

0

0.0 1.0 2.0 3.0 4.0 5.0 6.0

TC = 25 °C

= 125 °C

T

C

VGS - Gate-to-Source Voltage (V)

= - 55 °C

T

C

Transfer Characteristics

7000

C

iss

5600

4200

2800

C - Capacitance (pF)

1400

0

C

oss

C

rss

0 4 8 12 16 20

VDS - Drain-to-Source Voltage (V)

Capacitance

ID = 10 A

Document Number: 62839
S13-1158-Rev. A, 13-May-13

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Gate Charge

On-Resistance vs. Junction Temperature

For technical questions, contact: [e-mail]

This document is subject to change without notice.

VGS = 10 V

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3

Si7149ADP

- 0.4

- 0.2

0.20

0.4

0.6

0.8

- 50 - 25 0 25 50 75 100 125 150

V

GS(th)

- Variance (V)

TJ - Temperature (°C)

0

50

100

150

200

250

0.001 0.01 0.1 1 10

Power (W)

Time (s)

0.01

0.1

1

10

100

1000

0.01 0.1 1 10 100

I

D

- Drain Current (A)

VDS - Drain-to-Source Voltage (V)

* V

GS

> minimum VGS at which R

DS(on)

is specied

100 μs

100 ms

Limited by R

)

*

IDM Limited

Single Pulse

ID Limited

Vishay Siliconix

TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

100

- Source Current (A)

S

I

0.01

0.001

10

0.1

TJ = 150 °C

1

0.0 0.2 0.4 0.6 0.8 1.0 1.2

VSD - Source-to-Drain Voltage (V)

TJ = 25 °C

Source-Drain Diode Forward Voltage

I

= 250 μA

I

= 1 mA

0.030

0.024

0.018

0.012

- On-Resistance (Ω)

DS(on)

R

0.006

TJ = 25 °C

0.000
0 2 4 6 8 10

VGS - Gate-to-Source Voltage (V)

ID = 15 A

TJ = 125 °C

On-Resistance vs. Gate-to-Source Voltage

Threshold Voltage

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Single Pulse Power, Junction-to-Ambient

1 ms

10 ms

1 s

10 s

DC

DS(on

TA = 25 °C

BVDSS Limited

Safe Operating Area

This document is subject to change without notice.

Document Number: 62839

S13-1158-Rev. A, 13-May-13

TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

0

12

24

36

48

60

0 25 50 75 100 125 150

Power (W)

TC - Case Temperature (°C)

0.0

0.5

1.0

1.5

2.0

2.5

0 25 50 75 100 125 150

Power (W)

TA - Ambient Temperature (°C)

90

72

54

36

- Drain Current (A)

D

I

Limited by Package

18

0

0 25 50 75 100 125 150

TC - Case Temperature (°C)

Current Derating*

Si7149ADP

Vishay Siliconix

Power, Junction-to-Case

* The power dissipation PD is based on T
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.

Document Number: 62839
S13-1158-Rev. A, 13-May-13

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Power Derating, Junction-to-Ambient

= 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper

J(max.)

For technical questions, contact: [e-mail]

This document is subject to change without notice.

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5

Si7149ADP

0.01

0.1

1

0.0001 0.001 0.01 0.1 1 10 100 1000

Normalized Effective Transient

Thermal Impedance

Square Wave Pulse Duration (s)

Duty Cycle = 0.5

0.2

0.1

0.05

0.02

Single Pulse

t

1

t

2

Notes:

P

DM

1. Duty Cycle, D =

2. Per Unit Base = R

thJA

= 70 °C/W

3. T

JM-TA=PDMZthJA

(t)

t

1

t

2

4. Surface Mounted

0.01

0.1

1

0.0001 0.001 0.01 0.1 1 10

Normalized Effective Transient

Thermal Impedance

Square Wave Pulse Duration (s)

Duty Cycle = 0.5

0.2

0.1

0.05

0.02

Single Pulse

Vishay Siliconix

TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

Normalized Thermal Transient Impedance, Junction-to-Ambient

Normalized Thermal Transient Impedance, Junction-to-Case

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?62839

www.vishay.com Document Number: 62839
6

.

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S13-1158-Rev. A, 13-May-

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PowerPAK® SO-8, (Single/Dual)

Package Information

Vishay Siliconix

W

1

2

3

4

θ

c

Notes

1.

Inch will govern.

2

Dimensions exclusive of mold gate burrs.

3.

Dimensions exclusive of mold flash and cutting burrs.

DIM.

A 0.97 1.04 1.12 0.038 0.041 0.044

A1 - 0.05 0 - 0.002

b 0.33 0.41 0.51 0.013 0.016 0.020
c 0.23 0.28 0.33 0.009 0.011 0.013

D 5.05 5.15 5.26 0.199 0.203 0.207
D1 4.80 4.90 5.00 0.189 0.193 0.197
D2 3.56 3.76 3.91 0.140 0.148 0.154
D3 1.32 1.50 1.68 0.052 0.059 0.066
D4 0.57 typ. 0.0225 typ.
D5 3.98 typ. 0.157 typ.

E 6.05 6.15 6.25 0.238 0.242 0.246
E1 5.79 5.89 5.99 0.228 0.232 0.236
E2 3.48 3.66 3.84 0.137 0.144 0.151
E3 3.68 3.78 3.91 0.145 0.149 0.154

E4 0.75 typ. 0.030 typ.

e 1.27 BSC 0.050 BSC

K 1.27 typ. 0.050 typ.
K1 0.56 - - 0.022 - -

H 0.51 0.61 0.71 0.020 0.024 0.028

L 0.51 0.61 0.71 0.020 0.024 0.028
L1 0.06 0.13 0.20 0.002 0.005 0.008

 0° - 12° 0° - 12°
W 0.15 0.25 0.36 0.006 0.010 0.014
M 0.125 typ. 0.005 typ.

ECN: S17-0173-Rev. L, 13-Feb-17
DWG: 5881

H

M

e

L1

θ

A

2

E1

E

θ

Z

2

D

D1

θ

A1

Detail Z

D4

D2

Backside View of Single Pad

H

D4

D3 (2x)

D2

Backside View of Dual Pad

E2

D

E3

E2

D1

D2

E3

L

K

E4

1

2

D5

3

b

4

L

K

E4

1

2

D5

K1

3

b

4

MILLIMETERS INCHES

MIN. NOM. MAX. MIN. NOM. MAX.

Revison: 13-Feb-17

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1

Document Number: 71655

VISHAY SILICONIX

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Power MOSFETs

Application Note AN821

PowerPAK® SO-8 Mounting and Thermal Considerations

by Wharton McDaniel

MOSFETs for switching applications are now available with
die on resistances around 1 m and with the capability to
handle 85 A. While these die capabilities represent a major
advance over what was available just a few years ago, it is
important for power MOSFET packaging technology to keep
pace. It should be obvious that degradation of a high
performance die by the package is undesirable. PowerPAK
is a new package technology that addresses these issues.
In this application note, PowerPAK’s construction is
described. Following this mounting information is presented
including land patterns and soldering profiles for maximum
reliability. Finally, thermal and electrical performance is
discussed.

THE PowerPAK PACKAGE

The PowerPAK package was developed around the SO-8
package (figure 1). The PowerPAK SO-8 utilizes the same
footprint and the same pin-outs as the standard SO-8. This
allows PowerPAK to be substituted directly for a standard
SO-8 package. Being a leadless package, PowerPAK SO-8
utilizes the entire SO-8 footprint, freeing space normally
occupied by the leads, and thus allowing it to hold a larger
die than a standard SO-8. In fact, this larger die is slightly
larger than a full sized DPAK die. The bottom of the die
attach pad is exposed for the purpose of providing a direct,
low resistance thermal path to the substrate the device is
mounted on. Finally, the package height is lower than the
standard SO-8, making it an excellent choice for
applications with space constraints.

PowerPAK SO-8 SINGLE MOUNTING

The PowerPAK single is simple to use. The pin arrangement
(drain, source, gate pins) and the pin dimensions are the
same as standard SO-8 devices (see figure 2). Therefore, the
PowerPAK connection pads match directly to those of the
SO-8. The only difference is the extended drain connection
area. To take immediate advantage of the PowerPAK SO-8
single devices, they can be mounted to existing SO-8 land
patterns.

Standard SO-8 PowerPAK SO-8

Fig. 2

The minimum land pattern recommended to take full
advantage of the PowerPAK thermal performance see
Application Note 826, Recommended Minimum Pad

Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs. Click on the PowerPAK SO-8 single in the index

of this document.

In this figure, the drain land pattern is given to make full
contact to the drain pad on the PowerPAK package.

This land pattern can be extended to the left, right, and top
of the drawn pattern. This extension will serve to increase
the heat dissipation by decreasing the thermal resistance
from the foot of the PowerPAK to the PC board and
therefore to the ambient. Note that increasing the drain land
area beyond a certain point will yield little decrease
in foot-to-board and foot-to-ambient thermal resistance.
Under specific conditions of board configuration, copper
weight and layer stack, experiments have found that
more than about 0.25 in
(in addition to the drain land) will yield little improvement in
thermal performance.

2

to 0.5 in2 of additional copper

APPLICATION NOTE

Fig. 1 PowerPAK 1212 Devices

Revision: 16-Mai-13

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1

Document Number: 71622

Application Note AN821

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Vishay Siliconix

PowerPAK® SO-8 Mounting and Thermal Considerations

PowerPAK SO-8 DUAL

The pin arrangement (drain, source, gate pins) and the pin
dimensions of the PowerPAK SO-8 dual are the same as
standard SO-8 dual devices. Therefore, the PowerPAK
device connection pads match directly to those of the SO-8.
As in the single-channel package, the only exception is the
extended drain connection area. Manufacturers can likewise
take immediate advantage of the PowerPAK SO-8 dual
devices by mounting them to existing SO-8 dual land
patterns.

To take the advantage of the dual PowerPAK SO-8’s
thermal performance, the minimum recommended land
pattern can be found in Application Note 826,

Recommended Minimum Pad Patterns With Outline
Drawing Access for Vishay Siliconix MOSFETs. Click on the

PowerPAK 1212-8 dual in the index of this document.

The gap between the two drain pads is 24 mils. This
matches the spacing of the two drain pads on the
PowerPAK SO-8 dual package.

REFLOW SOLDERING

Vishay Siliconix surface-mount packages meet solder reflow
reliability requirements. Devices are subjected to solder
reflow as a test preconditioning and are then
reliability-tested using temperature cycle, bias humidity,
HAST, or pressure pot. The solder reflow temperature profile
used, and the temperatures and time duration, are shown in
figures 3 and 4.

For the lead (Pb)-free solder profile, see

www.vishay.com/doc?73257.

Fig. 3 Solder Reflow Temperature Profile

Ramp-Up Rate + 3 °C /s max.

Temperature at 150 - 200 °C 120 s max.

Temperature Above 217 °C 60 - 150 s

Maximum Temperature 255 + 5/- 0 °C

Time at Maximum
Temperature

Ramp-Down Rate + 6 °C/s max.

30 s

30 s

260 °C

3 °C(max) 6 ° C/s (max.)

150 - 200 °C

Maximum peak temperature at 240 °C is allowed.

Fig. 4 Solder Reflow Temperatures and Time Durations

Revision: 16-Mai-13

APPLICATION NOTE

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For technical questions, contact: [e-mail]

60 s (min.)

Pre-Heating Zone

2

217 °C

150 s (max.)

Reflow Zone

Document Number: 71622

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Si4874DY vs. Si7446DP PPAK on a 4-Layer Board

SO-8 Pattern, Trough Under Drain

Pulse Duration (sec)

)
s

ttaw/

C
( e

cn
adep

m

I

0.0001

0

1

50

60

10

100000.01

40

20

Si4874DY

Si7446DP

100

30

Rth vs. Spreading Copper

(0 %, 50 %, 100 % Back Copper)

Spreading Copper (sq in)

)sttaw/C(

ecn

adep

m

I

0.00

56

51

46

41

36

0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00

0 %

50 %

100 %

PowerPAK® SO-8 Mounting and Thermal Considerations

THERMAL PERFORMANCE

Introduction

A basic measure of a device’s thermal performance
is the junction-to-case thermal resistance, R
junction-to-foot thermal resistance, R

This parameter is

thJF

measured for the device mounted to an infinite heat sink and
is therefore a characterization of the device only, in other
words, independent of the properties of the object to which
the device is mounted. Table 1 shows a comparison of
the DPAK, PowerPAK SO-8, and standard SO-8. The
PowerPAK has thermal performance equivalent to the
DPAK, while having an order of magnitude better thermal
performance over the SO-8.

TABLE 1 - DPAK AND POWERPAK SO-8
EQUIVALENT STEADY STATE
PERFORMANCE

DPAK

Thermal

Resistance R

1.2 °C/W 1 °C/W 16 °C/W

thJC

Thermal Performance on Standard SO-8 Pad Pattern

Because of the common footprint, a PowerPAK SO-8
can be mounted on an existing standard SO-8 pad pattern.
The question then arises as to the thermal performance
of the PowerPAK device under these conditions. A
characterization was made comparing a standard SO-8 and
a PowerPAK device on a board with a trough cut out
underneath the PowerPAK drain pad. This configuration
restricted the heat flow to the SO-8 land pads. The results
are shown in figure 5.

PowerPAK

SO-8

, or the

thJC

Standard

SO-8

Application Note AN821

Vishay Siliconix

Because of the presence of the trough, this result suggests
a minimum performance improvement of 10 °C/W by using
a PowerPAK SO-8 in a standard SO-8 PC board mount.

The only concern when mounting a PowerPAK on a
standard SO-8 pad pattern is that there should be no traces
running between the body of the MOSFET. Where the
standard SO-8 body is spaced away from the pc board,
allowing traces to run underneath, the PowerPAK sits
directly on the pc board.

Thermal Performance - Spreading Copper

Designers may add additional copper, spreading copper, to
the drain pad to aid in conducting heat from a device. It is
helpful to have some information about the thermal
performance for a given area of spreading copper.

Figure 6 shows the thermal resistance of a PowerPAK SO-8
device mounted on a 2-in. 2-in., four-layer FR-4 PC board.
The two internal layers and the backside layer are solid
copper. The internal layers were chosen as solid copper to
model the large power and ground planes common in many
applications. The top layer was cut back to a smaller area
and at each step junction-to-ambient thermal resistance
measurements were taken. The results indicate that an area
above 0.3 to 0.4 square inches of spreading copper gives no
additional thermal performance improvement. A
subsequent experiment was run where the copper on the
back-side was reduced, first to 50 % in stripes to mimic
circuit traces, and then totally removed. No significant effect
was observed.

Fig. 5 PowerPAK SO-8 and Standard SO-0 Land Pad Thermal

Revision: 16-Mai-13

APPLICATION NOTE

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

Path

For technical questions, contact: [e-mail]

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Fig. 6 Spreading Copper Junction-to-Ambient Performance

3

Document Number: 71622

Application Note AN821

0.6

0.8

1.0

1.2

1.4

1.6

1.8

-50 -25 0 25 50 75 100 125 150

V

GS

= 10 V

I

D

= 23 A

On-Resistance vs. Junction Temperature

T

J

- Junction Temperature (°C)

)dezilamroN(( ecnatsiseR-nO -R

)no(SD

)

www.vishay.com

Vishay Siliconix

PowerPAK® SO-8 Mounting and Thermal Considerations

SYSTEM AND ELECTRICAL IMPACT OF
PowerPAK SO-8

In any design, one must take into account the change in
MOSFET R

A MOSFET generates internal heat due to the current
passing through the channel. This self-heating raises the
junction temperature of the device above that of the PC
board to which it is mounted, causing increased power
dissipation in the device. A major source of this problem lies
in the large values of the junction-to-foot thermal resistance
of the SO-8 package.

PowerPAK SO-8 minimizes the junction-to-board thermal
resistance to where the MOSFET die temperature is very
close to the temperature of the PC board. Consider two
devices mounted on a PC board heated to 105 °C by other
components on the board (figure 8).

with temperature (figure 7).

DS(on)

Fig. 7 MOSFET R

DS(on)

vs. Temperature

Suppose each device is dissipating 2.7 W. Using the
junction-to-foot thermal resistance characteristics of the
PowerPAK SO-8 and the standard SO-8, the die
temperature is determined to be 107 °C for the PowerPAK
(and for DPAK) and 148 °C for the standard SO-8. This is a
2 °C rise above the board temperature for the PowerPAK
and a 43 °C rise for the standard SO-8. Referring to figure 7,
a 2 °C difference has minimal effect on R
43 °C difference has a significant effect on R

DS(on)

DS(on)

whereas a

.

Minimizing the thermal rise above the board temperature by
using PowerPAK has not only eased the thermal design but
it has allowed the device to run cooler, keep r

DS(on)

low, and
permits the device to handle more current than the same
MOSFET die in the standard SO-8 package.

CONCLUSIONS

PowerPAK SO-8 has been shown to have the same thermal
performance as the DPAK package while having the same
footprint as the standard SO-8 package. The PowerPAK
SO-8 can hold larger die approximately equal in size to the
maximum that the DPAK can accommodate implying no
sacrifice in performance because of package limitations.

Recommended PowerPAK SO-8 land patterns are provided
to aid in PC board layout for designs using this new
package.

Thermal considerations have indicated that significant
advantages can be gained by using PowerPAK SO-8
devices in designs where the PC board was laid out for
the standard SO-8. Applications experimental data gave
thermal performance data showing minimum and
typical thermal performance in a SO-8 environment, plus
information on the optimum thermal performance
obtainable including spreading copper. This further
emphasized the DPAK equivalency.

PowerPAK SO-8 therefore has the desired small size
characteristics of the SO-8 combined with the attractive
thermal characteristics of the DPAK package.

PowerPAK SO-8

107 °C

0.8 °C/W

Fig. 8 Temperature of Devices on a PC Board

Revision: 16-Mai-13

PC Board at 105 °C

APPLICATION NOTE

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Standard SO-8

148 °C

16 C/W

4

For technical questions, contact: [e-mail]

Document Number: 71622

RECOMMENDED MINIMUM PADS FOR PowerPAK® SO-8 Single

0.260

(6.61)

0.150

(3.81)

0.024

(0.61)

Application Note 826

Vishay Siliconix

Return to Index

Return to Index

0.026

(0.66)

0.050

(1.27)

0.050

(1.27)

0.032

(0.82)

Recommended Minimum Pads

Dimensions in Inches/(mm)

0.154

(3.91)

0.040

(1.02)

0.174

(4.42)

APPLICATION NOTE

Document Number: 72599 www.vishay.com
Revision: 21-Jan-08 15

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Document Number: 91000