Vishay IRFR9220, IRFU9220, SiHFR9220, SiHFU9220 Data Sheet

IRFR9220, IRFU9220, SiHFR9220, SiHFU9220
www.vishay.com
Vishay Siliconix
S13-0166-Rev. E, 04-Feb-13
1
Document Number: 91283
For technical questions, contact: hvm@vishay.com
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Power MOSFET
FEATURES
Dynamic dV/dt Rating
Repetitive Avalanche Rated
Surface Mount (IRFR9220, SiHFR9220)
Straight Lead (IRFUFU9220, SiHFU9220)
Available in Tape and Reel
•P-Channel
Fast Switching
Material categorization: For definitions of compliance
please see www.vishay.com/doc?99912
DESCRIPTION
Third power MOSFETs technology is the key to Vishay
advanced line of Power MOSFET transistors. The efficient
geometry and unique processing of the Power MOSFETs
design achieve very low on-state resistance combined with
high transconductance and extreme device ruggedness.
The DPAK is designed for surface mounting using vapor
phase, infrared, or wave soldering techniques. The straight
lead version (IRFU, SiHFU series) is for through-hole
mounting applications. Power dissipation levels up to 1.5 W
are possible in typical surface mount applications.
Note
a. See device orientation.
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. V
DD
= - 50 V, Starting T
J
= 25 °C, L = 35 mH, R
g
= 25 , I
AS
= - 3.6 A (see fig. 12).
c. I
SD
- 3.9 A, dI/dt 95 A/μs, V
DD
V
DS
, T
J
150 °C.
d. 1.6 mm from case.
e. When mounted on 1" square PCB (FR-4 or G-10 material).
PRODUCT SUMMARY
V
DS
(V) - 200
R
DS(on)
()V
GS
= - 10 V 1.5
Q
g
(Max.) (nC) 20
Q
gs
(nC) 3.3
Q
gd
(nC) 11
Configuration Single
S
G
D
P-Channel MOSFET
DPAK
(TO-252)
IPAK
(TO-251)
G
D
S
S
D
G
D
ORDERING INFORMATION
Package DPAK (TO-252) DPAK (TO-252) DPAK (TO-252) DPAK (TO-252) IPAK (TO-251)
Lead (Pb)-free and
Halogen-free
SiHFR9220-GE3 SiHFR9220TRL-GE3
a
SiHFR9220TRR-GE3
a
SiHFR9220TR-GE3
a
SiHFU9220-GE3
Lead (Pb)-free
IRFR9220PbF IRFR9220TRLPbF
a
IRFR9220TRRPbF
a
IRFR9220TRPbF
a
IRFU9220PbF
SiHFR9220-E3 SiHFR9220TL-E3
a
SiHFR9220TR-E3
a
SiHFR9220T-E3
a
SiHFU9220-E3
ABSOLUTE MAXIMUM RATINGS (T
C
= 25 °C, unless otherwise noted)
PARAMETER SYMBOL LIMIT UNIT
Drain-Source Voltage V
DS
- 200
V
Gate-Source Voltage V
GS
± 20
Continuous Drain Current V
GS
at - 10 V
T
C
= 25 °C
I
D
- 3.6
AT
C
= 100 °C - 2.3
Pulsed Drain Current
a
I
DM
- 14
Linear Derating Factor 0.33
W/°C
Linear Derating Factor (PCB Mount)
e
0.020
Single Pulse Avalanche Energy
b
E
AS
310 mJ
Repetitive Avalanche Current
a
I
AR
- 3.6 A
Repetitive Avalanche Energy
a
E
AR
4.2 mJ
Maximum Power Dissipation T
C
= 25 °C
P
D
42
W
Maximum Power Dissipation (PCB Mount)
e
T
A
= 25 °C 2.5
Peak Diode Recovery dV/dt
c
dV/dt - 5.0 V/ns
Operating Junction and Storage Temperature Range T
J
, T
stg
- 55 to + 150
°C
Soldering Recommendations (Peak Temperature)
d
for 10 s 260
IRFR9220, IRFU9220, SiHFR9220, SiHFU9220
www.vishay.com
Vishay Siliconix
S13-0166-Rev. E, 04-Feb-13
2
Document Number: 91283
For technical questions, contact: hvm@vishay.com
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Note
a. When mounted on 1" square PCB (FR-4 or G-10 material).
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width 300 μs; duty cycle 2 %.
THERMAL RESISTANCE RATINGS
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Maximum Junction-to-Ambient R
thJA
- - 110
°C/W
Maximum Junction-to-Ambient
(PCB Mount)
a
R
thJA
--50
Maximum Junction-to-Case (Drain) R
thJC
--3.0
SPECIFICATIONS (T
J
= 25 °C, unless otherwise noted)
PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Static
Drain-Source Breakdown Voltage V
DS
V
GS
= 0 V, I
D
= - 250 μA - 200 - - V
V
DS
Temperature Coefficient V
DS
/T
J
Reference to 25 °C, I
D
= - 1 mA - - 0.22 - V/°C
Gate-Source Threshold Voltage V
GS(th)
V
DS
= V
GS
, I
D
= - 250 μA - 2.0 - - 4.0 V
Gate-Source Leakage I
GSS
V
GS
= ± 20 V - - ± 100 nA
Zero Gate Voltage Drain Current I
DSS
V
DS
= - 200 V, V
GS
= 0 V - - - 100
μA
V
DS
= - 160 V, V
GS
= 0 V, T
J
= 125 °C - - - 500
Drain-Source On-State Resistance R
DS(on)
V
GS
= - 10 V I
D
= - 2.2 A
b
--1.5
Forward Transconductance g
fs
V
DS
= - 50 V, I
D
= - 2.2 A 1.1 - - S
Dynamic
Input Capacitance C
iss
V
GS
= 0 V,
V
DS
= - 25 V,
f = 1.0 MHz, see fig. 5
- 340 -
pFOutput Capacitance C
oss
- 110 -
Reverse Transfer Capacitance C
rss
-33-
Total Gate Charge Q
g
V
GS
= - 10 V
I
D
= - 3.9 A, V
DS
= - 160 V,
see fig. 6 and 13
b
--20
nC Gate-Source Charge Q
gs
--3.3
Gate-Drain Charge Q
gd
--11
Turn-On Delay Time t
d(on)
V
DD
= - 100 V, I
D
= - 3.9 A,
R
g
= 18 , R
D
= 24 , see fig. 10
b
-8.8-
ns
Rise Time t
r
-27-
Turn-Off Delay Time t
d(off)
-7.3-
Fall Time t
f
-19-
Internal Drain Inductance L
D
Between lead,
6 mm (0.25") from
package and center of
die contact
-4.5-
nH
Internal Source Inductance L
S
-7.5-
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current I
S
MOSFET symbol
showing the
integral reverse
p - n junction diode
--- 3.6
A
Pulsed Diode Forward Current
a
I
SM
--- 14
Body Diode Voltage V
SD
T
J
= 25 °C, I
S
= - 3.6 A, V
GS
= 0 V
b
--- 6.3V
Body Diode Reverse Recovery Time t
rr
T
J
= 25 °C, I
F
= - 3.9 A, dI/dt = 100 A/μs
b
- 150 300 ns
Body Diode Reverse Recovery Charge Q
rr
- 0.97 2.0 μC
Forward Turn-On Time t
on
Intrinsic turn-on time is negligible (turn-on is dominated by L
S
and L
D
)
D
G
S
D
G
IRFR9220, IRFU9220, SiHFR9220, SiHFU9220
www.vishay.com
Vishay Siliconix
S13-0166-Rev. E, 04-Feb-13
3
Document Number: 91283
For technical questions, contact: hvm@vishay.com
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Fig. 1 - Typical Output Characteristics, T
C
= 25 °C
Fig. 2 - Typical Output Characteristics, T
C
= 150 °C
Fig. 3 - Typical Transfer Characteristics
Fig. 4 - Normalized On-Resistance vs. Temperature
IRFR9220, IRFU9220, SiHFR9220, SiHFU9220
www.vishay.com
Vishay Siliconix
S13-0166-Rev. E, 04-Feb-13
4
Document Number: 91283
For technical questions, contact: hvm@vishay.com
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 8 - Maximum Safe Operating Area
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