UTRON UT62256CPC-70LLE, UT62256CPC-70LE, UT62256CPC-70E, UT62256CLS-70LLE, UT62256CLS-70LE Datasheet
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UTRON
UT62256C(E)
Rev. 1.0
32K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80071
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
1
FEATURES
Access time : 35/70ns (max.)
Low power consumption:
Operating : 40/30 mA (typical.)
Standby : 2uA (typ.) L-version
1uA (typ.) LL-version
Single 5V power supply
Extended temperature : -20℃~80℃
All inputs and outputs are TTL compatible
Fully static operation
Three state outputs
Data retention voltage : 2V (min.)
Package : 28-pin 600 mil PDIP
28-pin 330 mil SOP
28-pin 8mmx13.4mm STSOP
FUNCTIONAL BLOCK DIAGRAM
COLUMN I/O
COLUMN DECODER
ROW
DECODER
I/O
CONTROL
LOGI C
CONTROL
A4
I/O1
VSS
VCC
WE
OE
CE
I/O8
.
.
.
.
.
.
. .
.
A3
A
14
A
13
A
12
A7
A6
A5
A8
A9 A2 A1 A
0
A
10
.
.
.
.
.
.
MEMORY ARRAY
512 ROWS × 512 COLUMNS
A
11
PIN DESCRIPTION
SYMBOL DESCRIPTION
A0 - A14 Address Inputs
I/O1 - I/O8 Data Inputs/Outputs
CE
Chip Enable Input
WE
Write Enable Input
OE
Output Enable Input
VCC Power Supply
VSS Ground
GENERAL DESCRIPTION
The UT62256C(E) is a 262,144-bit low power
CMOS static random access memory organized
as 32,768 words by 8 bits. It is fabricated using
high performance, high reliability CMOS
technology.
The UT62256C(E) is designed for high-speed and
low power application. It is particularly well
suited for battery back-up nonvolatile memory
application.
The UT62256C(E) operates from a single 5V
power supply and all inputs and outputs are fully
TTL compatible
PIN CONFIGURATION
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
Vcc
A8
A9
A11
A10
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
Vss
UT62256C
PDIP/SOP
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
16
15
20
19
18
22
23
24
25
26
27
21
CE
WE
OE
A13
A14
I/O4
A11
A9
A8
A13
I/O3
A10
A14
A12
A7
A6
A5
Vcc
I/O8
I/O7
I/O6
I/O5
Vss
I/O2
I/O1
A0
A1
A2
A4
A3
UT62256C
STSOP
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
16
15
20
19
18
22
23
24
25
26
27
21
WE
OE
CE
UTRON
UT62256C(E)
Rev. 1.0
32K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80071
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
2
ABSOLUTE MAXIMUM RATINGS
*
PARAMETER SYMBOL RATING UNIT
Terminal Voltage with Respect to VSS V
TERM
-0.5 to +7.0 V
Operating Temperature TA 0 to +70
℃
Storage Temperature T
STG
-65 to +150
℃
Power Dissipation PD 1 W
DC Output Current I
OUT
50 mA
Soldering Temperature (under 10 secs) Tsolder 260
℃
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device
reliability.
TRUTH TABLE
MODE
CE
OE
WE
I/O OPERATION SUPPLY CURRENT
Standby H X X High - Z ISB, ISB1
Output Disable L H H High - Z I
CC, ICC
1, ICC2
Read L L H D
OUT
I
CC, ICC
1, ICC2
Write L X L DIN I
CC, ICC
1, ICC2
Note: H = VIH, L=VIL, X = Don't care.
DC ELECTRICAL CHARACTERISTICS
(VCC = 5V±10%, TA = -20℃~80℃)
PARAMETER
SYMBOL
TEST CONDITION MIN. TYP. MAX. UNIT
Input High Voltage VIH 2.2 - VCC+0.5 V
Input Low Voltage VIL - 0.5 - 0.8 V
Input Leakage Current ILI
V
SS
≦VIN ≦VCC
- 1 - 1
µ
A
Output Leakage
Current
ILO
V
SS
≦V
I/O
≦V
CC
CE
=V
IH
or
OE
= V
IH
or
WE
= VIL
- 1 - 1
µ
A
Output High Voltage VOH IOH= - 1mA 2.4 - - V
Output Low Voltage VOL IOL= 4mA - - 0.4 V
- 35 - 40 50 mA ICC Cycle time=Min
CE
= V
IL
,I
I/O
= 0mA ,.
- 70 - 30 40 mA
ICC1
Cycle time=1µs,
CE
=0.2V; I
I/O
=0mA,
other pins at 0.2V or V
CC
-0.2V
- - 10 mA
Operating Power
Supply Current
I
CC
2
Cycle time=500ns,
CE
=0.2V;I
I/O
=0mA,
other pins at 0.2V or V
CC
-0.2V
- - 20 mA
Standby Current
(TTL)
I
SB
CE
=V
IH
- - 3 mA
I
SB1
CE
≧
V
CC
-0.2V
-L - 2 100
µ
A
Standby Current
(CMOS
)
-LL - 1 50
µ
A
UTRON
UT62256C(E)
Rev. 1.0
32K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80071
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
3
CAPACITANCE
(TA=25℃, f=1.0MHz)
PARAMETER SYMBOL MIN. MAX UNIT
Input Capacitance C
IN
-
8 pF
Input/Output Capacitance C
I/O
-
10 pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels 0V to 3.0V
Input Rise and Fall Times 5ns
Input and Output Timing Reference Levels 1.5V
Output Load CL = 100pF, IOH/IOL = -1mA/4mA
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 5V±10% , TA = -20℃~80℃)
(1) READ CYCLE
PARAMETER
SYMBOL UT62256C(E)-35 UT62256C(E)-70 UNIT
MIN. MAX. MIN. MAX.
Read Cycle Time
tRC 35 - 70 - ns
Address Access Time
tAA - 35 - 70 ns
Chip Enable Access Time
t
ACE
- 35 - 70 ns
Output Enable Access Time
tOE - 25 - 35 ns
Chip Enable to Output in Low Z
t
CLZ*
10 - 10 - ns
Output Enable to Output in Low Z
t
OLZ*
5 - 5 - ns
Chip Disable to Output in High Z
t
CHZ*
- 25 - 35 ns
Output Disable to Output in High Z
t
OHZ*
- 25 - 35 ns
Output Hold from Address Change
tOH 5 - 5 - ns
(2) WRITE CYCLE
PARAMETER SYMBOL UT62256C(E)-35 UT62256C(E)-70 UNIT
MIN. MAX. MIN. MAX.
Write Cycle Time
tWC 35 - 70 - ns
Address Valid to End of Write
tAW 30 - 60 - ns
Chip Enable to End of Write
tCW 30 - 60 - ns
Address Set-up Time
tAS 0 - 0 - ns
Write Pulse Width
tWP 25 - 50 - ns
Write Recovery Time
tWR 0 - 0 - ns
Data to Write Time Overlap
tDW 20 - 30 - ns
Data Hold from End of Write Time
tDH 0 - 0 - ns
Output Active from End of Write
t
OW*
5 - 5 - ns
Write to Output in High Z
t
WHZ*
- 15 - 25 ns
*These parameters are guaranteed by device characterization, but not production tested.
UTRON
UT62256C(E)
Rev. 1.0
32K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80071
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
4
TIMING WAVEFORMS
READ CYCLE 1
(Address Controlled)
(1,2,4)
t
RC
Address
DOUT Data Valid
t
AA
t
OH
t
OH
READ CYCLE 2
(CE and
OE
Controlled)
(1,3,5,6)
D
OUT
Address
CE
OE
t
RC
t
AA
t
ACE
t
OE
t
CLZ
t
OLZ
High-z
t
OHZ
t
CHZ
Data valid
High-Z
t
OH
Notes :
1.
WE
is HIGH for read cycle.
2. Device is continuously selected
CE
=V
IL.
3. Address must be valid prior to or coincident with
CE
transition; otherwise t
AA
is the limiting parameter.
4.
OE
is LOW.
5. t
CLZ
, t
OLZ
, t
CHZ
and t
OHZ
are specified with CL = 5pF. Transition is measured
±
500mV from steady state.
6. At any given temperature and voltage condition, t
CHZ
is less than t
CLZ
, t
OHZ
is less than t
OLZ.
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