UNITRODE UCC1888, UCC2888, UCC3888 Technical data

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Off-line Power Supply Controller
UCC1888 UCC2888 UCC3888
FEATURES
Transformerless Off-line Power Supply
Wide 100VDC to 400VDC Allowable Input Range
Fixed 5VDC or Adjustable Low Voltage Output
Output Sinks 200mA, Sources 150mA Into a MOSFET Gate
Uses Low Cost SMD Inductors
Short Circuit Protected
Optional Isolation Capability
TYPICAL APPLICATION
DESCRIPTION
The UCC3888 controller is optimized for use as an off-line, low power, low voltage, regulated bias supply. The unique circuit topology utilized in this device can be visualized as two cascaded flyback converters, each operating in the discontinu­ous mode, both driven from a single external power switch. The significant benefit of this approach is the ability to achieve voltage conversion ratios as high as 400V to 2.7V with no transformer and low internal losses.
The control algorithm utilized by the UCC3888 sets the switch on time inversely proportional to the input line voltage and sets the switch off time inversely propor­tional to the output voltage. This action is automatically controlled by an internal feedback loop and reference. The cascaded configuration allows a voltage conver­sion from 400V to 2.7V to be achieved with a switch duty cycle of 7.6%. This topol­ogy also offers inherent short circuit protection since as the output voltage falls to zero, the switch off time approaches infin ity.
The output voltage is set internally to 5V. It can be programmed for other output voltages with two external resis tors. An isolated version can be achieved with this topology as described fu rth er in Un itrode App licat ion N ote U-1 49.
OPERATION
With reference to the application diagram below, when input voltage is fir st ap plied, the current through R capacitor, C3, connected to V tage lockout holds the circuit off and the output at DRIVE low until V
8.4V. At this time, DRIVE goes high turning on the power switch, Q1, and redirect­ing the current into T with a current I long as C voltage. This provides a constant (line voltage) • (switch on time) product.
CHG
charges, the power switch on time will be inversely proportional to line
T
into TON is directed to VCC where it charges the external
ON
. As voltage builds on VCC, an internal undervol-
CC
reaches
CC
to the timing capacitor, CT. CT charges to a fixed threshold
ON
=0.8 • (VIN - 4.5V)/RON. Since DRIVE will only be high for as
Note: This devi ce inc orp ora tes patented tec hn ol og y us ed und er license from Lambda Electronics, Inc.
3/97
UDG-96013
OPERATION (cont.)
At the end of the on time, Q1 is turned off and the current through R through R tributes to supplying power to the chip during the off time.
The power sw itch off time is controlle d by the dis charge of C
which, in turn, is programmed by the regulated out-
T
put voltag e. The relationship between C rent, I
DCHG
is again diverted to VCC. Thus the current
ON
, which charges CT during the on time, c on-
ON
discharge cur-
T
, and output voltage is illustrated as follows:
UCC1888 UCC2888 UCC3888
I
As V
increases, I
OUT
DCHG
= (V
The operating frequency increases and V quickly to its regulated value.
Region 3. In th i s r eg i on , a tr ans conductance ampl ifi er re-
duces I V
Region 4. If V
I
DCHG
DCHG
.
OUT
should rise abov e it s regu lat ion range,
OUT
falls to zero and the circuit returns to the minimum frequency established by R C
.
T
The range of switching frequencies is established by RON, R
, RS, and CT as follows:
OFF
- 0.7V) / R
OUT
increases r e duc ing off time.
DCHG
OFF
rises
OUT
in order to maintain a regulated
and
S
Region 1. When V
feature provides inherent short circuit protec­tion. However, to ensure output voltage startup when the output is n ot a short, a high value resistor, R to establish a minimum switching frequency.
Region 2. As V
OUT
regulated value, I and is equal to:
= 0, the off time is infinite. This
OUT
, is placed in parallel with C
S
rises above approxi mately 0.7V to its
is defined by R
DCHG
OFF
Frequency = 1/(T
T
= R
ON
T
(max) = 1.4 • RS • CT
OFF
ON
C
Regions 1 and 4 T
OFF
= R
OFF
Region 2, excluding the effects of R
which have a minimal impact on T
T
The above equations assume that V voltage at T
6.5V while C
,
increases from approximately 2.5V to
ON
is charging. To take this into account, V
T
is adjusted by 4.5V in the calculation of TON. The voltage at T
is approximately 0.7V.
OFF
ON
4.6
T
C
• 3.7V /(V
T
+ T
)
OFF
V/(VIN - 4.5V)
OUT
CC
- 0.7V)
S
.
OFF
equals 9V. The
DESIGN EXAMPLE
The UCC3888 regulate s a 5 volt , 1 Watt nonisolated DC output from AC inputs between 80 and 265 volts. In this ex­ample, the I C is prog rammed t o deliver a maximum on time gate dri ve pulse width of 2.2 microseconds which occurs at 80 VAC. The corresponding switching frequency is approximately 100kHz at low line, and overall efficiency is ap­proximately 50%. Additional design information is available in Unitrode Application Note U-149.
IN
UDG-96014
2
ABSOLUTE MAXIMUM RATINGS
ICC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8mA
Current into TON Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5mA
Voltage on V Current into T
Storage Temperature . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
Note: Unless otherwise indicated, voltages are referenced to ground and currents are positive into, neg ative out of, the sp ec i­fied terminals.
Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V
OUT
Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250µA
OFF
UCC1888 UCC2888 UCC3888
CONNECTION DIAGRAM
DIL-8, SOIC-8 (Top View) N or J, D Package
ELECTRICAL CHARACTERISTICS
Unless otherwise stated, these specifications hold for T
= 0°C to 70°C for the
A
UCC3888, -40°C to +85°C for the UCC2888, and -55°C to +125°C for the UCC1888. No load at DRIVE pi n (C
LOAD
=0).
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
General
V
Zener Voltage ICC < 1.5mA 8.6 9.0 9.3 V
CC
Startup Current V Operating Current I(V
)V
CC
= 0 150 250 µA
OUT
= VCC(zener) – 100mV, F = 150kHz 1.2 2.5 mA
CC
Under-Voltage-Lockout
Start Threshold V Minimum Operating Voltage after Start V Hysteresis V
= 0 8.0 8.4 8.8 V
OUT
= 0 6.0 6.3 6.6 V
OUT
= 0 1.8 V
OUT
Oscillator
Amplitude VCC = 9V 3.5 3.7 3.9 V C
to DRIVE high Propagation Delay Overdrive = 0.2V 100 200 ns
T
to DRIVE low Propagation Delay Overdrive = 0.2V 50 100 ns
C
T
Driver
VOL I = 20mA, VCC = 9V 0.15 0.4 V
I = 100mA, V
VOH I = −20mA, V
I = −100mA, V Rise Time C Fall Time C
= 1nF 35 70 ns
LOAD
= 1nF 30 60 ns
LOAD
= 9V 0.7 1.8 V
CC
= 9V 8.5 8.8 V
CC
= 9V 6.1 7.8 V
CC
Line Voltage Detection
Charge Coefficient: I Minimum Line Voltage for Fault R Minimum Current I(T On Time During Fault C
/ I(TON) VCT = 3V, DRIVE = High, I(TON) = 1mA 0.73 0.79 0.85
CHG
= 330k 60 80 100 V
ON
) for Fault RON = 330k 220 µA
ON
= 150pF, V
T
= Min 1V 2 µs
LINE
Oscillator Restart Delay after Fault 0.5 ms
OUT
V
Error Amp
V
Regulated 5V (ADJ Open) VCC = 9V, I
OUT
Discharge Ratio: I Voltage at T
OFF
DCHG
/ I(T
)I(T
OFF
Regulation gm (Note 1) Max I
DCHG
Note 1: gm is defined as
I
at 65% and 35% of its maximum value.
DCHG
I
for the values of V
V
OUT
) = 50µA 0.95 1.01 1.07
OFF
I(T
) = 50µA 0.6 0. 95 1.3 V
OFF
DCHG
Max I
DCHG
when V
OUT
DCHG
= I(T
)/2 4.5 5.0 5.5 V
OFF
= 50µA2.4mA/V = 125µA 1.9 4.1 7.0 mA/V
is in regulation. The two points used to calculate gm are for
OUT
3
PIN DESCRIPTIONS
ADJ:
The ADJ pin i s u sed to provide a 5V regulated sup­ply without ad ditional ext ernal components. Other output voltages can be obtained by connecting a resistor divi der between V
where R1 is c onnected between V is connected between ADJ and GND. R1 || R2 should be less than 1kΩ to minimize the effect of the temperature coefficient of the internal 30k resistors which also connect to V
OUT
(timing capacitor):
C
T
peak-to-pe ak swi ng of 3.7V for 9V V C
crosses the oscillator upper threshold, DRIVE goes
T
low. As the voltage on C threshold, DRIVE goes high.
DRIVE:
200mA peak and sourcin g 150mA peak. The output volt­age swing is 0 to V
GND (chip ground):
spect to GND.
, ADJ and GND. Use the formula
OUT
OUT
V
= 2.5V •
R1 + R2
R2
and ADJ, and R2
OUT
, ADJ, and GND. See Block Diagram.
The signal voltage at C
. As the voltage at
CC
crosses the oscillator lower
T
has a
T
This output is a CMOS stage capable of sinking
.
CC
All voltages are measured with re-
UCC1888 UCC2888 UCC3888
(regulated output control):
T
OFF
charge current of the timing capacitor through an external resistor connected between V
(line voltage control ):
T
ON
When C T
ON
is discharging (off time), the current through
T
is routed to V
current through T
CC.
is split 80% to set the CT charge
ON
T
When CT is chargin g (o n time), the
time and 20% to sense minimum l ine voltage which oc­curs for a T age of 80V, R
The C
T
current of 220µA. For a minimum l i ne volt-
ON
is 330kΩ.
ON
voltage slightly affects the value of the charge current during the on time. During this time, the voltage at the T
V
device at pin V
pin increases from 2.5V to 6.5V.
ON
(chip supply voltage):
CC
is inter nall y c lampe d a t 9V. The device
CC
needs an external supply, from a source such as the rec­tified AC line or derived from the switching circuit. Pre­cautions m ust be taken to ensure that total I exceed 8mA.
(regulated output):
V
OUT
The V nected to the power supply output voltage. When V greater than V
CC
, V
bootstraps VCC.
OUT
T
sets the dis-
OFF
and T
OUT
serves three functions.
ON
OFF
.
The supply voltage of the
does not
CC
pin is direc tly con-
OUT
is
OUT
BLOCK DIAGRAM
UDG-96015
4
TYPICAL CHARACTERISTICS CURVES
UCC1888 UCC2888 UCC3888
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5
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