UCC1857
UCC1857
UCC2857
UCC3857
Isolated Boost PFC Preregulator Controller
PRELIMINARY
FEATURES
∙PFC With Isolation, VO < VIN
∙Single Power Stage
∙Zero Current Switched IGBT
∙Programmable ZCS Time
∙Corrects PF to >0.99
∙Fixed Frequency, Average Current Control
∙Improved RMS Feedforward
∙Soft Start
∙9V to 18V Supply V Range
∙20-Pin DW, N, J, and L Packages
TYPICAL APPLICATION CIRCUIT
DESCRIPTION
The UCC3857 provides all of the control functions necessary for an Isolated Boost PFC Converter. These converters have the advantage of transformer isolation between primary and secondary, as well as an output bus voltage that is lower than the input voltage. By providing both power factor correction and down conversion in a single power processing stage, the UCC3857 is ideal for applications which require high efficiency, integration, and performance.
The UCC3857 brings together the control functions and drivers necessary to generate overlapping drive signals for external IGBT switches, and provides a separate output to drive an external power MOSFET which provides zero current switching (ZCS) for both the IGBTs. Full programmability is provided for the MOSFET driver delay time with an external RC network. ZCS for the IGBT switches alleviates the undesirable turn off losses typically associated with these devices. This allows for higher switching frequencies, smaller magnetic components and higher efficiency. The power factor correction (PFC) portion of the UCC3857 employs the familiar average current control scheme used in previous Unitrode controllers. Internal circuitry changes, however, have simplified the design of the PFC section and improved performance.
(continued)
RECTIFIED
AC INPUT
REF
RAC
ZV |
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T1 |
+ |
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CF |
BIAS |
QA |
Q1 |
Q2 |
VOUT |
SUPPLY |
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– |
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RS |
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ZC |
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FEEDBACK |
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CKT |
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OPTO |
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13 |
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3 |
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4 |
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PKLMT MOUT |
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CA– |
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CAO |
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VIN |
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VD |
1 IAC
MOSDRV 14
2
CRMS IGDRV1 16 UCC3857
10 VA–
IGDRV2 18
11 VAO
DELAY 12 |
REF |
REF |
5 VREF |
SS |
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RT |
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CT |
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PGND |
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AGND |
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20 |
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19 |
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20 |
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UDG-98065
02/99
ABSOLUTE MAXIMUM RATINGS
Input Supply Voltage (VIN, VD) . . . . . . . . . . . . . . . . . . . . . . 18V General Analog/Logic Inputs
(CRMS, MOUT, CA–, VA–, CT, RT, PKLMT)
(Maximum Forced Voltage). . . . . . . . . . . . . . . . –0.3V to 5V IAC (Maximum Forced Current) . . . . . . . . . . . . . . . . . . . 300μA Reference Output Current . . . . . . . . . . . . . . . Internally Limited Output Current (MOSDRV, IGDRV1, IGDRV2)
Pulsed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1A Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200mA Storage Temperature . . . . . . . . . . . . . . . . . . . −65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . −55°C to +150°C Lead Temperature (Soldering, 10 Sec.). . . . . . . . . . . . . +300°C
Unless otherwise indicated, voltages are reference to ground and currents are positive into, negative out of the specified terminal. Pulsed is defined as a less than 10% duty cycle with a maximum duration of 500 s. Consult Packaging Section of Databook for thermal limitations and considerations of packages.
UCC1857
UCC2857
UCC3857
DESCRIPTION (continued)
Controller improvements include an internal 6 bit A-D converter for RMS input line voltage detection, a zero load power circuit, and significantly lower quiescent operating current. The A-D converter eliminates an external 2 pole low pass filter for RMS detection.
This simplifies the converter design, eliminates 2nd harmonic ripple from the feedforward component, and provides an approximate 6 times improvement in input line transient response. The zero load power comparator prevents energy transfer during open load conditions without compromising power factor at light loads. Low startup and operating currents which are achieved through the use of Unitrode's BCDMOS process simplify the auxiliary bootstrap supply design.
Additional features include: under voltage lockout for reliable off-line startup, a programmable over current shutdown, an auxiliary shutdown port, a precision 7.5V reference, a high amplitude oscillator ramp for improved noise immunity, softstart, and a low offset analog square, multiple and divide circuit. Like previous Unitrode PFC controllers, worldwide operation without range switches is easily implemented.
CONNECTION DIAGRAMS
DIL-20, SOIC20 (Top View) |
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PLCC-20 (Top View) |
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J, N and DW Packages |
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L Package |
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IAC |
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CT |
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IAC |
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1 |
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20 |
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CRMS |
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CRMS |
2 |
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19 |
RT |
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MOUT |
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RT |
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MOUT |
3 |
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18 |
IGDRV2 |
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3 |
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2 |
1 |
20 |
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VIN |
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4 |
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18 |
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IGDRV2 |
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VIN |
4 |
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17 |
PGND |
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VREF |
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5 |
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17 |
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PGND |
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VREF |
5 |
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16 |
IGDRV1 |
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AGND |
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16 |
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IGDRV1 |
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AGND |
6 |
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15 |
VD |
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CA– |
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7 |
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15 |
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VD |
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CA– |
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14 |
MOSDRV |
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CAO |
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14 |
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MOSDRV |
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CAO |
8 |
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13 |
PKLMT |
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9 |
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10 |
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12 |
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13 |
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SS |
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PKLMT |
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SS |
9 |
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12 |
DELAY |
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VA– |
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DELAY |
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VA– |
10 |
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11 |
VAO |
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VAO |
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2
UCC1857
UCC2857
UCC3857
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA = 0°C to 70°C for the UCC3857, –40°C to +85°C for the UCC2857, and –55°C to +125°C for the UCC1857, V VIN, VVD = 12V, RT = 19.2K, CT = 680pF. TA = TJ.
PARAMETER |
TEST CONDITIONS |
MIN |
TYP |
MAX |
UNITS |
Input Supply |
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Supply Current, Active |
No Load on Outputs, VVD = VVIN |
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3.5 |
5 |
mA |
Supply Current, Startup |
No Load on Outputs, VVD = VVIN |
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60 |
TBD |
μA |
VIN UVLO Threshold |
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13.75 |
15.5 |
V |
UVLO Threshold Hysteresis |
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3 |
3.75 |
TBD |
V |
Reference |
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Output Voltage (VVREF) |
TJ = 25°C, I REF = 1mA |
7.387 |
7.5 |
7.613 |
V |
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Over Temperature, UCC3857 |
7.368 |
7.5 |
7.631 |
V |
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Over Temperature, UCC1857, UCC2857 |
7.313 |
7.5 |
7.687 |
V |
Load Regulation |
IREF = 1mA to 10mA |
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2 |
10 |
mV |
Line Regulation |
VVIN = VVD = 12V to 16V |
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2 |
15 |
mV |
Short Circuit Current |
VVREF = 0V |
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–55 |
–30 |
mA |
Current Amplifier |
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Input Offset Voltage |
(Note 1) |
–3 |
0 |
3 |
mV |
Input Bias Current |
(Note 1) |
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–50 |
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nA |
Input Offset Current |
(Note 1) |
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25 |
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nA |
CMRR |
VCM = 0V to 1.5V, VCAO = 3V |
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80 |
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dB |
AVOL |
VCM = 0V, VCAO = 2V to 5V |
65 |
85 |
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dB |
VOH |
Load on CAO = 50μA, VMOUT = 1V, VCA– = 0V |
6 |
7 |
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V |
VOL |
Load on CAO = 50μA, VMOUT = 0V, VCA– = 1V |
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0.2 |
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V |
Maximum Output Current |
Source : VCA– = 0V, VMOUT = 1V, VCAO = 3V |
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–150 |
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μA |
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Sink : VCA– = 1V, VMOUT = 0V, VCAO = 3V |
5 |
30 |
50 |
mA |
Gain Bandwidth Product |
fIN = 100kHz, 10mV p – p |
3 |
5 |
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MHz |
Voltage Amplifier |
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Input Voltage |
Measured on VVA–, VVAO = 3V |
2.9 |
3 |
3.1 |
V |
Input Bias Current |
Measured on VVA–, VVAO = 3V |
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–50 |
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nA |
AVOL |
VVAO = 1V to 5V |
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75 |
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dB |
VOH |
Load on VVAO= –50μA, VVA–= 2.8V |
5.3 |
5.55 |
5.7 |
V |
VOL |
Load on VVAO= 50μA, VVA–= 3.2V |
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0.1 |
0.45 |
V |
Maximum Output Current |
Source: VVA– = 2.8V, VVAO = 3V |
–20 |
–12 |
–5 |
mA |
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Sink: VVA– = 3.2V, VVAO= 3V |
5 |
20 |
30 |
mA |
Oscillator |
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Initial Accuracy |
TJ = 25°C |
42.5 |
50 |
57.5 |
kHz |
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40 |
50 |
60 |
kHz |
Voltage Stability |
VVIN = 12V to 18V |
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1 |
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% |
CT Ramp Peak-Valley Amplitude |
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4 |
4.5 |
5 |
V |
CT Ramp Valley Voltage |
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1.5 |
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V |
Output Drivers |
|
|
|
|
|
VOH |
IL = –100mA |
9 |
10 |
|
V |
VOL |
IL = 100mA |
|
0.1 |
0.5 |
V |
Rise Time |
CLOAD = 1nF |
|
25 |
TBD |
ns |
Fall Time |
CLOAD = 1nF |
|
10 |
TBD |
ns |
Trailing Edge Delay |
|
|
|
|
|
Delay Time |
RD = 12k, CD = 200pF, VVAO = 4V |
1.6 |
2 |
2.4 |
μs |
3