The UCC3581 voltage mode pulse width modulator is de
signed to control low power isolated DC - DC converters
in applications such as Subscriber Line Power (ISDN
I.430). Primarily used for single switch forward and
flyback converters, the UCC3581 features BiCMOS cir
cuitry for low startup and operating current, while main
tainingtheabilitytodrivepowerMOSFETsat
frequencies up to 100kHz. The UCC3581 oscillator al
lows the flexibility to program both the frequency and the
maximum duty cycle with two resistors and a capacitor. A
TTL level input is also provided to allow synchronization
to an external frequency source.
The UCC3581 includes programmable soft start circuitry,
overcurrent detection, a 7.5V linear preregulator to con
trol chip V
supply.
The UCC3581 provides functions to maximize light load
efficiency that are not normally found in PWM controllers.
DD during startup, and an on-board 4.0V logic
UDG-95011-1
-
A linear preregulator driver in conjunction with an exter
nal depletion mode N-MOSFET provides initial controller
power. Once the bootstrap supply is functional, the
preregulator is shut down to conserve power. During light
-
load, power is saved by providing a programmable mini
-
mum duty cycle clamp. When a duty cycle below the
minimum is called for, the modulator skips cycles to pro
-
vide the correct average duty cycle required for output
regulation. This effectively reduces the switching fre
quency, saving significant gate drive and power stage
losses.
The UCC3581 is available in 14-pin plastic and ceramic
dual-in-line packages and in a 14-pin narrow body small
-
outline IC package (SOIC). The UCC1581 is specified for
operation from −55°C to +125°C, the UCC2581 is speci
fied for operation from −40°C to +85°C, and the
UCC3581 is specified for operation from 0°C to +70°C.
Lead Temperature (Soldering, 10 sec.). . . . . . . . . . . . . +300°C
= 25°C
D
Unless otherwise specified, all voltages are with respect to
Ground. Currents positive into, negative out of the specified ter
minal. Consult Packaging Section of Databook for thermal limi
tations and considerations of packages.
REF
+ 0.3V)
UCC1581
UCC2581
UCC3581
CONNECTION DIAGRAMS
DIL-14, SOIC-14 (Top View)
N or J, D Packages
-
-
ORDERING INFORMATION
TEMPERATURE RANGEPACKAGE
UCC1581J–55°C to +125°CCDIP
UCC2581D–40°C to +85°CSOIC
UCC2581N–40°C to +85°CPDIP
UCC3581D0°C to +70°CSOIC
UCC3581N0°C to +70°CPDIP
ELECTRICAL CHARACTERISTICS:
from VDD to GND, 1.0µF capacitor from REF to GND, RT1 = 680kΩ, RT2 = 12kΩ, CT = 750pF and T
PARAMETERTEST CONDITIONSMINTYPMAX UNITS
Reference Section
Output VoltageI = –0.2mA3.944.04.06V
Load Regulation–5.0mA < I < –0.2mA2045mV
Undervoltage Lockout Section
Start Threshold6.77.37.9V
Minimum Operating Voltage After Start6.26.87.4V
Hysteresis0.20.50.8V
Note 1: Guaranteed by design.Not 100% tested in production
PIN DESCRIPTIONS
CT: Oscillator timing capacitor pin. Minimum value is
100pF.
DCMIN: Input for programming minimum duty cycle
where pulse skipping begins. This pin can be grounded
to disable minimum duty cycle feature and pulse
skipping.
EN: Enable input. This pin has an internal 10µA pull-up.
A logic low input inhibits the PWM output and causes the
soft start capacitor to be discharged.
GND: Circuit ground.
GT: Pin for controlling the gate of an external depletion
mode N-MOSFET for the startup supply. The external
N-MOSFET regulates VDD to 7.5V until the bootstrap
supply comes up, then GT goes low.
ISEN: Input for overcurrent comparator. This function can
be used for pulse-by-pulse current limiting. The threshold
is 0.5V nominal.
OUT:Gate drive output to external N-MOSFET.
REF: 4.0V reference output. A minimum value bypass
capacitor of 1.0µF is required for stability.
RT1: Resistor pin to program oscillator charging current.
V
20
The oscillator charging current is
92
..•
RT
.
1
See Application Diagram Fig.1.
201.
V
The current into this pin is
RT
.
The value of RT1 should be between 220k and 1MΩ.
RT2: Resistor pin to program oscillator discharge time.
The minimum value of RT2 is 10kΩ. See Application
Diagram Fig.1.
SS: Soft start capacitor pin. The charging current out of
SS is 3.75X the current in RT1.
SYNC: Oscillator synchronization pin. Rising edge
triggered CMOS/TTL compatible input with a 2.1V
threshold. SYNC should be grounded if not used. The
minimum pulse width of the SYNC signal is 100ns.
VC: Control voltage input to PWM comparator. The
nominal control range of VC is 1.0V to 2.5V.
VDD: Chip input power with an 15V internal clamp. VDD
is regulated by startup FET to 7.5V until the bootstrap
voltage comes up. VDD should be bypassed at the chip
with a 0.1µF minimum capacitor.
3
APPLICATION INFORMATION
The UCC3581’s oscillator allows the user the flexibility to
program the frequency and the duty cycle by adjusting
two resistors and a capacitor. Application Diagram Fig. 1
shows these components as RT1, RT2, and C
grams the timing capacitor charging current which results
in a linear ramp charging C
T. Discharge of CT is accom
plished though RT2 which results in a standard RC dis
charge waveform. The oscillator on-time (C
calculated by the formula
tRTC
=••00821.
ONT
The off-time (C
tRTC
OFFT
T discharging) is calculated by the formula
=••0951.
.
.
Resistor RT1 programs the charging current. The current
is:
2.0V
.
RT
1
CT charging current is 9.2 times the current in RT1. RT1
can range from 220kΩ to 1MΩ. Minimum capacitor size
is 100pF, and minimum RT2 size is 10k.
A Block Diagram of the Oscillator is shown in Fig. 2. The
oscillator also has an external synchronization pin.
When a low to high level is detected, and if the oscillator’s output is in the high state (C
T charging), the oscilla-
tor outputimmediately goeslow andC
discharging. The sync input is rising edge sensitive and
is ignored when the oscillator output is low.
T. RT1 pro
T charging) is
T starts
-
1
CT
V
C
-
-
T
BSS129 OR
EQUIV.
IN
GT
D2
REF
V
IN
T1
2
3
VDD
1µF
Q1
4
OUT
5
GND
6
REF
1µF
7
ISEN
D1
Figure 1. Application diagram.
RT2
UCC3581
REF &
E/A
R
L
RT2
UCC1581
UCC2581
UCC3581
14
13SYNC
12RT1
RT1
11EN
10SS
C
9DCMIN
8VC
U1
SS
REF
REF
U1
UDG-99043
Figure 2. Oscillator.
UDG-96105
4
APPLICATION INFORMATION (cont.)
The externally bypassed 4.0V reference is controlled by
undervoltage lockout and chip enable circuitry. The en
able input is internally tied to a 10µA current source
which allows the pin to be driven by an open collector
driver. The part is also enabled if EN floats. The
UCC3581 has a soft start function which requires a user
supplied external timing capacitor. When in soft start
mode, the soft start capacitor, C
constant current source. The soft start current is 3.75X
the current in RT1.
There is an on-chip control amplifier, which when driving
the gate of an external depletion mode N-MOSFET, acts
as a 7.5V linear preregulator supplying VDD directly from
the primary input power line. The preregulator may sub
sequently be fully disabled by a tertiary bootstrap winding
providing a minimum of 8.2V to the VDD pin.
Computation of DCMIN
DCMIN for a given duty cycle is calculated as follows:
()
tt
+
∆
ViDC
=••
OSC
ONOFF
C
T
where:
• i = oscillator charge current = 9.2 . (2.0V/RT1)
• DC = Duty Cycle, as a fraction of 1
• t
= 0.082 • RT1 • CT
ON
•
t
= 0.95 • RT2 • CT
OFF
•
C
= Oscillator Capacitor
T
The CT pin ramp slews from 1V to 2.5V. Therefore, add
∆V to 1V to get DCMIN voltage.
Example: For 10% duty cycle with RT1 = 680kΩ, RT2 =
12kΩ, and CT = 705pF,
SS, is charged with a
UCC1581
UCC2581
UCC3581
A Typical Micropower Application
-
The circuit shown in Fig. 3 illustrates the use of the
UCC3581 in a micropower application. The isolated 5V
flyback power supply uses a minimum of parts and oper
ates over an 8:1 input voltage range (15VDC to 120VDC)
while delivering a regulated 5V output with a load swing
from 0W to 1W. It operates in the discontinuous mode at
light load or high line, and continuous mode at heavier
loads and lower line voltages. Higher input line voltages
are possible by simply increasing the voltage ratings of
C1, Q1, D1 and D2.
The most notable feature of the design is its efficiency.
With a load of 1 watt, the typical efficiency is 82%, drop
-
ping to 70% around 50mW. With a load of only 12.5mW,
the efficiency remains as high as 50%. At this load, with
an input of 50V, the total input current is only 500µA.
Note that the power supply can be disabled by pulling the
UCC3581 enable pin low, in which case the input current
drops to less than 150µA.
The UCC3581 achieves very low losses by means of low
quiescent current and pulse skipping at light loads which
reduces switching losses. The degree of pulse skipping is
controlled by programming the minimum duty cycle. In
this example, the frequency is 35kHz at maximum load
and drops to <2kHz at 12.5mW load (minimum pulse
width of around 6µsec, or 21% duty cycle at 35kHz).
Another way losses are reduced is operating with a VDD
of around 10V rather than the more common 12V to 16V.
At such light primary currents, the MOSFET remains in
full saturation with a gate drive voltage well below 10V.
Gate drive losses are minimized by choosing a MOSFET
with low total gate charge, in this case only 8nC maxi
mum. By choosing a large gate drive resistor, EMI is min
imized by reducing peak currents. Due to pulse skipping,
switching times are less critical for efficiency at light load.
-
-
-
-
∆
ViDC
=••
OSC
V
20
.
92
.
•
=
680
∆
VV
=018.
()
014 182 108 55 10
..sec.sec
•• •+•
k
Therefore,
DCMINVVV
=+=1018118..
()
tt
+
ONOFF
C
T
−−
56
750 1012•
−
Theshuntregulator(LM3411)andoptocoupler
(MOC8100) are also key to the efficiency at such light
loads, and were chosen for their low operating current.
The LM3411 has a quiescent current of only 150µA max
imum (compared to 1mA for the more common TL431).
In addition, because it is not a three terminal device, the
LM3411’s quiescent current does not flow in the
optocoupler LED. Since this bias current is not in the
feedback control path, a higher value pull-up resistor can
be used on the optocoupler output transistor, further re
ducing losses.
5
-
-
TYPICAL APPLICATION
UCC1581
UCC2581
UCC3581
Figure 3. Micropower power supply with 50% efficiency at 12.5mW load.
90
80
25V Line
70
60
100V Line
50
40
Efficiency [%]
30
20
10
0
UDG-96104
101001000
Figure 4. UCC3581 efficiency vs. line and load.
Output Load [mW]
6
APPLICATION INFORMATION (cont.)
A rather large soft start capacitor was chosen to give a
startup time of several hundred milliseconds, reducing
the input surge current while the output is coming up.
UCC1581
UCC2581
UCC3581
If the sync input is used, it should not be left in a high im
pedance state where noise could cause false triggering.
If unused, it should be grounded.
-
Note that for stability, the UCC3581 V
tor needs to be at least 1µF. The V
REF bypass capaci
DD supply also needs
some capacitance to hold it up between pulses at light
load and high line, where the frequency may drop to less
than 1kHz due to pulse skipping. Otherwise it may drop
low enough for the startup MOSFET to be biased on,
lowering efficiency.
TYPICAL CHARACTERISTIC CURVES
4.10
4.08
4.06
4.04
4.02
4.00
3.98
VREF [V]
3.96
3.94
3.92
3.90
-75-50-250255075100 125
TEMPERATURE [°C]
Figure 5. Reference voltage vs. temperature.
The transformer was designed with a standard Magnetics
RM8 ferrite core using P material, gapped for an A
1600mH/1000Turn
2
. The primary consists of 44 turns,
while the 5V secondary has 10 turns and the bootstrap
winding 18 turns. For simplicity, all the windings can be
#28 AWG.A two section bobbin was used to provide high
primary to secondary isolation. A much smaller design,
with reduced isolation, could have been done for this low
power level.
UCC2581JOBSOLETEUTRTBDCall TICall TI
UCC2581QOBSOLETEUTRTBDCall TICall TI
UCC3581DACTIVESOICD1450Green (RoHS &
no Sb/Br)
UCC3581DG4ACTIVESOICD1450Green (RoHS &
no Sb/Br)
UCC3581DTRACTIVESOICD142500 Green (RoHS &
no Sb/Br)
UCC3581DTRG4ACTIVESOICD142500 Green (RoHS &
no Sb/Br)
UCC3581NACTIVEPDIPN1425Green (RoHS &
no Sb/Br)
UCC3581NG4ACTIVEPDIPN1425Green (RoHS &
no Sb/Br)
UCC3581QOBSOLETEUTRTBDCall TICall TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Lead/Ball Finish MSL Peak Temp
CU NIPDAULevel-2-260C-1 YEAR
CU NIPDAULevel-2-260C-1 YEAR
CU NIPDAULevel-2-260C-1 YEAR
CU NIPDAULevel-2-260C-1 YEAR
CU NIPDAULevel-2-260C-1 YEAR
CU NIPDAULevel-2-260C-1 YEAR
CU NIPDAULevel-2-260C-1 YEAR
CU NIPDAULevel-2-260C-1 YEAR
CU NIPDAUN / A for Pkg Type
CU NIPDAUN / A for Pkg Type
(3)
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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