Toshiba TC58FVB641XB-10, TC58FVB641FT-10 Datasheet

TC58FVT641/B641FT/XB-70,-10

TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

64-MBIT (8M × 8 BITS / 4M × 16 BITS) CMOS FLASH MEMORY

DESCRIPTION

The TC58FVT641/B641 is a 67,108,864-bit, 3.0-V read-only electrically erasable and programmable flash memory organized as 8,388,608 words × 8 bits or as 4,194,304 words × 16 bits. The TC58FVT641/B641 features commands for Read, Program and Erase operations to allow easy interfacing with microprocessors. The commands are based on the JEDEC standard. The Program and Erase operations are automatically executed in the chip. The TC58FVT641/B641 also features a Simultaneous Read/Write operation so that data can be read during a Write or Erase operation.

FEATURES

• Power supply voltage

= 2.7 V~3.6 V

• Operating temperature

Ta = −40°C~85°C

• Organization

8M × 8 bits / 4M × 16 bits

• Functions

Simultaneous Read/Write Auto Program, Auto Erase Fast Program Mode / Acceleration Mode Program Suspend/Resume Erase Suspend/Resume data polling / Toggle bit block protection, boot block protection Automatic Sleep, support for hidden ROM area common flash memory interface (CFI) Byte/Word Modes

• Block erase architecture 8 × 8 Kbytes / 127 × 64 Kbytes

• Boot block architecture TC58FVT641FT/XB: top boot block TC58FVB641FT/XB: bottom boot block

• Mode control Compatible with JEDEC standard commands

• Erase/Program cycles

cycles typ.

• Access time 70 ns (C

: 30 pF)

100 ns (CL: 100 pF)

• Power consumption 10 µA (Standby) 30 mA (Read operation) 15 mA (Program/Erase operations)

• Package TSOPI48-P-1220-0.50 (weight: 0.52 g) P-TFBGA63-0911-0.80AZ (Weight: TBD)

000707EBA1

• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of th buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury o damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in th most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc..

• The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction o failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energ control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this documen shall be made at the customer’s own risk.

• The products described in this document are subject to the foreign exchange and foreign trade laws.

• The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed b

TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION o others.

• The information contained herein is subject to change without notice.

2001-09-06 1/53

TC58FVT641/B641FT/XB-70,-10

PIN ASSIGNMENT

(TOP VIEW)

…………TC58FVT641/B641FT PIN NAMES

RESET

/ACCWP

1 48

A15

2 47

A14

3 46

A13

4 45

A12

5 44

A11

6 43

A10

7 42

8 41

9 40

A19

10 39

A20

11 38

12 37 13 36

A21

14 35 15 34

BY/RY

16 33

A18

17 32

A17

18 31

19 30

20 29

21 28

22 27

23 26

24 25

A16

BYTE

VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4

V DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0

A-1, A0~A21 Address Input

DQ0~DQ15 Data Input/Output

Chip Enable Input

Output Enable Input

BYTE Word/Byte Select Input

WE Write Enable Input

BY/RY Ready/Busy Output

Hardware Reset Input

RESET

/ACCWP

VDD Power Supply

VSS Ground

…………TC58FVT641/B641XB

1 2 3 4 5 6 7 8

A NC NC NC NC

B NC NC NC

C A3 A7

D A4 A17 /ACCWP RESET A8 A12

E A2 A6 A18 A21 A10 A14

F A1 A5 A20 A19 A11 A15

G A0 DQ0 DQ2 DQ5 DQ7 A16

H CΕ DQ8 DQ10 DQ12 DQ14 BYTE

J OE DQ9 DQ11 VDD DQ13 DQ15

K VSS DQ1 DQ3 DQ4 DQ6 VSS

L NC NC NC NC

M NC NC NC NC

BY/RY

A9 A13

Write Protect / Program Acceleration Input

2001-09-06 2/53

BLOCK DIAGRAM



TC58FVT641/B641FT/XB-70,-10

DQ0 BY/RY

DQ15

/ACCWP

BYTE

RESET



Control Circuit

   

Command Register

BY/RY Buffer

I/O Buffer

Data Latch

 

Memory Cell

Array

 

Bank 16

A21

A-1

Address Buffer

 

Memory Cell

Array

 

Bank 0

Address Latch

 

Memory Cell

Array

 

Bank 15

2001-09-06 3/53

MODE SELECTION

BYTE MODE WORD MODE

TC58FVT641/B641FT/XB-70,-10

MODE

Read L L H A9 A6 A1 A0 H * D

ID Read (Manufacturer Code)

ID Read (Device Code)

Standby

Output Disable

Write L H

Block Protect 1 L VID

Verify Block Protect L L H VID L H L H * Code Code

Temporary Block Unprotect * * * * * * * VID * * *

Hardware Reset / Standby

Boot Block Protect * * * * * * * * L * *

Notes: * = VIH or VIL, L = VIL, H = VIH

(1) DQ8~DQ14 are High-Z and DQ15/A-1 is Address Input in Byte Mode.

Addresses are A21~A0 in Word Mode (

(2) Pulse input

CE OE

L L H VID L L L H * Code Code

L L H VID L L H H * Code Code

H * * * * * * H * High-Z High-Z

* H H * * * * * * High-Z High-Z

* * * * * * * L * High-Z High-Z

WE A9 A6 A1 A0

(2)

A9 A6 A1 A0 H * D

(2)

VID L H L H * * *

BYTE = VIH), A21~A-1 in Byte Mode ( BYTE = VIL).

RESET

/ACCWP

DQ0~DQ7

(1)

DQ0~DQ15

OUT

ID CODE TABLE

(3)

(1)

CODE TYPE A21~A12 A6 A1 A0 CODE (HEX)

Manufacturer Code * L L L 0098H

Device Code

Verify Block Protect BA

Notes: * = VIH or VIL, L = VIL, H = VIH

(1) DQ8~DQ14 are High-Z and DQ15/A-1 is Address Input in Byte Mode. (2) BA: Block Address (3) 0001H - Protected Block

0000H - Unprotected Block

TC58FVT641 * L L H 0093H

TC58FVB641 * L L H 0095H

(2)

L H L Data

2001-09-06 4/53

COMMAND SEQUENCES

TC58FVT641/B641FT/XB-70,-10

BUS

COMMAND

SEQUENCE

Read/Reset 1 XXXH F0H

Read/Reset

ID Read

Auto-Program

Program Suspend 1 BK

Program Resume 1 BK

Auto Chip

Erase

Auto Block

Erase

Block Erase Suspend 1 BK

Block Erase Resume 1 BK

Bloc k Protec t 2 4 XXXH 60H BPA

Verify Block

Protect

Fast Program

Set

Fast P rogram 2 XXXH A0H PA

Fast Program R eset 2 XXXH 90H XXXH F0H

Hidden ROM

Mode Entry

Hidden ROM

Program

Hidden ROM

Erase

Hidden ROM

Mode Exit

Query

Command

WRITE

CYCLES

REQ’D

Word 555H 2AAH 555H

Byte

Word 555H 2AAH

Byte

Word 555H 2AAH 555H

Byte

Word 555H 2AAH 555H 555H 2AAH 555H

Byte

Word 555H 2AAH 555H 555H 2AAH

Byte

Word 555H 2AAH

Byte

Word 555H 2AAH 555H

Byte

Word 555H 2AAH 555H

Byte

Word 555H 2AAH 555H

Byte

Word 555H 2AAH 555H 555H 2AAH

Byte

Word 555H 2AAH 555H

Byte

Word

Byte

FIRST BUS

WRITE CYCLE

Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data

AAAH

AAH

(3)

B0H

(3)

30H

AAH

(3)

B0H

(3)

30H

AAH

(3)

55H

(3)

AAH

98H CA

SECOND BUS

WRITE CYCLE

555H

55H

(9)

60H XXXH 40H BPA

55H

(6)

55H

(11)

THIRD BUS

WRITE CYCLE

AAAH

(3)

555H

(3)

AAAH

(3)

555H

(3)

AAAH

(7)

(13)

AAAH

(12)

FOURTH BUS

WRITE CYCLE

F0H RA

90H IA

A0H PA

80H

90H BPA

20H

88H

A0H PA

80H

90H XXXH 00H

(1)

(4)

(6)

AAAH

(6)

AAAH

(9)

BPD

(9)

BPD

AAH

FIFTH BUS

WRITE CYCLE

(2)

(5)

(7)

55H

555H

55H BA

555H

(10)

(7)

55H BA

555H

SIXTH BUS

WRITE CYCLE

AAAH

(8)

Notes: The system should generate the following address patterns:

Word Mode: 555H or 2AAH on address pins A10~A0 Byte Mode: AAAH or 555H on address pins A10~A-1 DQ8~DQ15 are ignored in Word Mode.



(1) RA: Read Address (2) RD: Read Data (3) BK: Bank Address = A21~A15 (4) IA: Bank Address and ID Read Address (A6, A1, A0)

Bank Address = A21~A15 Manufacturer Code = (0, 0, 0)

Device Code = (0, 0, 1) (5) ID: ID Data (6) PA: Program Address



(7) PD: Program Data (8) BA: Block Address = A21~A12 (9) BPA: Block Address and ID Read Address (A6, A1, A0)

Block Address = A21~A12

ID Read Address = (0, 1, 0) (10) BPD: Verify Data (11) CA: CFI Address (12) CD: CFI Data (13) F0H: 00H is valid too

10H

30H

2001-09-06 5/53

TC58FVT641/B641FT/XB-70,-10

SIMULTANEOUS READ/WRITE OPERATION

The TC58FVT641/B641 features a Simultaneous Read/Write operation. The Simultaneous Read/Write operation

enables the device to simultaneously write data to or erase data from a bank while reading data from another bank.

The TC58FVT641/B641 has a total of seventeen banks: 1 bank of 0.5 Mbits, 1 bank of 3.5 Mbits and 15 banks of 4 Mbits. Banks can be switched between using the bank addresses (A21~A15). For a description of bank blocks and addresses, please refer to the Block Address Table and Block Size Table.

The Simultaneous Read/Write operation cannot perform multiple operations within a single bank. The table below shows the operation modes in which simultaneous operation can be performed.

Note that during Auto-Program execution or Auto Block Erase operation, the Simultaneous Read/Write operation cannot read data from addresses in the same bank which have not been selected for operation. Data from these addresses can be read using the Program Suspend or Erase Suspend function, however.

SIMULTANEOUS READ/WRITE OPERATION

STATUS OF BANK ON WHICH OPERATION IS BEING

PERFORMED

Read Mode

ID Read Mode

Auto-Program Mode

Fast Program Mode

Program Suspend Mode

Auto Block Erase Mode

Auto Multiple Block Erase Mode

Erase Suspend Mode

Program Suspend during Erase Suspend

CFI Mode

(1) Only Command Mode is valid. (2) Including times when Acceleration Mode is in use. (3) If the selected blocks are spread across all nine banks, simultaneous operation cannot be carried out.

(1)

(2)

(3)

STATUS OF OTHER BANKS

Read Mode

OPERATION MODES

In addition to the Read, Write and Erase Modes, the TC58FVT641/B641 features many functions including block protection and data polling. When incorporating the device into a deign, please refer to the timing charts and flowcharts in combination with the description below.

READ MODE

To read data from the memory cell array, set the device to Read Mode. In Read Mode the device can perform

high-speed random access as asynchronous ROM.

The device is automatically set to Read Mode immediately after power-on or on completion of automatic operation. A software reset releases ID Read Mode and the lock state which the device enters if automatic operation ends abnormally, and sets the device to Read Mode. A hardware reset terminates operation of the device and resets it to Read Mode. When reading data without changing the address immediately after power-on, either input a hardware Reset or change

CE from H to L.

2001-09-06 6/53

TC58FVT641/B641FT/XB-70,-10

ID Read Mode

ID Read Mode is used to read the device maker code and device code. The mode is useful in that it allows EPROM programmers to identify the device type automatically.

ID read can be executed in two ways, as follows: (1) Applying V

This method is used mainly by EPROM programmers. Applying V Mode, outputting the maker code from address 00H and the device code from address 01H. Releasing V from A9 returns the device to Read Mode. With this method all banks are set to ID Read Mode; thus, simultaneous operation cannot be performed.

(2) Input command sequence

With this method simultaneous operation can be performed. Inputting an ID Read command sets the specified bank to ID Read Mode. Banks are specified by inputting the bank address (BK) in the third Bus Write cycle of the Command cycle. To read an ID code, the bank address as well as the ID read address must be specified. The maker code is output from address BK + 00; the device code is output from address BK +

01. From other banks data are output from the memory cells. Inputting a Reset command releases ID Read Mode and returns the device to Read Mode.

Access time in ID Read Mode is the same as that in Read Mode. For a list of the codes, please refer to the ID Code Table.

Standby Mode

There are two ways to put the device into Standby Mode.

(1) Control using

With the device in Read Mode, input V Mode and the current will be reduced to the standby current (I process of performing simultaneous operation, the device will not enter Standby Mode but will instead cause the operating current to flow.

(2) Control using

With the device in Read Mode, input V current will be reduced to the standby current (I simultaneous operation, this method will terminate the current operation and set the device to Standby Mode. This is a hardware reset and is described later.

In Standby Mode DQ is put in High-Impedance state.

Auto-Sleep Mode

This function suppresses power dissipation during reading. If the address input does not change for 150 ns, the device will automatically enter Sleep Mode and the current will be reduced to the standby current (I However, if the device is in the process of performing simultaneous operation, the device will not enter Standby Mode but will instead cause the operating current to flow. Because the output data is latched, data is output in Sleep Mode. When the address is changed, Sleep Mode is automatically released, and data from the new address is output.

Output Disable Mode

Inputting V

to A9

to A9 sets the device to ID Read

CE and RESET

± 0.3 V to CE and RESET . The device will enter Standby

). However, if the device is in the

DDS1

RESET only

± 0.3 V to RESET . The device will enter Standby Mode and the

). Even if the device is in the process of performing

DDS1

to OE disables output from the device and sets DQ to High-Impedance.

DDS2

2001-09-06 7/53

TC58FVT641/B641FT/XB-70,-10

Command Write

The TC58FVT641/B641 uses the standard JEDEC control commands for a single-power supply E Command Write is executed by inputting the address and data into the Command Register. The command is written by inputting a pulse to written by inputting a pulse to either input and DQ8~DQ15 are ignored.

and enter Read Mode. If an undefined command is input, the Command Register will be reset and the device will enter Read Mode.

WE or CE . The data is latched on the rising edge of either WE or CE . DQ0~DQ7 are valid for data

To abort input of the command sequence use the Reset command. The device will reset the Command Register

WE with CE = VIL and OE = VIH ( WE control). The command can also be

CE with WE = VIL ( CE control). The address is latched on the falling edge of

Software Reset

Apply a software reset by inputting a Read/Reset command. A software reset returns the device from ID Read Mode or CFI Mode to Read Mode, releases the lock state if automatic operation has ended abnormally, and clears the Command Register.

Hardware Reset

A hardware reset initializes the device and sets it to Read Mode. When a pulse is input to the device abandons the operation which is in progress and enters Read Mode after t hardware reset is applied during data overwriting, such as a Write or Erase operation, data at the address or block being written to at the time of the reset will become undefined.

After a hardware reset the device enters Read Mode if The DQ pins are High-Impedance when operations and input of any command are allowed.

RESET = VIL. After the device has entered Read Mode, Read

RESET = VIH or Standby Mode if RESET = VIL.

READY

Comparison between Software Reset and Hardware Reset

PROM. A

RESET for tRP,

. Note that if a

ACTION SOFTWARE RESET HARDWARE RESET

Releases ID Read Mode or CFI Mode. True True

Clears the Command Register. True True

Releases the lock state if automatic operation has ended abnormally. True True

Stops any automatic operation which is in progress. False True

Stops any operation other than the above and returns the device to Read Mode.

/Word Mode

BYTE

BYTE is used select Word Mode (16 bits) or Byte Mode (8 bits) for the TC58FVT641/B641. If VIH is input to

BYTE , the device will operate in Word Mode. Read data or write commands using DQ0~DQ15. When VIL is input to DQ8~DQ14 will become High-Impedance.

BYTE , read data or write commands using DQ0~DQ7. DQ15/A-1 is used as the lowest address.

False True

2001-09-06 8/53

TC58FVT641/B641FT/XB-70,-10

Auto-Program Mode

The TC58FVT641/B641 can be programmed in either byte or word units. Auto-Program Mode is set using the Program command. The program address is latched on the falling edge of the on the rising edge of the fourth Bus Write cycle (with of the executed by the chip. The device status during programming is indicated by the Hardware Sequence flag. To read the Hardware Sequence flag, specify the address to which the Write is being performed

cannot be accepted. To terminate execution, use a hardware reset. Note that if the Auto-Program operation is terminated in this manner, the data written so far is invalid.

rising edge of the

return to Read Mode. The device status is indicated by the Hardware Sequence flag. Either a Reset command or a hardware reset is required to return the device to Read Mode after a failure. If a programming operation fails, the block which contains the address to which data could not be programmed should not be used.

cells which contain 0s. If this is attempted, execution of Auto Program will fail. This is a user error, not a device error. A cell containing 0 must be erased in order to set it to 1.

WE signal in the fourth Bus Write cycle. The Program and Program Verify commands are automatically

During Auto Program execution, a command sequence for the bank on which execution is being performed

Any attempt to program a protected block is ignored. In this case the device enters Read Mode 3 µs after the

WE signal in the fourth Bus Write cycle.

If an Auto-Program operation fails, the device remains in the programming state and does not automatically

The device allows 0s to be programmed into memory cells which contain a 1. 1s cannot be programmed into

WE control). Auto programming starts on the rising edge

Fast Program Mode

Fast Program is a function which enables execution of the command sequence for the Auto Program to be completed in two cycles. In this mode the first two cycles of the command sequence, which normally requires four cycles, are omitted. Writing is performed in the remaining two cycles. To execute Fast Program, input the Fast Program command. Write in this mode uses the Fast Program command but operation is the same at that for ordinary Auto-Program. The status of the device is indicated by the Hardware Sequence flag and read operations can be performed as usual. To exit this mode, the Fast Program Reset command must be input. When the command is input, the device will return to Read Mode.

Acceleration Mode

The TC58FVT641/B641 features Acceleration Mode which allows write time to be reduced. Applying V

WP or ACC automatically sets the device to Acceleration Mode. In Acceleration Mode, Block Protect Mode changes to Temporary Block Unprotect Mode. Write Mode changes to Fast Program Mode. Modes are switched by the Program Mode. Operation of Write is the same as in Auto-Program Mode. Removing V terminates Acceleration Mode.

/ACCWP signal; thus, there is no need for a Temporary Block Unprotect operation or to set or reset Fast

WE signal and data is latched

from /ACCWP

ACC

2001-09-06 9/53

TC58FVT641/B641FT/XB-70,-10

Program Suspend/Resume Mode

Program Suspend is used to enable Data Read by suspending the Write operation. The device accepts a Program Suspend command in Write Mode (including Write operations performed during Erase Suspend) but ignores the command in other modes. When the command is input, the address of the bank on which Write is being performed must be specified. After input of the command, the device will enter Program Suspend Read Mode after t

During Program Suspend, Cell Data Read, ID Read and CFI Data Read can be performed. When Data Write is suspended, the address to which Write was being performed becomes undefined. ID Read and CFI Data Read are the same as usual.

After completion of Program Suspend input a Program Resume command to return to Write Mode. When inputting the command, specify the address of the bank on which Write is being performed. If the ID Read or CFI Data Read functions is being used, abort the function before inputting the Resume command. On receiving the Resume command, the device returns to Write Mode and resumes outputting the Hardware Sequence flag for the bank to which data is being written.

Program Suspend can be run in Fast Program Mode or Acceleration Mode. However, note that when running Program Suspend in Acceleration Mode, V

Auto Chip Erase Mode

The Auto Chip Erase Mode is set using the Chip Erase command. An Auto Chip Erase operation starts on the rising edge of verified as erased by the chip. The device status is indicated by the Hardware Sequence flag.

Command input is ignored during an Auto Chip Erase. A hardware reset can interrupt an Auto Chip Erase operation. If an Auto Chip Erase operation is interrupted, it cannot be completed correctly. Hence an additional Erase operation must be performed.

Any attempt to erase a protected block is ignored. If all blocks are protected, the Auto Erase operation will not be executed and the device will enter Read mode 100 µs after the rising edge of the cycle.

If an Auto Chip Erase operation fails, the device will remain in the erasing state and will not return to Read Mode. The device status is indicated by the Hardware Sequence flag. Either a Reset command or a hardware reset is required to return the device to Read Mode after a failure.

In this case it cannot be ascertained which block the failure occurred in. Either abandon use of the device altogether, or perform a Block Erase on each block, identify the failed block, and stop using it. The host processor must take measures to prevent subsequent use of the failed block.

SUSP

must not be released.

ACC

WE in the sixth bus cycle. All memory cells are automatically preprogrammed to 0, erased and

WE signal in the sixth bus

2001-09-06 10/53

TC58FVT641/B641FT/XB-70,-10

Auto Block Erase / Auto Multi-Block Erase Modes

The Auto Block Erase Mode and Auto Multi-Block Erase Mode are set using the Block Erase command. The block address is latched on the falling edge of the soon as the Erase Hold Time (t are erased, the sixth Bus Write cycle is repeated with each block address and Auto Block Erase command being input within the Erase Hold Time (this constitutes an Auto Multi-Block Erase operation). If a command other than an Auto Block Erase command or Erase Suspend command is input during the Erase Hold Time, the device will reset the Command Register and enter Read Mode. The Erase Hold Time restarts on each successive rising edge of preprogrammed to 0, erased and verified as erased by the chip. The device status is indicated by the setting of the Hardware Sequence flag. When the Hardware Sequence flag is read, the addresses of the blocks on which auto-erase operation is being performed must be specified. If the selected blocks are spread across all nine banks, simultaneous operation cannot be carried out.

All commands (except Erase Suspend) are ignored during an Auto Block Erase or Auto Multi-Block Erase operation. Either operation can be aborted using a Hardware Reset. If an auto-erase operation is interrupted, it cannot be completed correctly; therefore, a further erase operation is necessary to complete the erasing.

Any attempt to erase a protected block is ignored. If all the selected blocks are protected, the auto-erase operation is not executed and the device returns to Read Mode 100 µs after the rising edge of the the last bus cycle.

If an auto-erase operation fails, the device remains in Erasing state and does not return to Read Mode. The device status is indicated by the Hardware Sequence flag. After a failure either a Reset command or a Hardware Reset is required to return the device to Read Mode. If multiple blocks are selected, it will not be possible to ascertain the block in which the failure occurred. In this case either abandon use of the device altogether, or perform a Block Erase on each block, identify the failed block, and stop using it. The host processor must take measures to prevent subsequent use of the failed block.

WE . Once operation starts, all memory cells in the selected block are automatically

) has elapsed after the rising edge of the WE signal. When multiple blocks

BEH

Erase Suspend / Erase Resume Modes

Erase Suspend Mode suspends Auto Block Erase and reads data from or writes data to an unselected block. The Erase Suspend command is allowed during an auto block erase operation but is ignored in all other oreration modes. When the command is input, the address of the bank on which Erase is being performed must be specified.

In Erase Suspend Mode only a Read, Program or Resume command can be accepted. If an Erase Suspend command is input during an Auto Block Erase, the device will enter Erase Suspend Read Mode after t device status (Erase Suspend Read Mode) can be verified by checking the Hardware Sequence flag. If data is read consecutively from the block selected for Auto Block Erase, the DQ2 output will toggle and the DQ6 output will stop toggling and

Inputting a Write command during an Erase Suspend enables a Write to be performed to a block which has not been selected for the Auto Block Erase. Data is written in the usual manner.

To resume the Auto Block Erase, input an Erase Resume command. On input of the command, the address of the bank on which the Write was being performed must be specified. On receiving an Erase Resume command, the device returns to the state it was in when the Erase Suspend command was input. If an Erase Suspend command is input during the Erase Hold Time, the device will return to the state it was in at the start of the Erase Hold Time. At this time more blocks can be specified for erasing. If an Erase Resume command is input during an Auto Block Erase, Erase resumes. At this time toggle output of DQ6 resumes and 0 is output on

BY/RY .

BY/RY will be set to High-Impedance.

WE signal in the sixth bus cycle. The block erase starts as

WE signal in

SUSE

. The

2001-09-06 11/53

TC58FVT641/B641FT/XB-70,-10

BLOCK PROTECTION

Block Protection is a function for disabling writing and erasing specific blocks. Block protection can be carried out in two ways: by supplying a high voltage (V voltage and a command sequence (see Block protection 2).

(1) Block protection 1

Specify a device block address and make the following signal settings A9 = = A0 = A6 = V protection circuit. Block protection can be verified using the Verify Block Protect command. Inputting V on

OE sets the device to Verify Mode. 01H is output if the block is protected and 00H is output if the block is unprotected. If block protection was unsuccessful, the operation must be repeated. Releasing V and

OE terminates this mode.

(2) Block protection 2

Applying V first cycle of the command sequence is the Set-up command. In the second cycle, the Block Protect command is input, in which a block address and A1 = V block protection circuit. There is a wait of t necessary during this time. In the third cycle the Verify Block Protect command is input. This command verifies the write to the block protection circuit. Read is performed in the fourth cycle. If the protection operation is complete, 01H is output. If a value other than 01H is output, block protection is not complete and the Block Protect command must be input again. Removing the V mode.

. Now when a pulse is input to WE for t

to RESET and inputting the Block Protect 2 command also performs block protection. The

Temporary Block Unprotection

The TC58FVT641/B641 has a temporary block unprotection feature which disables block protection for all protected blocks. Unprotection is enabled by applying V can be performed on all blocks except the boot blocks which have been protected by the Boot Block Protect operation. The device returns to its previous state when V previously protected blocks will be protected again.

Verify Block Protect

The Verify Block Protect command is used to ascertain whether a block is protected or unprotected. Verification is performed either by inputting the Verify Block Protect command or by applying V as for ID Read Mode, and setting the block address = A0 = A6 = V is output. If the block is unprotected, 00H is output.

Boot Block Protection

Boot block protection temporarily protects certain boot blocks using a method different from ordinary block protection. Neither V on bottom boot blocks are BA0 and BA1. Inputting V necessary to protect these blocks, the ordinary Block Protection Mode must be used.

/ACCWP . The target blocks are the two pairs of boot blocks. The top boot blocks are BA133 and BA134; the

nor a command sequence is required. Protection is performed simply by inputting VIL

) to the device (see Block protection 1) or by supplying a high

OE = VID, A1 = VIH and CE

, the device will start to write to the block

PPLH

from A9

and A0 = A6 = VIL are input. Now the device writes to the

until this write is completed; however, no intervention is

PPLH

input from RESET exits this

to the RESET pin. Now Write and Erase operations

is removed from the RESET pin. That is,

to the A9 pin,

and A1 = VIH. If the block is protected, 01H

on /ACCWP releases the mode. From now on, if it is

2001-09-06 12/53

TC58FVT641/B641FT/XB-70,-10

Hidden ROM Area

The TC58FVT641/B641 features a 64-Kbyte hidden ROM area which is separate from the memory cells. The area consists of one block. Data Read, Write and Protect can be performed on this block. Because Protect cannot be released, once the block is protected, data in the block cannot be overwritten.

The hidden ROM area is located in the address space indicated in the HIDDEN ROM AREA ADDRESS TABLE. To access the Hidden ROM area, input a Hidden ROM Mode Entry command. The device now enters Hidden ROM Mode, allowing Read, Write, Erase and Block Protect to be executed. Write and Erase operations are the same as auto operations except that the device is in Hidden ROM Mode. However, regarding write operation, Accelaration mode can not be performed during Hidden ROM Mode. To protect the hidden ROM area, use the block protection function. The operation of Block Protect here is the same as a normal Block Protect except that V released, even using the temporary block unprotection function. Use Block Protect carefully. Note that in Hidden ROM Mode, simultaneous operation cannot be performed. Therefore, do not attempt to access areas other than the hidden ROM area.

To exit Hidden ROM Mode, use the Hidden ROM Mode Exit command. This will return the device to Read Mode.

HIDDEN ROM AREA ADDRESS TABLE

rather than VID is input to RESET . Once the block has been protected, protection cannot be

TYPE

TC58FVT641 TOP BOOT BLOCK 7F0000H~7FFFFFH 64 Kbytes 3F8000H~3FFFFFH 32 Kwords

TC58FVB641 BOTTOM BOOT BLOCK 000000H~00FFFFH 64 Kbytes 000000H~007FFFH 32 Kwords

BOOT BLOCK

ARCHITECTURE

ADDRESS RANGE SIZE ADDRESS RANGE SIZE

BYTE MODE WORD MODE

2001-09-06 13/53

TC58FVT641/B641FT/XB-70,-10

COMMON FLASH MEMORY INTERFACE (CFI)

The TC58FVT641/B641 conforms to the CFI specifications. To read information from the device, input the Query command followed by the address. In Word Mode DQ8~DQ15 all output 0s. To exit this mode, input the Reset command.

CFI CODE TABLE

ADDRESS A6~A0 DATA DQ15~DQ0 DESCRIPTION

10H 11H 12H

13H 14H

15H 16H

17H 18H

19H 1AH

1BH 0027H

1CH 0036H

1DH 0000H VPP (min) voltage

1EH 0000H VPP (max) voltage

1FH 0004H Typical time-out per single byte/word write (2N µs)

20H 0000H Typical time-out for minimum size buffer write (2N µs)

0051H 0052H 0059H

0002H 0000H

0040H 0000H

0000H 0000H

ASCII string “QRY”

Primary OEM command set 2: AMD/FJ standard type

Address for primary extended table

Alternate OEM command set 0: none exists

Address for alternate OEM extended table

(min) (Write/Erase)

DQ7~DQ4: 1 V DQ3~DQ0: 100 mV

(max) (Write/Erase)

DQ7~DQ4: 1 V DQ3~DQ0: 100 mV

21H 000AH Typical time-out per individual block erase (2N ms)

22H 0000H Typical time-out for full chip erase (2N ms)

23H 0005H Maximum time-out for byte/word write (2N times typical)

24H 0000H Maximum time-out for buffer write (2N times typical)

25H 0004H Maximum time-out per individual block erase (2N times typical)

26H 0000H Maximum time-out for full chip erase (2N times typical)

27H 0017H Device Size (2N byte)

28H 29H

2AH 2BH

0002H 0000H

0000H 0000H

Flash device interface description 2: ×8/×16

Maximum number of bytes in multi-byte write (2

)

2001-09-06 14/53

TC58FVT641/B641FT/XB-70,-10

ADDRESS A6~A0 DATA DQ15~DQ0 DESCRIPTION

2CH 0002H Number of erase block regions within device

2DH 2EH 2FH 30H

31H 32H 33H 34H

40H 41H 42H

43H 0031H Major version number, ASCII

44H 0031H Minor version number, ASCII

45H 0000H

46H 0002H

47H 0001H

0007H 0000H 0020H 0000H

007EH 0000H 0000H 0001H

0050H 0052H 0049H

Erase Block Region 1 information Bits 0~15: y = block number Bits 16~31: z = block size (z × 256 bytes)

Erase Block Region 2 information

ASCII string “PRI”

Address-Sensitive Unlock 0: Required 1: Not required

Erase Suspend 0: Not supported 1: For Read-only 2: For Read & Write

Block Protect 0: Not supported X: Number of blocks per group

Block Temporary Unprotect

48H 0001H

49H 0004H Block Protect/Unprotect scheme

4AH 0001H

4BH 0000H

4CH 0000H

4DH 0085H

4EH 0095H

4FH 000XH

50H 0001H

0: Not supported 1: Supported

Simultaneous operation 0: Not supported 1: Supported

Burst Mode 0: Not supported

Page Mode 0: Not supported

(min) voltage

ACC

DQ7~DQ4: 1 V DQ3~DQ0: 100 mV

(max) voltage

ACC

DQ7~DQ4: 1 V DQ3~DQ0: 100 mV

Top/Bottom Boot Block Flag 2: TC58FVB641 3: TC58FVT641

Program Suspend 0: Not supported 1: Supported

2001-09-06 15/53

TC58FVT641/B641FT/XB-70,-10

HARDWARE SEQUENCE FLAGS

The TC58FVT641/B641 has a Hardware Sequence flag which allows the device status to be determined during an auto mode operation. The output data is read out using the same timing as that used when Read Mode. The

BY/RY output can be either High or Low.

The device re-enters Read Mode automatically after an auto mode operation has been completed successfully. The Hardware Sequence flag is read to determine the device status and the result of the operation is verified by comparing the read-out data with the original data.

STATUS DQ7 DQ6 DQ5 DQ3 DQ2 BY/RY

CE = OE = VIL in

Auto Programming

Read in Program Suspend

Erase Hold Time

In Auto

Erase

In Progress

In Erase Suspend

Auto Programming

Time Limit Exceeded

Notes:DQ outputs cell data and BY/RY goes High-Impedence when the operation has been completed.

Auto Erase 0 Toggle 1 1 NA 0

Programming in Erase Suspend

DQ0 and DQ1 pins are reserved for future use. 0 is output on DQ0, DQ1 and DQ4. (1) Data output from an address to which Write is being performed is undefined. (2) Output when the block address selected for Auto Block Erase is specified and data is read from there.

During Auto Chip Erase, all blocks are selected.

(3) Output when a block address not selected for Auto Block Erase of same bank as selected block is specified and data is

read from there.

Auto Erase

Read

Programming

(1)

Data Data Data Data Data High-Z

Selected

Not-selected

Not-selected 0 Toggle 0 1 1 0

Not-selected Data Data Data Data Data High-Z

Not-selected

(2)

0 Toggle 0 0 Toggle 0

(3)

0 Toggle 0 0 1 0

Selected 0 Toggle 0 1 Toggle 0

Selected 1 1 0 0 Toggle High-Z

Selected

Toggle 0 0 1 0

7DQ

Toggle 0 0 Toggle 0

7DQ

Toggle 0 0 1 0

7DQ

Toggle 1 0 1 0

7DQ

Toggle 1 0 NA 0

7DQ

DQ7 ( polling)

DATA

During an Auto-Program or auto-erase operation, the device status can be determined using the data polling

function.

DATA polling begins on the rising edge of WE in the last bus cycle. In an Auto-Program operation, DQ7 outputs inverted data during the programming operation and outputs actual data after programming has finished. In an auto-erase operation, DQ7 outputs 0 during the Erase operation and outputs 1 when the Erase operation has finished. If an Auto-Program or auto-erase operation fails, DQ7 simply outputs the data.

When the operation has finished, the address latch is reset. Data polling is asynchronous with the

signal.

2001-09-06 16/53

+ 37 hidden pages

Toshiba TC58FVB641XB-10, TC58FVB641FT-10 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual