When the power supply is being turned on, you may not remove this laser cautions label. If it removes, radiation of a laser
may be recceived.
PREPARATION OF SERVICING
Pickup Head consists of a laser diode that is very susceptible to external static electricity.
Although it operates properly after replacement, if it was subject to electrostatic discharge during replacement,
its life might be shortened. When replacing, use a conductive mat, soldering iron with ground wire, etc. to
protect the laser diode from damage by static electricity.
Send each LSI hard RST
command and initial command.
Pickup head is positioned at
transmission initial position.
Is tray closed?
Pin 5 of CN502,
TCLS=L
Y
2
NG
Disc presence/absence and
disc judgement
Is a disc present?
Y
DVD or CD initial setting.
N
Tray close operation
Pin 126 of IC605: LDMP = H/L
Pin 127 of IC605: LDMN = L
Tray stops.
Pin 126 of IC605: LDMP = H
Pin 127 of IC605: LDMN = L
N
Laser OFF
Display: INSERT DISC
Monitor screen: NO DISC
1
Is tray closed?
Pin 5 of CN502:
TCLS = L
Y
N
DVD single (single-layer)
DVD single
Initial setting.
DVD single
(single-layer)/DVD dual
(dual-layer)/CD?
DVD dual (dual-layer)
DVD dual
Initial setting.
To each disc playback process.
Fig. 1-3-1
1-29
CD
CD
Initial setting.
Page 34
1
Pickup (P.U.) transmission initial
operation does not occur.
The pickup transmission initial operation is carried out to
determine the initial position by transmitting the pickup to the
innermost position once (start-limit switch (pin 4 of CN503)
develops "L".) and to the external direction at low speed
(start-limit switch develops "H", turning off the switch.).
Does pulse of
1.65V 1.65V develop at
pin 162 of IC401?
Y
Check feed gear.
N
Check BUS between IC401
and IC605 and oscillation.
Fig. 1-3-2
2-1
"No disc" misjudgement display of
N
disc presence.
Does lens move with
UP/DOWN full stroke in
focus direction?
Y
N
3
Does focus search
voltage of 1.65V 0.4V develop
at pin 1 of IC503 (E537)?
Y
Does search signal
output at both edges of focus coil?
(Pins 15 to 18 of CN501)
Y
Check pickup head
and wiring.
Is laser current normal?
Y
Does RFSB signal
develop more than 0.3V?
Y
Check peripheral
circuit of IC605.
N
N
Check IC401.
Check IC502.
Fig. 1-3-3
N
Check IC502.
Lens cleaning.
Replace pickup head.
1-30
Page 35
2-2
Disc kind misjudgement
(Initial setting is NG.)
N
Check IC502.
Lens cleaning.
Replace pickup head.
lop I min
Check wiring for
pickup head.
Check pins 13, 14
and 15 of IC502
serial bus.
Check peripheral
circuits of IC502,
Q501, Q502.
To turn on each laser diode forcibly, press the following buttons on the remote controller.
DVD LD: ZOOM, 0, 3, 0, ZOOM
CD LD: ZOOM, 0, 3, 1, ZOOM
After checked the laser current, press POWER or OPEN/CLOSE button to turn it off.
CAUTION
The laser ray emitting out from the pickup head is very harmful to your eyes.
Keep your eyes from the objective lens at least 300mm distance during the pickup head operating.
When you perform solder removal work, please turn OFF a set power supply and perform the
ground of human body and a tool.
Are FE and RFSB
signals for each disc normal?
Y
Check peripheral
circuit of IC605.
Fig. 1-3-4
3
Check laser operating current.
Check laser current.
I min lop I max
Y
Check FE and RFSB signal
lop I max
lop 200 mA
Check solder removal
of the short land for
laser diode protection.
PLL works as a servo loop to generate a clock signal for reading RF
signal binary data. With the PLL locked, the eye pattern is identified
clearly when triggered with the read clock PLCK.
Electronic parts are susceptible to static electricity and may easily damaged, so do not forget to take a proper grounding
treatment as required.
Many screws are used inside the unit. To prevent missing, dropping, etc. of the screws, always use a magnetized screwdriver in servicing. Several kinds of screws are used and some of them need special cautions. That is, take care of the
tapping screws securing molded parts and fine pitch screws used to secure metal parts. If they are used improperly , the
screw holes will be easily damaged and the parts can not be fixed.
ADJUSTMENT PROCEDURES
PART REPLACEMENT AND
1. REPLACEMENT OF MECHANICAL PARTS
1-1. Cabinet Replacement
1-1-1. Top Cover
1. Remove five screws (1) and remove the top cover (2).
Top cover (2)
Screw (1)
Screws (1)
Screw (1)
1-1-2. Clamper Stay
<Removal>
1. Remove two screws (1).
2. Release two claws and remove the clamper stay (2).
Clamper
stay (2)
Claw
SECTION 2
Screws (1)Clamper stay (2)
Clamper stay (2)
Claw
Fig. 2-1-1
2-1
Spring
Claws
Fig. 2-1-2
Page 42
<Mounting >
1. The spring for tray side pressure is inserted into the
portion “A”. (Refer to Fig. 2-1-2.)
2. By referring to Fig. 2-1-3, insert the spring normally
and mount the clamper stay.
This part should be touched
to the left side of the tray.
NG
OK
NG
1-1-3. Tray Panel
<T ray Ejection>
1. Slide the slider (2) of the mechanism chassis assembly
(1) with a screwdriver, etc. in the arrow direction, so
that the tray (3) is ejected.
Note:
• Take care not to damage the pickup and other parts.
Screwdriver
Mechanism
chassis assembly
Press down by finger
unitil fix the clamper assembly
No floating
OK
Fig. 2-1-3
Tray
Spring
Floating NG
NG
Slider (2)
Mechanism
chassis assembly (1)
Tray (3)
Front panel
Fig. 2-1-4
<Tray Panel Removal>
1. Eject the tray (3).
2. Twist the tray panel (4) a little in the arrow A direction
with the tray (3) hold by hand to release two claws and
lift up the tray panel (4) in the arrow B direction, then
the tray panel (4) is removed.
(Refer to Fig. 2-1-5.)
3. When mounting the tray panel (4), insert the tray panel
(4) along the grooves of the both sides of the tray (3)
until clicking.
2-2
Page 43
Traypanel(4)
Tray(3)
• The gears are required to match their phases each
other. After setting the gear (3) as shown in the figure
“A”, insert the tray (2). When inserting a tray (2), push
the rack gear side shown by the arrow.
B
• Confirm that the mark of the gear matches with the
triangle mark on the reverse side of the tray in the tray
close status. (The gear is rotated with the slider locks.)
(Refer to Fig. B.)
A
Gear (4)Triangle mark
Fig. A
Tray(3)
Claws
Traypanel(4)
Fig. 2-1-5
1-1-4. Front Panel and Tray
1. Remove the flexible cable (1).
2. Release four claws and remove the front panel (3).
3. Pull out the tray (2) to this side.
Claw
Position of the line
Pickup mechanism
assembly
Gear (4)
Tray rack gear
Slider
Triangle markMarking
Tray (2)
Gear
Fig. B
Tray (2)
Claws
Front panel (3)
Flexible cable (1)
Claw
Fig. 2-1-6
Note:
• Insert the tray (2) with the front side of the pickup
mechanism assembly descended. (The slider positions
to the left side.)
Fig. 2-1-7
1-1-5. Rear Panel
1. Remove six screws (1) and remove the rear panel (2).
Screws (1)
Rear panel (2)
2-3
Fig. 2-1-8
Screws (1)
Page 44
1-2. PC Board Replacement
1-2-1. Main PC Board
Note:
• Before removing the main PC board (5), be sure to
short-circuit the laser diode output land.
After replacing, open the land as it was after inserting
the flexible cables (1).
1. Remove the top cover. (Refer to item 1-1-1.)
2. Remove four flexible cables (1) and remove one
connector (2).
3. Remove four screws (3).
4. Remove three screws (4) and remove the main PC
board (5).
Note:
• When mounting, be sure to twist the wire for the
connector (3) several times.
Twist more than 7 times.
1-2-2. Power PC board
1. Peel off two tapes (1).
2. Remove the connectors (2).
3. Remove four screws (3).
4. Remove two screws (4) and remove the power supply
PC board (5).
Note:
• When mounting, be sure to twist the wire for the
connectors (2) several times.
Twist more than 9 times.
Power supply
PC board (5)
Screws (3)
Tapes (1)
Flexible cables (1)
Screw (3)
Plate spring
Main PC board (5)
Pickup head
Connector (2)
Pickup head
Plate spring
Screw (3)
Screws (4)
Connector (2)
Plate spring
Screws (4)
Fig. 2-1-10
Laser diode
output lands
Type AType B
Laser diode
output lands
Fig. 2-1-9
2-4
Page 45
1-2-3. Front PC Board
1. Remove the front panel. (Refer to item 1-1-4.)
2. Remove six screws (1) and remove the front display
PC board (2)
3. Remove two screws (3) and remove the power switch
PC board (4).
Power SW
PC board (4)
Screws (3)
Front display
PC board (2)
Screws (1)
1-3. Mechanism Parts
1-3-1. Mechanism Chassis Assembly
Note:
• When removing the mechanism chassis assembly (3),
be sure to short-circuit the laser diode output land
before removing the connector and the flexible cables.
After replacing, open the land as it was after inserting
the connector and flexible cables.
1. Remove the tray. (Refer to items 1-1-3 and 1-1-4.)
2. Remove three flexible cables (1).
3. Remove four screws (2) and remove the mechanism
chassis assembly (3).
Type A
Screws (2)
Mechanism
chassis assembly (3)
Pickup head
Fig. 2-1-11
Flexible
cables (1)
Fig. 2-1-12
Laser diode
output lands
Type B
Pickup head
Laser diode
output lands
2-5
Page 46
1-3-2. Loading Belt
1. Remove the gear (1) by releasing the claw.
2. Remove the gear (2).
3. Remove the gear (3) and the loading belt (4).
4. Replace the loading belt (4) with a new one.
5. When mounting, perform the reverse order of the
removal.
Note:
• When mounting the loading belt (4), twisting and
attaching of a grease, etc. are not allowed.
Gear (1)
Gear (2)
Loading belt (4)
1-3-3. Loading Motor
1. Remove the loading belt. (Refer to item 1-3-2.)
2. Remove two screws (1) and two claws. Then remove
the loading motor (2) (with the loading motor PC
board (3) attached).
3. Desolder the terminal section of the loading motor (2)
and remove the loading motor PC board (3).
4. Replace the loading motor (2) with a new one.
5. When mounting, perform the reverse order of the
removal.
Note:
• When replacing the loading motor, meet the polarity
phase of the terminals. (Mount the motor with the
label positioned as shown in Fig. 2-1-14.)
Screws (1)
Claw
Mechanism
chassis assembly
Fig. 2-1-13
Gear (3)
Mechanism
chassis assembly
Claws
Loading motor (2)
Desolder
Motor label
side
Loading motor
PC board (3)
Fig. 2-1-14
2-6
Page 47
r
1-3-4. Sub Chassis (with a pickup mechanism)
1. Turn the mechanism chassis assembly (1) upside down.
2. Remove one screw (2) and one washer (3) release the
boss “A” from the claw. Then remove the sub chassis (4)
(with the pickup mechanism) by sliding in the arrow
direction.
3. When mounting, perform the reverse order of the
removal.
Note:
• When mounting the sub chassis (4) (with the pickup
mechanism), first, insert the boss “C” along the groove
of the cam slider up/down cam (5) and next, the boss
“B” and “A”.
• The boss “A” may be used with washers. (One or two
washers are used to prevent from the slust rattling. In
some cases, no washer is used.)
When the washer(s) is used, be sure to assemble as it
was without losing.
Screw (2)
Washer
Sub chassis (4)
(with the pickup mechanism attached)
Boss C
Boss A
1-3-5. Pickup Mechanism Assembly
<Removal>
1. Remove four screws (1) and four washers (2) then
remove the pickup mechanism assembly (3).
<Mounting>
1. Replace the pickup mechanism assembly (3) with a
new one.
2. When mounting, perform the reverse order of the
removal.
Screws (1)
Washars (2)
Damper
(Blue)
Damper
(Black)
Dampe
(Blue)
Washer (3)
Claw
Claw
Boss B
Groove
Boss A
Boss B
Fig. 2-1-15
Groove
Cam slider
up/down cam (5)
Mechanism chassis
assembly (1)
Groove
Damper
(Black)
Fig. 2-1-16
Note:
• The dampers’ color differs when used for the front
side and the rear.
• When mounting the pickup mechanism assembly (2)
with the screws (1), push the pickup mechanism assembly (2) downward without being caught and tighten the
screws (1) after placing the washer with the damper bent.
Screw (1)
Washer (2)
2-7
Pickup mechanism
assembly (2)
Damper
Fig. 2-1-17
Pickup mechanism
assembly (3)
Page 48
1-3-6. Gear B Assembly , Gear A and Rack Gear
Gear B assembly (1)
Rack gear assembly (4)
Gear A (2)
Within the position shown
by the shaded portion.
Innermost position
of pickup head
Assembly
<Removal>
1. Remove one screw (3) and remove the gear B assembly
(1).
2. Remove the gear A (2).
3. Remove one screw (5) and remove the rack gear
assembly (4).
Positioning holes
Pickup Head (5)
Gear B assembly (1)
A
Screw (5)
Rack gear
assembly (4)
Gear A (2)
Screw (3)
Fig. 2-1-18
Gear B
assembly (1)
Pickup mechanism
assembly
B
Gear A (2)
Pickup mechanism
assembly
Rack gear assembly (4)
Fig. 2-1-19
Note:
• Mount the gear B assembly (1) and the gear A (2) with
their gear teeth placed more than one tooth at least
inside the shaded portion.
<Mounting>
1. When mounting, perform the reverse order of the
removal.
2. Mount the gear B assembly (1) by pushing the pickup
head (5) to the disc motor side (arrow A direction) and
shifting the upper gear of the rack gear assembly (4) in
the arrow B direction. (Refer to Fig. 2-1-19.)
3. Fit the positioning holes on the upper gear and lower
gear of the gear B assembly (1) and mount on the
pickup mechanism assembly with the phase matched.
At this time, note that the phase of the gear B assembly (1) and the gear A (2) shows the status in the Fig.
2-1-20.
Fig. 2-1-20
2-8
Page 49
1-3-7. Feed Motor
<Removal>
1. Remove the gear B assembly and the gear A. (Refer to
item 1-3-6.)
2. Remove two screws (1) and remove the feed motor (2)
(with the feed motor PC board (3) attached).
(Refer to Fig. 2-1-21.)
3. Desolder the terminals of the feed motor (2) and
remove the feed motor PC board (3).
<Mounting>
1. Tighten the feed motor (2) on the pickup mechanism
assembly with two screws (1).
2. Insert the feed motor PC board (3) with the positioning pin on the chassis matched and solder the terminals.
3. Perform the reverse order of the removal.
Note:
• After mounting, put the lead wires through the notch
of the pickup mechanism assembly.
• When replacing the loading motor, meet the polarity
phase of the terminals. (Mount the motor with the
label positioned as shown in Fig. 2-1-21.)
Pickup mechanism
assembly
Notch
Lead wires
Screws (1)
Feed motor (2)
Motor label side
Desolder
Feed motor
PC board (3)
Fig. 2-1-21
2-9
Page 50
This page is not printed.
2-10
Page 51
SECTION 3
SERVICING DIAGRAMS
1. STANDING PC BOARDS FOR SERVICING
EU02 Power supply PC board
EU01 Main PC board
SERVICING DIAGRAMS
SECTION 3
EU04 Power SW PC board
EU03 Front display PC board
Fig. 3-1-1
3-1
Page 52
2. CIRCUIT SYMBOLS AND SUPPLEMENTARY EXPLANATION
100k
RatedWattageTypeTolerance
100
m
Temperatureresponse
Ratedvoltage
Tolerance
2-1. Precautions for Part Replacement
• In the schematic diagram, parts marked (ex.
F801) are critical part to meet the safety regulations,
so always use the parts bearing specified part codes
(SN) when replacing them.
2-2. Solid Resistor Indication
UnitNone...........Ω
K...........kΩ
M...........MΩ
ToleranceNone...........±5%
B...........±0.1%
C...........±0.25%
D...........±0.5%
F...........±1%
G...........±2%
K...........±10%
M...........±20%
Rated Wattage(1) Chip Parts
None.........1/16W
(2) Other Parts
None.........1/6W
Other than above, described in the Circuit Diagram.
TypeNone...........Carbon film
S...........Solid
R...........Oxide metal film
W...........Metal film
W...........Cement
FR...........Fusible
• Using the parts other than those specified shall violate
the regulations, and may cause troubles such as
operation failures, fire etc.
Eg. 1
FIg. 3-2-1
2-3. Capacitance Indication
Symbol
UnitNone...........F
Rated voltageNone...........50V
Tolerance(1) Ceramic, plastic, and film capacitors of which
Temperature characteristicNone...........SL
(Ceramic capacitor)For others, temperature characteristics are
Static electricity capacitySometimes described with abbreviated letters as
(Ceramic capacitor)shown in Eg. 3.
+
...........Electrolytic, Special electrolytic
NP
...........Non polarity electrolytic
...........Ceramic, plastic
M
...........Film
...........Trimmer
µ...........µF
p...........pF
For other than 50V and electrolytic capacitors,
described in the Circuit Diagram.
capacitance are more than 10 pF.
None...........±5% or more
B...........±0.1%
C...........±0.25%
D...........±0.5%
F...........±1%
G...........±2%
(2) Ceramic, plastic, and film capacitors of which
capacitance are 10 pF or less.
None...........more than ±5% pF
B...........±0.1 pF
C...........±0.25 pF
(3) Electrolytic, Trimmer
Tolerance is not described.
described. (For capacitors of 0.01 µF and
no indications are described as F.)
(Ex. Pin 14 becomes HIGH, when pin 4 terminal voltage is
HIGH.)
Loading driver FWD input terminal
Loading driver REV input terminal
Loading driver output voltage control
terminal
CH1 mute terminal
Driver CH1 input terminal
Driver CH2 input terminal1
Pre driver, Loading power supply terminal
CH1, CH2 power step power supply
terminal
Loading driver minus output
Loading driver plus output
Driver CH2 minus output
Driver CH2 plus output
Driver CH1 minus output
Driver CH1 plus output
Driver CH4 plus output
Driver CH4 minus output
Driver CH3 plus output
Driver CH3 minus output
Ground terminal
CH3, CH4 power step power supply
terminal
Regulator part power supply terminal
Bias input terminal
Function
Setup default, memorization of specification setting.
Decryption, MPEG-2 Decode, Audio Decode, Sub Picture Decode,
OSD.
Performs servo control of DVD or CD, and performs demodulation
and correction of RF signal.
Equalizes playback RF signal and generates error detection signal
required for each servo operation.
Driver for motor driving.
Stereo audio DA converter.
Performs system control for all circuits.
Rate control and Buffer control.
Memorization for firmware.
8 bit programmable I/O (large current) port
(try state)
I/O can be assigned by one bit. When
using as the serial interface input, the input
mode is selected.
When using as the serial interface output,
the output mode is selected with the output
latch “1” set.
8 bit programmable I/O (P14 ~ P10 are
large current) port (try state)
I/O can be assigned by one bit. When
using as the external interrupting input and/
or timer counter input, the input mode is
selected.
When using as the timer counter output
and/or divider output, the output mode is
selected with the output latch to “1” set.
3 bit I/O (large current output) port.
When using as the input port, external
interrupting input/STOP mode release input
and/or the oscillator connection, the output
mode is selected with the output latch to
“1” set.
3 bit programmable I/O port (sync open
drain).
I/O can be assigned by one bit.
When using as the serial bus interface, the
output mode is selected with the output
latch to “1” set.
8 bit programmable I/O port (try state)
I/O can be assigned by one bit. When
using as the analog input, the input mode
is selected.
4 bit programmable I/O port (try state)
I/O can be assigned by one bit. When
using as the analog input, the input mode
is selected.
8 bit high dielectric strength I/O port.
When using as the fluorescent display
driver, the output latch is cleared to “0”.
Function
3-213-22
Page 65
Table 3-5-3 TMP87CH74AF-2C07 (2/2)
Table 3-5-4 TMP94C251AF(Z) (1/5)
Pin
No.
73
|
77
9,8
10
13
40,7
78
39,
38
Name
PD0 (V32)
|
PD4 (V36)
XIN, XOUT
RESET
TEST
VDD, VSS
VKK
VAREF,
VASS
Function
5 bit high dielectric strength I/O port.
When using as the fluorescent display
driver, the output latch is cleared to “0”.
High frequency oscillator connection
terminal.
Entered XIN when the external clock input
is selected, and XOUT is opened.
Reset signal input, watch dog timer output /
address trap reset output / system clock
reset output
Terminal for shipping test. Fixed to the low
level.
+5V, 0V (GND)
Power supply terminal for fluorescent
display driving
Analog reference voltage for A/D
conversion, reference GND. VASS should
be always fixed to 0V (GND) when A/D.
Pin
No.
70
77
79
86
108
115
99
106
90
97
68
67
66
65
64
63
62
60
|
|
|
|
|
Name
P00~P07
D0~D7
P10~P17
D8~D15
P40~P47
A0~A7
P50~P57
A8~A15
P60~P67
A16~A23
P70
RD
P71
WRL
P72
WRH
P73
P74
P75
BUSRQ
P76
BUSAK
P80
CS0
Function
Port 0: I/O port
Data 0~7: data bus 0~7
Initialized to this function in the external
ROM type, TMP94C251A.
Becomes high impedance when not
accessing to the external memory.
Port 1: I/O port
Data 8~15: data bus 8~15
Initialized to this function when starting with
data bus width higher than 16 bit in the
external ROM type, TMP94C251A.
Becomes to high impedance when not
accessing to the external memory.
Port 4: I/O port
Address 0~7: address bus 0~7
Initialized to this function in the external
ROM type, TMP94C251A.
The signal does not change when not
accessing to the external memory.
Port 5: I/O port
Address 8~15: address bus 8~15
Initialized to this function in the external
ROM type, TMP94C251A.
The signal does not change when not
accessing to the external memory.
Port 6: I/O port
Address 16~23: address bus 16~23
Initialized to this function in the external
ROM type, TMP94C251A.
The signal does not change when not
accessing to the external memory.
Port 70: Output port (initialized to “1”
output)
Read: Strobe signal, which reads the
external memory.
Develops no strobe signal when not
accessing to the external memory.
Initialized to this function in the external
ROM type, TMP94C251A.
Port 71: Output port (initialized to “1”
output)
Write: Strobe signal, which writes D0 ~ D7
of the external memory .
Develops no strobe signal when not
accessing to the external memory.
Port 72: Output port (initialized to “1”
output)
Write: Strobe signal, which writes D8 ~ D15
of the external memory .
Develops no strobe signal when not
accessing to the external memory.
Port 73: Output port (initialized to “1”
output)
Port 74: Output port (initialized to “1”
output)
Port 75: I/O port
Bus request: Signal, which requests to set
the memory interface terminal to high
impedance.
The following terminals become high
impedance. But the state does not change
while functioning as port.
A0~A23, D0~D15, RD, WRLL, WRLH,
CS0~CS5, OE0~OE1, WE0~WE1, RAS
group, CAS group
Port 76: Output port (initialized to “1”
output)
Bus Acknowledge: Signal, which indicates
that BUSRQ request is received.
Port 80: Output port (initialized to “1”
output)
Chip select 0: Develops “L” level when the
address is within the assigned address
area.
3-23
Page 66
Table 3-5-4 TMP94C251AF(Z) (2/5)
Table 3-5-4 TMP94C251AF(Z) (3/5)
Pin
No.
59
58
57
56
55
29
49
50
51
52
53
44
45
Name
P81
CS1
RAS0
P82
CS2
P83
CS3
RAS1
P84
CS4
P85
CS5
P86
WAIT
PA0
CAS0
LCAS0
PA1
UCAS0
PA2
OE0
PA3
OE1
PA4
WE0
PB0
CAS1
LCAS1
PB1
UCAS1
Function
Port 81: Output (initialized to “1” output)
Chip select 1: Develops “L” level when the
address is within the assigned address
area.
Low address strobe 0: Develops RAS
strobe signal for DRAM when the address
is within the assigned address area.
Port 82: Output port (initialized to “1”
output)
Chip select 2: Develops “L” level when the
address is within the assigned address
area.
Port 83: Output port (initialized to “1”
output)
Chip select 3: Develops “L” level when the
address is within the assigned address
area.
Low address strobe 1: Develops RAS
strobe signal for DRAM when the address
is within the assigned address area.
Port 84: Output port (initialized to “1”
output)
Chip select 4: Develops “L” level when the
address is within the assigned address
area.
Port 85: Output port (initialized to “1”
output)
Chip select 5: Develops “L” level when the
address is within the assigned address
area.
Port 86: I/O port
Wait: Bus wait request signal
Port A0: Output port (initialized to “1”
output)
Column address strobe 0: Develops CAS
strobe signal for DRAM when the address
is within the assigned address area.
Lower column address strobe 0: Develops
lower CAS strobe signal for DRAM when
the address is within the assigned address
area.
Port A1: Output port (initialized to “1”
output)
Upper column address strobe 0: Develops
upper CAS strobe signal for DRAM when
the address is within the assigned address
area.
Port A2: Output port (initialized to “1”
output)
Out enable 0: Develops out enable signal
for DRAM.
Port A3: Output port (initialized to “1”
output)
Out enable 1: Develops out enable signal
for DRAM.
Port A4: Output port (initialized to “1”
output)
Write enable 0: Develops write enable
signal for DRAM.
Port B0: Output port (initialized to “1”
output)
Column address strobe 1: Develops CAS
strobe signal for DRAM when the address
is within the assigned address area.
Lower column address strobe 1: Develops
lower CAS strobe signal for DRAM when
the address is within the assigned address
area.
Port B1: Output port (initialized to “1”
output)
Upper column address strobe 1: Develops
upper CAS strobe signal for DRAM when
the address is within the assigned address
area.
Pin
No.
46
47
48
6
7
8
9
10
11
12
13
15
16
17
18
19
20
21
22
23
Name
PB2
PB3
PB4
WE1
PC0
TO1
TO7
PC1
TO3
TOB
PD0
TO4
PD1
TI4
INT4
PD2
TI5
INT5
PD4
TO6
PD5
TI6
INT6
PD6
TI7
INT7
PE0
TO8
PE1
TI8
INT8
PE2
TI9
INT9
PE4
TOA
PE5
TIA
INTA
PE6
TIB
INTB
PF0
TXD0
PF1
RXD0
PF2
CTS0
SCLK0
Function
Port B2: Output port (initialized to “1”
output)
Port B3: Output port (initialized to “1”
output)
Port B4: Output port (initialized to “1”
output)
Write enable 1: Develops write enable
signal for DRAM.
Port C0: I/O port
Timer output 1: Develops 8 bit timer 0 or
timer 1.
Timer output 7: Develops 16 bit timer 7.
Port C1: I/O port
Timer output 3: Develops 8 bit timer 2 or
timer 3.
Timer output B: Develops 16 bit timer B.
Port D0: I/O port
Timer output 4: Develops 16 bit timer 4.
Port D1: I/O port
Timer input 4: Enters 16 bit timer 4.
Interrupt request terminal 4: Terminal for
interrupt request signal of which rising/
falling edge is programmable.
Port D2: I/O port
Timer input 5: Enters 16 bit timer 4.
Interrupt request terminal 5: Terminal for
interrupt request signal at the rising edge.
Port D4: I/O port
Timer output 6: Enters 16 bit timer 6.
Port D5: I/O port
Timer input 6: Enters 16 bit timer 6.
Interrupt request terminal 6: Terminal for
interrupt request signal of which rising/
falling edge is programmable.
Port D6: I/O port
Timer input 7: Enters 16 bit timer 6.
Interrupt request terminal 7: Terminal for
interrupt request signal at the rising edge.
Port E0: I/O port
Timer output 8: Enters 16 bit timer 8.
Port E1: I/O port
Timer input 8: Enters 16 bit timer 8.
Interrupt request terminal 8: Terminal for
interrupt request signal of which rising/
falling edge is programmable.
Port E2: I/O port
Timer input 9: Enters 16 bit timer 8.
Interrupt request terminal 9: Terminal for
interrupt request signal at the rising edge.
Port E4: I/O port
Timer output A: Develops 16 bit timer A.
Port E5: I/O port
Timer input A: Enters 16 bit timer A.
Interrupt request terminal A: Terminal for
Interrupt request signal of which rising/
falling edge is programmable.
Port E6: I/O port
Timer input B: Enters 16 bit timer A.
Interrupt request terminal B: Terminal for
interrupt request signal at the rising edge.
Port F0: I/O port
Serial transmission data 0 (open drain
output is possible)
Port F1: I/O port
Serial reception data 0
Port F2: I/O port
Serial transmission is possible 0
Serial clock I/O 0
3-24
Page 67
Table 3-5-4 TMP94C251AF(Z) (4/5)
Table 3-5-4 TMP94C251AF(Z) (5/5)
Pin
No.
24
25
26
131
138
3
4
126
127
128
129
125
117
124
28
42
30,
40
32,
33
31
38,
39
41
139
140
1
2
|
|
Name
PF4
TXD1
PF5
RXD1
PF6
CTS1
SCLK1
PG0~PG7
AN0~AN7
DAOUT0
DAOUT1
PH0
TC0
PH1
TC1
PH2
TC2
PH3
TC3
PH4
INT0
PZ0~PZ7
NMI
WDTOUT
AM0~1
TEST0~1
CLK
X1/X2
RESET
VREFH
VREFL
DAREFH
DAREFL
Function
Port F4: I/O port
Serial transmission data 1 (open drain
output is possible)
Port F5: I/O port
Serial reception data 1
Port F6: I/O port
Serial transmission is possible 1
Serial clock I/O 1
Port G: Input port
Analog input: Enters 10 bit AD converter
DA output 0: Develops 8 bit DA converter 0
DA output 1: Develops 8 bit DA converter 1
Port H0: I/O port
Terminal count 0: Develops “H” level with
strobe when micro DMA channel 0 counts
0.
Port H1: I/O port
Terminal count 1: Develops “H” level with
strobe when micro DMA channel 1 counts
0.
Port H2: I/O port
Terminal count 2: Develops “H” level with
strobe when micro DMA channel 2 counts
0.
Port H3: I/O port
Terminal count 3: Develops “H” level with
strobe when micro DMA channel 3 counts
0.
Port H4: I/O port (schmitt input)
Interrupt request terminal 0: Terminal for
interrupt request signal of which rising/
falling edge is programmable. (schmitt
input)
Port Z: I/O port
Non maskable interrupt request terminal:
Terminal for interrupt request signal at the
falling edge. Depending on the program,
interrupt request signal at rising edge may
be used. (schmitt input)
Watch dog timer output terminal
Address mode: Selects the starting
external data bus width after releasing the
reset
AM1 = “0”, AM0=”0”: starting at the 8 bit
external data bus
AM1 = “0”, AM0=”1”: starting at the 16 bit
external data bus
AM1 = “1”, AM0=”0”: Do not set.
AM1 = “1”, AM0=”1”: Do not set.
Test: Used to “GND”
Clock: Develops System clock
Oscillator connection terminal
Reset: Device is initialized.
(With the pull-up resistance) (schmitt input)
Reference voltage input terminal for 10 bit
AD converter (H)
Reference voltage input terminal for 10 bit
AD converter (L)
Reference voltage input terminal for 8 bit
DA converter (H)
Reference voltage input terminal for 8 bit
DA converter (L)
Pin
No.
142
141
144
143
36
34
5,
27,
43,
61,
78,
88,
98,
116
14,
37,
54,
69,
87,
89,
107,
130
Name
ADVCC
ADVSS
DAVCC
DAVSS
CLVCC
CLVSS
DVCC
DVSS
Function
10 bit AD converter power supply terminal
10 bit AD converter GND terminal (0V)
8 bit DA converter power supply terminal
8 bit DA converter GND terminal (0V)
Power supply terminal for clock doubler.
GND terminal for clock doubler.
Digital power supply terminal (+5V)
Digital GND terminal (0V)
3-25
Page 68
Table 3-5-5 ZR36732 (1/5)
Table 3-5-5 ZR36732 (2/5)
Pin
No.
Host interface, CD-DSP interface, sub code interface (32 pins)
Reset input (active: low). Initializing
process of the device will start when
deasserting is performed after asserting.
Standby input (active: low). When asserting
in accordance with RESET#, all the output
pins and bidirectional pins enter the float
state, and the device is electrically cut off.
All internal operations stop and the power
consumption can be minimized. At standby,
contents of SDRAM and setup parameters
are not preserved.
Display output of Idle, Init or Reset state
(active high). After reset, the device enters
the active state.
Determines the data bus width of host
interface. Only during reset, modification
will be available. At low level (GNDP), the
host interface of the device is set to 2 or 8
bit width, at high level (VDDP) is set to 16
bit width.
Determines the bite order of host interface
data bus at 16 bit width (HWID is VDDP).
Only during reset, modification will be
available. Sets the device so that m.s. bite
is entered/developed by HD [15:8] at low
level (GNDP), and m.s. bite is done by HD
[7:0] at high level (VDDP).
Connects to GNDP when HWID is at GND
level.
Determines protocol of the host bus. Only
during reset, modification will be available.
Sets the device to type A at low level
(GNDP) and type B at high level (VDDP).
8 l.s of the host data bus. When connecting
HWID input to GNDP, only the 8 l.s. signal
is defined as a host data signal. When
connecting HWID to VDDP, the connection
is used as a 8 l.s. line of 16 bit data bus.
When connecting HWID to VDDP, the
connection is used as 1 1:8 dat a line of 16
bit host data bus.
When connecting HWID to VDDP, the
connection is used as 15:12 data line of 16
bit host data bus. When connecting HWID
to GNDP, the connection is used as CDDSP serial input port pin as defined below.
CD-DSP bit clock input.
CD-DSP data input.
CD-DSP LR clock (Frame) input.
CD-DSP data error input.
Host address input. Inputs address signal
which specifies the physical address of the
device.
Host chip select input. Active: low.
Host protocol type A (HTYPE=GNDP): HR/
W#. The input to determine the direction of
host access.
Host protocol type B (HTYPE=VDDP):
HWR#. Host write input (Active: low).
Host protocol type A (HTYPE=GNDP):
HDS#. Data strobe input (Active: low).
Host protocol type B (HTYPE=VDDP):
HRD#. Host read in input (Active: low).
Function
Pin
No.
134
145
143
120
117
119
118
115
102
105
106
103
108
Name
36
HRDY
37
HIRQ#
39
HACK#
GPI/O signal (3 pins)
GPIO
GPSI
GPSO
PLL signal (5 pins)
GCLK
GCLK1
XO
PLLCFG
[1:0]
Analog video port (7 pins)
CVBS/G/Y
(DAC A)
Y/R/V
(DAC B)
C/B/U
(DAC C)
CVBS/C
(DAC D)
RSET
Host ready output (active: high). When
transmitting a stream through host bus with
this signal, use the signal. And an external
pull up resistor is required.
Confirm the signal becomes active before
transmitting every packet signal, 1 packet
signal is CodBurstLen byte length
transmission signal. After that, it is
available to write the bit stream signals up
to the CodBurstLen byte to the device
continuously.
Interrupt request (active: low). Deasserted
by host reading the interrupt status resistor
of the device. And also deasserted either
after host masks the interruption with the
interrupt mask resistor of the device or
after reset.
When HIRQ# is not asserted, 3-state
status starts. (External pull up resistor is
required.)
Host aknowledge output (active: Low).
When the type A protocol is used, the
device asserts the output and informs the
completion of read/write cycle.
When the signal is not active, 3-state
status starts. (External pull up resistor is
required.)
When the type B protocol is used, the
signal works as a Wait output signal. When
using a host with high speed
(microprocessor), the signal connection is
not always required.
General bidirectional pin to watch/control
by ADP micro code. After reset, the pin is
defined to use for input. By the ADP
command, setting is available.
General input to be watched by DVP micro
code.
General output to be controlled by DVP
micro code. After reset, the pin develops
Low.
27.000 MHz clock or X’tal input for main
processor.
27.000 MHz master clock input for audio.
In standard use, the pin should be
connected to GCLK.
Output to X’tal connected to GCLK. When
not using X’tal for GCLK, XO is kept
unconnected.
PLL configuration input. During reset,
modification will be available. For general
use, both pins should be connected to
GNDP.
At CVBS, the composite video signal is
developed.
At RGB, G signal is developed.
At YUV, Y signal is developed.
At CVBS, Y signal is developed.
At RGB, R signal is developed.
At YUV, V signal is developed.
At CVBS, C signal is developed.
At RGB, B signal is developed.
At YUV, U signal is developed.
Develops either of CVBS or C signal.
Insert a resistor load for DAC gain
adjustment between GND and DAC.
Function
3-26
Page 69
Table 3-5-5 ZR36732 (3/5)
Table 3-5-5 ZR36732 (4/5)
Pin
No.
111
100
Digital video port (5 pins)
127
Digital audio port (8 pins)
131
133
136
138
113
139
141
DVD-DSP interface (13 pins)
151
149
148
152
159
150
147
92
95
93
96
|
|
Name
VREF
COSYNC
VCLKx2
VCLK
HSYNC
VSYNC
FI
AMCLK
S/PDIF
(AOUT[3])
AOUT[2:0]
AIN
ALRCLK
ABCLK
DVDREQ
DVDVALID
DVDSOS
DVDDAT
[7:0]
DVDSTRB
DVDERR
Apply reference voltage for DAC gain
adjustment.
Composite sync output. Only when RGB
analog output is selected, the pin takes
effective. For other case, the pin is fixed to
Low.
Main video clock input or output. 27.000
MHz.
Two-divided VCLKx2 signal. The signal is
used as data and sync signal qualifier.
Horizontal sync bidirectional signal pin. The
polarity and length are programmable.
Vertical sync bidirectional signal pin. The
polarity and length are programmable.
Field identification bidirectional signal pin.
The polarity is programmable.
Audio master clock input/output. The
sampling frequency can be selected
among 384fs, 256fs, 192fs and 128fs.
(programmable)
S/PDIF transmitter output. Available to
connect to DAC as the 4th audio output
(AOUT[3]). After reset, the pin develops
low level signal.
PCM stereo audio serial output for DAC.
After reset, the pin develops low level
signal.
PCM stereo audio serial input for ADC.
AOUT [4:0] and LR clock output of AIN.
The square waveform appears in the
sampling frequency .
The polarity of LR is programmable.
AOUT [4:0] and bit clock output of AIN.
AOUT is developed at the rising and falling
edges of the clock signal and AIN is
latched.
DVD-DSP data request output (polarity
programmable).
DVD-DSP data effective input (polarity
programmable).
DVD-DSP data sector start input (polarity
programmable).
DVD-DSP data input bus.
DVD-DSP data bit strobe (clock) input.
Polarity programmable.
Fig. 3-6-7 EU01 Main PC Board (Bottom pattern and bottom parts location diagram)
R948
C711
R913
D901
C715
C716
C701
L303
C714
321
C713
F-MARK3
A
3-443-43
Page 81
D
C
B
A
CN502
C514
C621
IC607
R652
R635
R641
R643
R617
CN603
R613
R646
R647
R658
F-MARK2
C507
C509
Q503
C613
R642
R644
IC610
IC608
C604
R651
IC601
R509
C512
R513
IC611
C618
C620
RM604RM605
C619
C610
C611
R645
R627
R606
R612
R610
R607
C506
IC501
C505
IC503
R511
C614R638
IC606
RM606RM607RM608
R611
C535
IC605
CN503
C518
C536
JP501
R542
IC504
RM609RM610RM611
R546
RM614
RM603
IC502
R508
RM612
R640
C608
R625
C605C607
CN601
Q501Q502
R539
R556
C508
C542
R507
R510
R512
C541
C510
R522
R535
C530
C206
C207
R205
RM601RM602
R639
X601
R555
R553
R554
C543
R557
X401
R445
R447
R402
Q401
C454
R441
C436
R444
R446
C438
C437
C441
R448
C445
C453
R453
R440
C303
C452
C203
CN501
R425
C201
C202
R423
C410
R411R415
C314
R416
IC401
C517
C451
R449
IC201
IC301
C419
C425
C426
C448
C204
C702
R427
R429
R431
R433
R434
R435
R437
R439
C444
JP301
C313
R301
C427
C428
C429
C430
C433
C434
C435
C446
IC302
D308
C622
R305
C319
Q301
R316
R338
C310
C312
R307
L302
C336
R943
R653
R309
Q306Q307
C309
Q302Q303
R302
R303
C911
R947
R311
R942
C915
X901
R342
C717
C914
IC903
C903
R905
R944
C907
C905
R903
C934
C703
IC907
R907
R909
R904
C904
R906
C933
C937
Q912
R649
R648
IC901
C935
CN301
C338
C339
Q304
R912
R911
C902
R941
C917
C337
Q305
Q308
C705
Q901
Q914
R910
C908
C936
R953
R315
R328
R317
R320
JP701
Q907
C623
Q908
R312
C305
C307
C311
C318
C316
R921
R915
C910
C906
R922
R916
R920
R919
Q904Q905
R917
Q902
R918
R308
Q309
R313
C704
C916
R314
C918C919
C321
C306
R339
R340
C317
CN701
C712
C707
R650
Q903
C920
C322
R701
C706
R954
Q906
C921
R924
C924
IC912
C923
R923
C922
C332
R326
IC304
C928
R926
R925
C913
C912
C925
C328
C327
C323
R321
C901
R901
R940
C909
C932
R902
C929
Q913
R927R928R929R930
C926
R323
R324
C330
C324
C325
C326
IC913
R932
R931
Q910
R934
R935
Q911
R322
R329
R334
R332
C335
R327
Q909
R933
C927
R335
R936R937
C333C334
R336
R318
R319
F-MARK1
C931
R939
R908
C930
R938
R325
C331
R331
IC914J301J302
321
Fig. 3-6-8 EU01 Main PC Board (Top pattern, character/symbol)
3-463-45
Page 82
F-MARK4
D
C
B
A
Q604
R616
C617
C606
C602
C601
C603
R603
R615
C615
IC602
IC604
Q603
R604
R605
C616
R601
R602
R631
R634
C609
R618
R630
R636
R632
R633
R623
R624
R626
IC603
R619
R622
R609
R614
R608
RM613
R620
R621
Q601Q602
C612
IC609
R628R629
R637
IC303
C205
IC202
C315
C301C302
RM202
R451
IC305
C449
RM203
RM201
C450
R330
C320
D304 D305
D301
D303
D302
123
IC306
C308
R306
R310
C304
R304
C439
R450
C443C447
C440
R654R655
R656
R952
R945
R951
R914
R946
R950
R949
R333
R337
C329
C515
R516
R518
R517
R514 R515
C511
C504
R520
R521
Q505
R529
C527
C516
C520
R526
R547
R528
C529
C523
Q504
C533
C534
C525
C524
C522
R527
R551
C526
C528
C519
R545
R536
C513
R525
R519
C532
C539
R461
R506
R417
R405
C421
R410
C408
C412
R552
C404
C405
D502
R419
R420
C502
R504
R503
R502
R421
C503
C501
R409
R414
R422
C406
C413
R413
C403
R424
R406
C415
R505
IC402
R401
C411
C401
C417
C420
R403
C409
C402
R412
C416
D501
R408
R454
C423
R404
C424
R501
R443
R442
R407
C418
R418
C442
C422
C432
C431
R436
R438
R432
R430
R428
R426
R703
R702
Fig. 3-6-9 EU01 Main PC Board (Bottom pattern, character/symbol)
C708C709C710
R948
C711
R913
D901
C715
C716
C701
L303
C714
C713
F-MARK3
3-483-47
Page 83
This page is not printed.This page is not printed.
3-503-49
Page 84
SECTION 4
PARTS LIST
SAFETY PRECAUTION
The parts identified by ! ( ) mark are critical for safety. Replace only with part number specified.
The mounting position of replacement is to be identical with originals.
The substitute replacement parts which do not have the same safety characteristics as specified in the parts list may create
shock, fire or other hazards.
NOTICE
The part number must be used when ordering parts in order to assist in processing, be sure to include the model number and
description.
Parts marked # are of chip type and mounted on original PC boards.
However, when they are placed for servicing works, use discrete parts listed on the parts list.
ABBREVIATIONS
1. Integrated Circuit (IC)
2. Capacitor (Cap)
• Capacitance Tolerance (for Nominal Capacitance more than 10pF)
Table 4-2-1
Symbol
T olerance %B± 0.1C± 0.25D± 0.5
Symbol
T olerance %
• Capacitance Tolerance (for Nominal Capacitance 10pF or less)
Symbol
Tolerance pFB± 0.1C± 0.25D± 0.5
3. Resistor (Res)
• Resistance tolerance
P
+ 100
0
Q
+ 30
– 10
T
+ 50
– 10
Ex. 10pF G = 10pF ± 2pF
F
± 1
U
+ 75
– 10
Table 4-2-2
F
± 1
Table 4-3-1
G
± 2
V
+ 20
– 10
G
± 2
J
± 5
W
+ 100
– 10
K
± 10
X
+ 40
– 20
Ex. 10µF J = 10µF ± 5%
M
± 20
Y
+ 150
– 10
N
± 30
Z
+ 80
– 20
PARTS LIST
SECTION 4
Symbol
T olerance %B± 0.1C± 0.25D± 0.5
F
± 1
4-1
G
± 2
J
± 5
Ex. 470Ω J = 470Ω ± 5%
K
± 10
M
± 20
Page 85
4. EXPLODED VIEWS
4-1. Packing Assembly
ZF23
(SD-1300A)
ZK02
ZF10
ZF11
ZK01
ZK04
ZF30
ZF23
(SD-1300T)
ZF20
ZF01
ZF23
(SD-1300H)
ZF23
(SD-1300Y)
ZK02
Fig. 4-4-1
4-2
Page 86
4-2. Chassis Assembly
ZG60
BID 3.0x6.0
ZG60
BID 3.0x6.0
ZG67
ZG64
EU02
ZG63
W502
ZG20
ZG27
W503
ZG22
W501
ZG71
ZG64
ZG60
BID 3.0x6.0
ZG60
BID 3.0x6.0
ZG71
ZG67
ZG03
EU04
ZG68
W102
ZG01
EU03
EU01
ZG69
W603
Fig. 4-4-2
4-3
Page 87
4-3. Mechanism Assembly
MC61
PAN 2.6x8.0
MC04
MP61
PAN 2.6x16
W3.3xt1xD10
MP01
MP60
PAN 1.7x4.0
MP92
Type A
MP16
MP37
MP91
PAN 2.6x5
RM01
MC12
MC03
MC11
MC10
MC14
MC63
BID 2.6x4.0
MC33
ZG63
MP36
MC02
MP36
MP65
PAN 1.7x3
EU05
MP37
FM01
MC01
W6.15P0.4D10.5
Fig. 4-4-3
4-4
MC65
PAN 2.6x8
MP02
Page 88
Mechanism Assembly (Type B)
MP61
MP01
PAN 2.6x16
W3.3xt1xD10
PAN 2.6x5
MP60
MP16
MP37
MP36
MP36
PAN 1.7x4.0
MP65
PAN 1.7x3
MP92
MP91
MP37
FM01
EU05
Type B
Note:
The pickup mechanism assembly has two types, A and B of
which shapes differ.
For the SD-1300A/H/T/Y, only Type A is a service part. Type B
can be changed to Type A pickup free from any performance
problem.
Fig. 4-4-4
4-5
Page 89
5. PARTS LIST
4-6
Page 90
4-7
Page 91
4-8
Page 92
SPECIFICATIONS
DVD Video Player/Outputs/Supplied Accessories
[DVD Video Player]
Power supply100-240V AC, 50/60 Hz
Power consumption16 VA (SD-1300Y: 16W)
Mass2.4 kg
External dimensions430 x 81 x 225 mm (W/H/D)
Signal systemPAL/3.58 NTSC
LaserSemiconductor laser, wavelength 650/780 nm
Frequency rangeDVD linear sound :48 kHz sampling 4 Hz to 22 kHz
96 kHz sampling 4 Hz to 44 kHz
Signal-to-noise ratioMore than 112 dB
Audio dynamic rangeMore than 108 dB
Harmonic distortionLess than 0.002%
Wow and flutterBelow measurable level (less than ± 0.001% (W. PEAK))
Operating conditionsTemperature: 5 °C to 35 °C, Operation status: Horizontal
[Outputs]
Video output1.0 V (p-p), 75 Ω, negative sync., pin jack x 1
S video output(Y) 1.0 V (p-p), 75 Ω, negative sync., Mini DIN 4-pin x 1
(C) 0.3 V (p-p), 75 Ω
Component video output(Y) 1.0 V (p-p), 75 Ω, negative sync., pin jack x 1
(PB)/(PR) 0.7 V (p-p), 75 Ω, pin jack x 2
Audio output (BITSTREAM/PCMOptical connector x 1
OPTICAL)
Audio output (BITSTREAM/PCM0.5 V (p-p), 75 Ω, pin jack x 1
COAXIAL)