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P25-S526
Schematics
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Toshiba P25-S526 Schematics

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BTQ00 Rev0.1 Schematics Document
Intel Prescott uFCPGA-478 / P4 Northwood
with Springdale / ICH5 / nVIDIA NV18/34/31M chipset
2003/02/20
3 3
4 4
Compal Electronics, Inc.
Title
LA-1841
Cove r Sheet
1 57Thursday, February 20, 2003
E
Size Document Number Rev
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A
B
C
D
Date: Sheet of
A
B
C
D
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Compal Confidential
File Name : BTQ00
1 1
CRT Connector
LVDS Interface
TV OUT Connector (4Pin Reverse)
2 2
page 22
page 22
page 22
NV18/31/34M
PIRQA#
Fan Control
VGA
page 16,17, 18,19
VRAM DDR 32MB/64MB (FBGA)
page 20,21
page 45
AGP BUS(8X)
Desktop Northwood uFCPGA-478 CPU
page 4,5,6
PSB
400/533/667/800MHz
H_D#(0..63)H_A#(3..31)
Intel Springdale MCH
FCBGA-932
page 7,8,9,10,11
Hub-Link
Thermal Sensor ADM1032AR
Memory BUS(DDR)
2.5V DDR- 200/266
USB2.0
page 5
DDR-SO-DIMM X2
BANK 0, 1, 2, 3
Desktop Prescott uFCPGA-478 CPU
Clock Generator
ICS 952623
page 15
page 12,13,14
USB Conn *4
page 37
MDC & BT Conn
page 38
3.3V 33 MHz
IDSEL: AD18 IDSEL: AD16 PIRQA#, GNT0#, REQ0#
IEEE 1394 TSB43AB21
page 30
RTC CKT.
3 3
Power OK CKT.
Power On/Off CKT.
DC/DC Interface CKT.
4 4
PIRQC#, PIRQD#
GNT1#, REQ1#
page 41
Mini PCI socket
page 29
IDSEL: AD17 PIRQB#, GNT3#, REQ3#
LAN
RTL 8101L
page 26
RJ45/11 CONN
page 26
Touch Pad
page 44
EC I/O Buffer
page 40
IDSEL: AD20 PIRQB#, SIRQ, GNT2#, REQ2#
EC
PCI BUS
CardBus Controller Toshiba TC6385XB
Slot 0,1
page 28
page 27,28
SD Conn.
page 27
NS87591L
page 39
Int.KBD
BIOS (1MB)
page 39
page 40
Intel ICH5
mBGA-460
page 23,24,25
LPC BUS
PARALLEL
AC-LINK
ATA-100
Primary IDE
Secondary IDE
ATA-100
SMsC LPC47N227
Super I/O
page 36
page 38
FIR
page 37
master
Floppy
AC97 Codec
ALC202
page 31
HDD Connector
page 35
master/slave
Audio DJ
OZ-168
Module Conn.
(Main Module)
page 34
page 35
HW EQ CKT
page 32
Audio AMP
page 32
Module Conn.
(2nd Module)
page 35
Power Circuit DC/DC
Title
Size Document Number Rev
A
B
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Date: Sheet of
Compal Electronics, Inc.
Block Diag ram
LA-1841
2 57Thursday, February 20, 2003
E
0.1
A
B
C
D
E
Voltage Ra ils
Power Plane Description
1 1
2 2
VIN B+ +CPU_CORE +CPU_VID +VTT_GMCH +1.225V (Prescott) / +1.45V (Northwood) +VGA_CORE ON OFF OFF1.2V switched power rail for VGA chip +1.25VS 1.25V switched power rail +1.5VS +2.5V +2.5VS 2.5V switched power rail +3VALW +3V +3VS +5VALW +5V +5VS
+RTCVCC
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Adapter power supply (19V) AC or battery power rail for power circuit. Core voltage for CPU
1.2V switched power rail for CPU AGTL Bus
AGP 4X/8X
2.5V power rail
3.3V always on power rail
3.3V power rail
3.3V switched power rail 5V always on power rail 5V power rail 5V switched power rail 12V always on power rail RTC power
S1 S3 S5
N/A N/A N/A
ON OFF ON OFF ON OFF OFF
ON OFF OFF ON OFF OFF ON ON ON ON ON ON ON ON ON ON+12VALW ON
N/AN/AN/A OFF OFF
OFF
ON
OFF
OFF ON ON*
OFF
ON OFF
OFF
ON
ON* OFF
OFF
OFF
ON
ON* ON
ON
STATE
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
Board ID Table for AD channel
Vcc 3.3V +/- 5%
Board ID
0 1 2 3 4 5 6 7 NC
SIGNAL
SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
HIGH HIGH HIGH HIGH
LOW
LOW
LOW LOW LOW LOW
100K +/- 5%Ra
Rb V min
0
8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5%
ON
ON
ON ON
ON
ON
LOW
AD_BID
0 V
HIGH
LOWLOWLOW
HIGHHIGHHIGH
HIGH
HIGH
V typ
AD_BID
ON
ON
ON
0 V 0 V
ON
OFF
OFF
V
AD_BID
ON
OFF
OFF
OFF
max
0.216 V 0.250 V 0.289 V
0.436 V
0.712 V
1.036 V
0.503 V
0.819 V
0.538 V
0.875 V
1.185 V 1.264 V
1.453 V 1.650 V 1.759 V
1.935 V
2.500 V
2.200 V
3.300 V
2.341 V
3.300 V
LOW
OFF
OFF
OFF
External PCI Device s
Device IDSEL# REQ#/GNT# Interrupts
VGA
CardBus
LAN
Mini-PCI
1394 AD16 0 PIRQA
3 3
SD AD22
EC SM Bus1 address
Device
Smart Battery EEPROM(24C16/02)
(24C04)
AD20 AD17 AD18
2 3 PIRQB 1/4
EC SM Bus2 address
Address Address
1010 000X b 1011 000Xb
Device
ADM1032 OZ168
PIRQA PIRQA/PIRQB
PIRQC/PIRQD
1001 110X b0001 011X b 0011 0100 b
Board ID
0 1 2 3 4 5 6 7
PCB Revision
0.1
ICH4 SM Bus address
4 4
Device
Clock Generator ( ICS 952623)
DDR DIMM0 DDR DIMM1
A
Address
1101 001Xb
1001 000Xb 1001 001Xb
Compal Electronics, Inc.
Title
Size Document Number Rev
B
B
C
D
Date: Sheet of
LA-1841
Notes
3 57Thursday, February 20, 2003
E
5
4
3
2
1
D D
C C
1 2 1 2
B B
A20A8AA10
AA12
AA14
AA16
AA18
AA8
AB11
AB13
AB15
AB17
AB19
AB7
AB9
AC10
AC12
AC14
AC16
AC18
AC8
AD11
AD13
AD15
AD17
AD19
AD7
AD9
AE10
AE12
AE14
AE16
AE18
AE20
AE6
AE8
AF11
AF13
AF15
AF17
AF19
AF21
B19B7B9
C20C8D11
D19D7D9
VCC_0
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VSS_0
H1H4H23
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VCC_9
VSS_7
VCC_10
VCC_11
VSS_8
VSS_9
VCC_12
VCC_13
VSS_10
VSS_11
A26A3A9
VCC_14
VCC_15
VSS_12
VSS_13
AA1
VCC_16
VCC_17
VSS_14
VSS_15
AA11
AA13
VCC_18
VCC_19
VSS_16
VSS_17
AA15
AA17
VCC_20
VCC_21
VSS_18
VSS_19
AA19
AA23
VCC_22
VCC_23
VSS_20
VSS_21
AA26
AA4
VCC_24
VCC_25
VSS_22
VSS_23
AA7
AA9
VCC_26
VCC_27
VSS_24
VSS_25
AB10
AB12
VCC_28
VSS_26
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
Prescott
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
AB14
AB16
VSS_36
AB18
AB20
AB21
AB24
AB3
AB6
AB8
AC11
AC13
VCC_39
VCC_40
VSS_37
VSS_38
AC15
AC17
VCC_41
VCC_42
VSS_39
VSS_40
AC19
AC2
VCC_43
VCC_44
VSS_41
VSS_42
AC22
AC25
VCC_45
VCC_46
VSS_43
VSS_44
AC5
AC7
VCC_47
VCC_48
VSS_45
VSS_46
AC9
AD10
VCC_49
VCC_50
VSS_47
VSS_48
AD12
AD14
VCC_51
VCC_52
VSS_49
VSS_50
AD16
AD18
VCC_53
VCC_54
VSS_51
VSS_52
AD21
AD23
VCC_55
VCC_56
VSS_53
VSS_54
AD4
AD8
VCC_57
VSS_55
VCC_58
VCC_59
VCC_61
BOOTSELECT
AD1
VCC_62
VCC_63
VCC_81
VCC_82
VCC_64
VCC_65
VCC_83
VCC_84
F9
VCC_66
VCC_67
VCC_80
VCC_85
VCC_68
VCC_69
VCC_78
VCC_79
E20E8F11
VCC_70
VCC_71
VCC_76
VCC_77
VCC_72
VCC_73
VCC_74
VCC_75
B21
D#0
B22
D#1
A23
D#2
A25
D#3
C21
D#4
D22
D#5
B24
D#6
C23
D#7
C24
D#8
B25
D#9
G22
D#10
H21
D#11
C26
D#12
D23
D#13
J21
D#14
D25
D#15
H22
D#16
E24
D#17
G23
D#18
F23
D#19
F24
D#20
E25
D#21
F26
D#22
D26
D#23
L21
D#24
G26
D#25
H24
D#26
M21
D#27
L22
D#28
J24
D#29
K23
D#30
H25
D#31
M23
D#32
N22
D#33
P21
D#34
M24
D#35
N23
D#36
M26
D#37
N26
D#38
N25
D#39
R21
D#40
P24
D#41
R25
D#42
R24
D#43
T26
D#44
T25
D#45
T22
D#46
T23
D#47
U26
D#48
U24
D#49
U23
D#50
V25
D#51
U21
D#52
V22
D#53
V24
D#54
W26
D#55
Y26
D#56
W25
D#57
Y23
D#58
Y24
D#59
Y21
D#60
AA25
D#61
AA22
D#62
AA24
D#63
K2
A#3
K4
A#4
L6
A#5
K1
A#6
L3
A#7
M6
A#8
L2
A#9
M3
A#10
M4
A#11
N1
A#12
M1
A#13
N2
A#14
N4
A#15
N5
A#16
T1
A#17
R2
A#18
P3
A#19
P4
A#20
R3
A#21
T2
A#22
U1
A#23
P6
A#24
U3
A#25
T4
A#26
V2
A#27
R6
A#28
W1
A#29
T5
A#30
U4
A#31
V3
A#32
W2
A#33
Y1
A#34
AB1
A#35
J1
REQ#0
K5
REQ#1
J4
REQ#2
J3
REQ#3
H3
REQ#4
G1
ADS#
AC1
AP#0
V5
AP#1
AA3
BINIT#
AC3
IERR#
H6
BR0#
D2
BPRI#
G2
BNR#
G4
LOCK#
AF22
BCLK0
AF23
BCLK1
F3
HIT#
E3
HITM#
E2
DEFER#
1 2
1 2
R_C
Reference Intel document Desktop P4 Spec.: 10988 P4 0.13u 512KB L2 EMTS Rev.2.0 Desktop Prescott Spec.: 11910 Prescott EMTS Rev.0.5
Pin number Northwood
P in name
B6 FERR# F ERR#/PBE# Pull-up 62ohm
AA20 I TPCLKOUT0 Pull-up56ohm
AB22 I TPCLKOUT1 Pull-up 56ohm
AD2 NC V IDPWRGD Pull-up 8.2Kohm
AD3 NC float VID5 Pull-up1Kohm to
A A
AF3 NC float V CCVIDLB Connect to +VCCVID AD20 VCCA V CCIOPLLConnect to CPU
AF23 Connect to CPU
V CCIOPLL VCCA
AD1 VSS B OOTSELECTConnect to GND CPU determine AE26 VSS Connect to GND OPTIMIZED/
C ommend Commend
Pull-up 62ohm to +VCC_CORE
to +VCC_CORE
to +VCC_CORE float
Filter
Filter
5
P rescott P in name
to +VCC_CORE
T ESTHI6 Pull-up 62ohm
to +VCC_CORE
T ESTHI7 Pull-up 62ohm
to +VCC_CORE
to +VCCVID
+3VRUN & connect t o PWRIC
Connect to CPU Filter
Connect to CPU Filter
float
COMPAT#
N orthwood P rescott
Pop Pop
Pop Pop
Pop Pop
PopDepop
Depop
Depop
Pop
Pop
Pop Depop
Pop Depop
4
3
Pop: Northwood Depop: Prescott
Compal Electronics, Inc.
Prescott Processor in uFCPGA478 (1/2)
2
LA-1841
1
5
4
3
2
1
1 2
1 2
1 2
D D
1 2
C C
B B
Note: Please change to 10uH, DC current of 100mA parts and close to cap
1 2
1 2
PLL Layout note :
1.Place cap within 600 mils of the VCCA and VSSA pins.
2.H_VCCIOPLL,HVCCA,HVSSA trace wide 12 mils(min)
Place near ICH
Place near CPU
+
1 2
Pop: Prescott Depop: Northwood
1 2 1 2 1 2 1 2 1 2 1 2
1 2
1 2
AE11
AE13
AE15
AE17
AE19
AE22
AE24
AE7
AE9
AF10
AF12
AF14
AF16
AF18
AF20
B26B4B8
C19C2C22
C25C5C7C9D10
D24D3D6D8E1
E26E4E7E9F10
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_161
VSS_162
T24T3T6U2U22
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
U25U5V1
VSS_99
VSS_100
VSS_169
VSS_170
VSS_101
VSS_102
VSS_171
VSS_172
V26V4W21
VSS_103
VSS_104
VSS_173
VSS_174
W24W3W6Y2Y22
VSS_105
VSS_106
VSS_175
VSS_176
VSS_107
VSS_108
VSS_177
VSS_178
VSS_109
VSS_110
VSS_179
VSS_180
Y5
VSS_111
VSS_112
VSS_181
VSS_113
VSS_114
AE5
VSS_115
VSS_116
VID0
VID1
AE4
AE3
VSS_117
VSS_118
VID2
VID3
AE2
AE1
VSS_119
VSS_120
VID4
VID5
AD3
VSS_121
F1
RS#0
G5
RS#1
F4
RS#2
AB2
RSP#
J6
TRDY#
C6
A20M#
B6
FERR#
B2
IGNNE#
B5
SMI#
AB23
PWRGOOD
Y4
STPCLK#
D1
LINT0
E5
LINT1
W5
INIT#
AB25
RESET#
H5
DBSY#
H2
DRDY#
AD6
BSEL0
AD5
BSEL1
B3
THERMDA
C4
THERMDC
A2
THERMTRIP#
AC6
BPM#0
AB5
BPM#1
AC4
BPM#2
Y6
BPM#3
AA5
BPM#4
AB4
BPM#5
D4
TCK
C1
TDI
D5
TDO
F7
TMS
E6
TRST#
AD20
VCCIOPLL
AE23
VCCA
A5
VCCSENSE
A4
VSSSENSE
AF3
VCCVIDLB
AD22
VSSA
AC26
ITP_CLK0
AD26
ITP_CLK1
L24
COMP0
P1
12
12
COMP1
VSS_129
F8
G21
VSS_130
VSS_131
VSS_132
VSS_133
G24G3G6J2J22
VSS_134
VSS_135
J25J5K21
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
K24K3K6L1L23
VSS_142
VSS_143
L26L4M2
VSS_144
VSS_145
VSS_146
VSS_147
M22
M25M5N21
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
N24N3N6P2P22
Prescott
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
P25P5R1
R26R4T21
VSS_122
F18F2F22
VSS_123
VSS_124
VIDPWRGD
AD2
VSS_125
VSS_126
VSS_127
AF26
F5
VSS_128
SKTOCC#
OPTIMIZED/COMPAT#
VCCVID
1
2
GTLREF0 GTLREF1 GTLREF2 GTLREF3
TESTHI0 TESTHI1 TESTHI2 TESTHI3 TESTHI4 TESTHI5 TESTHI6 TESTHI7 TESTHI8
TESTHI9 TESTHI10 TESTHI11 TESTHI12
DSTBN#0 DSTBN#1 DSTBN#2 DSTBN#3
DSTBP#0 DSTBP#1 DSTBP#2 DSTBP#3
ADSTB#0 ADSTB#1
PROCHOT#
MCERR#
J26
DP#0
K25
DP#1
K26
DP#2
L25
DP#3
AA21 AA6 F20 F6
AE26
AD24 AA2 AC21 AC20 AC24 AC23 AA20 AB22 U6 W4 Y3 A6 AD25
E22 K22 R22 W22
F21 J23 P23 W23
L5 R5
E21
DBI#0
G25
DBI#1
P26
DBI#2
V21
DBI#3
AE25
DBR#
C3 V6 AB26
SLP#
A22
NC1
A7
NC2
AF25
NC3
AF24
NC4
AE21
NC5
R_E
1 2
R_G
1 2
1 2
RE Pop: Prescott Depop: Northwood
1 2 1 2
1 2
1 2 1 2 1 2 1 2 1 2
1 2 1 2
Pop: Northwood Depop: Prescott
1 2
Pop: P4 Protability Depop: Prescott/Northwood
1 2 1 2
45 36 27 18
122
12
GTL Reference Voltage
Layout note :
1. +CPU_GTLREF Trace wide 12mils(min),Space 15mils
2. Place R_A and R_B near CPU.
3. Place decoupling cap 220PF near CPU.
12
2
1 8 2 7
A A
3 6 4 5
+CPU_GMCH_GTLREF trace wide 12mils(min),Space 15mils
R_A
R_B
1212
2 1
1
Close to the CPU
31
1 2
1
2
Compal Electronics, Inc.
1
2
2
VDD1
D+
3
ALERT#
D-
8
THERM#
SCLK
7
GND
SDATA
12
1 6
4
5
Prescott Processor in uFCPGA478 (2/2)
5
4
3
2
LA-1841
1
5
4
3
2
1
Place 11 North of Socket(Stuff 8)
1
2
D D
1
2
1
2
1
2
1
2
1
2
1
2
1
2
Place 12 Inside Socket(Stuff all)
1
2
1
2
C C
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
22uF depop reference Springdale Customer Schematic R1.2 page82
1
2
1
2
1
2
1
2
Place 9 South of Socket(Unstuff all)
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
B B
470uF _ERS10m ohm* 15, ESR=0.5m ohm
1
2
1
2
A A
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
Decoupling Reference Document: Springdale Chipset Platform Design guide Rev1.11 (12474)page239
Decoupling Reference Requirement: 560uF Polymer, ESR:5m ohm(each) * 10 22uF X5R * 32
Compal Electronics, Inc.
CPU Decoupling
LA-1841
5
4
3
2
1
5
4
3
2
1
+VTT_GMCH
D D
C C
+CPU_GMCH_GTLREF
GTL Reference Voltage
B B
A A
Layout note :
1. +GMCH_GTLREF Trace wide 12mils(min),Space 15mils.
2. Place decoupling cap 220PF near GMCH.
Trace width 10mils,Space 7mils
12
R365 301_0603_1%
HD_SWING
12
R369 102_0603_1%
HDRCOMP
12
R362
24.9_0603_1%
+VTT_GMCH
12
R359 200_0603_1%
1 2
R647 0_0603_5%
1
C159
0.01U_0402_16V7K
2
+GMCH_GTLREF
1
C160 220P_0402_50V8K
2
H_RS#[0..2]5
H_A#[3..31]4
H_REQ#[0..4]4
H_TRDY#5
+GMCH_GTLREF
H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3
H_RS#0 H_RS#1 H_RS#2
HDRCOMP HD_SWING
H_REQ#4
H_ADSTB#05 H_ADSTB#15
CLK_HCLK15 CLK_HCLK#15
H_DSTBP#05 H_DSTBN#05 H_DINV#05 H_DSTBP#15 H_DSTBN#15 H_DINV#15 H_DSTBP#25 H_DSTBN#25 H_DINV#25 H_DSTBP#35 H_DSTBN#35 H_DINV#35
H_ADS#4 H_DRDY#5
H_DEFER#4 H_HITM#4 H_HIT#4 H_LOCK#4 H_BR0#4 H_BNR#4
H_BPRI#4 H_DBSY#5
H_RESET#5 MCH_CLKSEL0 15
SYS_PWROK24,42
U36A
D26
HA3#
D30
HA4#
L23
HA5#
E29
HA6#
B32
HA7#
K23
HA8#
C30
HA9#
C31
HA10#
J25
HA11#
B31
HA12#
E30
HA13#
B33
HA14#
J24
HA15#
F25
HA16#
D34
HA17#
C32
HA18#
F28
HA19#
C34
HA20#
J27
HA21#
G27
HA22#
F29
HA23#
E28
HA24#
H27
HA25#
K24
HA26#
E32
HA27#
F31
HA28#
G30
HA29#
J26
HA30#
G26
HA31#
B29
HREQ0#
J23
HREQ1#
L22
HREQ2#
C29
HREQ3#
J21
HREQ4#
B30
HADSTB0#
D28
HADSTB1#
B7
HCLKP
C7
HCLKN
B19
HDSTBP0#
C19
HDSTBN0#
C17
DINV0#
L19
HDSTBP1#
K19
HDSTBN1#
L17
DINV1#
G9
HDSTBP2#
HDSTBN2#
L14
DINV2#
D12
HDSTBP3#
E12
HDSTBN3#
C15
DINV3#
F27
ADS#
D24
HTRDY#
G24
DRDY#
L21
DEFER#
E23
HITM#
K21
HIT#
E25
HLOCK#
B24
BREQ0#
B28
BNR#
B26
BPRI#
E27
DBSY#
G22
RS0#
C27
RS1#
B27
RS2#
E8
CPURST#
AE14
PWROK#
E24
HDRCOMP
C25
HDSWING
F23
HDVREF
SPRINGDALE_UFCBGA932
HD10# HD11# HD12# HD13# HD14# HD15# HD16# HD17# HD18# HD19# HD20# HD21# HD22# HD23# HD24# HD25# HD26# HD27# HD28# HD29# HD30# HD31# HD32# HD33# HD34# HD35# HD36# HD37# HD38#
FSB
HD39# HD40# HD41# HD42# HD43# HD44# HD45# HD46# HD47# HD48# HD49# HD50# HD51# HD52# HD53# HD54# HD55# HD56# HD57# HD58# HD59# HD60# HD61# HD62# HD63#
PROCHOT#
BSEL0 BSEL1
HD0# HD1# HD2# HD3# HD4# HD5# HD6# HD7# HD8# HD9#
B23 E22 B21 D20 B22 D22 B20 C21 E18 E20 B16 D16 B18 B17 E16 D18 G20 F17 E19 F19 J17 L18 G16 G18 F21 F15 E15 E21 J19 G14 E17 K17 J15 L16 J13 F13 F11 E13 K15 G12 G10 L15 E11 K13 J11 H10 G8 E9 B13 E14 B14 B12 B15 D14 C13 B11 D10 C11 E10 B10 C9 B9 D8 B8
L20
L13 L12
H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8
H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63
H_PROCHOT#
H_D#[0..63] 4
H_PROCHOT# 5,52
MCH_CLKSEL1 15
U36F
AR32
VSS
AR29
VSS
AR27
VSS
AR25
VSS
AR23
VSS
AR20
VSS
AR16
VSS
AR13
VSS
AR11
VSS
AR9
VSS
AN32
VSS
AN30
VSS
AN28
VSS
AN26
VSS
AN24
VSS
AN22
VSS
AN20
VSS
AN18
VSS
AN16
VSS
AN14
VSS
AN12
VSS
AN10
VSS
AM35
VSS
AM29
VSS
AM27
VSS
AM25
VSS
AM23
VSS
AM21
VSS
AM19
VSS
AM17
VSS
AM15
VSS
AM13
VSS
AM11
VSS
AM9
VSS
AL32
VSS
AL1
VSS
AK28
VSS
AK26
VSS
AK24
VSS
AK22
VSS
AK20
VSS
AK18
VSS
AK16
VSS
AK14
VSS
AK12
VSS
AK10
VSS
AK8
VSS
AK3
VSS
AJ35
VSS
AJ32
VSS
AJ9
VSS
AJ4
VSS
AJ1
VSS
AH33
VSS
AH30
VSS
AH24
VSS
AH22
VSS
AH20
VSS
AH18
VSS
AH16
VSS
AH14
VSS
AH12
VSS
AH10
VSS
AH6
VSS
AH3
VSS
AG35
VSS
AG32
VSS
AG28
VSS
AG26
VSS
AG24
VSS
AG22
VSS
AG20
VSS
AG18
VSS
AG16
VSS
AG14
VSS
AG8
VSS
AG4
VSS
AF33
VSS
AF30
VSS
AF25
VSS
AF24
VSS
AF22
VSS
AF20
VSS
AF18
VSS
AF16
VSS
AF14
VSS
AF11
VSS
AF9
VSS
AF6
VSS
AF3
VSS
AE35
VSS
AE32
VSS
AE26
VSS
AE25
VSS
AE13
VSS
AE12
VSS
SPRINGDALE_UFCBGA932
GND
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
AE11 AE10 AE4 AE1 AD33 AD30 AD28 AD10 AD9 AD8 AD6 AD3 AC35 AC32 AC4 AC1 AB33 AB30 AB28 AB27 AB26 AB10 AB9 AB8 AB6 AB3 AA32 AA4 AA1 Y35 Y33 Y30 Y28 Y27 Y26 Y10 Y9 Y8 Y6 Y3 W32 W18 W17 W4 V33 V30 V28 V27 V26 V19 V17 V10 V9 V8 V6 V3 U32 U19 U18 U4 T35 T33 T30 T28 T27 T26 T10 T9 T8 T6 T3 T1 R32 R4 R1 P33 P30 P28 P27 P26 P9 P8 P6 P3 N35 N32 N4 N1 M33 M30 M28 M27 M26 M6 M3 L35
U36G
L31
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
GND
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
L26 L25 L24 K33 K29 K27 K25 K22 K20 K18 K16 K14 K12 K11
J35 J32 J28 J22 J20 J18 J16 J14 J12
J10 H33 H30 H26 H24 H22 H20 H18 H16 H14 H12
H9 H8 H5
H2 G35 G31 G28
F26 F24 F22 F20 F18
SPRINGDALE_UFCBGA932
F16 F14 F12 F10 F8 F5 F3 F1 E3 E1 D35 D33 D31 D29 D27 D25 D23 D21 D19 D17 D15 D13 D11 D9 D1 C28 C26 C24 C22 C20 C18 C16 C14 C12 C10 C8 C4 A32 A29 A27 A25 A23 A20 A16 A13 A11 A9 A7
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
3
2
Springdale-Host/GND (1/4)
Size Document Number Rev
B
LA-1841
Date: Sheet of
7 57Thursday, February 20, 2003
1
5
4
3
2
1
DDRA_SMA[0..12]12,14
D D
C C
+SM_VREF_A
+SM_VREF_A trace width of 12mils and space 12mils(min)
2
1
C528
2.2U_0805_16V4Z
2
1
C522
0.1U_0402_16V4Z
DDRA_SMA[0..12]
DDRA_SWE#12,14 DDRA_SCAS#12,14 DDRA_SRAS#12,14
DDRA_SBS012,14 DDRA_SBS112,14
DDRA_SCS#012,14 DDRA_SCS#112,14
DDRA_CKE012,14 DDRA_CKE112,14
DDRA_CLK112 DDRA_CLK1#12 DDRA_CLK212 DDRA_CLK2#12
DDRA_SMA0 DDRA_SMA1 DDRA_SMA2 DDRA_SMA3 DDRA_SMA4 DDRA_SMA5 DDRA_SMA6 DDRA_SMA7 DDRA_SMA8 DDRA_SMA9 DDRA_SMA10 DDRA_SMA11 DDRA_SMA12
DDRA_SCS#0 DDRA_SCS#1 DDRA_SDQ18
DDRA_CKE0 DDRA_CKE1
SMXRCOMP SMXRCOMPVOH SMXRCOMPVOL
Close to GMCH(E34)
B B
+2.5V
Trace width of 12mils and space 10mils(min)
12
R151
40.2_0603_1%
2
C201
2.2U_0805_16V4Z
1
A A
5
SMXRCOMP
12
R152
40.2_0603_1%
Change to 42.2_1%
Place resistors within
1.0 inch of GMCH (AK9)
Change to 42.2_1%
U36B
AJ34
SMAA_A0
AL33
SMAA_A1
AK29
SMAA_A2
AN31
SMAA_A3
AL30
SMAA_A4
AL26
SMAA_A5
AL28
SMAA_A6
AN25
SMAA_A7
AP26
SMAA_A8
AP24
SMAA_A9
AJ33
SMAA_A10
AN23
SMAA_A11
AN21
SMAA_A12
AL34
SMAB_A1
AM34
SMAB_A2
AP32
SMAB_A3
AP31
SMAB_A4
AM26
SMAB_A5
AB34
SWE_A#
Y34
SCAS_A#
AC33
SRAS_A#
AE33
SBA_A0
AH34
SBA_A1
AA34
SCS_A0#
Y31
SCS_A1#
Y32
SCS_A2#
W34
SCS_A3#
AL20
SCKE_A0
AN19
SCKE_A1
AM20
SCKE_A2
AP20
SCKE_A3
AK32
SCMDCLK_A0
AK31
SCMDCLK_A0#
AP17
SCMDCLK_A1
AN17
SCMDCLK_A1#
N33
SCMDCLK_A2
N34
SCMDCLK_A2#
AK33
SCMDCLK_A3
AK34
SCMDCLK_A3#
AM16
SCMDCLK_A4
AL16
SCMDCLK_A4#
P31
SCMDCLK_A5
P32
SCMDCLK_A5#
E34
SMVREF_A
AK9
SMXRCOMP
AN9
SMXRCOMPVOH
AL9
SMXRCOMPVOL
SPRINGDALE_UFCBGA932
4
AN11
SDQS_A0
AP12
SDM_A0
AP10
SDQ_A0
AP11
SDQ_A1
AM12
SDQ_A2
AN13
SDQ_A3
AM10
SDQ_A4
AL10
SDQ_A5
AL12
SDQ_A6
AP13
SDQ_A7
AP15
SDQS_A1
AP16
SDM_A1
AP14
SDQ_A8
AM14
SDQ_A9
AL18
SDQ_A10
AP19
SDQ_A11
AL14
SDQ_A12
AN15
SDQ_A13
AP18
SDQ_A14
AM18
SDQ_A15
AP23
SDQS_A2
AM24
SDM_A2
AP22
SDQ_A16
AM22
SDQ_A17
AL24
SDQ_A18
AN27
SDQ_A19
AP21
SDQ_A20 SDQ_A21 SDQ_A22 SDQ_A23
SDQS_A3
SDM_A3
SDQ_A24 SDQ_A25 SDQ_A26 SDQ_A27 SDQ_A28 SDQ_A29 SDQ_A30 SDQ_A31
SDQS_A4
SDM_A4
SDQ_A32 SDQ_A33 SDQ_A34 SDQ_A35 SDQ_A36 SDQ_A37 SDQ_A38 SDQ_A39
SDQS_A5
SDM_A5
SDQ_A40 SDQ_A41 SDQ_A42 SDQ_A43 SDQ_A44 SDQ_A45 SDQ_A46 SDQ_A47
SDQS_A6
SDM_A6
SDQ_A48 SDQ_A49 SDQ_A50 SDQ_A51 SDQ_A52 SDQ_A53 SDQ_A54 SDQ_A55
SDQS_A7
SDM_A7
SDQ_A56 SDQ_A57 SDQ_A58 SDQ_A59 SDQ_A60 SDQ_A61 SDQ_A62 SDQ_A63
AL22 AP25 AP27
AM30 AP30
AP28 AP29 AP33 AM33 AM28 AN29 AM31 AN34
AF34 AF31
AH32 AG34 AF32 AD32 AH31 AG33 AE34 AD34
V34 W33
AC34 AB31 V32 V31 AD31 AB32 U34 U33
M32 M34
T34 T32 K34 K32 T31 P34 L34 L33
H31 H32
J33 H34 E33 F33 K31 J34 G34 F34
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DDR Channel A
DDRA_SDQS0 12,14
DDRA_SDQ0 DDRA_SDQ1 DDRA_SDQ2 DDRA_SDQ3 DDRA_SDQ4 DDRA_SDQ5 DDRA_SDQ6 DDRA_SDQ7
DDRA_SDQ8 DDRA_SDQ9 DDRA_SDQ10 DDRA_SDQ11 DDRA_SDQ12 DDRA_SDQ13 DDRA_SDQ14 DDRA_SDQ15
DDRA_SDQ16 DDRA_SDQ17
DDRA_SDQ19 DDRA_SDQ20 DDRA_SDQ21 DDRA_SDQ22 DDRA_SDQ23
DDRA_SDQ24 DDRA_SDQ25 DDRA_SDQ26 DDRA_SDQ27 DDRA_SDQ28 DDRA_SDQ29 DDRA_SDQ30 DDRA_SDQ31
DDRA_SDQ32 DDRA_SDQ33 DDRA_SDQ34 DDRA_SDQ35 DDRA_SDQ36 DDRA_SDQ37 DDRA_SDQ38 DDRA_SDQ39
DDRA_SDQ40 DDRA_SDQ41 DDRA_SDQ42 DDRA_SDQ43 DDRA_SDQ44 DDRA_SDQ45 DDRA_SDQ46 DDRA_SDQ47
DDRA_SDQ48 DDRA_SDQ49 DDRA_SDQ50 DDRA_SDQ51 DDRA_SDQ52 DDRA_SDQ53 DDRA_SDQ54 DDRA_SDQ55
DDRA_SDQ56 DDRA_SDQ57 DDRA_SDQ58 DDRA_SDQ59 DDRA_SDQ60 DDRA_SDQ61 DDRA_SDQ62 DDRA_SDQ63
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DDRA_SDM0 12,14
DDRA_SDQS1 12,14 DDRA_SDM1 12,14
DDRA_SDQS2 12,14 DDRA_SDM2 12,14
DDRA_SDQS3 12,14 DDRA_SDM3 12,14
DDRA_SDQS4 12,14 DDRA_SDM4 12,14
DDRA_SDQS5 12,14 DDRA_SDM5 12,14
DDRA_SDQS6 12,14 DDRA_SDM6 12,14
DDRA_SDQS7 12,14 DDRA_SDM7 12,14
3
DDRA_SDQ[0..63]
DDRA_SDQ[0..63] 12,14
2
C523
2.2U_0805_16V4Z
1
1
C533 1U_0603_10V6K
2
2
C217
2.2U_0805_16V4Z
1
1
C220 1U_0603_10V6K
2
+2.5V
Trace width of 12mils and space 10mils(min)
12
R390 10K_0603_1%
SMXRCOMPVOH
12
R391
30.9K_0603_1%
*
*
Change to 31.12K
Follow Intel design guide R1.11(12474) page124,125
+2.5V
Trace width of 12mils and space 10mils(min)
12
R153
30.9K_0603_1%
*
SMXRCOMPVOL
12
R154 10K_0603_1%
Title
Size Document Number Rev
B
2
Date: Sheet of
1
C196
0.01U_0402_16V7K
2
Close to Pin AN9
Close to GMCH <1"
1
C190
0.01U_0402_16V7K
2
Close to Pin AL9
Close to GMCH <1"
Compal Electronics, Inc.
Springdale-DDR Interface-A(2/5)
LA-1841
1
8 57Thursday, February 20, 2003
5
4
3
2
1
DDRB_SMA[0..12]13,14
D D
C C
SM_VREF_B and SM_VREF_A are connected inside GMCH.
+2.5V
2
12
R392 150_0603_1%
12
B B
R396 150_0603_1%
1
2
1
C539
2.2U_0805_16V4Z
C547
2.2U_0805_16V4Z
DDRB_SMA[0..12]
DDRB_SWE#13,14 DDRB_SCAS#13,14 DDRB_SRAS#13,14
DDRB_SBS013,14 DDRB_SBS113,14
DDRB_SCS#013,14 DDRB_SCS#113,14
DDRB_CKE013,14 DDRB_CKE113,14
DDRB_CLK113 DDRB_CLK1#13 DDRB_CLK213 DDRB_CLK2#13
+SM_VREF_B
+SM_VREF_B trace width of 12mils and space 12mils(min)
2
C200
0.1U_0402_16V4Z
1
DDRB_SMA0 DDRB_SMA1 DDRB_SMA2 DDRB_SMA3 DDRB_SMA4 DDRB_SMA5 DDRB_SMA6 DDRB_SMA7 DDRB_SMA8 DDRB_SMA9 DDRB_SMA10 DDRB_SMA11 DDRB_SMA12
DDRB_SCS#0 DDRB_SCS#1
DDRB_CKE0 DDRB_CKE1
SMYRCOMP SMYRCOMPVOH SMYRCOMPVOL
Close to GMCH(AP9)
+2.5V
2
12
R399
Change to 42.2_1%
Change to 42.2_1%
A A
40.2_0603_1%
SMYRCOMP
12
R400
40.2_0603_1%
C553
2.2U_0805_16V4Z
1
Trace width of 12mils and space 10mils(min)
Place resistors within
1.0 inch of GMCH (AA33)
U36C
AG31
SMAA_B0
AJ31
SMAA_B1
AD27
SMAA_B2
AE24
SMAA_B3
AK27
SMAA_B4
AG25
SMAA_B5
AL25
SMAA_B6
AF21
SMAA_B7
AL23
SMAA_B8
AJ22
SMAA_B9
AF29
SMAA_B10
AL21
SMAA_B11
AJ20
SMAA_B12
AE27
SMAB_B1
AD26
SMAB_B2
AL29
SMAB_B3
AL27
SMAB_B4
AE23
SMAB_B5
W27
SWE_B#
W31
SCAS_B#
W26
SRAS_B#
Y25
SBA_B0
AA25
SBA_B1
U26
SCS_B0#
T29
SCS_B1#
V25
SCS_B2#
W25
SCS_B3#
AK19
SCKE_B0
AF19
SCKE_B1
AG19
SCKE_B2
AE18
SCKE_B3
AG29
SCMDCLK_B0
AG30
SCMDCLK_B0#
AF17
SCMDCLK_B1
AG17
SCMDCLK_B1#
N27
SCMDCLK_B2
N26
SCMDCLK_B2#
AJ30
SCMDCLK_B3
AH29
SCMDCLK_B3#
AK15
SCMDCLK_B4
AL15
SCMDCLK_B4#
N31
SCMDCLK_B5
N30
SCMDCLK_B5#
AP9
SMVREF_B
AA33
SMYRCOMP
R34
SMYRCOMPVOH
R33
SMYRCOMPVOL
SPRINGDALE_UFCBGA932
AF15
SDQS_B0
AG11
SDM_B0
AJ10
SDQ_B0
AE15
SDQ_B1
AL11
SDQ_B2
AE16
SDQ_B3
AL8
SDQ_B4
AF12
SDQ_B5
AK11
SDQ_B6
AG12
SDQ_B7
AG13
SDQS_B1
AG15
SDM_B1
AE17
SDQ_B8
AL13
SDQ_B9
AK17
SDQ_B10
AL17
SDQ_B11
AK13
SDQ_B12
AJ14
SDQ_B13
AJ16
SDQ_B14
AJ18
SDQ_B15
AG21
SDQS_B2
AE21
SDM_B2
AE19
SDQ_B16
AE20
SDQ_B17
AG23
SDQ_B18
AK23
SDQ_B19 SDQ_B20 SDQ_B21 SDQ_B22 SDQ_B23
SDQS_B3
SDM_B3
SDQ_B24 SDQ_B25 SDQ_B26 SDQ_B27 SDQ_B28 SDQ_B29 SDQ_B30 SDQ_B31
SDQS_B4
SDM_B4
SDQ_B32 SDQ_B33 SDQ_B34 SDQ_B35 SDQ_B36 SDQ_B37 SDQ_B38 SDQ_B39
SDQS_B5
SDM_B5
SDQ_B40 SDQ_B41 SDQ_B42 SDQ_B43 SDQ_B44 SDQ_B45 SDQ_B46 SDQ_B47
SDQS_B6
SDM_B6
SDQ_B48 SDQ_B49 SDQ_B50 SDQ_B51 SDQ_B52 SDQ_B53 SDQ_B54 SDQ_B55
SDQS_B7
SDM_B7
SDQ_B56 SDQ_B57 SDQ_B58 SDQ_B59 SDQ_B60 SDQ_B61 SDQ_B62 SDQ_B63
AL19 AK21 AJ24 AE22
AH27 AJ28
AK25 AH26 AG27 AF27 AJ26 AJ27 AD25 AF28
AD29 AC31
AE30 AC27 AC30 Y29 AE31 AB29 AA26 AA27
U30 U31
AA30 W30 U27 T25 AA31 V29 U25 R27
L27 M29
P29 R30 K28 L30 R31 R26 P25 L32
J30 J31
K30 H29 F32 G33 N25 M25 J29 G32
DDR Channel B
DDRB_SDQ0 DDRB_SDQ1 DDRB_SDQ2 DDRB_SDQ3 DDRB_SDQ4 DDRB_SDQ5 DDRB_SDQ6 DDRB_SDQ7
DDRB_SDQ8 DDRB_SDQ9 DDRB_SDQ10 DDRB_SDQ11 DDRB_SDQ12 DDRB_SDQ13 DDRB_SDQ14 DDRB_SDQ15
DDRB_SDQ16 DDRB_SDQ17 DDRB_SDQ18 DDRB_SDQ19 DDRB_SDQ20 DDRB_SDQ21 DDRB_SDQ22 DDRB_SDQ23
DDRB_SDQ24 DDRB_SDQ25 DDRB_SDQ26 DDRB_SDQ27 DDRB_SDQ28 DDRB_SDQ29 DDRB_SDQ30 DDRB_SDQ31
DDRB_SDQ32 DDRB_SDQ33 DDRB_SDQ34 DDRB_SDQ35 DDRB_SDQ36 DDRB_SDQ37 DDRB_SDQ38 DDRB_SDQ39
DDRB_SDQ40 DDRB_SDQ41 DDRB_SDQ42 DDRB_SDQ43 DDRB_SDQ44 DDRB_SDQ45 DDRB_SDQ46 DDRB_SDQ47
DDRB_SDQ48 DDRB_SDQ49 DDRB_SDQ50 DDRB_SDQ51 DDRB_SDQ52 DDRB_SDQ53 DDRB_SDQ54 DDRB_SDQ55
DDRB_SDQ56 DDRB_SDQ57 DDRB_SDQ58 DDRB_SDQ59 DDRB_SDQ60 DDRB_SDQ61 DDRB_SDQ62 DDRB_SDQ63
DDRB_SDQS0 13,14 DDRB_SDM0 13,14
DDRB_SDQS1 13,14 DDRB_SDM1 13,14
DDRB_SDQS2 13,14 DDRB_SDM2 13,14
DDRB_SDQS3 13,14 DDRB_SDM3 13,14
DDRB_SDQS4 13,14 DDRB_SDM4 13,14
DDRB_SDQS5 13,14 DDRB_SDM5 13,14
DDRB_SDQS6 13,14 DDRB_SDM6 13,14
DDRB_SDQS7 13,14 DDRB_SDM7 13,14
DDRB_SDQ[0..63]
2
C541
2.2U_0805_16V4Z
1
1
C546 1U_0603_10V6K
2
2
C219
2.2U_0805_16V4Z
1
1
C223 1U_0603_10V6K
2
DDRB_SDQ[0..63] 13,14
+2.5V
Trace width of 12mils and space 10mils(min)
12
R394 10K_0603_1%
SMYRCOMPVOH
12
R398
30.9K_0603_1%
1
C213
0.01U_0402_50V7K
2
Close to Pin R14
Close to GMCH <1"
+2.5V
Trace width of 12mils and space 10mils(min)
12
R163
30.9K_0603_1%
SMYRCOMPVOL
12
R164 10K_0603_1%
1
C211
0.01U_0402_50V7K
2
Close to Pin R33
Close to GMCH <1"
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Springdale-DDR Interface-B(3/5)
Size Document Number Rev
B
LA-1841
Date: Sheet of
9 57Thursday, February 20, 2003
1
5
4
3
2
1
+1.5VS
Change to 43.2_1%
12
R123
43_0402_5%
D D
C C
B B
A A
GRCOMP
+1.5VS
12
R353 226_0603_1%
HI_SWING_MCH
12
R368 147_0603_1%
HI_VREF_MCH
12
R372 113_0603_1%
1
C147
0.1U_0402_16V4Z
2
1
C166
0.1U_0402_16V4Z
2
1 2
R56
33.2_0603_1%
1
2
1
2
+1.5VS
12
CI_SWING_GMCH
12
12
+1.5VS
12
12
12
+1.5VS
Change to 52.3_1%
12
R116
51.1_0603_1%
HI_RCOMP_MCH
Note: HI_SWING_MCH, HI_VREF_MCH trace width of 10mils and space 7mils
Close to GMCH(AE3)
C499
0.1U_0402_16V4Z
C500
0.1U_0402_16V4Z
R122 226_0603_1%
R127 147_0603_1%
CI_VREF_GMCH
R130 113_0603_1%
1
C498
0.01U_0402_16V7K
2
Close to GMCH ball <250mils
Close to GMCH(AE2)
1
C503
0.01U_0402_16V7K
2
Close to GMCH ball <250mils
Note: CI_SWING_MCH, CI_VREF_MCH trace width of 10mils and space 20mils
0.8V
Close to GMCH(AF2)
1
C155
0.01U_0402_16V7K
2
Close to GMCH ball <250mils
0.35V
Close to GMCH(AF4)
1
C165
0.01U_0402_16V7K
2
Close to GMCH ball <250mils
R31
60.4_0603_1%
AGP_SWING
R32
39.2_0603_1%
R55
100_0603_1%
Close GMCH ball (AD2) less than 250mils
5
Close GMCH ball (AC3) less than 250mils
1
C9
0.1U_0402_16V4Z
2
+AGP_VREF
1
C127
0.01U_0402_16V7K
2
+1.5VS
?
R121 @10K_0402_5%
1 2
AGP_PAR
1: External AGP 0: Internal Graphics
CLK_MCH_66M
12
R337 @10_0402_5%
1
C486 @10P_0402_50V8K
2
AGP_C/BE#[0..3]16
AGP_FRAME#16 CLK_MCH_66M15 AGP_DEVSEL#16
AGP_IRDY#16 AGP_TRDY#16 AGP_STOP#16
AGP_PAR16
AGP_REQ#16 AGP_GNT#16
+AGP_VREF
AGP_RBF#16 AGP_WBF#16
AGP_DBIHI16 AGP_DBILO16
AGP_ST[0..2]16
HUB_HL[0..10]23
HUB_HLSTRF23
HUB_HLSTRS23
change to 52.3_1%
R375 54.9_0603_1%
+1.5VS
R92 0_0402_5%
ICH_SYNC#24
PCIRST#23,26,27,29,30,36,39
1
C113
0.01U_0402_16V7K
2
Follow Springdale Chipset Platform Design guide Rev1.11(12474)
Note: Springdale Customer Schematic R1.2 page18 AGP_SWING only had 0.1u cap ; But Springdale Chipset Platform Design guide Rev1.11(12474) page138 had a 0.01uf cap. need confirm with Intel.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1 2
R134 0_0402_5%
3
AGP_C/BE#0 AGP_C/BE#1 AGP_C/BE#2 AGP_C/BE#3
CLK_MCH_66M AGP_AD3
AGP_PAR
GRCOMP AGP_SWING +AGP_VREF
AGP_ST0 AGP_ST1 AGP_ST2
HUB_HL0 HUB_HL1 HUB_HL2 HUB_HL3 HUB_HL4 HUB_HL5 HUB_HL6 HUB_HL7 HUB_HL8 HUB_HL9 HUB_HL10
HI_RCOMP_MCH HI_SWING_MCH HI_VREF_MCH
CI_SWING_GMCH CI_VREF_GMCH
12
12
U36D
Y7
GCBE0
W5
GCBE1
AA3
GCBE2
U2
GCBE3
U6
GFRAME
H4
GCLKIN
AB4
GDEVSEL
V11
GIRDY
AB5
GTRDY
W11
GSTOP
AB2
GPAR/ADD_DETECT
N6
GREQ
M7
GGNT
AC2
GRCOMP/DVOBCGCOMP
AC3
GVSWING
AD2
GVREF
R10
GRBF
R9
GWBF
M4
DBI_HI
M5
DBI_LO
N3
GST0
N5
GST1
N2
GST2
AF5
AG3
AK2
AG5
AD11
AC10
AG7
AG6
AG2
AG10
AG9 AN35 AP34
HUB
AK5
AL3
AL2
AL4
AJ2
AH2
AJ3
HI10
AH5
HISTRF
AH4
HISTRS
AD4
HI_RCOMP
AE3
HI_SWING
AE2
HI_VREF
AK7
AH7
AF7
AD7
CSA
AF8
AE9
AH9
AJ6
CISTRF
AJ5
CISTRS CI_RCOMP
AF2
CI_SWING
AF4
CI_VREF
G4
DREFCLK
AP8
EXTTS#
AJ8
ICH_SYNC#
AK4
RSTIN# RESERVED_1
RESERVED_2 RESERVED_3 RESERVED_4
AR1
RESERVED_5
SPRINGDALE_UFCBGA932
AGP
GADSTBF0
GADSTBS0#
GAD0 GAD1 GAD2 GAD3 GAD4 GAD5 GAD6 GAD7 GAD8
GAD9 GAD10 GAD11 GAD12 GAD13 GAD14 GAD15
GADSTBF1
GADSTBS1#
GAD16 GAD17 GAD18 GAD19 GAD20 GAD21 GAD22 GAD23 GAD24 GAD25 GAD26 GAD27 GAD28 GAD29 GAD30 GAD31
GSBSTBF
GSBSTBS#
GSBA0# GSBA1# GSBA2# GSBA3# GSBA4# GSBA5# GSBA6# GSBA7#
DDCA_DATA
DDCA_CLK
RED#
GREEN
GREEN#
VGA
BLUE
BLUE# HSYNC
VSYNC
REFSET
NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8
NC_9 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16 NC_17 NC_18 NC_19 NC_20
2
RED
AC6 AC5
AGP_AD0
AE6
AGP_AD1
AC11
AGP_AD2
AD5 AE5
AGP_AD4
AA10
AGP_AD5
AC9
AGP_AD6
AB11
AGP_AD7
AB7
AGP_AD8
AA9
AGP_AD9
AA6
AGP_AD10
AA5
AGP_AD11
W10
AGP_AD12
AA11
AGP_AD13
W6
AGP_AD14
W9
AGP_AD15
V7 V4
V5
AGP_AD16
AA2
AGP_AD17
Y4
AGP_AD18
Y2
AGP_AD19
W2
AGP_AD20
Y5
AGP_AD21
V2
AGP_AD22
W3
AGP_AD23
U3
AGP_AD24
AGP_AD25
AGP_AD26
AGP_AD27
R2
AGP_AD28
P2
AGP_AD29
P5
AGP_AD30
P4
AGP_AD31
M2 U11
T11
AGP_SBA0
R6
AGP_SBA1
P7
AGP_SBA2
R3
AGP_SBA3
R5
AGP_SBA4
U9
AGP_SBA5
U10
AGP_SBA6
U5
AGP_SBA7
R88 0_0402_5%12
H3
R84 0_0402_5%12
R91 0_0402_5%12
R101 0_0402_5%12
H6 G5
R104 0_0402_5%
H7 G6
G3 E2
R322 0_0402_5%12
D2 A3
A33 A35
Analog RGB/CRT guidelines for Springdale-P
AF13 AF23 AJ12 AN1 AP2 AR3 AR33 AR35 B2 B25 B34 C1 C23 C35 E26 M31 R25
AGP_AD_STBF0 16 AGP_AD_STBS0 16
AGP_AD[0..31] 16
AGP_AD_STBF1 16 AGP_AD_STBS1 16
AGP_SB_STBF 16 AGP_SB_STBS 16 AGP_SBA[0..7] 16
12
Title
Springdale-AGP/HUB/VGA/CSA (4/5)
Size Document Number Rev
B
LA-1841
Date: Sheet of
10 57Thursday, February 20, 2003
1
5
Note: Placed less than 100 mils from ball
Route to GMCH ball without via
D D
1
C490
0.47U_0603_16V7K
2
2
C535
0.1U_0402_10V6K
1
C C
C548
0.1U_0402_10V6K
12
C552 0.22U_0603_10V7K
C520
0.47U_0603_16V7K
12
C532 0.22U_0603_10V7K
C163
Trace 14mils
B B
Note: Placed less than 100 mils from ball
Route to GMCH ball without via
A A
0.1U_0402_10V6K
12
12
C168 0.1U_0402_10V6K
R321 0_0402_5%12
12
R316 0_0402_5%
1 2
C242 0.1U_0402_10V6K
VTT_DCAP1 VTT_DCAP2
1
C496
0.47U_0603_16V7K
2
+VTT_GMCH
+2.5V
VCC_DDR_DCAP5
12
VCC_DDR_DCAP4
VCC_DDR_DCAP1
12
VCC_AGP_DCAP2
+3VS
+1.5VS
VTT_DCAP3 VCCA_FSB VCCA_DPLL VCCA_DAC
VCC_DDR_DCAP2 VCCA_FSB1 VCCA_FSB
VCCA1P5_DDR_SM
(1A)
A15 A21
AA35
AL6
AL7 AM1 AM2 AM3 AM5 AM6 AM7 AM8
AN2
AN4
AN5
AN6
AN7
AN8
AP3
AP4
AP5
AP6
AP7
AR15 AR21 AR31
*
AR4
AR5
AR7
E35
R35
G1 G2
AG1
Y11
A31
AL35 AB25 AC25 AC26
Decoupling Reference Document: Springdale Chipset Platform Design guide Rev1.11 (12474)page246,248
Decoupling Reference Document: Springdale Customer Schematic R1.2 page84
4
U36E
VTT VTT
A4
VTT
A5
VTT
A6
VTT
B5
VTT
B6
VTT
C5
VTT
C6
VTT
D5
VTT
D6
VTT
D7
VTT
E6
VTT
E7
VTT
VTT VCC_DDR
VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR VCC_DDR
VCC_DAC VCC_DAC
VCCA_AGP VCCA_AGP
VCCA_FSB
B4
VCCA_FSB
B3
VCCA_DPLL
C2
VCCA_DAC VCCA_DDR
VCCA_DDR VCCA_DDR VCCA_DDR
SPRINGDALE_UFCBGA932
POWER
VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP VCC_AGP
VSSA_DAC
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
J6 J7 J8 J9 K6 K7 K8 K9 L6 L7 L9 L10 L11 M8 M9 M10 M11 N9 N10 N11 P10 P11 R11 T16 T17 T18 T19 T20 U16 U17 U20 V16 V18 V20 W16 W19 W20 Y16 Y17 Y18 Y19 Y20
J1 J2 J3 J4 J5 K2 K3 K4 K5 L1 L2 L3 L4 L5
VCC_AGP_DCAP1
Y1 D3
+1.5VS
3
+2.5V
1
C174 22U_1206_10V4Z
2
+2.5V
1
C189
0.1U_0402_10V6K
2
+1.5VS
1
C171
0.1U_0402_10V6K
2
+1.5VS
1
+
C72 470U_D4_2.5VM
2
2
C186
4.7U_0805_6.3V6K
1
1
C185
0.1U_0402_10V6K
2
1
C112
0.1U_0402_10V6K
2
2
C157
4.7U_0805_6.3V6K
1
1
C169
0.1U_0402_10V6K
2
1
C222
0.1U_0402_10V6K
2
1
C135
0.1U_0402_10V6K
2
C156 10U_1206_16V4Z
Place at the output of the 1.5V VR
+VTT_GMCH +2.5V
1
C92
0.1U_0402_10V6K
2
Place near GMCH
1 2
C117
0.1U_0402_10V6K
+1.5VS
1
C126
0.1U_0402_10V6K
2
Place near ball Y11,routing trace from cap to ball
Note: Please change to 0.82uH, DC current of 30mA parts and close to cap
+1.5VS
12
R315 0_0603_5%
Note: Please change to 1uH(0.54uH-D-IN), DC current of 1000mA parts and close to cap Trace 50mils Trace 35mils (under GMCH ball field)
+1.5VS
VCCA_DDR VCCA1P5_DDR_SM
12
R144 0_0603_5%
1
C238
0.1U_0402_10V6K
2
+1.5VS
1
C175
0.1U_0402_10V6K
2
1
C125
0.1U_0402_10V6K
2
+VTT_GMCH
1
+
C28 470U_D4_2.5VM
2
L21
1 2
LQG21F4R7N00_0805
L16
1 2
LQG21F4R7N00_0805
2
1
C191
0.1U_0402_10V6K
2
1
C99
0.1U_0402_10V6K
2
1
C106
0.1U_0402_10V6K
2
2
C70
0.1U_0402_16V4Z
1
1
C183
0.1U_0402_10V6K
2
Place near GMCH
Trace 14milsTrace 14mils
12
C32
+
150U_D2_6.3VM
Trace 35mils
(1A)(1A)
1
C197 22U_1210_6.3V6M
2
1
C198
0.1U_0402_10V6K
2
1
C181
0.1U_0402_10V6K
2
2
C47
4.7U_0805_6.3V6K
1
1
C172
0.1U_0402_10V6K
2
1
C167
0.1U_0402_10V6K
2
2
1
2
C475
0.1U_0402_16V4Z
1
Close to GMCH
2
C212
0.1U_0402_16V4Z
1
Close to GMCH
1
C195
0.1U_0402_10V6K
2
1
C143
0.1U_0402_10V6K
2
C60
4.7U_0805_6.3V6K
1
1
C199
0.1U_0402_10V6K
2
1
C184
0.1U_0402_10V6K
2
1
C42 1U_0603_6.3V6M
2
1
C26
0.47U_0603_16V7K
2
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Size Document Number Rev
B
Date: Sheet of
Springdale-Decoupling (5/5)
LA-1841
1
11 57Thursday, February 20, 2003
5
D D
DDRA_CLK18 DDRA_CLK1#8
C C
DDRA_CKE18,14
DDRA_SBS08,14 DDRA_SWE#8,14 DDRA_SCS#08,14
B B
A A
ICH_SMB_DATA13,15,23 ICH_SMB_CLK13,15,23
5
+2.5V
JP26
1
VREF
3
DDRA_SDQ0 DDRA_SDQ1
DDRA_SDQS0 DDRA_SDQ6 DDRA_SDQ7
DDRA_SDQ2 DDRA_SDQ12
DDRA_SDQ8 DDRA_SDQS1
DDRA_SDQ10 DDRA_SDQ15
DDRA_SDQ20 DDRA_SDQ16
DDRA_SDQS2 DDRA_SDQ18
DDRA_SDQ19 DDRA_SDQ28
DDRA_SDQ29 DDRA_SDQS3
DDRA_SDQ30 DDRA_SDQ27
DDRA_CKE1 DDRA_SMA12
DDRA_SMA9 DDRA_SMA7
DDRA_SMA5 DDRA_SMA3 DDRA_SMA1
DDRA_SMA10 DDRA_SBS0 DDRA_SWE# DDRA_SCS#0
DDRA_SDQ36 DDRA_SDQ37
DDRA_SDQS4 DDRA_SDQ34
DDRA_SDQ35 DDRA_SDQ44
DDRA_SDQ41 DDRA_SDQ45 DDRA_SDQS5
DDRA_SDQ43 DDRA_SDQ46
DDRA_SDQ48 DDRA_SDQ53
DDRA_SDQS6 DDRA_SDQ54
DDRA_SDQ55 DDRA_SDQ60
DDRA_SDQ61 DDRA_SDQS7
DDRA_SDQ62 DDRA_SDQ59
+3VS
VSS
5
DQ0
7
DQ1
9
VDD
11
DQS0
13
DQ2
15
VSS
17
DQ3
19
DQ8
21
VDD
23
DQ9
25
DQS1
27
VSS
29
DQ10
31
DQ11
33
VDD
35
CK0
37
CK0#
39
VSS
41
DQ16
43
DQ17
45
VDD
47
DQS2
49
DQ18
51
VSS
53
DQ19
55
DQ24
57
VDD
59
DQ25
61
DQS3
63
VSS
65
DQ26
67
DQ27
69
VDD
71
CB0
73
CB1
75
VSS
77
DQS8
79
CB2
81
VDD
83
CB3
85
DU
87
VSS
89
CK2
91
CK2#
93
VDD
95
CKE1
97
DU/A13
99
A12
101
A9
103
VSS
105
A7
107
A5
109
A3
111
A1
113
VDD
115
A10/AP
117
BA0
119
WE#
121
S0#
123
DU
125
VSS
127
DQ32
129
DQ33
131
VDD
133
DQS4
135
DQ34
137
VSS
139
DQ35
141
DQ40
143
VDD
145
DQ41
147
DQS5
149
VSS
151
DQ42
153
DQ43
155
VDD
157
VDD
159
VSS
161
VSS
163
DQ48
165
DQ49
167
VDD
169
DQS6
171
DQ50
173
VSS
175
DQ51
177
DQ56
179
VDD
181
DQ57
183
DQS7
185
VSS
187
DQ58
189
DQ59
191
VDD
193
SDA
195
SCL
197
VDD_SPD
199
VDD_ID
KEYLINK_5762-3-111
4
4
VREF
VSS DQ4 DQ5
VDD DM0 DQ6
VSS DQ7
DQ12
VDD
DQ13
DM1
VSS
DQ14 DQ15
VDD
VDD
VSS
VSS
DQ20 DQ21
VDD DM2
DQ22
VSS
DQ23 DQ28
VDD
DQ29
DM3
VSS
DQ30 DQ31
VDD
CB4
CB5
VSS DM8
CB6
VDD
CB7
DU/RESET#
VSS
VSS
VDD
VDD
CKE0
DU/BA2
A11
A8
VSS
A6 A4 A2
A0 VDD BA1
RAS# CAS#
S1#
DU VSS
DQ36 DQ37
VDD
DM4
DQ38
VSS
DQ39 DQ44
VDD
DQ45
DM5
VSS
DQ46 DQ47
VDD
CK1#
CK1 VSS
DQ52 DQ53
VDD
DM6
DQ54
VSS
DQ55 DQ60
VDD
DQ61
DM7
VSS
DQ62 DQ63
VDD SA0 SA1 SA2
DU
H = 5.2mm
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200
+2.5V
DDRA_SDQ5 DDRA_SDQ4
DDRA_SDM0
DDRA_SDQ3 DDRA_SDQ9
DDRA_SDQ13 DDRA_SDM1
DDRA_SDQ14 DDRA_SDQ11
DDRA_SDQ21 DDRA_SDQ17
DDRA_SDM2 DDRA_SDQ22
DDRA_SDQ23 DDRA_SDQ24
DDRA_SDQ25 DDRA_SDM3
DDRA_SDQ26 DDRA_SDQ31
DDRA_CKE0 DDRA_SMA11
DDRA_SMA8 DDRA_SMA6
DDRA_SMA4 DDRA_SMA2 DDRA_SMA0
DDRA_SBS1 DDRA_SRAS# DDRA_SCAS# DDRA_SCS#1
DDRA_SDQ32 DDRA_SDQ33
DDRA_SDM4 DDRA_SDQ38
DDRA_SDQ39 DDRA_SDQ40
DDRA_SDM5 DDRA_SDQ42
DDRA_SDQ47
DDRA_SDQ49 DDRA_SDQ52
DDRA_SDM6 DDRA_SDQ51
DDRA_SDQ50 DDRA_SDQ56
DDRA_SDQ57 DDRA_SDM7
DDRA_SDQ63 DDRA_SDQ58
3
DDRA_VREF trace width of 12mils and space 12mils(min)
DDRA_VREF
1
C305
0.1U_0402_16V4Z
2
Close to SO-DIMM
+2.5V
1
C310
0.1U_0402_10V6K
2
DDRA_CKE0 8,14
DDRA_SBS1 8,14 DDRA_SRAS# 8,14 DDRA_SCAS# 8,14 DDRA_SCS#1 8,14
DDRA_CLK2# 8 DDRA_CLK2 8
+2.5V
+2.5V
1
C331 22U_1206_10V4Z
2
1
C335
0.1U_0402_10V6K
2
12
R204 75_0603_1%
12
R203 75_0603_1%
System Memory Decoupling caps
1
2
1
2
Decoupling Reference Document: Springdale Customer Schematic R1.2 page22 each Channel(two DIMMs) requirement 22uF*1 ; 0.1uF*14
Decoupling Reference Document: Springdale Chipset Platform Design guide Rev1.11 (12474)pag 271 each DIMM(two) requirement 0.1uF*42
2
C314
0.1U_0402_10V6K
C334
0.1U_0402_10V6K
1
2
1
2
SO-DIMM 0 REVERSE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
3
2
C339
0.1U_0402_10V6K
C308
0.1U_0402_10V6K
1
DDRA_SDQ[0..63]8,14 D DRA_SDQS[0..7]8,14 DDRA_SMA[0..12]8,14 DDRA_SDM[0..7]8,14
1
C312
0.1U_0402_10V6K
2
1
C333
0.1U_0402_10V6K
2
Title
Size Document Number Rev
Date: Sheet of
DDRA_SDQ[0..63] DDRA_SDQS[0..7] DDRA_SMA[0..12] DDRA_SDM[0..7]
1
C337
0.1U_0402_10V6K
2
1
C307
0.1U_0402_10V6K
2
1
C311
0.1U_0402_10V6K
2
1
C332
0.1U_0402_10V6K
2
Compal Electronics, Inc.
DDR-SODIMM SLOT1
LA-1841
1
1
C336
0.1U_0402_10V6K
2
1
C306
0.1U_0402_10V6K
2
12 57Thursday, February 20, 2003
5
4
3
2
1
JP24
1
VREF
3
DDRB_SDQ4 DDRB_SDQ0
DDRB_SDQS0 DDRB_SDQ7
D D
DDRB_CLK19 DDRB_CLK1#9
C C
DDRB_CKE19,14
DDRB_SBS09,14 DDRB_SWE#9,14 DDRB_SCS#09,14
B B
A A
ICH_SMB_DATA12,15,23 ICH_SMB_CLK12,15,23
DDRB_SDQ5 DDRB_SDQ9
DDRB_SDQ12 DDRB_SDQS1
DDRB_SDQ10 DDRB_SDQ14
DDRB_SDQ20 DDRB_SDQ21
DDRB_SDQS2 DDRB_SDQ22
DDRB_SDQ17 DDRB_SDQ24
DDRB_SDQ25 DDRB_SDQS3
DDRB_SDQ26 DDRB_SDQ30
DDRB_CKE1 DDRB_SMA12
DDRB_SMA9 DDRB_SMA7
DDRB_SMA5 DDRB_SMA3 DDRB_SMA1
DDRB_SMA10 DDRB_SBS0 DDRB_SWE# DDRB_SCS#0
DDRB_SDQ33 DDRB_SDQ34
DDRB_SDQS4 DDRB_SDQ37
DDRB_SDQ38 DDRB_SDQ40
DDRB_SDQ44 DDRB_SDQS5
DDRB_SDQ43 DDRB_SDQ41 DDRB_SDQ42
DDRB_SDQ52 DDRB_SDQ49
DDRB_SDQS6 DDRB_SDQ55
DDRB_SDQ60 DDRB_SDQ56
DDRB_SDQS7 DDRB_SDQ58
DDRB_SDQ57
+3VS
5
VSS
5
DQ0
7
DQ1
9
VDD
11
DQS0
13
DQ2
15
VSS
17
DQ3
19
DQ8
21
VDD
23
DQ9
25
DQS1
27
VSS
29
DQ10
31
DQ11
33
VDD
35
CK0
37
CK0#
39
VSS
41
DQ16
43
DQ17
45
VDD
47
DQS2
49
DQ18
51
VSS
53
DQ19
55
DQ24
57
VDD
59
DQ25
61
DQS3
63
VSS
65
DQ26
67
DQ27
69
VDD
71
CB0
73
CB1
75
VSS
77
DQS8
79
CB2
81
VDD
83
CB3
85
DU
87
VSS
89
CK2
91
CK2#
93
VDD
95
CKE1
97
DU/A13
99
A12
101
A9
103
VSS
105
A7
107
A5
109
A3
111
A1
113
VDD
115
A10/AP
117
BA0
119
WE#
121
S0#
123
DU
125
VSS
127
DQ32
129
DQ33
131
VDD
133
DQS4
135
DQ34
137
VSS
139
DQ35
141
DQ40
143
VDD
145
DQ41
147
DQS5
149
VSS
151
DQ42
153
DQ43
155
VDD
157
VDD
159
VSS
161
VSS
163
DQ48
165
DQ49
167
VDD
169
DQS6
171
DQ50
173
VSS
175
DQ51
177
DQ56
179
VDD
181
DQ57
183
DQS7
185
VSS
187
DQ58
189
DQ59
191
VDD
193
SDA
195
SCL
197
VDD_SPD
199
VDD_ID
KLINK_5746-3-111
4
VREF
VSS DQ4 DQ5
VDD DM0 DQ6
VSS DQ7
DQ12
VDD
DQ13
DM1
VSS
DQ14 DQ15
VDD
VDD
VSS
VSS
DQ20 DQ21
VDD DM2
DQ22
VSS
DQ23 DQ28
VDD
DQ29
DM3
VSS
DQ30 DQ31
VDD
CB4
CB5
VSS DM8
CB6
VDD
CB7
DU/RESET#
VSS
VSS
VDD
VDD
CKE0
DU/BA2
A11
A8
VSS
A6 A4 A2
A0 VDD BA1
RAS# CAS#
S1#
DU VSS
DQ36 DQ37
VDD
DM4
DQ38
VSS
DQ39 DQ44
VDD
DQ45
DM5
VSS
DQ46 DQ47
VDD
CK1#
CK1 VSS
DQ52 DQ53
VDD
DM6
DQ54
VSS
DQ55 DQ60
VDD
DQ61
DM7
VSS
DQ62 DQ63
VDD SA0 SA1 SA2
DU
H= 9.2mm
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200
+2.5V
DDRB_VREF trace width of 12mils and space 12mils(min)
DDRB_SDQ2 DDRB_SDQ6
DDRB_SDM0 DDRB_SDQ1
DDRB_SDQ3 DDRB_SDQ13
DDRB_SDQ11 DDRB_SDM1
DDRB_SDQ15 DDRB_SDQ8
DDRB_SDQ19 DDRB_SDQ16
DDRB_SDM2 DDRB_SDQ18
DDRB_SDQ23 DDRB_SDQ28
DDRB_SDQ29 DDRB_SDM3
DDRB_SDQ27 DDRB_SDQ31
DDRB_CKE0 DDRB_SMA11
DDRB_SMA8 DDRB_SMA6
DDRB_SMA4 DDRB_SMA2 DDRB_SMA0
DDRB_SBS1 DDRB_SRAS# DDRB_SCAS# DDRB_SCS#1
DDRB_SDQ32 DDRB_SDQ36
DDRB_SDM4 DDRB_SDQ39
DDRB_SDQ35 DDRB_SDQ46
DDRB_SDQ45 DDRB_SDM5
DDRB_SDQ47
DDRB_SDQ48 DDRB_SDQ53
DDRB_SDM6 DDRB_SDQ51
DDRB_SDQ54DDRB_SDQ50 DDRB_SDQ62
DDRB_SDQ61 DDRB_SDM7
DDRB_SDQ59 DDRB_SDQ63
+3VS
DDRB_VREF
2
C300
0.1U_0402_16V4Z
1
DDRB_CKE0 9,14
DDRB_SBS1 9,14 DDRB_SRAS# 9,14 DDRB_SCAS# 9,14 DDRB_SCS#1 9,14
DDRB_CLK2# 9 DDRB_CLK2 9
REVERSESO-DIMM 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
+2.5V
1
C299
0.1U_0402_10V6K
2
+2.5V
1
C294
0.1U_0402_10V6K
2
+2.5V
1
C338
0.1U_0402_10V6K
2
+2.5V+2.5V
12
R197 75_0603_1%
12
R196 75_0603_1%
DDRB_SDQ[0..63]9,14 D DRB_SDQS[0..7]9,14 DDRB_SMA[0..12]9,14 DDRB_SDM[0..7]9,14
System Memory Decoupling caps
1
C270
0.1U_0402_10V6K
2
1
C292
0.1U_0402_10V6K
2
1
C313
0.1U_0402_10V6K
2
1
C298
0.1U_0402_10V6K
2
1
C264
0.1U_0402_10V6K
2
Decoupling Reference Document: Springdale Customer Schematic R1.2 page26 each Channel(two DIMMs) requirement 0.1uF*24
1
C295
0.1U_0402_10V6K
2
1
C269
0.1U_0402_10V6K
2
1
C263
0.1U_0402_10V6K
2
1
C265
0.1U_0402_10V6K
2
2
1
2
1
2
1
C271
0.1U_0402_10V6K
2
Title
Size Document Number Rev
Date: Sheet of
DDRB_SDQ[0..63] DDRB_SDQS[0..7] DDRB_SMA[0..12] DDRB_SDM[0..7]
C297
0.1U_0402_10V6K
C291
0.1U_0402_10V6K
1
2
LA-1841
1
C267
0.1U_0402_10V6K
2
1
C262
0.1U_0402_10V6K
2
C309
0.1U_0402_10V6K
1
C296
0.1U_0402_10V6K
2
1
C290
0.1U_0402_10V6K
2
1
C293
0.1U_0402_10V6K
2
Compal Electronics, Inc. DDR-SODIMM SLOT2
13 57Thursday, February 20, 2003
1
1
C266
0.1U_0402_10V6K
2
1
C261
0.1U_0402_10V6K
2
1
C268
0.1U_0402_10V6K
2
5
4
3
2
1
Channel A(DIMM0) Termination resistors & Decoupling caps Channel B(DIMM1) Termination resistors & Decoupling caps
+1.25VS +1.25VS
DDRA_SDQ5 DDRA_SDQ4
DDRA_SDQ1 DDRA_SDQ0
D D
DDRA_SDQ6 DDRA_SDQS0
DDRA_SDM0 DDRA_SDQ7
DDRA_SDQ13 DDRA_SDM1
DDRA_SDQ3 DDRA_SDQ9
DDRA_SDQ14 DDRA_SDQ11
C C
DDRA_SDQ12 DDRA_SDQ2
DDRA_SDQS1 DDRA_SDQ8
DDRA_SDQ15 DDRA_SDQ10
DDRA_SDQ16 DDRA_SDQ20
DDRA_SDQ21 DDRA_SDQ17
DDRA_SDQ18 DDRA_SDQS2
B B
DDRA_SDM2 DDRA_SDQ22
DDRA_SDQ23 DDRA_SDQ24
DDRA_SDQ25 DDRA_SDM3
DDRA_SDQS5 DDRA_SDQ41
DDRA_SDM6 DDRA_SDQ51
DDRA_SDQ46 DDRA_SDQ43
A A
DDRA_SDQ50 DDRA_SDQ56
RP77
1 4 2 3
56_0404_4P2R_5%
RP114
1 4 2 3
56_0404_4P2R_5%
RP115
1 4 2 3
56_0404_4P2R_5%
RP76
1 4 2 3
56_0404_4P2R_5%
RP74
1 4 2 3
56_0404_4P2R_5%
RP75
1 4 2 3
56_0404_4P2R_5%
RP73
1 4 2 3
56_0404_4P2R_5%
RP116
1 4 2 3
56_0404_4P2R_5%
RP117
1 4 2 3
56_0404_4P2R_5%
RP118
1 4 2 3
56_0404_4P2R_5%
RP119
1 4 2 3
56_0404_4P2R_5%
RP72
1 4 2 3
56_0404_4P2R_5%
RP120
1 4 2 3
56_0404_4P2R_5%
RP71
1 4 2 3
56_0404_4P2R_5%
RP70
1 4 2 3
56_0404_4P2R_5%
RP69
1 4 2 3
56_0404_4P2R_5%
RP130
1 4 2 3
56_0404_4P2R_5%
RP56
1 4 2 3
56_0404_4P2R_5%
RP131
1 4 2 3
56_0404_4P2R_5%
RP55
1 4 2 3
56_0404_4P2R_5%
5
RP121
DDRA_SDQ28
14
DDRA_SDQ19
23
56_0404_4P2R_5%
RP68
DDRA_SDQ26
14
DDRA_SDQ31
23
56_0404_4P2R_5%
RP132
DDRA_SDQ53
14
DDRA_SDQ48
23
56_0404_4P2R_5%
RP79
DDRA_SDQ57
14
DDRA_SDM7
23
56_0404_4P2R_5%
RP78
DDRA_SDQ63
14
DDRA_SDQ58
23
56_0404_4P2R_5%
RP135
DDRA_SDQS7
14
DDRA_SDQ61
23
56_0404_4P2R_5%
RP133
DDRA_SDQ54
14
DDRA_SDQS6
23
56_0404_4P2R_5%
RP62
DDRA_SDQ32
14
DDRA_SDQ33
23
56_0404_4P2R_5%
RP61
DDRA_SDM4
14
DDRA_SDQ38
23
56_0404_4P2R_5%
RP127
DDRA_SDQ37
14
DDRA_SDQ36
23
56_0404_4P2R_5%
RP128
DDRA_SDQ34
14
DDRA_SDQS4
23
56_0404_4P2R_5%
RP59
DDRA_SDQ45
14
DDRA_SDM5
23
56_0404_4P2R_5%
RP60
DDRA_SDQ39
14
DDRA_SDQ40
23
56_0404_4P2R_5%
RP58
DDRA_SDQ42
14
DDRA_SDQ47
23
56_0404_4P2R_5%
RP129
DDRA_SDQ44
14
DDRA_SDQ35
23
56_0404_4P2R_5%
RP57
DDRA_SDQ49
14
DDRA_SDQ52
23
56_0404_4P2R_5%
RP122
DDRA_SDQS3
14
DDRA_SDQ29
23
56_0404_4P2R_5%
RP123
DDRA_SDQ27
14
DDRA_SDQ30
23
56_0404_4P2R_5%
RP136
DDRA_SDQ59
14
DDRA_SDQ62
23
56_0404_4P2R_5%
RP134
DDRA_SDQ60
14
DDRA_SDQ55
23
56_0404_4P2R_5%
Decoupling Reference Document: Springdale Customer Schematic R1.2 page22 each Channel(two DIMMs) requirement 4.7u*2 ; 0.1uF*28
RP80
DDRA_SCS#0
1 4
DDRA_SCS#1
2 3
56_0404_4P2R_5%
RP66
DDRA_SMA8
14
DDRA_SMA6
23
56_0404_4P2R_5%
RP67
DDRA_SMA12
14
DDRA_SMA11
23
56_0404_4P2R_5%
RP125
DDRA_SMA3
14
DDRA_SMA5
23
56_0404_4P2R_5%
RP126
DDRA_SMA10
14
DDRA_SMA1
23
56_0404_4P2R_5%
RP65
DDRA_SMA4
14
DDRA_SMA2
23
56_0404_4P2R_5%
RP124
DDRA_SMA7
14
DDRA_SMA9
23
56_0404_4P2R_5%
RP64
DDRA_SMA0
14
DDRA_SBS1
23
56_0404_4P2R_5%
RP63
DDRA_SRAS#
14
DDRA_SCAS#
23
56_0404_4P2R_5%
RP81
DDRA_CKE0
1 4
DDRA_CKE1
2 3
56_0404_4P2R_5%
RP137
DDRA_SBS0
1 4
DDRA_SWE#
2 3
56_0404_4P2R_5%
+1.25VS
0.1U_0402_10V6K
1
C621
2
0.1U_0402_10V6K
+1.25VS
0.1U_0402_10V6K
1
C634
2
0.1U_0402_10V6K
+1.25VS
0.1U_0402_10V6K
1
C626
2
0.1U_0402_10V6K
+1.25VS
0.1U_0402_10V6K
1
C326
2
0.1U_0402_10V6K
+1.25VS
0.1U_0402_10V6K
1
C323
2
0.1U_0402_10V6K
1
C630
2
1
C622
2
1
C627
2
1
C329
2
1
C322
2
4
DDRA_SCS#0 8,12 DDRA_SCS#1 8,12
DDRA_SDQ[0..63]8,12 DDRA_SDQS[0..7]8,12 DDRA_SMA[0..12]8,12 DDRA_SDM[0..7]8,12
DDRA_SBS1 8,12
DDRA_SRAS# 8,12 DDRA_SCAS# 8,12
DDRA_CKE0 8,12 DDRA_CKE1 8,12
DDRA_SBS0 8,12 DDRA_SWE# 8,12
0.1U_0402_10V6K
1
C631
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C327
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C628
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C325
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C320
2
0.1U_0402_10V6K
1
C629
2
0.1U_0402_10V6K
1
C564
2
0.1U_0402_10V6K
1
C316
2
0.1U_0402_10V6K
1
C324
2
4.7U_1206_16V6K
1
C318
2
0.1U_0402_10V6K
DDRA_SDQ[0..63]
DDRB_SDQ2 DDRB_SDQ6
DDRB_SDQ0 DDRB_SDQ4
1 4 2 3
1 4 2 3
D DRA_SDQS[0..7]
DDRA_SMA[0..12]
DDRA_SDM[0..7]
0.1U_0402_10V6K
1
1
C632
C633
2
2
0.1U_0402_10V6K
1
1
C624
C625
2
2
0.1U_0402_10V6K
1
1
C321
C328
2
2
4.7U_1206_16V6K
1
1
C619
C618
2
2
0.1U_0402_10V6K
1
1
C319
C317
2
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DDRB_SDQ7 DDRB_SDQS0
DDRB_SDM0 DDRB_SDQ1
DDRB_SDQ3 DDRB_SDQ13
DDRB_SDQ15 DDRB_SDQ8
DDRB_SDQ9 DDRB_SDQ14 DDRB_SDQ5
DDRB_SDQ11 DDRB_SDM1
DDRB_SDQS1 DDRB_SDQ12
DDRB_SDQ19 DDRB_SDQ16
DDRB_SDQ21 DDRB_SDQ20
DDRB_SDQ29 DDRB_SDM3
DDRB_SDQ22 DDRB_SDQS2
DDRB_SDQ24 DDRB_SDQ17
DDRB_SDQ23 DDRB_SDQ28
DDRB_SDM2 DDRB_SDQ18
DDRB_SDM6 DDRB_SDQ51
1 4 2 3
1 4 2 3
1 4 2 3
1 4 2 3
1 4 2 3
1 4 2 3
1 4 2 3
1 4 2 3
1 4 2 3
1 4 2 3
1 4 2 3
1 4 2 3
1 4 2 3
1 4 2 3
1 4 2 3
56_0404_4P2R_5%
DDRB_SDQ42 DDRB_SDQ43
1 4 2 3
56_0404_4P2R_5%
DDRB_SDM7
DDRB_SDQ54
1 4 2 3
56_0404_4P2R_5%
DDRB_SDQ49 DDRB_SDQ52
1 4 2 3
56_0404_4P2R_5%
3
+1.25VS +1.25VS
RP92
56_0404_4P2R_5%
RP52
56_0404_4P2R_5%
RP51
56_0404_4P2R_5%
RP93
56_0404_4P2R_5%
RP94
56_0404_4P2R_5%
RP96
56_0404_4P2R_5%
RP50
56_0404_4P2R_5%
RP95
56_0404_4P2R_5%
RP49
56_0404_4P2R_5%
RP97
56_0404_4P2R_5%
RP48
56_0404_4P2R_5%
RP100
56_0404_4P2R_5%
RP47
56_0404_4P2R_5%
RP46
56_0404_4P2R_5%
RP99
56_0404_4P2R_5%
RP98
56_0404_4P2R_5%
RP109
RP32
RP26
RP31
RP45
56_0404_4P2R_5%
RP44
56_0404_4P2R_5%
RP24
56_0404_4P2R_5%
RP30
56_0404_4P2R_5%
RP25
56_0404_4P2R_5%
RP29
56_0404_4P2R_5%
RP43
56_0404_4P2R_5%
RP35
56_0404_4P2R_5%
RP104
56_0404_4P2R_5%
RP36
56_0404_4P2R_5%
RP105
56_0404_4P2R_5%
RP106
56_0404_4P2R_5%
RP108
56_0404_4P2R_5%
RP34
56_0404_4P2R_5%
RP107
56_0404_4P2R_5%
RP33
56_0404_4P2R_5%
RP103
56_0404_4P2R_5%
RP101
56_0404_4P2R_5%
RP28
56_0404_4P2R_5%
RP27
56_0404_4P2R_5%
DDRB_SDQS3
14
DDRB_SDQ25
23
DDRB_SDQ30
14
DDRB_SDQ26
23
DDRB_SDQ62
14
DDRB_SDQ59
23
DDRB_SDQ55
14
DDRB_SDQS6
23
DDRB_SDQ63
14
DDRB_SDQ61
23
DDRB_SDQ60
14
DDRB_SDQ50
23
14
DDRB_SDQ10
23
DDRB_SDQ37
14
DDRB_SDQS4
23
DDRB_SDM4
14
DDRB_SDQ39
23
DDRB_SDQ34
14
DDRB_SDQ33
23
DDRB_SDQ35
14
DDRB_SDQ46
23
DDRB_SDQ45
14
DDRB_SDM5
23
DDRB_SDQ48
14
DDRB_SDQ53
23
DDRB_SDQ40
14
DDRB_SDQ38
23
DDRB_SDQ41
14
DDRB_SDQ47
23
DDRB_SDQS5
14
DDRB_SDQ44
23
DDRB_SDQ32
14
DDRB_SDQ36
23
DDRB_SDQ27
14
DDRB_SDQ31
23
DDRB_SDQS7
14
DDRB_SDQ56
23
DDRB_SDQ57
14
DDRB_SDQ58
23
2
RP37
DDRB_SCS#0
14
DDRB_SWE#
23
56_0404_4P2R_5%
RP38
DDRB_SMA10
14
DDRB_SBS0
23
56_0404_4P2R_5%
RP41
DDRB_SMA12
14
DDRB_SMA9
23
56_0404_4P2R_5%
RP89
DDRB_SMA8
1 4
DDRB_SMA11
2 3
56_0404_4P2R_5%
RP39
DDRB_SMA1
14
DDRB_SMA3
23
56_0404_4P2R_5%
RP91
DDRB_SMA6
14
DDRB_SMA4
23
56_0404_4P2R_5%
RP40
DDRB_SMA5
14
DDRB_SMA7
23
56_0404_4P2R_5%
RP102
DDRB_SMA2
14
DDRB_SMA0
23
56_0404_4P2R_5%
RP42
DDRB_CKE1
14
DDRB_CKE0
23
56_0404_4P2R_5%
RP110
DDRB_SCAS#
14
DDRB_SCS#1
23
56_0404_4P2R_5%
RP90
DDRB_SRAS#
1 4
DDRB_SBS1
2 3
56_0404_4P2R_5%
DDRB_SCS#0 9,13
DDRB_SWE# 9,13
DDRB_SBS0 9,13
DDRB_SDQ[0..63]9,13 D DRB_SDQS[0..7]9,13 DDRB_SMA[0..12]9,13 DDRB_SDM[0..7]9,13
DDRB_CKE1 9,13 DDRB_CKE0 9,13
DDRB_SCAS# 9,13
DDRB_SCS#1 9,13
DDRB_SRAS# 9,13
DDRB_SBS1 9,13
+1.25VS
1
2
0.1U_0402_10V6K
+1.25VS
1
2
0.1U_0402_10V6K
+1.25VS
1
2
0.1U_0402_10V6K
+1.25VS
1
2
0.1U_0402_10V6K
Decoupling Reference Document: Springdale Customer Schematic R1.2 page26 each Channel(two DIMMs) requirement 4.7u*2 ; 0.1uF*26
C284
2
0.1U_0402_10V6K
1
C277
2
0.1U_0402_10V6K
1
C563
2
0.1U_0402_10V6K
4.7U_1206_16V6K
1
C570
2
C283
0.1U_0402_10V6K
C276
0.1U_0402_10V6K
C623
C572
4.7U_1206_16V6K
0.1U_0402_10V6K
1
1
C282
2
0.1U_0402_10V6K
1
C275
2
0.1U_0402_10V6K
1
C565
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C573
2
1
2
1
2
1
2
1
2
C281
C274
C566
C571
Title
DDR Termination Resistors
Size Document Number Rev
B
Date: Sheet of
LA-1841
0.1U_0402_10V6K
1
C280
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C273
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C567
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C259
2
0.1U_0402_10V6K
14 57Thursday, February 20, 2003
1
DDRB_SDQ[0..63] D DRB_SDQS[0..7] DDRB_SMA[0..12] DDRB_SDM[0..7]
0.1U_0402_10V6K
1
C279
2
0.1U_0402_10V6K
1
C272
2
0.1U_0402_10V6K
1
C568
2
1
C258
2
1
2
1
2
1
2
C278
C562
C569
5
4
3
2
1
SEL0 SEL1 CPU 3V66[0..3] REF0 REF1 SRC USB/Dot
0 0 100 66 14.3 14.3 100/200
0 MID REF REF REF REF REF
D D
0 1 200
66 14.3 100/200 48
1 0 133 66 14.3
1 1 166
66 14.3
14.3
14.3
14.3
100/200
100/2004848
REF
48
L29
1 2
BLM21A601SPT_0805
L28
1 2
BLM21A601SPT_0805
1
2
+3VS_CLK+3VS
C591 10U_1206_6.3V7K
1 MID Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
CLK_ICH_14M24
CLK_14M_SIO36
C C
PM_SLP_S1#24 STP_PCI#24 STP_CPU#24,53
+3VS
12
R421 1K_0603_1%
B B
12
R420 2K_0603_1%
12
R185
2.49K_0603_1%
A A
12
R444 1K_0603_1%
CLKSEL0 CLKSEL1
12
R443 2K_0603_1%
12
R190
2.49K_0603_1%
R462 @0_0402_5% R425 @0_0402_5% R424 @0_0402_5%
R187 @0_0402_5% R186 0_0402_5%12 R188 0_0402_5%12 R189 @0_0402_5%
5
12 12 12
+CPU_CORE
12
12
MCH_CLKSEL0 7 MCH_CLKSEL1 7
SLP_S1# STPPCI# STPCPU#
1 2
+3VS
R422 10K_0402_5%
1 2
R439 62_0402_5%
220_0402_5%
CPU_CLKSEL0 5 CPU_CLKSEL1 5
Check SPEC (250mA,300 ohm)
+3VS
R450 33_0402_5%
R451 33_0402_5%
+3VS
CLK_ICH_48M24
L27 BLM11A601S_0603
1 2
12
12
C602
@10P_0402_50V8K
12
12
C603
@10P_0402_50V8K
12
Place crystal within 500 mils of CK409
R463 1K_0402_5%1 2 R412 1K_0402_5%
1 2
R411 1K_0402_5%1 2
Q40
1
MMBT3904_SOT232
3
ICH_SMB_CLK12,13,23 ICH_SMB_DATA12,13,23
R438 33_0402_5%
CLK_VDD_PLL
1
C578 10U_1206_6.3V7K
2
4
CLKREF1 CLKREF0
CLK_XTAL_IN
X3
14.31818MHz_20P_1BX14318CC1A~L
CLK_XTAL_OUT
SLP_S1# STPPCI# STPCPU#
CLK_VTT_PG#
CK_SCLK CK_SDATA
CLK48M_OUT0
12
1 2
R437 475_0603_1%
1
C579
0.1U_0402_16V4Z
2
101624
34
3
VDD_PCI
VDD_PCI
VDD_REF
CK409
VSS_REF
VSS_PCI
6
11
172125
36
VDD_48
VDD_SRC
VDD_3V66
VSS_PCI
VSS_3V66
VSS_48
33
U42
1
REF_0
2
REF_1
4
XTAL_IN
5
XTAL_OUT
CLKSEL0
51
SEL0
CLKSEL1
56
SEL1
PWRDWN#
49
PCI_STP#
50
CPU_STP#
35
VTT_PWRGD#
28
SCLK
30
SDATA
37
SRCLKN_100MHZ
38
SRCLKP_100MHZ
31
USB_48MHZ
32
DOT_48MHZ
52
IREF
55
VDD_PLL
54
VSS_PLL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
Place near each pin W>40 mil
1
C583
0.1U_0402_10V6K
2
424548
VDD_CPU
VDD_CPU
CPU_CLKC2
48/66MHZ_OUT/3V66_4
66MHZ_OUT3/3V66_3 66MHZ_OUT2/3V66_2 66MHZ_OUT1/3V66_1 66MHZ_OUT0/3V66_0
PCICLK_F2 PCICLK_F1 PCICLK_F0
VSS_SRC
VSS_IREF
ICS952623BG_TSSOP56
39
53
VSS_CPU
CPUCLKT2
CPUCLKT1
CPUCLKC1 CPUCLKT0
CPUCLKC0
PCICLK6 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0
1
C582
0.1U_0402_10V6K
2
1
C581
0.1U_0402_10V6K
2
47
46 44
43 41
40 29 27 26 23 22 9 8 7
20 19 18 15 14 13 12
CLK_CPU2
CLK_CPU2# CLK_CPU1
CLK_CPU1# CLK_CPU0
CLK_CPU0#
CLK66M_OUT3
CLK66M_OUT1 CLK66M_OUT0 PCICLK_F2
PCICLK6 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1
1
C597
0.1U_0402_10V6K
2
1
C592
4.7U_0805_6.3V6K
2
1 2
R428 33_0402_5%
1 2
R429 33_0402_5%
1 2
R430 33_0402_5%
1 2
R431 33_0402_5%
1 2
R432 33_0402_5%
1 2
R433 33_0402_5%
1 2
R457 33_0402_5%
1 2
R456 33_0402_5%
1 2
R455 33_0402_5%
1 2
R452 33_0402_5%
1 2
R461 33_0402_5%
1 2
R460 33_0402_5%
1 2
R454 33_0402_5%
1 2
R459 33_0402_5%
1 2
R458 33_0402_5%
1 2
R453 33_0402_5%
1 2
1 2
1 2
1 2
1 2
1 2
2
Trace wide=40 mils
1
C596
0.1U_0402_10V6K
2
1
C595
0.1U_0402_10V6K
2
CLK_HCLK
R41349.9_0402_1%
R41449.9_0402_1%
CLK_HCLK# CLK_ITP
R41549.9_0402_1%
R41649.9_0402_1%
CLK_ITP# CLK_BCLK
R41749.9_0402_1%
R41849.9_0402_1%
CLK_BCLK#
CLK_AGP_66M 16
CLK_MCH_66M 10 CLK_ICH_66M 23 CLK_PCI_ICH 23
CLK_PCI_MINI 29 CLK_PCI_PCM 27 CLK_PCI_LPC 39 CLK_PCI_1394 30 CLK_PCI_LAN 26 CLK_PCI_SIO 36
Title
Size Document Number Rev
LA-1841
Date: Sheet of
1
C594
0.1U_0402_10V6K
2
CLK_HCLK 7
CLK_HCLK# 7 CLK_ITP 5
CLK_ITP# 5 CLK_BCLK 4
Place near CK409
CLK_BCLK# 4
Compal Electronics, Inc.
Clock Generator
1
2
1
C580
0.1U_0402_10V6K
15 57Thursday, February 20, 2003
5
Place close to pin H2 & H3
@2200P_0402_50V7K
1
C145
NV_THERMDA
2
D D
AGP_AD[0..31]10
AGP_SBA[0..7]10
AGP_C/BE#[0..3]10
AGP_ST[0..2]10
C C
0.1U_0402_10V6K
12
Selection Table For W180
B B
Modulation Setting
XTALOUTBUFF
+3VS
R318 1K_0402_5%
1 2 1 2
A A
R317 1K_0402_5%
NV_THERMDC I2CC_SCL I2CC_SDA
+3VS
R35 10K_0402_5%
1 2 1 2
R36 10K_0402_5%
4.7U_0805_10V4Z
12
C479
C30
4.7U_0805_10V4Z
1 2
R67 220K_0402_5%
1 2
R69 220K_0402_5%
SST
SS%
Ratio
1
8
1.25%
3.75%
U31
X1/CLK
FS2
0 1
U33
2
D+
3
D-
8
SCLK
7
SDATA
@ADM1032ARM_RM8
AGP_AD[0..31]
AGP_SBA[0..7]
AGP_C/BE#[0..3]
AGP_ST[0..2]
STP_AGP# AGP_BUSY#
12
C31
+SVDD
PLACE COLSE TO VGA
6
Pin AJ5, AJ7,
VDD
5
CLKOUT
27
X2FS1
SPREAD_RATE
4
SS%
GND
W180-01GT_SO8
3
5
VDD1
ALERT#
THERM#
+SVDD
L10
1 2
FCM2012C-800_0805
12
C478
0.1U_0402_10V6K
AGP_AD_STBS0 AGP_AD_STBS1
Close VGA ball (AK29) less than 250mils
+AGP_VREF
1 2
R323 22_0402_5%
1 2
1
NV_THERCTL#
6 4 5
GND
+3VS
XTALSSIN
1 2
R341 @1K_0402_5%
R345 10K_0402_5%
@2.2K_0402_5%
1
2
12
R128
@0.1U_0402_16V4Z
C16
1 2
@10P_0402_50V8K
CLK_AGP_66M15
C13
0.1U_0402_10V6K
+3VS
SWAPRDY_B NV31,NV34 use. NV18 not use.
+SVDD
4
+3VS+3VS
12
R124 @2.2K_0402_5%
+3VS
1
C148
2
R68
1 2
@10_0402_5%
B_PCIRST#23,35
AGP_REQ#10 AGP_GNT#10
AGP_PAR10
AGP_STOP#10
AGP_DEVSEL#10
AGP_TRDY#10
AGP_IRDY#10
AGP_FRAME#10
PCI_PIRQA#23,27,30
AGP_WBF#10 AGP_RBF#10 AGP_DBIHI10 AGP_DBILO10
AGP_SB_STBF10
AGP_SB_STBS10 AGP_AD_STBF010 AGP_AD_STBS010 AGP_AD_STBF110 AGP_AD_STBS110
R42 10K_0402_5%12
CRMA22
LUMA22
COMPS22
1 2
R70 63.4_0603_1%
R343 10K_0402_5%
12
4
AGP_AD0 AGP_AD1 AGP_AD2 AGP_AD3 AGP_AD4 AGP_AD5 AGP_AD6 AGP_AD7 AGP_AD8 AGP_AD9 AGP_AD10 AGP_AD11 AGP_AD12 AGP_AD13 AGP_AD14 AGP_AD15 AGP_AD16 AGP_AD17 AGP_AD18 AGP_AD19 AGP_AD20 AGP_AD21 AGP_AD22 AGP_AD23 AGP_AD24 AGP_AD25 AGP_AD26 AGP_AD27 AGP_AD28 AGP_AD29 AGP_AD30 AGP_AD31
AGP_C/BE#0 AGP_C/BE#1 AGP_C/BE#2 AGP_C/BE#3
CLK_AGP_66M B_PCIRST# AGP_REQ# AGP_GNT# AGP_PAR AGP_STOP# AGP_DEVSEL# AGP_TRDY# AGP_IRDY# AGP_FRAME# PCI_PIRQA#
AGP_WBF# AGP_RBF#
AGP_SB_STBF AGP_SB_STBS AGP_AD_STBF0 AGP_AD_STBS0 AGP_AD_STBF1 AGP_AD_STBS1
AGP_SBA0 AGP_SBA1 AGP_SBA2 AGP_SBA3 AGP_SBA4 AGP_SBA5 AGP_SBA6 AGP_SBA7 AGP_ST0 AGP_ST1 AGP_ST2
+AGP_REF
AGP_BUSY# STP_AGP#
CRMA LUMA
COMPS DACB_HSYNC DACB_VSYNC DACB_RSET
XTALIN XTALOUT
XTALSSIN XTALOUTBUFF NV_THERMDA NV_THERMDC
PROPRIETARY NOTE
DAC2
SSC
3
CLK
3
ZV PORT / EXT TMDS / GPIO / ROMLVDSTMDS
DAC1
GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9
FPBCLKOUT#
FPBCLKOUT
ROMA14 ROMA15 ROMCS#
VIPPCLK VIPHCTL VIPHCLK
VIPHAD0 VIPHAD1
VIPD0 VIPD1 VIPD2 VIPD3 VIPD4 VIPD5 VIPD6 VIPD7
DVOD0 DVOD1 DVOD2 DVOD3 DVOD4 DVOD5 DVOD6 DVOD7 DVOD8
DVOD9 DVOD10 DVOD11
DVOHSYNC DVOVSYNC
DVODE
DVOCLKOUT
DVOCLKOUT#
I2CC_SCL I2CC_SDA
BUFRST#
DVOCLKIN
STRAP0 STRAP1 STRAP2 STRAP3
IFPATXDO#
IFPATXDO
IFPATXD1#
IFPATXD1
IFPATXD2#
IFPATXD2
IFPATXD3#
IFPATXD3 IFPATXC#
IFPATXC
IFPBTXD4#
IFPBTXD4
IFPBTXD5#
IFPBTXD5
IFPBTXD6#
IFPBTXD6
IFPBTXD7#
IFPBTXD7 IFPBTXC#
IFPBTXC
DACA_RED
DACA_GREEN
DACA_BLUE DACA_HSYNC DACA_VSYNC
DACA_RSET
I2CA_SCL I2CA_SDA
SWAPRDY_A
DACA_IDUMP
IFPCTXD0#
IFPCTXD0
IFPCTXD1#
IFPCTXD1
IFPCTXD2#
IFPCTXD2 IFPCTXC#
IFPCTXC
VGA_GPIO0
G5 F4
ENBKL
G4
ENVDD
H5 H4
VGA_GPIO5
J4
VAG_GPIO6
J5
POWER_SEL
J6
NV_THERCTL#
K4 K6
M2 M3
ROMA14
R2
ROMA15
R1 AF2
L4
VIPHCTL
M4 M5
P3 P2
J3 J2
VIPD2
K2
VIPD3
K1
VIPD4
L3
VIPD5
L2
VIPD6
N2
VIPD7
N1 AG2
AH1
DVOD2
AG3
DVOD3
AJ1 AH2 AK1 AJ3 AK3
DVOD8
AH4
DVOD9
AK4 AJ4 AH5
DVO_HSYNC
AD5 AD6 AE4 AJ2 AK2 AG6 AG7 B1 AG1
G1 G2 F2 F3
AK10 AJ10 AJ9 AH9 AJ8
AG8 AG5
AF7 AF9 AG10
I2CC_SCL I2CC_SDA
STRAP0 STRAP1 STRAP2 STRAP3
TXOUT0­TXOUT0+ TXOUT1­TXOUT1+ TXOUT2­TXOUT2+ TXOUT3­TXOUT3+ TXCLK­TXCLK+ TZOUT0­TZOUT0+ TZOUT1­TZOUT1+ TZOUT2­TZOUT2+ TZOUT3­TZOUT3+ TZCLK­TZCLK+
R G
B DACA_HSYNC DACA_VSYNC
DACA_RSET
R39 63.4_0603_1%
DDC_CLK DDC_DATA
R41 @10K_0402_5%
SWAPRDY_A NV31,NV34 use. NV18 not use.
R132 0_0402_5%
R374 @0_0402_5% R129 10K_0402_5%12
TXOUT0- 22 TXOUT0+ 22 TXOUT1- 22 TXOUT1+ 22 TXOUT2- 22 TXOUT2+ 22 TXOUT3- 22 TXOUT3+ 22 TXCLK- 22 TXCLK+ 22 TZOUT0- 22 TZOUT0+ 22 TZOUT1- 22 TZOUT1+ 22 TZOUT2- 22 TZOUT2+ 22 TZOUT3- 22 TZOUT3+ 22 TZCLK- 22 TZCLK+ 22
R 22 G 22 B 22 DACA_HSYNC 22 DACA_VSYNC 22
1 2
12
U35A
AJ28
AD0
AK28
AD1
AH27
AD2
AK27
AD3
AJ27
AD4
AH26
AD5
AJ26
AD6
AH25
AD7
AH23
AD8
AJ23
AD9
AH22
AD10
AJ22
AD11
AJ21
AD12
AK21
AD13
AH20
AD14
AJ20
AD15
AG26
AD16
AE24
AD17
AG25
AD18
AG24
AD19
AF24
AD20
AG23
AD21
AE22
AD22
AF22
AD23
AE21
AD24
AG20
AD25
AG19
AD26
AF19
AD27
AE19
AD28
AF18
AD29
AG18
AD30
AE18
AD31
AJ24
C/BE#0
AH19
C/BE#1
AF25
C/BE#2
AG22
C/BE#3
AG12
PCICLK
AF15
PCIRST#
AF13
PCIREQ#
AE15
PCIGNT#
AK18
PCIPAR
AH17
PCISTOP#
AJ16
PCIDEVSEL#
AJ17
PCITRDY#
AG16
PCIIRDY#
AK16
PCIFRAME#
AG15
PCIINTA#
AE10
NC
AG17
AGPWBF#
AG14
AGPRBF#
AJ18
AGPPIPE/ DBI_HI
AJ19
NC/ DBI_LO
AK13
AGPSB_STB/ ADSTBF
AJ13
AGPSB_STB#/ ADSTBS
AK24
AGPADSTB0/ ADSTBF0
AJ25
AGPADSTB0#/ADSTBS0
AG21
AGPADSTB1/ ADSTBF1
AF21
AGPADSTB1#/ADSTBS1
AJ11
AGPSBA0
AH11
AGPSBA1
AJ12
AGPSBA2
AH12
AGPSBA3
AJ14
AGPSBA4
AH14
AGPSBA5
AJ15
AGPSBA6
AH15
AGPSBA7
AG13
AGPST0
AE16
AGPST1
AE13
AGPST2
AK29
AGPVREF
AF16
NC/AGPMBDET#
AF12
AGP_BUSY#
AG11
STP_AGP#
AE2
DACB_RED/CHROMA
AD2
DACB_GREEN/LUMA
AD1
DACB_BLUE/COMPOSITE
AF3
DACB_HSYNC
AE3
DACB_VSYNC
AD3
DACB_RSET
AE7
I2CB_SCL
AF6
I2CB_SDA
AD4
SWAPRDY_B
Y5
STEREO
AC4
DACB_IDUMP
AJ6
XTALIN
AH6
XTALOUT
AJ7
XTALSSIN
AJ5
XTALOUTBUFF
H2
THERMDA
H3
THERMDC
C2
JTAG[0]
C1
JTAG[1]
D1
JTAG[2]
E2
JTAG[3]
D2
JTAG[4]
NV34M_EPBGA701
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
nVIDIA NV31/34
PCI/AGP
AGP4X/8X
12
ENBKL 22,39 ENVDD 22
12
R133 10K_0402_5%12
DDC_CLK 22 DDC_DATA 22
+3VS
2
SPREAD_RATE
(SUS_STAT#)
+3VS
+3VS
PCI_AD_SWAP: 0-RVSERSED 1-NORMAL
1
SUB_VENDOR: 0-SYSTEM BIOS 1-ADAPTER BIOS
2
R376 10K_0402_5%12
RAM_CFG[3:0]
3
(1001 = 4Mx32 DDR, DQS per byte)
Low
R378 @10K_0402_5%
NV18M
0
R334 @10K_0402_5%12
NV31M:NV34M
4
R380 @10K_0402_5%12
1
NV18M
R329 10K_0402_5%12
NV31M:NV34M
5
R49 10K_0402_5%12
2
R50 @10K_0402_5%12
3
High
CRYSTAL: (10)-27MHz
6
Low
R373 10K_0402_5%12
0
High
1
TVMODE: (01)-NTSC
7
Low
0
R339 10K_0402_5%
1
High
AGP8X/4X: (0)-8X / (1)-4X
8
R48 10K_0402_5%12
AGP_SIDEBAND: (0)-ENABLE
9
R360 @10K_0402_5%12
AGP_FASTWRITE: (0)-ENABLE
10
PCI_DEVID[3:0]
11
Low
R366 10K_0402_5%12
0
R363 @10K_0402_5%12
1
R370 @10K_0402_5%
2
High
R346 10K_0402_5%12
3
BUS_TYPE: (1)-AGP
12
ROM TYPE: (00)-PARALLEL
Low
R354 10K_0402_5%
0
High
R351 10K_0402_5%12
1
Title
Size Document Number Rev
2
Date: Sheet of
POWER_SEL 51
12
12
12
12
1
2
1
STRAP0
R377 10K_0402_5%
STRAP1
STRAP2
R379 @10K_0402_5%
DVOD2
R335 10K_0402_5%12
STRAP3
R381 @10K_0402_5%12
DVOD3
R330 @10K_0402_5%12
DACA_VSYNC DACA_HSYNC
DACB_VSYNC DACB_HSYNC
0110 NV18M
DVO_HSYNC
R311 @2M_0402_5% C468 22P_0402_50V8J
R29 @10K_0402_5%12 R30 10K_0402_5%12
VIPD2 VIPD6
R357 10K_0402_5%12
R340 10K_0402_5%12
DVOD9
VIPD7
R361 @10K_0402_5%12
DVOD8
R320 @10K_0402_5%12R319 @10K_0402_5%12
VIPD4
R367 @10K_0402_5%12
VIPD5
R364 10K_0402_5%12
VIPD3
R371 10K_0402_5% R347 @10K_0402_5%12
VIPHCTL
R126 10K_0402_5%
ROMA14
R355 @10K_0402_5%
ROMA15
R352 @10K_0402_5%12
Y2
XTALOUTXTALIN
1 2
27MHZ_16PF
1 2
1
C469 22P_0402_50V8J
2
Compal Electronics, Inc. nVIDIA NV31M (AGP BUS)
LA-1841
16 57Thursday, February 20, 2003
1
+3VS
12
12
12
12
12
5
4
3
2
1
R_NDQMA[0..7]20
R_NDQSA[0..7]20
D D
C C
B B
A A
NMAA[0..11]20 R_NMDA[0..63]20
R_NDQMA[0..7] R_NDQSA[0..7] NMAA[0..11] R_NMDA[0..63]
R_NMDA0 R_NMDA1 R_NMDA2 R_NMDA3 R_NMDA4 R_NMDA5 R_NMDA6 R_NMDA7 R_NMDA8 R_NMDA9 R_NMDA10 R_NMDA11 R_NMDA12 R_NMDA13 R_NMDA14 R_NMDA15 R_NMDA16 R_NMDA17 R_NMDA18 R_NMDA19 R_NMDA20 R_NMDA21 R_NMDA22 R_NMDA23 R_NMDA24 R_NMDA25 R_NMDA26 R_NMDA27 R_NMDA28 R_NMDA29 R_NMDA30 R_NMDA31 R_NMDA32 R_NMDA33 R_NMDA34 R_NMDA35 R_NMDA36 R_NMDA37 R_NMDA38 R_NMDA39 R_NMDA40 R_NMDA41 R_NMDA42 R_NMDA43 R_NMDA44 R_NMDA45 R_NMDA46 R_NMDA47 R_NMDA48 R_NMDA49 R_NMDA50 R_NMDA51 R_NMDA52 R_NMDA53 R_NMDA54 R_NMDA55 R_NMDA56 R_NMDA57 R_NMDA58 R_NMDA59 R_NMDA60 R_NMDA61 R_NMDA62 R_NMDA63
U35B
N25
FBAD0
N27
FBAD1
N26
FBAD2
M25
FBAD3
K26
FBAD4
K27
FBAD5
J27
FBAD6
H27
FBAD7
N29
FBAD8
M29
FBAD9
M28
FBAD10
L29
FBAD11
J29
FBAD12
J28
FBAD13
H29
FBAD14
G30
FBAD15
K25
FBAD16
J26
FBAD17
J25
FBAD18
G26
FBAD19
F28
FBAD20
F26
FBAD21
E27
FBAD22
D27
FBAD23
H28
FBAD24
G29
FBAD25
F29
FBAD26
E29
FBAD27
C30
FBAD28
C29
FBAD29
B30
FBAD30
A30
FBAD31
AJ29
FBAD32
AJ30
FBAD33
AH29
FBAD34
AH30
FBAD35
AF29
FBAD36
AE29
FBAD37
AD29
FBAD38
AC28
FBAD39
AG28
FBAD40
AF27
FBAD41
AE26
FBAD42
AE28
FBAD43
AD25
FBAD44
AB25
FBAD45
AB26
FBAD46
AA25
FBAD47
AD30
FBAD48
AC29
FBAD49
AB28
FBAD50
AB29
FBAD51
Y29
FBAD52
W28
FBAD53
W29
FBAD54
V29
FBAD55
AC27
FBAD56
AB27
FBAD57
AA27
FBAD58
AA26
FBAD59
W25
FBAD60
V26
FBAD61
V27
FBAD62
V25
FBAD63
NV34M_EPBGA701
FBAA0 FBAA1 FBAA2 FBAA3 FBAA4 FBAA5 FBAA6 FBAA7 FBAA8
FBAA9 FBAA10 FBAA11 FBAA12
FBADQM0 FBADQM1 FBADQM2 FBADQM3 FBADQM4 FBADQM5 FBADQM6 FBADQM7
FBADQS0 FBADQS1 FBADQS2 FBADQS3 FBADQS4 FBADQS5 FBADQS6 FBADQS7
FBARAS#
MEMORY
INTERFACE A
FBACAS#
FBAWE# FBACS0# FBACS1#
FBACKE
FBACLK0
FBACLK0#
FBACLK1
FBACLK1#
FBABA0 FBABA1
FB_VREF
NMAA1
U28
NMAA2
U29
NMAA3
T28
NMAA4
T29
NMAA5
T27
NMAA6
T30
NMAA7
T26
NMAA8
T25
NMAA9
R27
NMAA10
R25
NMAA11
R30 U24
R_NDQMA0
L27
R_NDQMA1
K29
R_NDQMA2
G25
R_NDQMA3
E28
R_NDQMA4
AF28
R_NDQMA5
AD27
R_NDQMA6
AA30
R_NDQMA7
Y27
M27
R_NDQSA1
K30
R_NDQSA2
G27
R_NDQSA3
D30
R_NDQSA4
AG30
R_NDQSA5
AD26
R_NDQSA6
AA29
R_NDQSA7
W27
NMRASA#
P28
NMCASA#
P29
NMWEA#
R28
NMCSA0#
U27 P27
NMCKEA
N30
NMCLKA0
U21
NMCLKA0#
V21
NMCLKA1 NMCLKB1#
N21
NMCLKA1#
P21
NMA_BA0
R26 R29
C28
NMA_BA1
A_REF
(10 mil)
NMA_BA0 20 NMA_BA1 20
1
C173
0.1U_0402_10V6K
2
NMAA0
V30
NMRASA# 20 NMCASA# 20 NMWEA# 20 NMCSA0# 20
NMCKEA 20
R_NDQMB[0..7]21
R_NDQSB[0..7]21
NMAB[0..11]21
R_NMDB[0..63]21
+2.5VS
12
12
12
12
R138 1K_0402_1%
R135 1K_0402_1%
R_NDQMB[0..7] R_NDQSB[0..7] NMAB[0..11] R_NMDB[0..63]
NMCLKA0 20
R89 @120_0402_5%
NMCLKA0# 20 NMCLKA1 20
R105 @120_0402_5%
NMCLKA1# 20
R_NMDB0 R_NMDB1 R_NMDB2 R_NMDB3 R_NMDB4 R_NMDB5 R_NMDB6 R_NMDB7 R_NMDB8 R_NMDB9 R_NMDB10 R_NMDB11 R_NMDB12 R_NMDB13 R_NMDB14 R_NMDB15 R_NMDB16 R_NMDB17 R_NMDB18 R_NMDB19 R_NMDB20 R_NMDB21 R_NMDB22 R_NMDB23 R_NMDB24 R_NMDB25 R_NMDB26 R_NMDB27 R_NMDB28R_NDQSA0 R_NMDB29 R_NMDB30 R_NMDB31 R_NMDB32 R_NMDB33 R_NMDB34 R_NMDB35 R_NMDB36 R_NMDB37 R_NMDB38 R_NMDB39 R_NMDB40 R_NMDB41 R_NMDB42 R_NMDB43 R_NMDB44 R_NMDB45 R_NMDB46 R_NMDB47 R_NMDB48 R_NMDB49 R_NMDB50 R_NMDB51 R_NMDB52 R_NMDB53 R_NMDB54 R_NMDB55 R_NMDB56 R_NMDB57 R_NMDB58 R_NMDB59 R_NMDB60 R_NMDB61 R_NMDB62 R_NMDB63
1 2
R358 1K_0402_5%~D
1 2
R389 1K_0402_5%~D
F13 D13 E13 F12 E10 D10
B13 B12 C12 B11
F10
B29 A29 B28 A28 B26 B25 B24 C23 E26 D26 E25 C25 E24 F22 E22 F21 A24 B23 C22 B22 B20 C19 B19 B18 D23 D22 D21 E21 F19 E18 D18 F18
NMCKEA
NMCKEB
D9 D8
B9 C9 B8 A7
E9 F9 F7 C6 E6 D5 C4 C8 B7 B6 B5 A3 B3 A2 B2
U35C
FBCD0 FBCD1 FBCD2 FBCD3 FBCD4 FBCD5 FBCD6 FBCD7 FBCD8 FBCD9 FBCD10 FBCD11 FBCD12 FBCD13 FBCD14 FBCD15 FBCD16 FBCD17 FBCD18 FBCD19 FBCD20 FBCD21 FBCD22 FBCD23 FBCD24 FBCD25 FBCD26 FBCD27 FBCD28 FBCD29 FBCD30 FBCD31 FBCD32 FBCD33 FBCD34 FBCD35 FBCD36 FBCD37 FBCD38 FBCD39 FBCD40 FBCD41 FBCD42 FBCD43 FBCD44 FBCD45 FBCD46 FBCD47 FBCD48 FBCD49 FBCD50 FBCD51 FBCD52 FBCD53 FBCD54 FBCD55 FBCD56 FBCD57 FBCD58 FBCD59 FBCD60 FBCD61 FBCD62 FBCD63
NV34M_EPBGA701
MEMORY INTERFACE
B
FBCA0 FBCA1 FBCA2 FBCA3 FBCA4 FBCA5 FBCA6 FBCA7 FBCA8
FBCA9 FBCA10 FBCA11 FBCA12
FBCDQM0 FBCDQM1 FBCDQM2 FBCDQM3 FBCDQM4 FBCDQM5 FBCDQM6 FBCDQM7
FBCDQS0 FBCDQS1 FBCDQS2 FBCDQS3 FBCDQS4 FBCDQS5 FBCDQS6 FBCDQS7
FBCRAS# FBCCAS#
FBCWE# FBCCS0# FBCCS1#
FBCCKE
FBCCLK0
FBCCLK0#
FBCCLK1
FBCCLK1#
FBCBA0 FBCBA1
A18 C17 B17 C16 B16 D16 A16 E16 F16 D15 F15 A15 G17
D11 B10 D7 C5 C26 F24 B21 D20
D12 A10 E7 A4 A27 D24 A21 D19
C14 B14 C15 D17 D14 A13 K18
K17
K13 K14
E15 B15
NMAB0 NMAB1 NMAB2 NMAB3 NMAB4 NMAB5 NMAB6 NMAB7 NMAB8 NMAB9 NMAB10 NMAB11
R_NDQMB0 R_NDQMB1 R_NDQMB2 R_NDQMB3 R_NDQMB4 R_NDQMB5 R_NDQMB6 R_NDQMB7
R_NDQSB0 R_NDQSB1 R_NDQSB2 R_NDQSB3 R_NDQSB4 R_NDQSB5 R_NDQSB6 R_NDQSB7
NMRASB# NMCASB# NMWEB# NMCSB0#
NMCKEB NMCLKB0
NMCLKB0#
NMCLKB1
NMB_BA0 NMB_BA1
NMRASB# 21 NMCASB# 21 NMWEB# 21 NMCSB0# 21
NMCKEB 21
NMB_BA0 21 NMB_BA1 21
12
R111 @120_0402_5%
12
R110 @120_0402_5%
NMCLKB0 21
NMCLKB0# 21
NMCLKB1 21
NMCLKB1# 21
Title
Size Document Number Rev
5
4
3
2
Date: Sheet of
Compal Electronics, Inc.
nVIDIA NV31M (DDR)
LA-1841
17 57Thursday, February 20, 2003
1
5
4
3
2
1
U35D
AGP_VDD1
AGP_VDD2
AD11
AGPVDDQ
AD14
AGPVDDQ
AD17
AGPVDDQ
AD20
AGPVDDQ
AD23
AGPVDDQ
AE11
AGPVDDQ
AE14
AGPVDDQ
AE17
AGPVDDQ
AE20
AGPVDDQ
AE23
AGPVDDQ
L11
VDD
L13
VDD
L14
VDD
L17
VDD
L18
VDD
L20
VDD
N6
VDD
N11
VDD
N20
VDD
P11
VDD
P20
VDD
U11
VDD
U20
VDD
V11
VDD
V20
VDD
Y11
VDD
Y13
VDD
Y14
VDD
Y17
VDD
Y18
VDD
Y20
VDD
AA17
VDD
AA18
VDD
G14
VDD33
H6
VDD33
H7
VDD33
M6
VDD33
P24
VDD33
U6
VDD33
U7
VDD33
AC6
VDD33
AC7
VDD33
AD12
VDD33
AD15
VDD33
AD19
VDD33
AD22
VDD33
AD16
VDD33
N4
VD50CLAMP0
AE9
VD50CLAMP1
AA13
AGPCALPD_VDDQ
AA14
AGPCALPU_GND
AE12
AGP_PLLVDD
FBVDDQ
F11
FBVDDQ
F14
FBVDDQ
F17
FBVDDQ
F20
FBVDDQ
F23
FBVDDQ
G8
FBVDDQ
G11
FBVDDQ
G20
FBVDDQ
G23
FBVDDQ
H24
FBVDDQ
H25
FBVDDQ
L24
FBVDDQ
L25
FBVDDQ
P25
FBVDDQ
U25
FBVDDQ
Y24
FBVDDQ
Y25
FBVDDQ
AC24
FBVDDQ
AC25
FBVDDQ
AA6
NC
AC5
NC
AF10
NC
AG29
NC
AE27
NC
G9
NC
Y28
NC
NV34M_EPBGA701
VIPCAL_PD_VDDQ
VIPCAL_PU_GND
DVOCAL_PD_VDDQ
DVOCAL_PU_GND
I/O
POWER
FBCAL_PD_VDDQ
FBCAL_PU_GND
FBCAL_TERM_GND
FBCAL_CLK_GND
IFPABVPROBE
IFPABRSET
IFPABPLLVDD
IFPABPLLGND
IFPAIOVDD
IFPAIOGND
IFPBIOVDD
IFPBIOGND
IFPCVPROBE
IFPCRSET
IFPCPLLVDD
IFPCPLLGND
IFPCIOVDD
IFPCIOGND
VIPVDDQ VIPVDDQ VIPVDDQ
DVOVDDQ DVOVDDQ DVOVDDQ
DVO_VREF
TESTMODE
TESTMECLK
DACB_VDD
DACB_VREF
DACA_VDD
DACA_VREF
FB_DLLVDD
PLLVDD
NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
+1.5VS
D D
+VGA_CORE
R108
1 2
0_0402_5%
C C
+3VS
R113
1 2
0_0402_5%
+1.5VS
R40 49.9_0603_1%
1 2 1 2
R82 49.9_0603_1%
B B
FBCAL_PD_VDDQ NV31,NV34 use. NV18 not use.
FBCAL_PUK_GND NV31,NV34 use. NV18 not use.
FBCAL_TERM_GND NV31 use (tie to GND). NV18,NV34 not use.
FBCAL_CLK_GND NV31 use. NV18,NV34 not use.
A A
+5VS
AGPCALPD_VDDQ AGPCALPU_GND +AGP_PLLVDD
+2.5VS
IFABVPROBE
AA4
IFPABREST
V6
+IFPABPLLVDD
U10 V10
+IFPABIOVDD
Y4 W5
IFPCVPROBE
AA3 R4
+IFPCPLLVDD
P10 N10
+IFPCIOVDD
R5 R6
L6 L7 M7
VIPCAL_1
P6
VIPCAL_2
P7
AD8 AD9 AE8
DVOCAL_1
AB6
DVOCAL_2
AB7 AF4
R342 10K_0402_5%1 2
AE5 G24
R117 @10K_0402_5%
+DACA/BVDD
AB4
DACAVREF
AB5
DACBVREF
AG9 AH8
C27 AK7
B4 B27 C11 C20 D6 D25 D29 E12 E19 F27 L28 M26 N5 W7 W26 Y7
+FB_DLLVDD +PLLVDD
1
2
C44 0.1U_0402_10V6K
1 2
1 2
R109 1K_0402_5%
C55 0.1U_0402_10V6K
1 2
1 2
R112 1K_0402_5%
1 2
R107 10K_0402_5%
1 2
R114 10K_0402_5%
R120 @49.9_0402_1% R125 @49.9_0402_1%1 2
NV31 use only. NV18,NV34 not use.
R349 @49.9_0402_1%1 2 R348 @49.9_0402_1%1 2
1 2
C10
0.01U_0603_50V7K
12
TESTMECLK NV31,NV34 use. NV18 not use.
1
C67
0.01U_0402_50V7K
2
+VIP/DVOVDDQ
NV31 use only. NV18,NV34 not use.
+DVO_VREF
+2.5VS
R13649.9_0402_1% 12 R13949.9_0402_1%
12
R385@0_0402_5% 12 R137@549_0402_1% 12
1
C176 @4700P_0402_25V7K
2
+1.5VS
1
C61
4.7U_0805_10V4Z
2
1
C23
0.1U_0402_10V6K
2
1
C100 470P_0402_50V8J
2
@KC FBM-L11-201209-221LMAT_0805
1
C182 @470P_0402_50V8J
2
1
2
1
C62 4700P_0402_25V7K
2
L15
1 2
+FB_DLLVDD NV31 use. NV18,NV34 not use.
C36
0.1U_0402_16V4Z
+VIP/DVOVDDQ
12
R76 1K_0603_1%
12
R71 1K_0603_1%
KC FBM-L11-201209-221LMAT_0805
1
C131
4.7U_0805_10V4Z
2
+3VS
1
C40
0.022U_0402_16V7K
2
+3VS
L14
12
1
C39
0.022U_0402_16V7K
2
+DACA/BVDD
1
C53
4.7U_0805_10V4Z
2
+PLLVDD
C472
1
4.7U_0805_10V4Z
2
+IFPABPLLVDD
1
C87 470P_0402_50V8J
2
1
2
+AGP_PLLVDD+FB_DLLVDD
C471
4.7U_0805_10V4Z
1
C49
0.022U_0402_16V7K
2
1
C65 4700P_0402_25V7K
2
1
C474
2
1
2
+VIP/DVOVDDQ+IFPABIOVDD
C50 470P_0402_50V8J
1
C37 4700P_0402_25V7K
2
+5VS
1
C41
0.1U_0402_10V6K
2
KC FBM-L11-201209-221LMAT_0805
1
C24 470P_0402_50V8J
2
1
4700P_0402_25V7K
C88 4700P_0402_25V7K
1
C114 4700P_0402_25V7K
2
C15
470P_0402_50V8J
2
KC FBM-L11-201209-221LMAT_0805
L19
1 2
KC FBM-L11-201209-221LMAT_0805
1
C43 470P_0402_50V8J
2
+AGP_PLLVDD NV31,NV34 use. NV18 not use.
1
C110
0.1U_0402_10V6K
2
+3VS
L11
1 2
+3VS
L20
1 2
KC FBM-L11-201209-221LMAT_0805
+3VS
L13
12
+3VS
L12
1 2
KC FBM-L11-201209-221LMAT_0805
+3VS
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.
nVIDIA NV31M POWER)
LA-1841
18 57Thursday, February 20, 2003
1
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