Toshiba l500, LA-5321P Schematics

A

1 1

B

C

D

E

NSWAA/NTWAA

Liverpool 10

2 2

Sunderland 10

LA-5321P Schematic

3 3

REV 1.0

Intel Arrandale /IBEX PEAK

2009-11-12 Rev 1.0

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/01/23 2010/01/23

2009/01/23 2010/01/23

2009/01/23 2010/01/23

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

B

B

B

Date: Sheet

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Schematic,LA5321P M/B

Schematic,LA5321P M/B

Schematic,LA5321P M/B

401782

401782

401782

148Monday, January 25, 2010

148Monday, January 25, 2010

148Monday, January 25, 2010

E

D

D

D

of

of

of

A

B

C

D

E

Compal Confidential

Model Name : NSWAA/NTWAA

Intel Arrandale

Fan Control

APL5607

page 6

Clock Generator

SLG8SP587VTR

page 13

File Name : LA-5321P

1 1

rPGA-988

page 5,6,7,8,9,10

FDI X8

LCD Conn.

page 13

2 2

HDMI Conn.

page 15

HDMI Level Shifter

RJ45

3 3

CRT

page 14

page 15

Express Card

USB port 8

Express Card

PCIe port 0

(Reserve)

(Reserve)

page 27

RTL8103EL-VB 10/100M

PCIe port 2

PCMCIA

OZ601

page 28page 28

(Reserve)

page 32

USB

5V 480MHz

PCIe 1x

1.5V 2.5GHz(250MB/s)

PCIe 1x

1.5V 2.5GHz(250MB/s)

PCI

3V 33MHz

Intel Ibex Peak

DMI X4

2.5GHz2.7GHz

BGA-951

page 16~24

Memory BUS(DDRIII)

Dual Channel

1.5V DDRIII 800/1066 MT/s

3G 3IN1

USB port 12

USB

5V 480MHz

USB

5V 480MHz

PCIe 1x

1.5V 2.5GHz(250MB/s)

SATA port 1

5V 3GHz(300MB/s)

SATA port 4

5V 3GHz(300MB/s)

SATA port 5

5V 3GHz(300MB/s)

USB port 3

5V 480MHz

page 27

PCIeMini Card
WiMax

PCIeMini Card
WLAN

SATA HDD0

SATA ODD

eSATA

page 25

200pin DDRIII-SO-DIMM X2

BANK 0, 1, 2, 3

USB/B

USB port 0,1

page 25

(Reserve)

USB port 13

page 27

PCIe port 1

page 27

page 25

page 25

USB

USB port 10

USB port 3

page 25

BT conn

USB port 5

RTS5159E

page 31

page 26

Int. Camera

page 11,12

USB port 11

page 13

HD Audio

3.3V 33 MHz

LPC BUS

Power/B

USB/B

4 4

ODD/B for 17"

page 26

page 25

page 25

RTC CKT.

DC/DC Interface CKT.

Power Circuit DC/DC

A

page 16

page 36

page 37~45

B

SPI ROM

page 16

Debug Port

page 34

Touch Pad

page 26

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

ENE KB926 D3

page 33

Int.KBD

page 26

2009/01/23 2010/01/23

2009/01/23 2010/01/23

2009/01/23 2010/01/23

C

EC ROM

page 34

Compal Secret Data

Compal Secret Data

Compal Secret Data

3.3V/1.5V 24MHz

MDC 1.5 Conn

page 26 page 29

MIC CONN

page 30

Deciphered Date

Deciphered Date

Deciphered Date

D

HDA Codec

ALC272

Int.

AMP.

TPA6017

page 30

MIC CONN

page 30

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

HP CONN

page 30

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Schematic,LA5321P M/B

Schematic,LA5321P M/B

Schematic,LA5321P M/B

401782

401782

401782

SPK CONN

page 30

E

of

248Monday, January 25, 2010

of

248Monday, January 25, 2010

of

248Monday, January 25, 2010

D

D

D

5

4

3

2

1

NSWAA Liverpool Intel Arrandale
NTWAA Sunderland Intel Arrandale

B+

Ipeak=5A, Imax=3.5A, Iocp min=7.9

DESIGN CURRENT 5A

+5VALW

SUSP

D D

N-CHANNEL

SI4800

DESIGN CURRENT 4A

+5VS

TPS51125RGER

Ipeak=5A, Imax=3.5A, Iocp min=7.7

SUSP

N-CHANNEL

SI4800

P-CHANNEL

AO-3413

P-CHANNEL

AO-3413

C C

P-CHANNEL

AO-3413

VR_ON

ISL62883

GFXVR_EN

ISL62881

DESIGN CURRENT 5A

DESIGN CURRENT 6A

VGA_ENVDD

DESIGN CURRENT 1.5A

WOL_EN#

DESIGN CURRENT 330mA

BT_PWR#

DESIGN CURRENT 180mA

DESIGN CURRENT 48A

DESIGN CURRENT 15A

+3VALW

+3VS

+LCD_VDD

+3V_LAN

+BT_VCC

+CPU_CORE

+GFX_CORE

VTTP_EN#

B B

APW7138

SYSON

TPS51117

Ipeak=18A, Imax=12.6A, Iocp min=20.64

Ipeak=9A, Imax=6.3A, Iocp min=9.98

SUSP

N-CHANNEL

SI4856

SUSP

G2992F1U

DESIGN CURRENT 18A

DESIGN CURRENT 9A

DESIGN CURRENT 1.2A

DESIGN CURRENT 1.5A

+VTT

+1.5V
+1.5VS

+0.75VS

SUSP#

APL5930

DESIGN CURRENT 1.5A

+1.8VS

SUSP#

A A

5

TPS51117RGYR

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Ipeak=7A, Imax=4.9A, Iocp min=8.54

Compal Secret Data

Compal Secret Data

2009/01/23 2010/01/23

2009/01/23 2010/01/23

2009/01/23 2010/01/23

3

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

DESIGN CURRENT 7A

2

+1.05VS

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

Schematic,LA5321P M/B

Schematic,LA5321P M/B

Schematic,LA5321P M/B

401782

401782

401782

348Monday, January 25, 2010

348Monday, January 25, 2010

348Monday, January 25, 2010

1

of

of

of

D

D

D

A

B

C

D

E

Voltage Rails

1 1

power
plane

( O MEANS ON X MEANS OFF )

+RTCVCC

+B

+5VALW
+3VALW
+VSB

+1.5V

+5VS
+3VS
+1.5VS
+VGA_CORE
+CPU_CORE
+VTT

BTO Option Table

Function

description

explain

BTO

Bluetooth

(B)

Bluetooth MDC

BT@

RJ11 MIC

MIC

MDC@

MIC@

HDMI

(Y)

HDMI

IHDMI@

Panel

16" 17"

16@ 17@

3G

(G)

3G

3G@

New Card

Express Card

(E)

PCMCIA

NEW@

(A)

PCM@

Mini Card

WIRELESS

WLAN@

+1.05VS
+1.8VS
+1.1VS

State

S0

2 2

S1

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery
don't exist

O
O
O
O
O
O

O
O
O
O
O

X

O
O
O
O

X

O

XX
X

XX X

+0.75VS

OO
OO

X

X

STATE

SIGNAL

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SLP_S3#

SLP_S4# SLP_S5#

HIGH HIGHHIGH

LOW

LOW LOW

HIGH HIGHHIGH

HIGH

LOW LOWLOW

G3 LOW LOWLOW

HIGH

HIGH

3 3

EC SM Bus1 address

Device

EC KB926 D3

+3VALW

Smart Battery+3VALW VGA THM Sensor

Address Address

EC SM Bus2 address

Device

PowerPower

EC KB926 D3

+3VS
+3VS

ADM1032ARMZ

+3VS

PCH

1001 110x b0001 011x b

0100 110x b

PCH SM Bus address

Power

+3VALW
+3VS

4 4

+3VS
+3VS
+3VS
+3VS

Device

PCH
Clock Generator
DDR DIMM0
DDR DIMM1
Express
WLAN/Wimax/3G

A

Address

1101 001x b
1001 000x b
1001 010x b

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/01/23 2010/01/23

2009/01/23 2010/01/23

2009/01/23 2010/01/23

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Schematic,LA5321P M/B

Schematic,LA5321P M/B

Schematic,LA5321P M/B

401782

401782

401782

448Monday, January 25, 2010

448Monday, January 25, 2010

448Monday, January 25, 2010

of

of

E

of

D

D

D

5

1 2

R1 20_0402_1%R1 20_0402_1%

1 2

R2 20_0402_1%R2 20_0402_1%

1 2

R4 49.9_0402_1%R4 49.9_0402_1%

1 2

R3 49.9_0402_1%R3 49.9_0402_1%

PECI21

+VTT

XDP_RST#_R

H_PWRGOOD

DRAMPWROK

+VTT

@

12

R370_0402_5%@R370_0402_5%

1 2

R18 49.9_0402_1%R18 49.9_0402_1%

1 2

R9 68_0402_5%R9 68_0402_5%

1 2

R40 0_0402_5%R40 0_0402_5%

1 2

R36 1K_0402_5%R36 1K_0402_5%

1 2

R43 0_0402_5%R43 0_0402_5%

VTTPWROK_CPU

TAPPWRGD

R301.5K_0402_1% R301.5K_0402_1%

750_0402_1%

750_0402_1%

D D

+VTT

R10

R10
68_0402_5%

68_0402_5%
@

@

1 2

H_CPURST#

C C

+1.5V_CPU

R28

R28

1.1K_0402_1%

1.1K_0402_1%

1 2

DRAMPWROK

R29

R29
3K_0402_1%

3K_0402_1%

1 2

R29

@ R29

@

750_0402_1%

750_0402_1%

H_PROCHOT#33,44

H_THERMTRIP#21

PLT_RST#20,27,28,33,34

PMSYNCH18

H_PWRGOOD21

DRAMPWROK18

BUF_PLT_RST#20

TP_SKTOCC#

T41PAD T41PAD

CATERR#

H_PROCHOT#_D

H_CPURST#

H_PMSYNCH

H_PWRGOOD1_R

12

R250_0402_5% R250_0402_5%

H_PWRGOOD0_R

12

R240_0402_5% R240_0402_5%

DRAMPWROK_R

12

R690_0402_5% R690_0402_5%

R31

R31

4

H_COMP3
H_COMP2
H_COMP1
H_COMP0

JCPUB

JCPUB

AT23

COMP3

AT24

COMP2

G16

COMP1

AT26

COMP0

AH24

SKTOCC#

AK14

CATERR#

AT15

PECI

AN26

PROCHOT#

AK15

THERMTRIP#

AP26

RESET_OBS#

AL15

PM_SYNC

AN14

VCCPWRGOOD_1

AN27

VCCPWRGOOD_0

AK13

SM_DRAMPWROK

AM15

VTTPWRGOOD

AM26

TAPPWRGOOD

AL14

RSTIN#

IC,AUB_CFD_rPGA,R0P9

IC,AUB_CFD_rPGA,R0P9
@

@

3

MISC THERMAL

MISC THERMAL

CLOCKS

CLOCKS

DDR3

MISC

DDR3

MISC

PWR MANAGEMENT

PWR MANAGEMENT

JTAG & BPM

JTAG & BPM

BCLK

BCLK#

BCLK_ITP

BCLK_ITP#

PEG_CLK

PEG_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

SM_DRAMRST#

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

PM_EXT_TS#[0]
PM_EXT_TS#[1]

PRDY#
PREQ#

TRST#

TDI_M

TDO_M

DBR#

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

TCK
TMS

TDO

TDI

A16
B16

CLK_CPU_XDP_R

AR30

CLK_CPU_XDP#_R

AT30
E16

D16
A18

A17

SM_DRAMRST#_CPU

F6

SM_RCOMP_0

AL1

SM_RCOMP_1

AM1

SM_RCOMP_2

AN1

PM_EXTTS#0

AN15

PM_EXTTS#_R

AP15

XDP_PRDY#

AT28

XDP_PREQ#

AP27

XDP_TCK

AN28

XDP_TMS

AP28

XDP_TRST#

AT27

XDP_TDI_R

AT29

XDP_TDO_R

AR27

XDP_TDI_M

AR29

XDP_TDO_M

AP29
AN25

XDP_BPM#0

AJ22

XDP_BPM#1

AK22

XDP_BPM#2

AK24

XDP_BPM#3

AJ24

XDP_BPM#4

AJ25

XDP_BPM#5

AH22

XDP_BPM#6

AK23

XDP_BPM#7

AH23

CLK_CPU_BCLK 21
CLK_CPU_BCLK# 21

1 2

R41 0_0402_5%@R41 0_0402_5%@

1 2

R42 0_0402_5%@R42 0_0402_5%@

CLK_PEG 17
CLK_PEG# 17

Unused by Clarksfield rPGA989

R6 100_0402_1%R6 100_0402_1%

1 2

R7 24.9_0402_1%R7 24.9_0402_1%

1 2

R8 130_0402_1%R8 130_0402_1%

1 2

12

R12 0_0402_5%R12 0_0402_5%

Routed as a single daisy chain

R312 1K_0402_5%R312 1K_0402_5%

EMI reverse, close to JCPU

CLK_CPU_XDP
CLK_CPU_XDP#

DDR3 Compensation Signals
Layout Note:Please these
resistors near Processor

PM_EXTTS# 11,12

12

+3VS

XDP_DBRESET# 18

XDP_PRDY#
XDP_PREQ#
XDP_TCK
XDP_TMS
XDP_TRST#
XDP_TDI_R
XDP_TDO_R
XDP_TDI_M
XDP_TDO_M
XDP_DBRESET#

2

C7 0.1U_0402_10V6K@C7 0.1U_0402_10V6K@
C8 0.1U_0402_10V6K@C8 0.1U_0402_10V6K@
C9 0.1U_0402_10V6K@C9 0.1U_0402_10V6K@
C10 0.1U_0402_10V6K@C10 0.1U_0402_10V6K@
C11 0.1U_0402_10V6K@C11 0.1U_0402_10V6K@
C12 0.1U_0402_10V6K@C12 0.1U_0402_10V6K@
C13 0.1U_0402_10V6K@C13 0.1U_0402_10V6K@
C14 0.1U_0402_10V6K@C14 0.1U_0402_10V6K@
C15 0.1U_0402_10V6K@C15 0.1U_0402_10V6K@
C17 0.1U_0402_10V6K@C17 0.1U_0402_10V6K@

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

SM_DRAMRST#_CPU

@ R127

@

100K_0402_5%

100K_0402_5%

JTAG MAPPING

1

12

R19 0_0402_5%R19 0_0402_5%

D

S

D

S

12

R127

PM_EXTTS#0
PM_EXTTS#_R

XDP_TDI_R XDP_TDI

XDP_TDO_M

0_0402_5%

0_0402_5%

XDP_TDI_M

XDP_TDO_R

Scan Chain
(Default)

CPU Only

GMCH Only

13

Q41

Q41

G

G

BSS138_NL_SOT23-3

BSS138_NL_SOT23-3

2

C301

0.047U_0402_16V7K

0.047U_0402_16V7K

1 2

R15 10K_0402_5%R15 10K_0402_5%
R13 10K_0402_5%R13 10K_0402_5%

1 2

R20 0_0402_5%R20 0_0402_5%

@

@

1 2

R21 0_0402_5%

R21 0_0402_5%

12

R23

R23

@

@

1 2

R26 0_0402_5%

R26 0_0402_5%

1 2

R27 0_0402_5%R27 0_0402_5%

STUFF -> R20, R23, R27
NO STUFF -> R21, R26

STUFF -> R20, R21
NO STUFF -> R23, R26, R27

STUFF -> R26, R27
NO STUFF -> R20, R21, R23

@

@

RST_GATE 21

@C301

@

SM_DRAMRST# 11,12

Add on 10/28

+VTT

12
12

XDP_TDO

XDP_PREQ#
XDP_PRDY#

XDP_BPM#0
XDP_BPM#1

XDP_BPM#2
XDP_BPM#3

XDP_BPM#4
XDP_BPM#5

XDP_BPM#6
XDP_BPM#7

T1PAD T1PAD
T2PAD T2PAD

XDP_TCK

Deciphered Date

Deciphered Date

Deciphered Date

+VTT

XDP Connector

JXDP

JXDP

1

GND0

3

OBSFN_A0

5

OBSFN_A1

7

GND2

9

OBSDATA_A0

11

OBSDATA_A1

13

GND4

15

OBSDATA_A2

17

OBSDATA_A3

19

GND6

21

OBSFN_B0

23

OBSFN_B1

25

GND8

27

OBSDATA_B0

29

OBSDATA_B1

31

GND10

33

OBSDATA_B2

35

OBSDATA_B3

37

GND12

39

PWRGOOD/HOOK0

41

HOOK1

43

VCC_OBS_AB

45

HOOK2

47

HOOK3

49

GND14

51

SDA

53

SCL

55

TCK1

57

TCK0

59

GND16

SAMTE_BSH-030-01-L-D-A @

SAMTE_BSH-030-01-L-D-A @

2

2

GND1

4

OBSFN_C0

6

OBSFN_C1

8

GND3
OBSDATA_C0
OBSDATA_C1

OBSDATA_C2
OBSDATA_C3

OBSDATA_D0
OBSDATA_D1

OBSDATA_D2
OBSDATA_D3

ITPCLK/HOOK4

ITPCLK#/HOOK5

VCC_OBS_CD

RESET#/HOOK6

DBR#/HOOK7

10
12
14

GND5

16
18
20

GND7

22

OBSFN_D0

24

OBSFN_D1

26

GND9

28
30
32

GND11

34
36
38

GND13

GND15

TD0

TRST#

TDI

TMS

GND17

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

CLK_CPU_XDP

40

CLK_CPU_XDP#

42
44

XDP_RST#_R

46

XDP_DBRESET#

48
50

XDP_TDO

52

XDP_TRST#

54

XDP_TDI

56

XDP_TMS

58
60

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.
Schematic,LA5321P M/B

Schematic,LA5321P M/B

Schematic,LA5321P M/B
401782

401782

401782

1 2

R14 51_0402_5%R14 51_0402_5%

12

R11

R11
51_0402_5%

51_0402_5%

1

+VTT

1

C2

0.1U_0402_10V6K

0.1U_0402_10V6K

2

548Monday, January 25, 2010

548Monday, January 25, 2010

548Monday, January 25, 2010

of

of

of

@C2

@

D

D

D

@

Close to JCPU

B B

+VTT

12

R960_0402_5% R960_0402_5%

PMEG2010AEH_SOD123

PMEG2010AEH_SOD123

@ D54

@

A A

VTTPWROK36,41

VTTPWROK

5

21

D54

+3VALW

5

U16

@U16

@

1

P

IN1

O

2

IN2

G

SN74AHC1G08DCKR_SC70-5

SN74AHC1G08DCKR_SC70-5

3

@

12

R840_0402_5%@R840_0402_5%

4

12

R22
1K_0402_5%

1K_0402_5%

@

@

R33 1.5K_0402_1%

R33 1.5K_0402_1%

DRAMPWROK

@R22

@

VTTPWROK_CPU

4

VTTPWROK_CPU

DRAMPWROK

12

C384 1000P_0402_50V7K@C384 1000P_0402_50V7K@

12

C389 1000P_0402_50V7K@C389 1000P_0402_50V7K@

PM_PBTN_OUT#18

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

H_PWRGOOD H_PWRGOOD_R

TAPPWRGD

2009/01/23 2010/01/23

2009/01/23 2010/01/23

2009/01/23 2010/01/23

C1 0.1U_0402_10V6K

C1 0.1U_0402_10V6K

R32 1K_0402_5%@R32 1K_0402_5%@

1 2

1 2

R35 0_0402_5%@ R35 0_0402_5%@

@

12

TAPPWRGD_R

Compal Secret Data

Compal Secret Data

Compal Secret Data

5

4

3

2

1

D D

DMI_PTX_CRX_N018
DMI_PTX_CRX_N118
DMI_PTX_CRX_N218
DMI_PTX_CRX_N318

DMI_PTX_CRX_P018
DMI_PTX_CRX_P118
DMI_PTX_CRX_P218
DMI_PTX_CRX_P318

DMI_CTX_PRX_N018
DMI_CTX_PRX_N118
DMI_CTX_PRX_N218
DMI_CTX_PRX_N318

DMI_CTX_PRX_P018
DMI_CTX_PRX_P118
DMI_CTX_PRX_P218
DMI_CTX_PRX_P318

C C

B B

A A

FDI_CTX_PRX_N018
FDI_CTX_PRX_N118
FDI_CTX_PRX_N218
FDI_CTX_PRX_N318
FDI_CTX_PRX_N418
FDI_CTX_PRX_N518
FDI_CTX_PRX_N618
FDI_CTX_PRX_N718

FDI_CTX_PRX_P018
FDI_CTX_PRX_P118
FDI_CTX_PRX_P218
FDI_CTX_PRX_P318
FDI_CTX_PRX_P418
FDI_CTX_PRX_P518
FDI_CTX_PRX_P618
FDI_CTX_PRX_P718

FDI_FSYNC018
FDI_FSYNC118

FDI_INT18
FDI_LSYNC018

FDI_LSYNC118

JCPUA

JCPUA

A24

DMI_RX#[0]

C23

DMI_RX#[1]

B22

DMI_RX#[2]

A21

DMI_RX#[3]

B24

DMI_RX[0]

D23

DMI_RX[1]

B23

DMI_RX[2]

A22

DMI_RX[3]

D24

DMI_TX#[0]

G24

DMI_TX#[1]

F23

DMI_TX#[2]

H23

DMI_TX#[3]

D25

DMI_TX[0]

F24

DMI_TX[1]

E23

DMI_TX[2]

G23

DMI_TX[3]

E22

FDI_TX#[0]

D21

FDI_TX#[1]

D19

FDI_TX#[2]

D18

FDI_TX#[3]

G21

FDI_TX#[4]

E19

FDI_TX#[5]

F21

FDI_TX#[6]

G18

FDI_TX#[7]

D22

FDI_TX[0]

C21

FDI_TX[1]

D20

FDI_TX[2]

C18

FDI_TX[3]

G22

FDI_TX[4]

E20

FDI_TX[5]

F20

FDI_TX[6]

G19

FDI_TX[7]

F17

FDI_FSYNC[0]

E17

FDI_FSYNC[1]

C17

FDI_INT

F18

FDI_LSYNC[0]

D17

FDI_LSYNC[1]

IC,AUB_CFD_rPGA,R0P9

IC,AUB_CFD_rPGA,R0P9
@

@

PEG_COMP

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]

PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]

B26
A26
B27
A25

K35
J34
J33
G35
G32
F34
F31
D35
E33
C33
D32
B32
C31
B28
B30
A31

J35
H34
H33
F35
G33
E34
F32
D34
F33
B33
D31
A32
C30
A28
B29
A30

L33
M35
M33
M30
L31
K32
M29
J31
K29
H30
H29
F29
E28
D29
D27
C26

L34
M34
M32
L30
M31
K31
M28
H31
K28
G30
G29
F28
E27
D28
C27
C25

PEG_RBIAS

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RBIAS
PEG_RX#[0]

PEG_RX#[1]

DMI Intel(R) FDI

DMI Intel(R) FDI

PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]

PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

PEG_RX[10]

PEG_RX[11]

PEG_RX[12]

PEG_RX[13]

PEG_RX[14]

PEG_RX[15]

PEG_TX#[0]

PEG_TX#[1]

PEG_TX#[2]

PEG_TX#[3]

PEG_TX#[4]

PEG_TX#[5]

PEG_TX#[6]

PEG_TX#[7]

PEG_TX#[8]

PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]

PCI EXPRESS -- GRAPHICS

PCI EXPRESS -- GRAPHICS

PEG_TX#[15]

PEG_TX[10]

PEG_TX[11]

PEG_TX[12]

PEG_TX[13]

PEG_TX[14]

PEG_TX[15]

1 2

R38 49.9_0402_1%R38 49.9_0402_1%

1 2

R39 750_0402_1%R39 750_0402_1%

+5VS

1A

EN_DFAN133

+FAN1

10mil

1

C5

C5
10U_0805_10V4Z

10U_0805_10V4Z

2

FAN Control Circuit

1SS355_SOD323-2

1SS355_SOD323-2

2

C3

C3

10U_0805_10V4Z

U1

U1

1

EN

GND

2

VIN

GND

3

VOUT

GND

4

VSET

GND

APL5607KI-TRG_SO8

APL5607KI-TRG_SO8

10U_0805_10V4Z

1

8
7
6
5

BAS16_SOT23-3

BAS16_SOT23-3

12

D1

D1
@

@

12

+FAN1

2

D2

D2

C4

@

@

1000P_0402_50V7K@C41000P_0402_50V7K@

1

1
2
3

4
5

ACES_85204-0300N

ACES_85204-0300N

@

@

R34 10K_0402_5%R34 10K_0402_5%

2

C6

C6

0.01U_0402_16V7K

0.01U_0402_16V7K

1

@

@

JFAN

JFAN

1
2
3

GND
GND

12

FAN_SPEED1 33

+3VS

Security Classification

Security Classification

Security Classification

2009/01/23 2010/01/23

2009/01/23 2010/01/23

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/01/23 2010/01/23

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

B

B

B

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

Schematic,LA5321P M/B

Schematic,LA5321P M/B

Schematic,LA5321P M/B

401782

401782

401782

648Monday, January 25, 2010

648Monday, January 25, 2010

648Monday, January 25, 2010

1

D

D

D

of

of

of

5

JCPUC

JCPUC

DDR_A_D[0..63]11

4

3

JCPUD

JCPUD

DDR_B_D[0..63]12

2

1

AA6

SA_CK[0]

AA7

SA_CK#[0]

P7

DDR_A_D0
DDR_A_D1

D D

C C

B B

DDR_A_BS011
DDR_A_BS111
DDR_A_BS211

DDR_A_CAS#11
DDR_A_RAS#11

DDR_A_WE#11

DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

A10

C10

B10

D10

E10

F10

H10

G10

J10

AH5
AF5
AK6
AK7
AF6
AG5

AJ7
AJ6

AJ10

AJ9

AL10

AK12

AK8

AL7

AK11

AL8

AN8
AM10
AR11

AL11

AM9

AN9

AT11

AP12
AM12
AN12
AM13

AT14

AT12

AL13
AR14

AP14

AC3
AB2

AE1
AB3
AE9

C7
A7

A8
D8

E6
F7
E9
B7
E7
C6

G8

K7

J8

G7

J7

L7
M6
M8

L9

L6

K8

N8

P9

U7

SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

SA_BS[0]
SA_BS[1]
SA_BS[2]

SA_CAS#
SA_RAS#
SA_WE#

SA_CKE[0]

Y6

SA_CK[1]

Y5

SA_CK#[1]

P6

SA_CKE[1]

AE2

SA_CS#[0]

AE8

SA_CS#[1]

SA_DM[0]
SA_DM[1]
SA_DM[2]
SA_DM[3]
SA_DM[4]
SA_DM[5]
SA_DM[6]
SA_DM[7]

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]

AD8
AF9

B9
D7
H7
M7
AG6
AM7
AN10
AN13

DDR_A_DQS#0

C9

DDR_A_DQS#1

F8

DDR_A_DQS#2

J9

DDR_A_DQS#3

N9

DDR_A_DQS#4

AH7

DDR_A_DQS#5

AK9

DDR_A_DQS#6

AP11

DDR_A_DQS#7

AT13

C8
F9
H9
M9
AH8
AK10
AN11
AR13

Y3
W1
AA8
AA3
V1
AA9
V8
T1
Y9
U6
AD4
T2
U3
AG8
T3
V9

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8

DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

SA_ODT[0]
SA_ODT[1]

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY A

SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

DDRA_CLK0 11 DDRB_CLK0 12
DDRA_CLK0# 11
DDRA_CKE0 11 DDRB_CKE0 12

DDRA_CLK1 11
DDRA_CLK1# 11
DDRA_CKE1 11

DDRA_SCS0# 11
DDRA_SCS1# 11 DDRB_SCS1# 12

DDRA_ODT0 11 DDRB_ODT0 12
DDRA_ODT1 11 DDRB_ODT1 12

DDR_A_DM[0..7] 11

DDR_A_DQS#[0..7] 11

DDR_A_DQS[0..7] 11

DDR_A_MA[0..15] 11

DDR_B_BS012
DDR_B_BS112
DDR_B_BS212

DDR_B_CAS#12
DDR_B_RAS#12

DDR_B_WE#12

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

AF3

AG1

AJ3
AK1
AG4
AG3

AJ4
AH4
AK3
AK4
AM6
AN2
AK5
AK2
AM4
AM3
AP3
AN5

AT4
AN6
AN4
AN3

AT5

AT6
AN7
AP6
AP8

AT9

AT7
AP9

AR10
AT10

AB1

AC5
AC6

B5
A5
C3
B3
E4
A6
A4
C4
D1
D2
F2
F1
C2
F5
F3

G4

H6

G2

J6

J3
G1
G5

J2

J1

J5

K2

L3
M1

K5
K4

M4

N5

W5

R7

Y7

SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

SB_BS[0]
SB_BS[1]
SB_BS[2]

SB_CAS#
SB_RAS#
SB_WE#

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

DDR SYSTEM MEMORY - B

DDR SYSTEM MEMORY - B

SB_CK[0]
SB_CK#[0]
SB_CKE[0]

SB_CK[1]
SB_CK#[1]
SB_CKE[1]

SB_CS#[0]
SB_CS#[1]

SB_ODT[0]
SB_ODT[1]

SB_DM[0]

SB_DM[1]

SB_DM[2]

SB_DM[3]

SB_DM[4]

SB_DM[5]

SB_DM[6]

SB_DM[7]

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

SB_MA[0]

SB_MA[1]

SB_MA[2]

SB_MA[3]

SB_MA[4]

SB_MA[5]

SB_MA[6]

SB_MA[7]

SB_MA[8]

SB_MA[9]

SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

W8
W9
M3

V7
V6
M2

AB8
AD6

AC7
AD1

D4
E1
H3
K1
AH1
AL2
AR4
AT8

D5
F4
J4
L4
AH2
AL4
AR5
AR8

C5
E3
H4
M5
AG2
AL5
AP5
AR7

U5
V2
T5
V3
R1
T8
R2
R6
R4
R5
AB5
P3
R3
AF7
P5
N1

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8

DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

DDRB_CLK0# 12

DDRB_CLK1 12
DDRB_CLK1# 12
DDRB_CKE1 12

DDRB_SCS0# 12

DDR_B_DM[0..7] 12

DDR_B_DQS#[0..7] 12

DDR_B_DQS[0..7] 12

DDR_B_MA[0..15] 12

IC,AUB_CFD_rPGA,R0P9

IC,AUB_CFD_rPGA,R0P9
@

@

A A

Security Classification

Security Classification

Security Classification

2009/01/23 2010/01/23

2009/01/23 2010/01/23

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/01/23 2010/01/23

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

IC,AUB_CFD_rPGA,R0P9

IC,AUB_CFD_rPGA,R0P9
@

@

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

B

B

B

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

Schematic,LA5321P M/B

Schematic,LA5321P M/B

Schematic,LA5321P M/B

401782

401782

401782

748Monday, January 25, 2010

748Monday, January 25, 2010

748Monday, January 25, 2010

1

D

D

D

of

of

of

5

4

3

2

1

Material Note (+VTT):

JCPUF

JCPUF

+CPU_CORE

D D

C C

B B

A A

Clarksfield: 65A Clarksfield: 21A
Auburndale:48A

AG35

VCC1

AG34

VCC2

AG33

VCC3

AG32

VCC4

AG31

VCC5

AG30

VCC6

AG29

VCC7

AG28

VCC8

AG27

VCC9

AG26

VCC10

AF35

VCC11

AF34

VCC12

AF33

VCC13

AF32

VCC14

AF31

VCC15

AF30

VCC16

AF29

VCC17

AF28

VCC18

AF27

VCC19

AF26

VCC20

AD35

VCC21

AD34

VCC22

AD33

VCC23

AD32

VCC24

AD31

VCC25

AD30

VCC26

AD29

VCC27

AD28

VCC28

AD27

VCC29

AD26

VCC30

AC35

VCC31

AC34

VCC32

AC33

VCC33

AC32

VCC34

AC31

VCC35

AC30

VCC36

AC29

VCC37

AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26

VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

CPU CORE SUPPLY

CPU CORE SUPPLY

POWER

POWER

SENSE LINES

SENSE LINES

Auburndale:18A

VTT0_1
VTT0_2
VTT0_3
VTT0_4
VTT0_5
VTT0_6
VTT0_7
VTT0_8

VTT0_9
VTT0_10
VTT0_11
VTT0_12
VTT0_13
VTT0_14
VTT0_15
VTT0_16
VTT0_17
VTT0_18
VTT0_19
VTT0_20
VTT0_21
VTT0_22
VTT0_23
VTT0_24
VTT0_25
VTT0_26
VTT0_27
VTT0_28
VTT0_29
VTT0_30
VTT0_31

1.1V RAIL POWER

1.1V RAIL POWER

VTT0_32

VTT0_33
VTT0_34
VTT0_35
VTT0_36
VTT0_37
VTT0_38
VTT0_39
VTT0_40
VTT0_41
VTT0_42
VTT0_43
VTT0_44

PSI#

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

PROC_DPRSLPVR

CPU VIDS

CPU VIDS

VTT_SELECT

ISENSE

VCC_SENSE
VSS_SENSE

VTT_SENSE

VSS_SENSE_VTT

AH14
AH12
AH11
AH10
J14
J13
H14
H12
G14
G13
G12
G11
F14
F13
F12
F11
E14
E12
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11

AF10
AE10
AC10
AB10
Y10
W10
U10
T10
J12
J11
J16
J15

AN33

AK35
AK33
AK34
AL35
AL33
AM33
AM35
AM34

G15

AN35

AJ34
AJ35

B15
A15

330uF/ 6mohm, number are 3,
power x1, HW x2

(Place these capacitors under CPU socket Edge, top layer) (Place these capacitors between inductor and socket on Bottom)

@

@

+

+

C80 330U_D2E_2.5VM_R6M

C80 330U_D2E_2.5VM_R6M

1 2

@

@

+

+

C82 330U_D2E_2.5VM_R6M

C82 330U_D2E_2.5VM_R6M

1 2

@

@

+

+

C84 330U_D2E_2.5VM_R6M

C84 330U_D2E_2.5VM_R6M

1 2

C89 22U_0805_6.3V6MC89 22U_0805_6.3V6M

1 2

C91 22U_0805_6.3V6MC91 22U_0805_6.3V6M

1 2

Co-layout with C80, C82

+VTT

1

1

+

+

+

+

2

2

H_PSI# 44

CPU_VID0 44
CPU_VID1 44
CPU_VID2 44
CPU_VID3 44
CPU_VID4 44
CPU_VID5 44
CPU_VID6 44
H_DPRSLPVR 44

H_VTTSELECT 41

IMVP_IMON 44

VTT_SENSE 41
VSS_SENSE_VTT 41

390U_2.5V_M_R10

390U_2.5V_M_R10

H_DPRSLPVR_R

VCCSENSE_R

C159

C159

390U_2.5V_M_R10

390U_2.5V_M_R10

1 2

R62 0_0402_5%R62 0_0402_5%

R65 0_0402_5%R65 0_0402_5%

1 2

R66 0_0402_5%R66 0_0402_5%

1 2

+VTT

C160

C160

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C150

C150

C158

C158

@

@

@

@

2

22U_0805_6.3V6M

22U_0805_6.3V6M

C81 10U_0805_10V4KC81 10U_0805_10V4K

1 2

C83 10U_0805_10V4KC83 10U_0805_10V4K

1 2

C85 10U_0805_10V4KC85 10U_0805_10V4K

1 2

C87 10U_0805_10V4KC87 10U_0805_10V4K

1 2

C88 10U_0805_10V4KC88 10U_0805_10V4K

1 2

C90 10U_0805_10V4KC90 10U_0805_10V4K

1 2

C92 10U_0805_10V4KC92 10U_0805_10V4K

1 2

C94 10U_0805_10V4K@C94 10U_0805_10V4K@

1 2

Add on 5/25 for power team request

+CPU_CORE

22U_0805_6.3V6M

22U_0805_6.3V6M

1

1

1

2

C144

C144

C148

C148

2

22U_0805_6.3V6M

22U_0805_6.3V6M

C131

C131

2

22U_0805_6.3V6M

22U_0805_6.3V6M

CRB default setting:
VID[6:0]=[0100111]

VTT Rail

Auburndale +1.1VS_VTT=1.05V
Clarksfield +1.1VS_VTT=1.1V

H_VTTSELECT = low, 1.1V
H_VTTSELECT = high, 1.05V

1 2

R64 100_0402_1%R64 100_0402_1%

VCCSENSE
VSSSENSEVSSSENSE_R

1 2

R67 100_0402_1%R67 100_0402_1%

near CPU

+CPU_CORE

VCCSENSE 44
VSSSENSE 44

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C130

C130

2

1

1

C132

C132

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C129

C129

C149

C149

2

22U_0805_6.3V6M

22U_0805_6.3V6M

+CPU_CORE

10U_0805_10V4K

10U_0805_10V4K

1

C71

C71

2

10U_0805_10V4K

10U_0805_10V4K

1

C72

C72

2

10U_0805_10V4K

10U_0805_10V4K

10U_0805_10V4K

10U_0805_10V4K

1

C73

C73

2

1

2

1

C75

C75

C74

C74

2

10U_0805_10V4K

10U_0805_10V4K

10U_0805_10V4K

10U_0805_10V4K

1

C76

C76

2

10U_0805_10V4K

10U_0805_10V4K

10U_0805_10V4K

10U_0805_10V4K

1

C77

C77

2

1

C78

C78

2

10U_0805_10V4K

10U_0805_10V4K

1

C79

C79

2

(Place these capacitors under CPU socket, top layer)

+CPU_CORE

10U_0805_10V4K

10U_0805_10V4K

1

C98

C98

2

10U_0805_10V4K

10U_0805_10V4K

1

C99

C99

2

10U_0805_10V4K

10U_0805_10V4K

10U_0805_10V4K

10U_0805_10V4K

1

C100

C100

2

1

C101

C101

2

10U_0805_10V4K

10U_0805_10V4K

10U_0805_10V4K

10U_0805_10V4K

1

C102

C102

2

1

1

C103

C103

C104

C104

2

2

10U_0805_10V4K

10U_0805_10V4K

(Place these capacitors on CPU cavity, Bottom Layer)

+CPU_CORE

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C106

C106

C105

1

2

C105

2

22U_0805_6.3V6M

22U_0805_6.3V6M

+CPU_CORE

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C112

C112

C111

C111

2

22U_0805_6.3V6M

22U_0805_6.3V6M

TOP side (under inductor)

+CPU_CORE

330U_D2_2.5VY_R9M

330U_D2_2.5VY_R9M

C124

C124

1

+

+

330U_D2_2.5VY_R9M

330U_D2_2.5VY_R9M

2

1

+

+

C121

C121

330U_D2_2.5VY_R9M

330U_D2_2.5VY_R9M

2

1

1

C107

C107

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

1

C113

C113

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

330U_D2_2.5VY_R9M

330U_D2_2.5VY_R9M

1

+

+

C122

C122

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C108

C108

2

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C114

C114

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

+

+

C123

C123

2

C109

C109

C115

C115

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C110

C110

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C116

C116

2

C271

C271

560U_2.5V_M

560U_2.5V_M

@

@

1

2

1

2

Co-layout with C124, C122

1

+

+

560U_2.5V_M

560U_2.5V_M

2

C180

C180

1

@

@

2

+CPU_CORE

+

+

+

+

1

C179

C179

560U_2.5V_M

560U_2.5V_M

@

@

2

IC,AUB_CFD_rPGA,R0P9

IC,AUB_CFD_rPGA,R0P9
@

@

5

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/01/23 2010/01/23

2009/01/23 2010/01/23

2009/01/23 2010/01/23

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

Schematic,LA5321P M/B

Schematic,LA5321P M/B

Schematic,LA5321P M/B

401782

401782

401782

1

848Monday, January 25, 2010

848Monday, January 25, 2010

848Monday, January 25, 2010

D

D

D

of

of

of

5

4

3

2

1

Q33

1

+GFX_CORE

R424

@ R424

@

470_0805_5%

47P_0402_50V8J

C118

C118
@

@

1

2

C95

C95

12

C119

C119
@

@

47P_0402_50V8J

12

C93

C93
@

@

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C127

C127

2

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1

C117

C117

2

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1

1

C120

C120

C96

C96

2

2

10U_0805_6.3V6M

10U_0805_6.3V6M

C141

C141

22U_0805_6.3V6M

22U_0805_6.3V6M

C146

C146

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C86

C86
10U_0805_6.3V6M

10U_0805_6.3V6M

2

+VTT

1

2

+VTT

1

2

1

2

1

2

(Place these capacitors under CPU socket, top layer)

C142

C142
22U_0805_6.3V6M

22U_0805_6.3V6M

C147

C147
22U_0805_6.3V6M

22U_0805_6.3V6M

JCPUG

JCPUG

AT21

VAXG1

AT19

VAXG2

AT18

VAXG3

AT16

VAXG4

AR21

VAXG5

AR19

VAXG6

AR18

VAXG7

AR16

VAXG8

AP21

VAXG9

AP19

VAXG10

AP18

VAXG11

AP16

VAXG12

AN21

VAXG13

AN19

VAXG14

AN18

VAXG15

AN16

VAXG16

AM21

VAXG17

AM19

VAXG18

AM18

VAXG19

AM16

VAXG20

AL21

VAXG21

AL19

VAXG22

AL18

VAXG23

AL16

VAXG24

AK21

VAXG25

AK19

VAXG26

AK18

VAXG27

AK16

VAXG28

AJ21

VAXG29

AJ19

VAXG30

AJ18

VAXG31

AJ16

VAXG32

AH21

VAXG33

AH19

VAXG34

AH18

VAXG35

AH16

VAXG36

J24

VTT1_45

J23

VTT1_46

H25

VTT1_47

K26

VTT1_48

J27

VTT1_49

J26

VTT1_50

J25

VTT1_51

H27

VTT1_52

G28

VTT1_53

G27

VTT1_54

G26

VTT1_55

F26

VTT1_56

E26

VTT1_57

E25

VTT1_58

IC,AUB_CFD_rPGA,R0P9

IC,AUB_CFD_rPGA,R0P9
@

@

GRAPHICS

GRAPHICS

Clarksfield: 5A
Auburndale:3A

FDI PEG & DMI

FDI PEG & DMI

POWER

POWER

Clarksfield: 21A
Auburndale:18A

Clarksfield: 0.6A
Auburndale:0.6A

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8

VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18

VTT0_59
VTT0_60
VTT0_61
VTT0_62

VTT1_63
VTT1_64
VTT1_65
VTT1_66
VTT1_67
VTT1_68

VCCPLL1
VCCPLL2
VCCPLL3

AR22
AT22

AM22
AP22
AN22
AP23
AM23
AP24
AN24

AR25
AT25
AM24

AJ1
AF1
AE7
AE4
AC1
AB7
AB4
Y1
W7
W4
U1
T7
T4
P1
N7
N4
L1
H1

P10
N10
L10
K10

J22
J20
J18
H21
H20
H19

L26
L27
M26

VAXG_SENSE

VSSAXG_SENSE

SENSE

LINES

SENSE

LINES

GFX_VID[0]
GFX_VID[1]
GFX_VID[2]
GFX_VID[3]
GFX_VID[4]
GFX_VID[5]
GFX_VID[6]

GFX_VR_EN

GFX_DPRSLPVR

GFX_IMON

GRAPHICS VIDs

GRAPHICS VIDs

DDR3 - 1.5V RAILS

DDR3 - 1.5V RAILS

1.1V1.8V

1.1V1.8V

1U_0402_6.3V4Z

1U_0402_6.3V4Z

+1.8VS_H_PLL

C151

C151

1U_0402_6.3V4Z

1U_0402_6.3V4Z

47P_0402_50V8J

47P_0402_50V8J

12

12

C97

C97
@

@

D D

C C

B B

A A

47P_0402_50V8J

47P_0402_50V8J

C128

330U_D2_2VM_R6M

330U_D2_2VM_R6M

C128

+GFX_CORE

1

+

+

@

@

2

Co-layout with C128

+GFX_CORE

1

+

+

2

47P_0402_50V8J

47P_0402_50V8J

22U_0805_6.3V6M

22U_0805_6.3V6M

C185

C185
390U_2.5V_M_R10

390U_2.5V_M_R10

470_0805_5%

Q46B

@ Q46B

@

SUSP SUSP

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

R687 1K_0402_5%

R687 1K_0402_5%

C133

C133

+VTT

1

2

1

2

5

VCC_AXG_SENSE 45
VSS_AXG_SENSE 45

GFXVR_VID_0 45
GFXVR_VID_1 45
GFXVR_VID_2 45
GFXVR_VID_3 45
GFXVR_VID_4 45
GFXVR_VID_5 45
GFXVR_VID_6 45

GFXVR_EN 45
GFXVR_DPRSLPVR 45
GFXVR_IMON 45

12

@

@

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1

C134

C134

2

1

1

C135

C135

2

2

1U_0402_6.3V4Z

1U_0402_6.3V4Z

(Place these capacitors under CPU socket Edge, top layer)

C143

C143
10U_0805_10V4K

10U_0805_10V4K

+VTT

C145

C145
22U_0805_6.3V6M

22U_0805_6.3V6M

(Place these capacitors under CPU socket, top layer)

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1

1

1

C152

C152

2

2

2

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

1

1 2

2

3

4

R50 330_0402_5%R50 330_0402_5%

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1

C137

C137

C136

C136

2

1U_0402_6.3V4Z

1U_0402_6.3V4Z

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

C153

C153

C154

C154

C267

@C267

@

10U_0805_10V4K

10U_0805_10V4K

1 2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

1

C138

C138

2

2

1

C155

C155

2

22U_0805_6.3V6M

22U_0805_6.3V6M

C139

C139

22U_0805_6.3V6M

22U_0805_6.3V6M

S

2

S

3

S

4

G

FDS6676AS_SO8

FDS6676AS_SO8

12

1

C472

C472

2

@

@

0.1U_0402_25V6

0.1U_0402_25V6

+1.5V_CPU

1

1

+

+

2

2

12

R71 0_0805_5%R71 0_0805_5%

+1.5V+1.5V_CPU

@Q33

@

8

D

7

D

6

D

5

D

R417
820K_0402_5%

820K_0402_5%

C140

C140
330U_D2E_2.5VM_R9M

330U_D2E_2.5VM_R9M
@

@

+1.8VS

61

@R417

@

C230 0.1U_0402_16V4ZC230 0.1U_0402_16V4Z

1 2

C218 0.1U_0402_16V4ZC218 0.1U_0402_16V4Z

1 2

C205 0.1U_0402_16V4ZC205 0.1U_0402_16V4Z

1 2

C186 0.1U_0402_16V4ZC186 0.1U_0402_16V4Z

1 2

2

JUMP_43X79

JUMP_43X79

2

JUMP_43X79

JUMP_43X79

@

@

R418

R418

1 2

220K_0402_5%

220K_0402_5%

Q46A

@Q46A

@

2

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

PJ30

@PJ30

@

112

PJ31

@PJ31

@

112

Co-layout with C140

390U_2.5V_M_R10

390U_2.5V_M_R10

+VSB

SUSP 36,43

+1.5V_CPU

C217

C217

+1.5V

1

+

+

2

Security Classification

Security Classification

Security Classification

2009/01/23 2010/01/23

2009/01/23 2010/01/23

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/01/23 2010/01/23

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

B

B

B

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

Schematic,LA5321P M/B

Schematic,LA5321P M/B

Schematic,LA5321P M/B

401782

401782

401782

948Monday, January 25, 2010

948Monday, January 25, 2010

948Monday, January 25, 2010

1

D

D

D

of

of

of

5

JCPUI

JCPUI

K27

VSS161

K9

VSS162

K6

VSS163

D D

C C

B B

K3

VSS164

J32

VSS165

J30

VSS166

J21

VSS167

J19

VSS168

H35

VSS169

H32

VSS170

H28

VSS171

H26

VSS172

H24

VSS173

H22

VSS174

H18

VSS175

H15

VSS176

H13

VSS177

H11

VSS178

H8

VSS179

H5

VSS180

H2

VSS181

G34

VSS182

G31

VSS183

G20

VSS184

G9

VSS185

G6

VSS186

G3

VSS187

F30

VSS188

F27

VSS189

F25

VSS190

F22

VSS191

F19

VSS192

F16

VSS193

E35

VSS194

E32

VSS195

E29

VSS196

E24

VSS197

E21

VSS198

E18

VSS199

E13

VSS200

E11

VSS201

E8

VSS202

E5

VSS203

E2

VSS204

D33

VSS205

D30

VSS206

D26

VSS207

D9

VSS208

D6

VSS209

D3

VSS210

C34

VSS211

C32

VSS212

C29

VSS213

C28

VSS214

C24

VSS215

C22

VSS216

C20

VSS217

C19

VSS218

C16

VSS219

B31

VSS220

B25

VSS221

B21

VSS222

B18

VSS223

B17

VSS224

B13

VSS225

B11

VSS226

B8

VSS227

B6

VSS228

B4

VSS229

A29

VSS230

A27

VSS231

A23

VSS232

A9

VSS233

IC,AUB_CFD_rPGA,R0P9

IC,AUB_CFD_rPGA,R0P9
@

@

VSS

VSS

NCTF

NCTF

VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7

AT35
AT1
AR34
B34
B2
B1
A35

H_NCTF1
H_NCTF2

H_NCTF6
H_NCTF7

PADT4PAD
PADT5PAD

PADT6PAD
PADT7PAD

4

JCPUH

JCPUH

AT20

VSS1

AT17

VSS2

AR31

VSS3

AR28

VSS4

AR26

VSS5

AR24

VSS6

AR23

VSS7

AR20

VSS8

AR17

VSS9

AR15

VSS10

AR12

VSS11

AR9

VSS12

AR6

VSS13

AR3

VSS14

AP20

VSS15

AP17

VSS16

AP13

VSS17

AP10

VSS18

AP7

VSS19

AP4

VSS20

AP2

VSS21

AN34

VSS22

AN31

VSS23

AN23

VSS24

AN20

VSS25

AN17

VSS26

AM29

VSS27

AM27

VSS28

AM25

VSS29

AM20

VSS30

AM17

VSS31

AM14

VSS32

AM11

VSS33

AM8

VSS34

AM5

VSS35

AM2

VSS36

AL34

VSS37

AL31

VSS38

AL23

VSS39

AL20

VSS40

AL17

VSS41

AL12

VSS42

AL9

VSS43

AL6

VSS44

AL3

VSS45

AK29

T4
T5

T6
T7

VSS46

AK27

VSS47

AK25

VSS48

AK20

VSS49

AK17

VSS50

AJ31

VSS51

AJ23

VSS52

AJ20

VSS53

AJ17

VSS54

AJ14

VSS55

AJ11

VSS56

AJ8

VSS57

AJ5

VSS58

AJ2

VSS59

AH35

VSS60

AH34

VSS61

AH33

VSS62

AH32

VSS63

AH31

VSS64

AH30

VSS65

AH29

VSS66

AH28

VSS67

AH27

VSS68

AH26

VSS69

AH20

VSS70

AH17

VSS71

AH13

VSS72

AH9

VSS73

AH6

VSS74

AH3

VSS75

AG10

VSS76

AF8

VSS77

AF4

VSS78

AF2

VSS79

AE35

VSS80

IC,AUB_CFD_rPGA,R0P9

IC,AUB_CFD_rPGA,R0P9
@

@

VSS

VSS

VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160

3

AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE6
AD10
AC8
AC4
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
AB6
AA10
Y8
Y4
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
W6
V10
U8
U4
U2
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
T6
R10
P8
P4
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
N6
M10
L35
L32
L29
L8
L5
L2
K34
K33
K30

2

WW41 Recommend not pull down
PCIE2.0 Jitter is over on ES1

R743.01K_0402_1% @R743.01K_0402_1% @

1 2

R753.01K_0402_1% @R753.01K_0402_1% @

1 2

R763.01K_0402_1% @R763.01K_0402_1% @

1 2

Reserve via for test

@

@

0_0402_5%

0_0402_5%

R114

R114

1 2
1 2

R111

R111

0_0402_5%

0_0402_5%

@

@

CFG0 - PCI-Express Configuration Select

*1:Single PEG
0:Bifurcation enabled

CFG3 - PCI-Express Static Lane Reversal

*1 :Normal Operation
0 :Lane Numbers Reversed
15 -> 0, 14 -> 1, ...

CFG4 - Display Port Presence

*1:Disabled; No Physical Display Port
attached to Embedded Display Port
0:Enabled; An external Display Port
device is connected to the Embedded
Display Port

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11

CFG13
CFG14
CFG15
CFG16
CFG17
CFG18

JCPUE

JCPUE

AP25

RSVD1

AL25

RSVD2

AL24

RSVD3

AL22

RSVD4

AJ33

RSVD5

AG9

RSVD6

M27

RSVD7

L28

RSVD8

J17

RSVD9

H17

RSVD10

G25

RSVD11

G17

RSVD12

E31

RSVD13

E30

RSVD14

AM30

CFG[0]

AM28

CFG[1]

AP31

CFG[2]

AL32

CFG[3]

AL30

CFG[4]

AM31

CFG[5]

AN29

CFG[6]

AM32

CFG[7]

AK32

CFG[8]

AK31

CFG[9]

AK28

CFG[10]

AJ28

CFG[11]

AN30

CFG[12]

AN32

CFG[13]

AJ32

CFG[14]

AJ29

CFG[15]

AJ30

CFG[16]

AK30

CFG[17]

H16

RSVD_TP_86

B19

RSVD15

A19

RSVD16

A20

RSVD17

B20

RSVD18

U9

RSVD19

T9

RSVD20

AC9

RSVD21

AB9

RSVD22

C1

RSVD_NCTF_23

A3

RSVD_NCTF_24

J29

RSVD26

J28

RSVD27

A34

RSVD_NCTF_28

A33

RSVD_NCTF_29

C35

RSVD_NCTF_30

B35

RSVD_NCTF_31

IC,AUB_CFD_rPGA,R0P9

IC,AUB_CFD_rPGA,R0P9
@

@

(SA_DIMM_VREF)
(SB_DIMM_VREF)

RSVD32
RSVD33

RSVD34
RSVD35

RSVD36

RSVD_NCTF_37

RSVD38
RSVD39

RSVD_NCTF_40
RSVD_NCTF_41

RSVD_NCTF_42
RSVD_NCTF_43

RSVD45
RSVD46
RSVD47
RSVD48
RSVD49
RSVD50
RSVD51
RSVD52

RSVD53
RSVD_NCTF_54
RSVD_NCTF_55
RSVD_NCTF_56
RSVD_NCTF_57

RSVD58

RSVD_TP_59
RSVD_TP_60

RESERVED

RESERVED

RSVD62

RSVD63

RSVD64

RSVD65

RSVD_TP_66
RSVD_TP_67
RSVD_TP_68
RSVD_TP_69
RSVD_TP_70
RSVD_TP_71
RSVD_TP_72
RSVD_TP_73
RSVD_TP_74
RSVD_TP_75

RSVD_TP_76
RSVD_TP_77
RSVD_TP_78
RSVD_TP_79
RSVD_TP_80
RSVD_TP_81
RSVD_TP_82
RSVD_TP_83
RSVD_TP_84
RSVD_TP_85

KEY

VSS

1

AJ13
AJ12

AH25
AK26

AL26
AR2

AJ26
AJ27

AP1
AT2

AT3
AR1

AL28
AL29
AP30
AP32
AL27
AT31
AT32
AP33
AR33
AT33
AT34
AP35
AR35
AR32

E15
F15
A2

@

@

D15

0_0402_5%

0_0402_5%

C15

R116

R116

1 2

AJ15

1 2

AH15

R115

R115

0_0402_5%

0_0402_5%

@

@

AA5
AA4
R8
AD3
AD2
AA2
AA1
R9
AG7
AE3

V4
V5
N2
AD5
AD7
W3
W2
N3
AE5
AD9

AP34

*:Default

A A

Security Classification

Security Classification

Security Classification

2009/01/23 2010/01/23

2009/01/23 2010/01/23

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/01/23 2010/01/23

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

Schematic,LA5321P M/B

Schematic,LA5321P M/B

Schematic,LA5321P M/B

401782

401782

401782

10 48Monday, January 25, 2010

10 48Monday, January 25, 2010

10 48Monday, January 25, 2010

1

D

D

D

of

of

of

5

+VREF_DQA

1

C157

C157

C156

C156

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

D D

close to JDDRL.1

C C

B B

A A

+3VS

C181

C181

DDR_A_BS27

DDRA_CLK07
DDRA_CLK0#7

DDR_A_BS07

DDR_A_WE#7

DDR_A_CAS#7

DDRA_SCS1#7

1

C182

C182

2

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

1

2

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

R90

R90
10K_0402_5%

10K_0402_5%

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

5

DDR_A_D0
DDR_A_D1

DDR_A_DM0
DDR_A_D2

DDR_A_D3
DDR_A_D8

DDR_A_D9
DDR_A_DQS#1

DDR_A_DQS1
DDR_A_D10

DDR_A_D11
DDR_A_D16

DDR_A_D17
DDR_A_DQS#2

DDR_A_DQS2
DDR_A_D18

DDR_A_D19
DDR_A_D24

DDR_A_D25
DDR_A_DM3
DDR_A_D26

DDR_A_D27

DDR_A_MA12
DDR_A_MA9

DDR_A_MA8
DDR_A_MA5

DDR_A_MA3
DDR_A_MA1

DDR_A_MA10

DDR_A_MA13

DDR_A_D32
DDR_A_D33

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D34
DDR_A_D35

DDR_A_D40
DDR_A_D41

DDR_A_DM5
DDR_A_D42

DDR_A_D43
DDR_A_D48

DDR_A_D49
DDR_A_DQS#6

DDR_A_DQS6
DDR_A_D50

DDR_A_D51
DDR_A_D56

DDR_A_D57
DDR_A_DM7
DDR_A_D58

DDR_A_D59

1 2

R91

R91

10K_0402_5%

10K_0402_5%

+1.5V

+0.75VS

12

JDDRL

JDDRL

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT

GND1
GND2

VREF_CA

127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

205
207

FOX_AS0A626-U2SN-7F_204P

FOX_AS0A626-U2SN-7F_204P
@

@

VSS
DQ4
DQ5
VSS

DQS0#

DQS0

VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

RESET#

VSS
DQ14
DQ15

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

CKE1

VDD

VDD

VDD

VDD

VDD

CK1
CK1#

VDD

BA1

RAS#

VDD

ODT0

VDD

ODT1

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

EVENT#

SDA

SCL

VTT

BOSS1
BOSS2

A15
A14

A11

S0#

A7
A6

A4
A2

A0

NC

4

+1.5V

2

DDR_A_D4

4

DDR_A_D5

6
8

DDR_A_DQS#0

10

DDR_A_DQS0

12
14

DDR_A_D6

16

DDR_A_D7

18
20

DDR_A_D12

22

DDR_A_D13

24
26

DDR_A_DM1

28
30
32

DDR_A_D14

34

DDR_A_D15

36
38

DDR_A_D20

40

DDR_A_D21

42
44

DDR_A_DM2

46
48

DDR_A_D22

50

DDR_A_D23

52
54

DDR_A_D28

56

DDR_A_D29

58
60

DDR_A_DQS#3

62

DDR_A_DQS3

64
66

DDR_A_D30

68

DDR_A_D31

70
72

74
76

DDR_A_MA15

78

DDR_A_MA14

80
82

DDR_A_MA11

84

DDR_A_MA7

86
88

DDR_A_MA6

90

DDR_A_MA4

92
94

DDR_A_MA2

96

DDR_A_MA0

98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206
208

+DDR_VREF_CA_DIMMA

DDR_A_D36
DDR_A_D37

DDR_A_DM4
DDR_A_D38

DDR_A_D39
DDR_A_D44

DDR_A_D45
DDR_A_DQS#5

DDR_A_DQS5
DDR_A_D46

DDR_A_D47
DDR_A_D52

DDR_A_D53
DDR_A_DM6
DDR_A_D54

DDR_A_D55
DDR_A_D60

DDR_A_D61
DDR_A_DQS#7

DDR_A_DQS7
DDR_A_D62

DDR_A_D63

+0.75VS

4

DDR3 SO-DIMM A
Standard Type

+1.5V

12

R83

@R83

@

1K_0402_1%

1K_0402_1%

DDRA_CKE1 7DDRA_CKE07

DDRA_CLK1 7
DDRA_CLK1# 7

DDR_A_BS1 7
DDR_A_RAS# 7

DDRA_SCS0# 7
DDRA_ODT0 7

DDRA_ODT1 7

C161

C161

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

close to JDDRL.126

PM_EXTTS# 5,12

PM_SMBDATA 12,13,17,27
PM_SMBCLK 12,13,17,27

+V_DDR3_DIMM_REF

R89

R89

1 2

0_0402_5%

0_0402_5%

1

1

C162

C162

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Reserve for cost down

C268

C268

390U_2.5V_M_R10

390U_2.5V_M_R10

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SM_DRAMRST# 5,12

+1.5V

3

DDR_A_DQS[0..7]7

DDR_A_DQS#[0..7]7

DDR_A_D[0..63]7

DDR_A_DM[0..7]7

DDR_A_MA[0..15]7

Layout Note:
Place near JDDRL

+1.5V

1

+

+

2

2009/01/23 2010/01/23

2009/01/23 2010/01/23

2009/01/23 2010/01/23

3

@

@

+

+

C163 330U_B2_2.5VM_R15M

C163 330U_B2_2.5VM_R15M

1 2

C166 10U_0805_6.3V6MC166 10U_0805_6.3V6M

1 2

C168 10U_0805_6.3V6MC168 10U_0805_6.3V6M

1 2

C171 10U_0805_6.3V6MC171 10U_0805_6.3V6M

1 2

C174 10U_0805_6.3V6MC174 10U_0805_6.3V6M

1 2

C176 10U_0805_6.3V6MC176 10U_0805_6.3V6M

1 2

C178 10U_0805_6.3V6MC178 10U_0805_6.3V6M

1 2

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

M1 Circuit

1K_0402_1%

1K_0402_1%

1K_0402_1%

1K_0402_1%

Layout Note: Place these 4 Caps near
Command and Control signals of DIMMA

2

+1.5V

12

R79

R79

+V_DDR3_DIMM_REF

12

R81

R81

+1.5V +0.75VS

C164 0.1U_0402_16V4ZC164 0.1U_0402_16V4Z

1 2

C167 0.1U_0402_16V4ZC167 0.1U_0402_16V4Z

1 2

C170 0.1U_0402_16V4ZC170 0.1U_0402_16V4Z

1 2

C173 0.1U_0402_16V4ZC173 0.1U_0402_16V4Z

1 2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

2

Date: Sheet

12

R78 0_0402_5%R78 0_0402_5%

12

R80 0_0402_5%R80 0_0402_5%

Layout Note:
Place near JDDRL1.203 and 204

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Schematic,LA5321P M/B

Schematic,LA5321P M/B

Schematic,LA5321P M/B

401782

401782

401782

1

+VREF_DQB

+VREF_DQA

C165 10U_0805_6.3V6MC165 10U_0805_6.3V6M

1 2

C169 1U_0402_6.3V4ZC169 1U_0402_6.3V4Z

12

C172 1U_0402_6.3V4ZC172 1U_0402_6.3V4Z

12

C175 1U_0402_6.3V4ZC175 1U_0402_6.3V4Z

12

C177 1U_0402_6.3V4ZC177 1U_0402_6.3V4Z

12

11 48Monday, January 25, 2010

11 48Monday, January 25, 2010

11 48Monday, January 25, 2010

1

D

D

D

of

of

of

A

+VREF_DQB

1

2

C183

C183

2.2U_0603_6.3V4Z

1 1

2.2U_0603_6.3V4Z

close to JDDRH.1

2 2

3 3

4 4

DDRB_CKE07

DDR_B_BS27

DDRB_CLK07
DDRB_CLK0#7

DDR_B_WE#7
DDR_B_CAS#7

DDRB_SCS1#7

+3VS

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

1

C207

C207

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C208

C208

2

1

2

C184

C184

0.1U_0402_16V4Z

0.1U_0402_16V4Z

R98

R98
10K_0402_5%

10K_0402_5%

R99

R99

1 2

10K_0402_5%

10K_0402_5%

DDR_B_D0
DDR_B_D1

DDR_B_DM0
DDR_B_D2

DDR_B_D3
DDR_B_D8

DDR_B_D9
DDR_B_DQS#1

DDR_B_DQS1
DDR_B_D10

DDR_B_D11
DDR_B_D16

DDR_B_D17
DDR_B_DQS#2

DDR_B_DQS2
DDR_B_D18

DDR_B_D19
DDR_B_D24

DDR_B_D25
DDR_B_DM3
DDR_B_D26

DDR_B_D27

DDR_B_MA12
DDR_B_MA9

DDR_B_MA8
DDR_B_MA5

DDR_B_MA3
DDR_B_MA1

DDR_B_MA10

DDR_B_MA13

DDR_B_D32
DDR_B_D33

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D34
DDR_B_D35

DDR_B_D40
DDR_B_D41

DDR_B_DM5
DDR_B_D42

DDR_B_D43
DDR_B_D48

DDR_B_D49
DDR_B_DQS#6

DDR_B_DQS6
DDR_B_D50

DDR_B_D51
DDR_B_D56

DDR_B_D57
DDR_B_DM7
DDR_B_D58

DDR_B_D59

1 2

A

+0.75VS

+1.5V

JDDRH

JDDRH

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT

GND1
GND2

VREF_CA

127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

205
207

FOX_AS0A626-UASN-7F_204P

FOX_AS0A626-UASN-7F_204P
@

@

VSS

DQ4

DQ5

VSS

DQS0#

DQS0

VSS

DQ6

DQ7

VSS
DQ12
DQ13

VSS

DM1

RESET#

VSS
DQ14
DQ15

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

CKE1

VDD

VDD

VDD

VDD

VDD

CK1
CK1#

VDD

BA1

RAS#

VDD

ODT0

VDD

ODT1

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

EVENT#

SDA

SCL

VTT

BOSS1
BOSS2

A15
A14

A11

S0#

A7
A6

A4
A2

A0

NC

+1.5V

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206
208

B

DDR_B_D4
DDR_B_D5

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D6
DDR_B_D7

DDR_B_D12
DDR_B_D13

DDR_B_DM1

DDR_B_D14
DDR_B_D15

DDR_B_D20
DDR_B_D21

DDR_B_DM2
DDR_B_D22

DDR_B_D23
DDR_B_D28

DDR_B_D29
DDR_B_DQS#3

DDR_B_DQS3
DDR_B_D30

DDR_B_D31

DDR_B_MA15
DDR_B_MA14

DDR_B_MA11
DDR_B_MA7

DDR_B_MA6
DDR_B_MA4

DDR_B_MA2
DDR_B_MA0

+DDR_VREF_CA_DIMMB
DDR_B_D36

DDR_B_D37
DDR_B_DM4
DDR_B_D38

DDR_B_D39
DDR_B_D44

DDR_B_D45
DDR_B_DQS#5

DDR_B_DQS5
DDR_B_D46

DDR_B_D47
DDR_B_D52

DDR_B_D53
DDR_B_DM6
DDR_B_D54

DDR_B_D55
DDR_B_D60

DDR_B_D61
DDR_B_DQS#7

DDR_B_DQS7
DDR_B_D62

DDR_B_D63

+0.75VS

B

Standard Type
DDR3 SO-DIMM B

SM_DRAMRST# 5,11

DDRB_CKE1 7

DDRB_CLK1 7
DDRB_CLK1# 7

DDR_B_BS1 7
DDR_B_RAS# 7DDR_B_BS07

DDRB_SCS0# 7
DDRB_ODT0 7

DDRB_ODT1 7

R97

R97

1 2

1

2

C188

C188

C187

C187

close to JDDRH.126

PM_EXTTS# 5,11

PM_SMBDATA 11,13,17,27
PM_SMBCLK 11,13,17,27

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+V_DDR3_DIMM_REF

0_0402_5%

0_0402_5%

1

2

C

DDR_B_DQS#[0..7]7

DDR_B_DQS[0..7]7

DDR_B_D[0..63]7

DDR_B_DM[0..7]7

DDR_B_MA[0..15]7

Layout Note:
Place near JDDRH

+1.5V

2009/01/23 2010/01/23

2009/01/23 2010/01/23

2009/01/23 2010/01/23

C

@

@

+

+

C189 330U_B2_2.5VM_R15M

C189 330U_B2_2.5VM_R15M

1 2

C192 10U_0805_6.3V6MC192 10U_0805_6.3V6M

1 2

C194 10U_0805_6.3V6MC194 10U_0805_6.3V6M

1 2

C197 10U_0805_6.3V6MC197 10U_0805_6.3V6M

1 2

C200 10U_0805_6.3V6MC200 10U_0805_6.3V6M

1 2

C202 10U_0805_6.3V6MC202 10U_0805_6.3V6M

1 2

C204 10U_0805_6.3V6MC204 10U_0805_6.3V6M

1 2

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Layout Note: Place these 4 Caps near
Command and Control signals of DIMMB

D

C190 0.1U_0402_16V4ZC190 0.1U_0402_16V4Z

1 2

C193 0.1U_0402_16V4ZC193 0.1U_0402_16V4Z

1 2

C196 0.1U_0402_16V4ZC196 0.1U_0402_16V4Z

1 2

C199 0.1U_0402_16V4ZC199 0.1U_0402_16V4Z

1 2

D

E

Layout Note:
Place near JDDRH.203 and 204

+0.75VS+1.5V

C191 10U_0805_6.3V6MC191 10U_0805_6.3V6M

1 2

C195 1U_0402_6.3V4ZC195 1U_0402_6.3V4Z

12

C198 1U_0402_6.3V4ZC198 1U_0402_6.3V4Z

12

C201 1U_0402_6.3V4ZC201 1U_0402_6.3V4Z

12

C203 1U_0402_6.3V4ZC203 1U_0402_6.3V4Z

12

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

Schematic,LA5321P M/B

Schematic,LA5321P M/B

Schematic,LA5321P M/B

401782

401782

401782

12 48Monday, January 25, 2010

12 48Monday, January 25, 2010

12 48Monday, January 25, 2010

E

of

of

of

D

D

D

A

Clock Generator

1 1

+1.5VS +1.5VS_CK505

R145 0_0402_5%R145 0_0402_5%

CLK_DOT17
CLK_DOT#17

CLK_48M_CR31

2 2

CLK_SATA17
CLK_SATA#17

PCH_CLK_DMI17

PCH_CLK_DMI#17

1 2

R148 0_0402_5%R148 0_0402_5%

1 2

1 2

R390 33_0402_5%R390 33_0402_5%
R149 0_0402_5%R149 0_0402_5%

1 2

R150 0_0402_5%R150 0_0402_5%

1 2

R151 0_0402_5%R151 0_0402_5%

1 2

R152 0_0402_5%R152 0_0402_5%

1 2

B

C

D

E

F

For SED For SED

FBMH1608HM601-T_0603

FBMH1608HM601-T_0603

+3VS +3VS_CK505 +1.05VS +1.05VS_CK505

1 2

R100

R100

R401

R401

0_0603_5%

0_0603_5%

FBMH1608HM601-T_0603

FBMH1608HM601-T_0603

1 2

R126

@ R126

@

For SED

+1.05VS_CK505
+3VS_CK505

CLK_DOT#_R

CLK_48M_CR_R

CLK_SATA_R
CLK_SATA#_R

PCH_CLK_DMI_R
PCH_CLK_DMI#_R

H_STP_CPU#

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C210

C210

C209

C209

2

10U_0805_10V4Z

10U_0805_10V4Z

1 2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C213

C213

C214

C214

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+1.5VS_CK505

U5

U5

1

VDD_USB_48

2

VSS_48M

3

DOT_96

4

DOT_96#

5

VDD_27

6

27MHZ

7

27MHZ_SS

8

USB_48

9

VSS_27M

10

SATA

11

SATA#

12

VSS_SRC

13

SRC_1

14

SRC_1#

15

VDD_SRC_IO

16

CPU_STOP#

33

TGND

RTM890N-631-GRT_QFN32_5X5

RTM890N-631-GRT_QFN32_5X5

1

1

C211

C211

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

C215

C215

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

SA00002XY00

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C212

C212

For SED For SED

1

12

C251

C251
47P_0402_50V8J

2

47P_0402_50V8J

SCL
SDA

REF_0/CPU_SEL

VDD_REF

XTAL_IN

XTAL_OUT

VSS_REF

CKPWRGD/PD#

VDD_CPU

CPU_0

CPU_0#

VSS_CPU

CPU_1

CPU_1#

VDD_CPU_IO

VDD_SRC

+1.05VS_CK505

+3VS_CK505

32
31
30
29
28
27
26
25

24
23
22
21
20
19
18
17

FBMH1608HM601-T_0603

FBMH1608HM601-T_0603

CPU_SELCLK_DOT_R

1 2

CLK_XTAL_IN
CLK_XTAL_OUT

CK_PWRGD

CLK_BCLK_R
CLK_BCLK_R#

+1.5VS_CK505

1 2

R101

R101

R10233_0402_5% R10233_0402_5%

R103 0_0402_5%R103 0_0402_5%

1 2

R104 0_0402_5%R104 0_0402_5%

1 2

10U_0805_10V4Z

10U_0805_10V4Z

1

C219

C219

C220

C220

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

PM_SMBCLK 11,12,17,27

PM_SMBDATA 11,12,17,27

CLK_14M_PCH 17

CLK_XTAL_IN

C223

C223

22P_0402_50V8J

22P_0402_50V8J

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

C221

C221

2

CLK_BCLK 17
CLK_BCLK# 17

CLK_XTAL_OUT

1 2

2

14.31818MHZ_20P_6X1430004201

14.31818MHZ_20P_6X1430004201

1

C222

C222

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Y1

Y1

1

2

12

C252

C252
47P_0402_50V8J

47P_0402_50V8J

Routing the
trace at

2

least 10mil

C224

C224
22P_0402_50V8J

22P_0402_50V8J

1

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

G

+3VS_CK505

12

R110

R110
10K_0402_5%

10K_0402_5%

CK_PWRGD

3

Q35B

Q35B

5

4

Silego Have Internal Pull-Up

H_STP_CPU#

CPU_SEL

IDT Have Internal Pull-Down

(Default)

0 133MHz

1

100MHz 100MHz

H

CLK_ENABLE# 44

+3VS_CK505

R10510K_0402_5% R10510K_0402_5%

12

R11910K_0402_5% @ R11910K_0402_5% @

12

+1.05VS

R10610K_0402_5% R10610K_0402_5%

12

CPU_1/1#CPU_SEL CPU_0/0#

133MHz

For SED

LCD/PANEL BD. Conn.

0.1U_0402_16V4Z

+LCD_VDD

Q1A

Q1A

R112

R112

100K_0402_5%

100K_0402_5%

USB20_N1120

USB20_P1120

12

61

3 3

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

UMA_ENVDD19

4 4

A

R107

R107
150_0603_5%

150_0603_5%

2

5

1 2

+3VS

12

R108

R108
100K_0402_5%

100K_0402_5%

C228

0.1U_0402_16V7K

0.1U_0402_16V7K

1 2

R109 47K_0402_5%R109 47K_0402_5%

3

Q1B

Q1B
2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

4

0.01U_0402_25V7K

0.01U_0402_25V7K

C228

C229

C229

Reserve for EMI request

R93 0_0402_5%R93 0_0402_5%

1 2

L55

@L55

@

1

1

4

4

WCM-2012-900T_0805

WCM-2012-900T_0805
R92 0_0402_5%R92 0_0402_5%

1 2

B

2

2

3

3

2

1

2

1

2

+3VS

G

G

1 3

USB20_N11_R

USB20_P11_R

W=60mils

S

S

Q17

Q17
AO3413_SOT23

AO3413_SOT23

D

D

+LCD_VDD

C

W=60mils

1

C233

C233

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

+5VS_LVDS_CAM

0_0603_5%

0_0603_5%

R388

R388

+5VS

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1 2

LCD_TXOUT0+19
LCD_TXOUT0-19
LCD_TXOUT1+19
LCD_TXOUT1-19
LCD_TXOUT2+19
LCD_TXOUT2-19

LCD_TZOUT0+19
LCD_TZOUT0-19
LCD_TZOUT1+19
LCD_TZOUT1-19
LCD_TZOUT2+19
LCD_TZOUT2-19

BKOFF#33

D

W=20mils

USB20_P11_R
USB20_N11_R

12

R113

R113

10K_0402_5%

10K_0402_5%

2009/01/23 2010/01/23

2009/01/23 2010/01/23

2009/01/23 2010/01/23

0.1U_0402_16V4Z

1 2

C225

C225
JLVDS

JLVDS

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

GMD

GND

ACES_87242-4001-09

ACES_87242-4001-09
@

@

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

E

1
3
5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41

68P_0402_50V8J

68P_0402_50V8J

INVT_PWM_R

+LCDVDD_R

R155 0_0402_5%R155 0_0402_5%

1 2

+LCD_INV

Rated Current MAX:3000mA

1

C234

C234

2

F

+1.5V

12

@

@
C292

C292
47P_0402_50V8J

47P_0402_50V8J

LCD_TXCLK+ 19
LCD_TXCLK- 19

DAC_BRIG 33INT_MIC_R30

LCD_TZCLK+ 19
LCD_TZCLK- 19

LCD_EDID_CLK 19
LCD_EDID_DATA 19

LVDS_SEL 21

L2

L2

FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805

1

C235

C235

0.1U_0402_25V6

0.1U_0402_25V6

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

+LCDVDD_R

1

2

INVT_PWM_R

12

Schematic,LA5321P M/B

Schematic,LA5321P M/B

Schematic,LA5321P M/B

G

1 2

R128 0_0402_5%

R128 0_0402_5%

1 2

R130 0_0402_5%R130 0_0402_5%

B+

680P_0402_50V7K

680P_0402_50V7K

For EMI request

1

C236

C236
680P_0402_50V7K

680P_0402_50V7K

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

401782

401782

401782

1.5A

L1

L1

12

0_0805_5%

0_0805_5%

C226

C226

0.1U_0402_16V4Z

0.1U_0402_16V4Z

@

@

C231

C231

1

2

+3VS

1

2

+LCD_VDD

C227

C227

4.7U_0805_10V4Z

4.7U_0805_10V4Z

INVT_PWM 33
PCH_PWM 19

1

C232

C232

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

13 48Monday, January 25, 2010

13 48Monday, January 25, 2010

13 48Monday, January 25, 2010

of

of

of

H

D

D

D

A

CRT CONNECTOR

B

C

D

E

1

D3

D3

DAN217_SC59

1 1

L3

L3

UMA_CRT_R19

UMA_CRT_G19

UMA_CRT_B19

12

12

R139

R139

R138

R138

150_0402_1%

150_0402_1%

2 2

1 2

C244 0.1U_0402_16V4ZC244 0.1U_0402_16V4Z

UMA_CRT_HSYNC19

UMA_CRT_VSYNC19

3 3

12

R140

R140

150_0402_1%

150_0402_1%

SN74AHCT1G125GW_SOT353-5

SN74AHCT1G125GW_SOT353-5

1

C239

C239

C238

C238

2

2.2P_0402_50V8C

150_0402_1%

150_0402_1%

+CRT_VCC

2.2P_0402_50V8C

1

5

P

4

OE#

A2Y

G

U6

U6

3

+CRT_VCC

5

P

A2Y

SN74AHCT1G125GW_SOT353-5

SN74AHCT1G125GW_SOT353-5

G

3

1 2

NBQ100505T-800Y_0402

NBQ100505T-800Y_0402

L4

L4

1 2

NBQ100505T-800Y_0402

NBQ100505T-800Y_0402

L5

L5

1 2

NBQ100505T-800Y_0402

NBQ100505T-800Y_0402

1

1

C240

C240

2

2

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

R141 10K_0402_5%R141 10K_0402_5%

D_CRT_HSYNC

1

4

OE#

U7

U7

1

C242

C242

C241

C241

2

2.2P_0402_50V8C

2.2P_0402_50V8C

12

1 2

L6 10_0402_5%L6 10_0402_5%

1 2

L7 10_0402_5%L7 10_0402_5%

+3VS

DAN217_SC59
@

@

CRT_R_L

CRT_G_L

CRT_B_L

1

C243

C243

2

2.2P_0402_50V8C

2.2P_0402_50V8C

2

3

1

2

2.2P_0402_50V8C

2.2P_0402_50V8C

C245

C245
@

@

D4

D4

DAN217_SC59

DAN217_SC59

2

@

@

1

C246

C246
@

@

2

10P_0402_50V8J

10P_0402_50V8J

1

3

1

2

1

D5

D5

DAN217_SC59

DAN217_SC59

2

3

@

@

HSYNC

VSYNCD_CRT_VSYNC

10P_0402_50V8J

10P_0402_50V8J

+3VS

+CRT_VCC

+5VS

2
3

CRT_R_L
CRT_DDC_DAT

CRT_G_L
HSYNC

CRT_B_L
VSYNC

CRT_DDC_CLK

+CRT_VCC_R +CRT_VCC

D6

D6

RB491D_SOT23-3

RB491D_SOT23-3

If=1A

F1

F1

1

1.1A_6V_MINISMDC110F-2

1.1A_6V_MINISMDC110F-2

21

6

11

1
7

12

2
8

13

3
9

14

4
10
15

5

ALLTO_C10532-11505-L_15P-T

ALLTO_C10532-11505-L_15P-T
@

@

30mil

0.1U_0402_16V4Z@

0.1U_0402_16V4Z@

JCRT

JCRT

6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

G
G

C237

C237

1

2

16
17

12

R144

R144

0_0402_5%

0_0402_5%

UMA_CRT_DATA19

UMA_CRT_CLK19

C247

C247

33P_0402_50V8K

33P_0402_50V8K

@

@

4 4

A

B

1

2

Q2B

Q2B

4

1

C248

C248
33P_0402_50V8K

33P_0402_50V8K

2

@

@

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

12

R142

R142
0_0402_5%

0_0402_5%

4.7K_0402_5%

4.7K_0402_5%

2

Q2A

Q2A

5

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

61

3

470P_0402_50V8J

470P_0402_50V8J

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C249

C249

R146

R146

@

@

+CRT_VCC

1 2

1 2

1

1

2

2

R147

R147

4.7K_0402_5%

4.7K_0402_5%

CRT_DDC_DAT

CRT_DDC_CLK

C250

C250
470P_0402_50V8J

470P_0402_50V8J
@

@

Compal Secret Data

Compal Secret Data

2009/01/23 2010/01/23

2009/01/23 2010/01/23

2009/01/23 2010/01/23

C

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Schematic,LA5321P M/B

Schematic,LA5321P M/B

Schematic,LA5321P M/B

401782

401782

401782

E

of

14 48Monday, January 25, 2010

of

14 48Monday, January 25, 2010

of

14 48Monday, January 25, 2010

D

D

D

5

D D

UMA_DVI_TXC-

UMA_DVI_TXC+

C C

B B

UMA_DVI_TXD0+

UMA_DVI_TXD0-

UMA_DVI_TXD1-

UMA_DVI_TXD1+

UMA_DVI_TXD2+

UMA_DVI_TXD2-

L8

1

1

4

4

L9

1

1

4

4

L10

L10

1

1

4

4

L11

L11

1

1

4

4

1 2

OCE2012120YZF_0805IHDMI@L8OCE2012120YZF_0805IHDMI@

1 2

1 2

OCE2012120YZF_0805IHDMI@L9OCE2012120YZF_0805IHDMI@

1 2

1 2

OCE2012120YZF_0805IHDMI@

OCE2012120YZF_0805IHDMI@

1 2

1 2

OCE2012120YZF_0805IHDMI@

OCE2012120YZF_0805IHDMI@

1 2

0_0402_5%@

0_0402_5%@

0_0402_5%@

0_0402_5%@

0_0402_5%@

0_0402_5%@

0_0402_5%@

0_0402_5%@

0_0402_5%@

0_0402_5%@

0_0402_5%@

0_0402_5%@

0_0402_5%@

0_0402_5%@

0_0402_5%@

0_0402_5%@

R157

R157

2

3

R173

R173

R175

R175

2

3

R180

R180

R182

R182

2

3

R183

R183

R187

R187

2

3

R188

R188

HDMI_R_CK-

2

3

HDMI_R_CK+

HDMI_R_D0+

2

3

HDMI_R_D0-

HDMI_R_D1-

2

3

HDMI_R_D1+

HDMI_R_D2+

2

3

HDMI_R_D2-

4

10U_0805_10V4Z

10U_0805_10V4Z

R161

R161

PCH_HDMI_HPD

+3VS

10K_0402_5%

10K_0402_5%

@

@

+3VS

12

R189

R189

100K_0402_5%

100K_0402_5%

1 2

R167 0_0402_5%@R167 0_0402_5%@

1 2

R158 0_0402_5%@R158 0_0402_5%@

1 2

R163 0_0402_5%@R163 0_0402_5%@

1 2

R154 0_0402_5%IHDMI@ R154 0_0402_5%IHDMI@

1 2

PCH_HDMI_HPD19,21

UMA_HDMI_DATA19

UMA_HDMI_CLK19

R689

@R689

@

1 2

0_0402_5%

0_0402_5%

R160

R160

3.3K_0402_1% IHDMI@

3.3K_0402_1% IHDMI@

UMA_DVI_TXC+
UMA_DVI_TXC-

UMA_DVI_TXD2+
UMA_DVI_TXD2-

UMA_DVI_TXD1+
UMA_DVI_TXD1-

UMA_DVI_TXD0+
UMA_DVI_TXD0-

C256

C256

IHDMI@

IHDMI@

+3VS

12

+3VS

3

1

2

11
15
21
26
33
40
46

10

13
14

16
17

19
20

22
23

12
18
24
27
31
36
37
43

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C266

C266
IHDMI@

IHDMI@

2

U10

U10

2

VCC3V
VCC3V
VCC3V
VCC3V
VCC3V
VCC3V
VCC3V
VCC3V

3

FUNCTION1

4

FUCNTION2

6

ANALOG1(REXT)

7

HPD_SOURCE

8

SDA_SOURCE

9

SCL_SOURCE

ANALOG2

OUT_D4+
OUT_D4-

OUT_D3+
OUT_D3-

OUT_D2+
OUT_D2-

OUT_D1+
OUT_D1-

1

GND

5

GND
GND
GND
GND
GND
GND
GND
GND
GND

ASM1442 QFN_48P_7X7

ASM1442 QFN_48P_7X7
IHDMI@

IHDMI@

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C257

C257
IHDMI@

IHDMI@

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C258

C258
IHDMI@

IHDMI@

1

C262

C262
IHDMI@

IHDMI@

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C263

C263
IHDMI@

IHDMI@

2

OE*

SCL_SINK
SDA_SINK

HPD_SINK

DDC_EN

FUNCTION3
FUNCTION4

IN_D4+

IN_D4-

IN_D3+

IN_D3-

IN_D2+

IN_D2-

IN_D1+

IN_D1-

THERMAL_PAD

2

1

C261

C261
IHDMI@

IHDMI@

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

OE

25

28
29

HDMI_HPD_R

30
32

34
35

HDMI_TXC+

48

HDMI_TXC-

47

HDMI_TX2+

45

HDMI_TX2-

44

HDMI_TX1+

42

HDMI_TX1-

41

HDMI_TX0+

39

HDMI_TX0-

38

49

1

C260

C260
IHDMI@

IHDMI@

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

IHDMI@

IHDMI@

12

R159 10K_0402_5%

R159 10K_0402_5%
HDMI_SCLK
HDMI_SDATA

R168 4.7K_0402_5%

R168 4.7K_0402_5%

R162 0_0402_5% @R162 0_0402_5% @

R165 0_0402_5% @R165 0_0402_5% @

R166 0_0402_5% IHDMI@R166 0_0402_5% IHDMI@

R164 0_0402_5% @R164 0_0402_5% @

IHDMI@

IHDMI@

1 2

R122 2.2K_0402_5%

R122 2.2K_0402_5%

IHDMI@

IHDMI@

1 2

R123 2.2K_0402_5%

R123 2.2K_0402_5%
@

@

12

R177 10K_0402_5%

R177 10K_0402_5%

1 2
1 2

12

IHDMI@

IHDMI@

12
12

IHDMI@

IHDMI@
C279 0.1U_0402_16V7K

C279 0.1U_0402_16V7K

1 2

C280 0.1U_0402_16V7K

C280 0.1U_0402_16V7K

1 2

IHDMI@

IHDMI@

IHDMI@

IHDMI@

C281 0.1U_0402_16V7K

C281 0.1U_0402_16V7K

1 2

C282 0.1U_0402_16V7K

C282 0.1U_0402_16V7K

1 2

IHDMI@

IHDMI@

IHDMI@

IHDMI@
C283 0.1U_0402_16V7K

C283 0.1U_0402_16V7K

1 2

C284 0.1U_0402_16V7K

C284 0.1U_0402_16V7K

1 2

IHDMI@

IHDMI@

IHDMI@

IHDMI@
C285 0.1U_0402_16V7K

C285 0.1U_0402_16V7K

1 2

C286 0.1U_0402_16V7K

C286 0.1U_0402_16V7K

1 2

IHDMI@

IHDMI@

+HDMI_5V_OUT

+3VS

+3VS

1

+3VS

UMA_HDMI_TXC+ 19
UMA_HDMI_TXC- 19

UMA_HDMI_TX2+ 19
UMA_HDMI_TX2- 19

UMA_HDMI_TX1+ 19
UMA_HDMI_TX1- 19

UMA_HDMI_TX0+ 19
UMA_HDMI_TX0- 19

+5VS

R186

R186
@

@

HDMI_HPD

2

1

1 2

1

C265

C265

0.1U_0402_16V4Z

0.1U_0402_16V4Z

15 48Monday, January 25, 2010

15 48Monday, January 25, 2010

15 48Monday, January 25, 2010

D

D

D

of

of

of

HDMI Connector

PMEG2010AEH_SOD123 IHDMI@

JHDMI

HDMI_HPD

+HDMI_5V_OUT

HDMI_SDATA
HDMI_SCLK

HDMI_R_CK­HDMI_R_CK+

A A

HDMI_R_D0­HDMI_R_D0+

HDMI_R_D1­HDMI_R_D1+

HDMI_R_D2­HDMI_R_D2+

JHDMI

19

HP_DET

18

+5V

17

DDC/CEC_GND

16

SDA

15

SCL

14

Reserved

13

CEC

12

CK-

11

CK_shield

10

CK+

9

D0-

8

D0_shield

7

D0+

6

D1-

5

D1_shield

4

D1+

3

D2-

2

D2_shield

1

D2+

TYCO_1939864-1_19P@

TYCO_1939864-1_19P@

5

GND
GND
GND
GND

20
21
22
23

PMEG2010AEH_SOD123 IHDMI@

2 1

D53

D53

4

F2

IHDMI@F2

IHDMI@

1.1A_6V_MINISMDC110F-2

1.1A_6V_MINISMDC110F-2

2 1

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+HDMI_5V_OUT+5VS

1

C259

C259
IHDMI@

IHDMI@

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

Compal Secret Data

Compal Secret Data

2009/01/23 2010/01/23

2009/01/23 2010/01/23

2009/01/23 2010/01/23

3

Compal Secret Data

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Deciphered Date

Deciphered Date

Deciphered Date

2

C264

C264

@

@

1

74AHCT1G125GW_SOT353-5

74AHCT1G125GW_SOT353-5

1

5

P

A2Y

G

@

@

3

2

OE#

U9

U9

HDMI_HPD_R

4

100K_0402_5%

100K_0402_5%

1 2

R691 0_0402_5%

R691 0_0402_5%

IHDMI@

IHDMI@

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

Schematic,LA5321P M/B

Schematic,LA5321P M/B

Schematic,LA5321P M/B

401782

401782

401782