How it Works
Toshiba
Loading...
A210
User Manual [fr]
190 pgs4.84 Mb0
User Manual
244 pgs4.81 Mb0
User Manual
276 pgs5.21 Mb1
User Manual
186 pgs4.98 Mb0
User Manual
170 pgs4.39 Mb0
User Manual [fr]
180 pgs4.44 Mb0
User Manual
216 pgs5.42 Mb0
Schematics
45 pgs1.07 Mb0

Toshiba A210, A215 Schematics

A
1 1
B
C
D
E
IALAA
2 2
Minnesota 10A/10AG
LA3631P
3 3
REV 1A
Schematic
AMD Turion,Sempron/ATI RX690/RS690MC / ATI SB600
2007-05-04 Rev. 1A
4 4
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2007/5/4 2008/5/4
C
Deciphered Date
Compal Electronics, Inc.
Title
Cover
Size Document Number Rev
IALAA-Minnesota10A LA3631P 1A
B
Monday, May 14, 2007
D
Date: Sheet
145
E
of
A
B
C
D
E
Compal confidential
IALAA Minnesota10A FUNCTION BLOCK DIAGRAM
File Name : IALAA Minnesota10A LA3631P P/N :
Clock Generator
4 4
3 3
ICS951462AGLFT
PAGE 13
TV-OUT Conn.
HDMI Conn.
page 20
Thermal Sensor GMT G781P8F
CPU VID
CRT Conn.
page 15
LVDS Conn
page 27
page 14
VGA Conn
page 15
33MHz (3.3V)
PAGE 6
PAGE 6
PCI
AMD S1 CPU
638 pin
Turion 64 X2 Turion 64 Sempron
PAGE 1,2,3,4,5,6,7
16x16 1000MHZ
ATI-RX/RS690MC
VGA M26P Embeded
465 pin BGA
PAGE 10,11,12
A-Link Express II
x4 PCIE
HT
533/667MHz (1.8V)
Memory Bus
x1 PCI-E
x1 PCI-E
x1 PCI-E
x1 PCI-E
USB 2.0
SO-DIMM x 2(DDRII)
BANK 0,1,2,3
HD DVD
PAGE 24
Mini Card-WLAN
PAGE 24
New Card
PAGE 28
LAN
RTL8111B-1G RTL8101E-10/100M
PAGE 25
480MHz(5V)
PAGE 8,9
RJ-45
PAGE 25
MiniCard w/ 3G (Port 8)
USB Port * 2 (Port 0, 1)
USB Port 0 be debug port.
PAGE 24
PAGE 29
FANController
RTC Battery
DC/DC Interface
Power Buttom
Finger Printer (Port 5)
Int. Camera (Port 7)
PAGE 41
PAGE 22
PAGE 42
PAGE 39
PAGE 29
PAGE 29
ATI-SB600
RealTek WLAN (Port3)
USB/B (Port 6, 2)
PAGE 24
PAGE 29
SATA
PATA
Primary SATA
3.3V,5V
1.5GHz(150MB/s)
Secondary ATA-100 (5V)
SATA HDD0
PAGE 21
IDE ODD
PAGE 28
CardBus/ 5I N1/ 1394 PCI8412-1394/CardBus/5IN1
2 2
PAGE 22, 23
548 pin BGA
PAGE 16,17,18,19
LPC
33MHz (3.3V)
1394-Port
PAGE 22
1 1
CARD BUS SOCKET
PAGE 23
A
5 IN 1 Conn
PAGE 22
Debug Port
PAGE 34
B
Embedded Controller
PS2
Issued Date
PAGE 30
Scan KB
PAGE 33
Int. K/B Matrix
ENE KB926
SPI
BIOS
PAGE 31
Track Pad
PAGE 33
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Azalia
24MHz(3.3V)
HD CODEC ALC268-GR
PAGE 26
MDC w/Rev1.5
PAGE 28
2007/5/4 2008/5/4
C
Deciphered Date
Audio Amplifier
APA2057A
D
PAGE 27
Bluetooth (Port 4)
NewCard (Port 9)
Compal Electronics, Inc.
Title
Black Diagram
Size Document Number Rev
IALAA-Minnesota10A LA3631P 1A
Custom
Monday, May 14, 2007
Date: Sheet
PAGE 29
PAGE 28
DCIN&DETECTOR
BATT CONN/OTP
2.5V/0.9V/1.5V
E
PAGE 36
PAGE 37
CHARGER
PAGE 38
3V/5V/
PAGE 39
1.8V/1.2V
PAGE 40
PAGE 41
CPU_CORE
PAGE 42
245
of
A
B
C
D
E
Rb
0
NC7
SIGNAL
HIGH
LOW
LOW
AD_BID
0.436 V
0.712 V
1.036 V
1.935 V
2.500 V
SLP_S5#STATE
HIGHHIGH
HIGH
HIGH
LOW
LOWLOW
minV
0 V
+VALW
ON
ON
ON
ON
ON
+V
ON
ON
ON
OFF
OFF
AD_BID
0.503 V
0.819 V
1.650 V1.453 V
2.200 V
3.300 V
typV
0 V
+VSSLP_S3#
ON
OFF
OFF
OFF
Clock
ONON
LOW
OFF
OFF
OFF
V
AD_BID
0.289 V0.250 V0.216 V
0.538 V
0.875 V
1.264 V1.185 V
1.759 V
2.341 V
3.300 V
max
0 V
Voltage Rails
S1 S3 S5Power Plane Description
1 1
2 2
VIN B+
+VSB B+ switched power rail ON ON ON +5VALW 5V always on power rail ONONON
+0.9V 0.9V switched power rail OFFON ON
+1.5VS +CPU_COR E Core voltage for CPU +1.2V_HT 1.2VS switched power rail ON
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Adapter power supply (19V) AC or batte ry power rail for power circuit.
3.3V always on power rail+3VALW ON ON ON
1.2V always on power rail+1.2VALW ONON ON
ON ONON
ON+RTC V C C RTC power ON ON
ON OFF OFF+ 5VS 5VS switched power rail ON+3VS 3.3VS switched power rail OFF OFF ON OFF OFF+2.5VS 2.5VS switched power rail ON OFF OFF+1.8VS 1.8VS switched power rail ON OFF OFF1.5VS switched power rail ON
OFF OFF
ONONON
OFF+1.8V 1.8V power rail ON ON
OFFOFF
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
ID Table for AD channel
Vcc Ra
Board ID
0 1 2 3 4 5 6
3.3V +/- 5% 100K +/- 5%
8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5%
External PCI Devices
Device IDSEL # REQ # / GNT # Interrupts
EC SM Bus1 address
3 3
Device
Smart Battery 24C16
HEX 16H A0H
AD20 2/ 2
PIRQE/F/G1394/ CardBus/ 5IN1
EC SM Bus2 address
Address Address
1010 000X b
Device
CPU Thermal-G781P8F VGA Thermal-
HEX 98H
1001 100X b0001 011X b
BTN_ID BOM STURCTUREBTO
0 1 2 3 4 5 6 7
ATi SB600 SM Bus address SM Bus0 address SM Bus1 address
Device
Clock GEN. (ICS951462AGLFT)
DDR DIMM0 DDR DIMM1
4 4
Mini Card-WLAN Mini Card-3G New Card
HEX
A4 A6
A
Address
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2007/5/4 2008/5/4
C
Deciphered Date
Title
Size Document Number Rev
Custom
D
Date: Sheet
Compal Electronics, Inc.
Notes List
IALAA-Minnesota10A LA3631P 1A
Monday, May 14, 2007
345
E
of
5
4
3
2
1
D D
C C
B B
H_CADIP[0..15]<10>
+1.2V_HT
AMD : 49.9 1% ATI : 51 1%
R52 51_0402_1% R51 51_0402_1%
H_CLKIP1<10> H_CLKIN1<10> H_CLKIP0<10> H_CLKIN0<10>
H_CTLIP0<10> H_CTLOP0 <10> H_CTLIN0<10>
H_CADIP[0..15] H_CADIN[0..15]
VLDT=500mA
H_CADIP15 H_CADIN15 H_CADIP14 H_CADIN14 H_CADIP13 H_CADIN13 H_CADIP12 H_CADIN12 H_CADIP11 H_CADIN11 H_CADIP10 H_CADIN10 H_CADIP9 H_CADIN9 H_CADIP8 H_CADIN8 H_CADIP7 H_CADIN7 H_CADIP6 H_CADIN6 H_CADIP5 H_CADIN5 H_CADIP4 H_CADOP4 H_CADIN4 H_CADIP3 H_CADIN3 H_CADIP2 H_CADIN2 H_CADIP1 H_CADIN1 H_CADIP0 H_CADIN0
12 12
H_CTLIP0
+1.2V_HT
D4
VLDT_A3
D3
VLDT_A2
D2
VLDT_A1
D1
VLDT_A0
N5
L0_CADIN_H15
P5
L0_CADIN_L15
M3
L0_CADIN_H14
M4
L0_CADIN_L14
L5
L0_CADIN_H13
M5
L0_CADIN_L13
K3
L0_CADIN_H12
K4
L0_CADIN_L12
H3
L0_CADIN_H11
H4
L0_CADIN_L11
G5
L0_CADIN_H10
H5
L0_CADIN_L10
F3
L0_CADIN_H9
F4
L0_CADIN_L9
E5
L0_CADIN_H8
F5
L0_CADIN_L8
N3
L0_CADIN_H7
N2
L0_CADIN_L7
L1
L0_CADIN_H6
M1
L0_CADIN_L6
L3
L0_CADIN_H5
L2
L0_CADIN_L5
J1
L0_CADIN_H4
K1
L0_CADIN_L4
G1
L0_CADIN_H3
H1
L0_CADIN_L3
G3
L0_CADIN_H2
G2
L0_CADIN_L2
E1
L0_CADIN_H1
F1
L0_CADIN_L1
E3
L0_CADIN_H0
E2
L0_CADIN_L0
J5
L0_CLKIN_H1
K5
L0_CLKIN_L1
J3
L0_CLKIN_H0
J2
L0_CLKIN_L0
P3
L0_CTLIN_H1
P4
L0_CTLIN_L1
N1
L0_CTLIN_H0
P1
L0_CTLIN_L0
FOX_PZ63823-284S-41F
Athlon 64 S1 Processor Socket
JP27A
VLDT_B3 VLDT_B2 VLDT_B1 VLDT_B0
L0_CADOUT_H15
L0_CADOUT_L15
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H0
HTT Interface
L0_CADOUT_L0 L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
AE5 AE4 AE3 AE2
T4 T3 V5 U5 V4 V3 Y5 W5 AB5 AA5 AB4 AB3 AD5 AC5 AD4 AD3 T1 R1 U2 U3 V1 U1 W2 W3 AA2 AA3 AB1 AA1 AC2 AC3 AD1 AC1
Y4 Y3 Y1 W1
T5 R5
R2 R3
H_CADOP[0..15] H_CADON[0..15]
C107 4.7U_0805_10V4Z
H_CADOP15 H_CADON15 H_CADOP14 H_CADON14 H_CADOP13 H_CADON13 H_CADOP12 H_CADON12 H_CADOP11 H_CADON11 H_CADOP10 H_CADON10 H_CADOP9 H_CADON9 H_CADOP8 H_CADON8 H_CADOP7 H_CADON7 H_CADOP6 H_CADON6 H_CADOP5 H_CADON5
H_CADON4 H_CADOP3 H_CADON3 H_CADOP2 H_CADON2 H_CADOP1 H_CADON1 H_CADOP0 H_CADON0
H_CTLOP0 H_CTLON0H_CTLIN0
1 2
H_CLKOP1 <10> H_CLKON1 <10> H_CLKOP0 <10> H_CLKON0 <10>
H_CTLON0 <10>
H_CADOP[0..15] <10> H_CADON[0..15] <10>H_CADIN[0..15]<10>
+1.2V_HT
250 mil
1
C102
4.7U_0805_10V4Z
2
VLDT CAP.
1
C103
4.7U_0805_10V4Z
2
1 2
C497 0.01U_0402_25V4Z@
1 2
C503 0.01U_0402_25V4Z@
1 2
C496 0.01U_0402_25V4Z@
1
C101
0.22U_0603_16V4Z
2
Near CPU Socket
1
2
1
C104
0.22U_0603_16V4Z
C1447 Near H_CADIP/N[2..4] and H_CLKIP/N0 near CPU BOT Side
C1448 Near H_CADIP/N[5..7] and H_CTLIP/N0 near CPU BOT Side
C1449 Near H_CADOP/N[0..1] near CPU BOT Side
C106 180P_0402_50V8J
2
1
2
GND1VCC GND
C112 180P_0402_50V8J
For IALAA Only-­Change Layer Bridge for HOST3 CADOP/N[0..7]
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2007/5/4 2008/5/4
3
Deciphered Date
Title
Size Document Number Rev
Custom
2
Date: Sheet
Compal Electronics, Inc.
S1g1 HT I/F
IALAA-Minnesota10A LA3631P
1A
445Monday, May 14, 2007
1
of
A
B
C
D
E
Processor DDR2 Memory Interface
+1.8V
R91
1K_0402_1%
R90
1K_0402_1%
1 2
1 2
1
2
1
C151
2
0.1U_0402_16V4Z
4 4
Need to link SD000006980
R331
+1.8V
3 3
2 2
1 1
1 2
R335
DDR_CS3_DIMMA#<8> DDR_CS2_DIMMA#<8> DDR_CS1_DIMMA#<8> DDR_CS0_DIMMA#<8>
DDR_CS3_DIMMB#<9> DDR_CS2_DIMMB#<9> DDR_CS1_DIMMB#<9> DDR_CS0_DIMMB#<9>
DDR_CKE1_DIMMB<9> DDR_CKE0_DIMMB<9> DDR_CKE1_DIMMA<8> DDR_CKE0_DIMMA<8>
DDR_A_MA[15..0]<8>
DDR_A_BS#2<8> DDR_A_BS#1<8> DDR_A_BS#0<8>
DDR_A_RAS#<8> DDR_A_CAS#<8> DDR_A_WE#<8>
C156
1000P_0402_25V8J
12
TP2
39.2_0402_1%
39.2_0402_1%
+CPU_M_VREF
+CPU_M_VREF
VTT_SENSE
DDR_CS3_DIMMA# DDR_CS2_DIMMA# DDR_CS1_DIMMA# DDR_CS0_DIMMA#
DDR_CS3_DIMMB# DDR_CS2_DIMMB# DDR_CS1_DIMMB# DDR_CS0_DIMMB#
DDR_CKE1_DIMMB DDR_CKE0_DIMMB DDR_CKE1_DIMMA DDR_CKE0_DIMMA
DDR_A_MA15 DDR_A_MA14 DDR_A_MA13 DDR_A_MA12 DDR_A_MA11 DDR_A_MA10 DDR_A_MA9 DDR_A_MA8 DDR_A_MA7 DDR_A_MA6 DDR_A_MA5 DDR_A_MA4 DDR_A_MA3 DDR_A_MA2 DDR_A_MA1 DDR_A_MA0
DDR_A_BS#2 DDR_A_BS#1 DDR_A_BS#0
DDR_A_RAS# DDR_A_CAS# DDR_A_WE#
M_ZN M_ZP
W17
M_VREF
Y10
VTT_SENSE
AE10
M_ZN
AF10
M_ZP
V19
MA0_CS_L3
J22
MA0_CS_L2
V22
MA0_CS_L1
T19
MA0_CS_L0
Y26
MB0_CS_L3
J24
MB0_CS_L2
W24
MB0_CS_L1
U23
MB0_CS_L0
H26
MB_CKE1
J23
MB_CKE0
J20
MA_CKE1
J21
MA_CKE0
K19
MA_ADD15
K20
MA_ADD14
V24
MA_ADD13
K24
MA_ADD12
L20
MA_ADD11
R19
MA_ADD10
L19
MA_ADD9
L22
MA_ADD8
L21
MA_ADD7
M19
MA_ADD6
M20
MA_ADD5
M24
MA_ADD4
M22
MA_ADD3
N22
MA_ADD2
N21
MA_ADD1
R21
MA_ADD0
K22
MA_BANK2
R20
MA_BANK1
T22
MA_BANK0
T20
MA_RAS_L
U20
MA_CAS_L
U21
MA_WE_L
FOX_PZ63823-284S-41F
Athlon 64 S1 Processor Socket
JP27B
VTT1 VTT2 VTT3 VTT4 VTT5 VTT6 VTT7 VTT8 VTT9
MA0_CLK_H2
MA0_CLK_L2
MA0_CLK_H1
MA0_CLK_L1
MB0_CLK_H2
MB0_CLK_L2
MB0_CLK_H1
MB0_CLK_L1
MB0_ODT1 MB0_ODT0 MA0_ODT1 MA0_ODT0
MB_ADD15 MB_ADD14 MB_ADD13 MB_ADD12 MB_ADD11 MB_ADD10
MB_ADD9
DDRII Cmd/Ctrl//Clk
MB_ADD8 MB_ADD7 MB_ADD6 MB_ADD5 MB_ADD4 MB_ADD3 MB_ADD2 MB_ADD1 MB_ADD0
MB_BANK2 MB_BANK1 MB_BANK0
MB_RAS_L MB_CAS_L
MB_WE_L
D10 C10 B10 AD10 W10 AC10 AB10 AA10 A10
Y16 AA16 E16 F16
AF18 AF17 A17 A18
W23 W26 V20 U19
J25 J26 W25 L23 L25 U25 L24 M26 L26 N23 N24 N25 N26 P24 P26 T24
K26 T26 U26
U24 V26 U22
+0.9V
DDR_A_CLK2 DDR_A_CLK#2 DDR_A_CLK1 DDR_A_CLK#1
DDR_B_CLK2 DDR_B_CLK#2 DDR_B_CLK1 DDR_B_CLK#1
DDR_B_ODT1 DDR_B_ODT0 DDR_A_ODT1 DDR_A_ODT0
DDR_B_MA15 DDR_B_MA14 DDR_B_MA13 DDR_B_MA12 DDR_B_MA11 DDR_B_MA10 DDR_B_MA9 DDR_B_MA8 DDR_B_MA7 DDR_B_MA6 DDR_B_MA5 DDR_B_MA4 DDR_B_MA3 DDR_B_MA2 DDR_B_MA1 DDR_B_MA0
DDR_B_BS#2 DDR_B_BS#1 DDR_B_BS#0
DDR_B_RAS# DDR_B_CAS# DDR_B_WE#
DDR_A_CLK2 <8> DDR_A_CLK#2 <8> DDR_A_CLK1 <8> DDR_A_CLK#1 <8>
DDR_B_CLK2 <9> DDR_B_CLK#2 <9> DDR_B_CLK1 <9> DDR_B_CLK#1 <9>
DDR_B_ODT1 <9> DDR_B_ODT0 <9> DDR_A_ODT1 <8> DDR_A_ODT0 <8>
DDR_B_MA[15..0] <9>
DDR_B_BS#2 <9> DDR_B_BS#1 <9> DDR_B_BS#0 <9>
DDR_B_RAS# <9> DDR_B_CAS# <9> DDR_B_WE# <9>
PLACE CLOSE TO PROCESSOR WITHIN 1.5 INCH
DDR_A_CLK2
DDR_A_CLK#2 DDR_A_CLK1
DDR_A_CLK#1
DDR_B_CLK2
DDR_B_CLK#2 DDR_B_CLK1
DDR_B_CLK#1
DDR_B_D[63..0]<9>
1
C148
1.5P_0402_50V9C
2
1
C150
1.5P_0402_50V9C
2
1
C149
1.5P_0402_50V9C
2
1
C568
1.5P_0402_50V9C
2
DDR_B_DM[7..0]<9> DDR_A_DM[7..0] <8>
DDR_B_DQS7<9> DDR_B_DQS#7<9> DDR_B_DQS6<9> DDR_B_DQS#6<9> DDR_B_DQS5<9> DDR_B_DQS#5<9> DDR_B_DQS4<9> DDR_B_DQS#4<9> DDR_B_DQS3<9> DDR_B_DQS#3<9> DDR_B_DQS2<9> DDR_B_DQS#2<9> DDR_B_DQS1<9> DDR_B_DQS#1<9> DDR_B_DQS0<9> DDR_B_DQS#0<9>
DDR_B_D63 DDR_B_D62 DDR_B_D61 DDR_B_D60 DDR_B_D59 DDR_B_D58 DDR_B_D57 DDR_B_D56 DDR_B_D55 DDR_B_D54 DDR_B_D53 DDR_B_D52 DDR_B_D51 DDR_B_D50 DDR_B_D49 DDR_B_D48 DDR_B_D47 DDR_B_D46 DDR_B_D45 DDR_B_D44 DDR_B_D43 DDR_B_D42 DDR_B_D41 DDR_B_D40 DDR_B_D39 DDR_B_D38 DDR_B_D37 DDR_B_D36 DDR_B_D35 DDR_B_D34 DDR_B_D33 DDR_B_D32 DDR_B_D31 DDR_B_D30 DDR_B_D29 DDR_B_D28 DDR_B_D27 DDR_B_D26 DDR_B_D25 DDR_B_D24 DDR_B_D23 DDR_B_D22 DDR_B_D21 DDR_B_D20 DDR_B_D19 DDR_B_D18 DDR_B_D17 DDR_B_D16 DDR_B_D15 DDR_B_D14 DDR_B_D13 DDR_B_D12 DDR_B_D11 DDR_B_D10 DDR_B_D9 DDR_B_D8 DDR_B_D7 DDR_B_D6 DDR_B_D5 DDR_B_D4 DDR_B_D3 DDR_B_D2 DDR_B_D1 DDR_B_D0
DDR_B_DM7 DDR_B_DM6 DDR_B_DM5 DDR_B_DM4 DDR_B_DM3 DDR_B_DM2 DDR_B_DM1 DDR_B_DM0
DDR_B_DQS7 DDR_B_DQS#7 DDR_B_DQS6 DDR_B_DQS#6 DDR_B_DQS5 DDR_B_DQS#5 DDR_B_DQS4 DDR_B_DQS#4 DDR_B_DQS3 DDR_B_DQS#3 DDR_B_DQS2 DDR_B_DQS#2 DDR_B_DQS1 DDR_B_DQS#1 DDR_B_DQS0 DDR_B_DQS#0
AD11
MB_DATA63
AF11
MB_DATA62
AF14
MB_DATA61
AE14
MB_DATA60
Y11
MB_DATA59
AB11
MB_DATA58
AC12
MB_DATA57
AF13
MB_DATA56
AF15
MB_DATA55
AF16
MB_DATA54
AC18
MB_DATA53
AF19
MB_DATA52
AD14
MB_DATA51
AC14
MB_DATA50
AE18
MB_DATA49
AD18
MB_DATA48
AD20
MB_DATA47
AC20
MB_DATA46
AF23
MB_DATA45
AF24
MB_DATA44
AF20
MB_DATA43
AE20
MB_DATA42
AD22
MB_DATA41
AC22
MB_DATA40
AE25
MB_DATA39
AD26
MB_DATA38
AA25
MB_DATA37
AA26
MB_DATA36
AE24
MB_DATA35
AD24
MB_DATA34
AA23
MB_DATA33
AA24
MB_DATA32
G24
MB_DATA31
G23
MB_DATA30
D26
MB_DATA29
C26
MB_DATA28
G26
MB_DATA27
G25
MB_DATA26
E24
MB_DATA25
E23
MB_DATA24
C24
MB_DATA23
B24
MB_DATA22
C20
MB_DATA21
B20
MB_DATA20
C25
MB_DATA19
D24
MB_DATA18
A21
MB_DATA17
D20
MB_DATA16
D18
MB_DATA15
C18
MB_DATA14
D14
MB_DATA13
C14
MB_DATA12
A20
MB_DATA11
A19
MB_DATA10
A16
MB_DATA9
A15
MB_DATA8
A13
MB_DATA7
D12
MB_DATA6
E11
MB_DATA5
G11
MB_DATA4
B14
MB_DATA3
A14
MB_DATA2
A11
MB_DATA1
C11
MB_DATA0
AD12
MB_DM7
AC16
MB_DM6
AE22
MB_DM5
AB26
MB_DM4
E25
MB_DM3
A22
MB_DM2
B16
MB_DM1
A12
MB_DM0
AF12
MB_DQS_H7
AE12
MB_DQS_L7
AE16
MB_DQS_H6
AD16
MB_DQS_L6
AF21
MB_DQS_H5
AF22
MB_DQS_L5
AC25
MB_DQS_H4
AC26
MB_DQS_L4
F26
MB_DQS_H3
E26
MB_DQS_L3
A24
MB_DQS_H2
A23
MB_DQS_L2
D16
MB_DQS_H1
C16
MB_DQS_L1
C12
MB_DQS_H0
B12
MB_DQS_L0
FOX_PZ63823-284S-41F
Athlon 64 S1 Processor Socket
JP27C
MA_DATA63 MA_DATA62 MA_DATA61 MA_DATA60 MA_DATA59 MA_DATA58 MA_DATA57 MA_DATA56 MA_DATA55 MA_DATA54 MA_DATA53 MA_DATA52 MA_DATA51 MA_DATA50 MA_DATA49 MA_DATA48 MA_DATA47 MA_DATA46 MA_DATA45 MA_DATA44 MA_DATA43 MA_DATA42 MA_DATA41 MA_DATA40 MA_DATA39 MA_DATA38 MA_DATA37 MA_DATA36 MA_DATA35 MA_DATA34 MA_DATA33 MA_DATA32 MA_DATA31 MA_DATA30 MA_DATA29 MA_DATA28 MA_DATA27 MA_DATA26 MA_DATA25 MA_DATA24 MA_DATA23 MA_DATA22 MA_DATA21 MA_DATA20 MA_DATA19 MA_DATA18 MA_DATA17 MA_DATA16 MA_DATA15 MA_DATA14
DDRII Data
MA_DATA13 MA_DATA12 MA_DATA11 MA_DATA10
MA_DATA9 MA_DATA8 MA_DATA7 MA_DATA6 MA_DATA5 MA_DATA4 MA_DATA3 MA_DATA2 MA_DATA1 MA_DATA0
MA_DM7 MA_DM6 MA_DM5 MA_DM4 MA_DM3 MA_DM2 MA_DM1 MA_DM0
MA_DQS_H7
MA_DQS_L7
MA_DQS_H6
MA_DQS_L6
MA_DQS_H5
MA_DQS_L5
MA_DQS_H4
MA_DQS_L4
MA_DQS_H3
MA_DQS_L3
MA_DQS_H2
MA_DQS_L2
MA_DQS_H1
MA_DQS_L1
MA_DQS_H0
MA_DQS_L0
AA12 AB12 AA14 AB14 W11 Y12 AD13 AB13 AD15 AB15 AB17 Y17 Y14 W14 W16 AD17 Y18 AD19 AD21 AB21 AB18 AA18 AA20 Y20 AA22 Y22 W21 W22 AA21 AB22 AB24 Y24 H22 H20 E22 E21 J19 H24 F22 F20 C23 B22 F18 E18 E20 D22 C19 G18 G17 C17 F14 E14 H17 E17 E15 H15 E13 C13 H12 H11 G14 H14 F12 G12
Y13 AB16 Y19 AC24 F24 E19 C15 E12
W12 W13 Y15 W15 AB19 AB20 AD23 AC23 G22 G21 C22 C21 G16 G15 G13 H13
DDR_A_D63 DDR_A_D62 DDR_A_D61 DDR_A_D60 DDR_A_D59 DDR_A_D58 DDR_A_D57 DDR_A_D56 DDR_A_D55 DDR_A_D54 DDR_A_D53 DDR_A_D52 DDR_A_D51 DDR_A_D50 DDR_A_D49 DDR_A_D48 DDR_A_D47 DDR_A_D46 DDR_A_D45 DDR_A_D44 DDR_A_D43 DDR_A_D42 DDR_A_D41 DDR_A_D40 DDR_A_D39 DDR_A_D38 DDR_A_D37 DDR_A_D36 DDR_A_D35 DDR_A_D34 DDR_A_D33 DDR_A_D32 DDR_A_D31 DDR_A_D30 DDR_A_D29 DDR_A_D28 DDR_A_D27 DDR_A_D26 DDR_A_D25 DDR_A_D24 DDR_A_D23 DDR_A_D22 DDR_A_D21 DDR_A_D20 DDR_A_D19 DDR_A_D18 DDR_A_D17 DDR_A_D16 DDR_A_D15 DDR_A_D14 DDR_A_D13 DDR_A_D12 DDR_A_D11 DDR_A_D10 DDR_A_D9 DDR_A_D8 DDR_A_D7 DDR_A_D6 DDR_A_D5 DDR_A_D4 DDR_A_D3 DDR_A_D2 DDR_A_D1 DDR_A_D0
DDR_A_DM7 DDR_A_DM6 DDR_A_DM5 DDR_A_DM4 DDR_A_DM3 DDR_A_DM2 DDR_A_DM1 DDR_A_DM0
DDR_A_DQS7 DDR_A_DQS#7 DDR_A_DQS6 DDR_A_DQS#6 DDR_A_DQS5 DDR_A_DQS#5 DDR_A_DQS4 DDR_A_DQS#4 DDR_A_DQS3 DDR_A_DQS#3 DDR_A_DQS2 DDR_A_DQS#2 DDR_A_DQS1 DDR_A_DQS#1 DDR_A_DQS0 DDR_A_DQS#0
DDR_A_D[63..0] <8>
DDR_A_DQS7 <8> DDR_A_DQS#7 <8> DDR_A_DQS6 <8> DDR_A_DQS#6 <8> DDR_A_DQS5 <8> DDR_A_DQS#5 <8> DDR_A_DQS4 <8> DDR_A_DQS#4 <8> DDR_A_DQS3 <8> DDR_A_DQS#3 <8> DDR_A_DQS2 <8> DDR_A_DQS#2 <8> DDR_A_DQS1 <8> DDR_A_DQS#1 <8> DDR_A_DQS0 <8> DDR_A_DQS#0 <8>
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2007/5/4 2008/5/4
C
Deciphered Date
Title
S1g1 DDRII I/F
Size Document Number Rev
Custom
IALAA-Minnesota10A LA3631P
D
Date: Sheet
545Monday, May 14, 2007
E
of
1A
5
100U_D2_10VM
+2.5VS
C119
A:Need to re-Link "SGN00000200"
R87
H_PWRGD
12
H_PWRGD<16>
D D
680_0402_5%
A:PA_IXP600AD12
LDT_STOP#<11,16>
680_0402_5%
LDT_RST#<16>
680_0402_5%
C C
LDT_STOP# CPU_SIC
R89
1 2
A:PA_IXP600AD12
LDT_RST#
R44
1 2
A:PA_IXP600AD12
CPUCLK0_H<13>
CPUCLK0_L< 13>
+1.8V
R86 510_0402_5%
R48 510_0402_5% R49 300_0402_5% R50 300_0402_5%
Thermal Sensor GMT G781P8F
1
C111
B B
A A
2200P_0402_50V7K
EC_SMB_CK2<15,30> EC_SMB_DA2<15,30>
2
B: Change to GM T G 7 81P8F from DVT.
THERMDA_CPU THERMDC_CPU
U6
2
DXP+
3
DXN-
8
SCLK
7
SDATA
G781P8F_MSOP8
ALERT#
THERM#
VCC
GND
1 6 4 5
4
L16
1 2
FBM_L11_201209_300L_0805
1
+
2
1 2
C547
1 2
C545 3900P_0402_50V7K
CPU_TEST25_H_BYPASSCLK_H
12
CPU_TEST25_L_BYPASSCLK_L
12 12 12
+3VS
1
2
+2.5VDDA
1
C1324.7U_0805_10V4Z
2
+1.2V_HT
3900P_0402_50V7K
12
R333 169_0402_1%
CPU_TEST19_PLLTEST0 CPU_TEST18_PLLTEST1
C105
0.1U_0402_16V4Z
VDDA=300mA
3300P_0402_50V7K
1
1
2
R53 44.2_0402_1% R54 44.2_0402_1%
R53&R54 place them to CPU within 1"
CPU_VCC_SENSE<42> CPU_VSS_SENSE<42>
CPU_CLKIN_SC_P CPU_CLKIN_SC_N
C139
C131
0.22U_0603_16V4Z
2
LDT_RST# H_PWRGD LDT_STOP#
R332 300_0402_5%
1 2 1 2
VDDIOFB_H<40>
CPU_TEST25_H_BYPASSCLK_H CPU_TEST25_L_BYPASSCLK_L CPU_TEST19_PLLTEST0 CPU_TEST18_PLLTEST1
12
TP1
CPU_DBRDY CPU_TMS
CPU_TCK CPU_TRST# CPU_TDI
TP4 TP5 TP6 TP3 TP11
THERMDC_CPU THERMDA_CPU
CPU_DBREQ# CPU_DBRDY CPU_TCK CPU_TMS CPU_TDI CPU_TRST# CPU_TDO
NOTE: HD T TE RM INATION IS REQU IRED FOR REV. Ax SILICON ONLY.
3
CPU_HTREF1 CPU_HTREF0
+1.8V
R77220_0402_5%@
12
F8
VDDA2
F9
VDDA1
B7
RESET_L
A7
PWROK
F10
LDTSTOP_L
AF4
SIC
AF5
SID
P6
HTREF1
R6
HTREF0
F6
VDD_FB_H
E6
VDD_FB_L
W9
VDDIO_FB_H
Y9
VDDIO_FB_L
A9
CLKIN_H
A8
CLKIN_L
G10
DBRDY
AA9
TMS
AC9
TCK
AD9
TRST_L
AF9
TDI
E9
TEST25_H
E8
TEST25_L
G9
TEST19
H10
TEST18
AA7
TEST13
C2
TEST9
D7
TEST17
E7
TEST16
F7
TEST15
C7
TEST14
AC8
TEST12
C3
TEST7
AA6
TEST6
W7
THERMDC
W8
THERMDA
Y6
TEST3
AB6
TEST2
P20
RSVD0
P19
RSVD1
N20
RSVD2
N19
RSVD3
R26
RSVD4
R25
RSVD5
P22
RSVD6
R22
RSVD7
FOX_PZ63823-284S-41F
R75220_0402_5%@
R76220_0402_5%@
12
12
12
R74220_0402_5%@
12
CPU_PRESENT_L
R73220_0402_5%@
JP27D
THERMTRIP_L
PROCHOT_L
VID5 VID4 VID3 VID2 VID1 VID0
PSI_L
DBREQ_L
TDO
TEST29_H
TEST29_L
TEST24 TEST23
MISC
TEST22 TEST21 TEST20
TEST28_H
TEST28_L
TEST27 TEST26 TEST10
TEST8
RSVD8 RSVD9
RSVD10 RSVD11
RSVD12 RSVD13 RSVD14
RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20
2
+1.8V
CPU_THERMTRIP#_R
AF6 AC7
A5 C6 A6 A4 C5 B5
CPU_PRESENT#
AC6 A3
E10
AE9
CPU_TEST29_H_FBCLKOUT_P
C9
CPU_TEST29_L_FBCLKOUT_N
C8
ROUTE AS 80 Ohm DIFFER EN T IAL PAIR PLACE IT CLOSE TO CPU WITHIN 1"
AE7 AD7 AE8 AB8 AF7
J7 H8 AF8 AE6 K8 C4
H16 B18
B3 C1
H6 G6 D5
R24 W18 R23 AA8 H18 H19
1 2
R37 10K_0402_5%
1 2
R38 300_0402_5%
CPU_PROCHOT#_1.8
CPU_DBREQ#
CPU_TDO
TP8 TP9 TP10
CPU_TEST21_SCANEN
TP7
CPU_TEST26_BURNIN#
VID5 <42> VID4 <42> VID3 <42> VID2 <42> VID1 <42> VID0 <42>
+1.8V
TP15
PSI# <42>
HDT Connector
JP9
2
1
4
3
6
5
8
7
10
9
12
11
14
13
16
15
18
17
20
19
22
21
2423 26
SAMTEC_ASP-68200-07
@
HDT_RST#
SN74LVC08APW_TSSOP14
C:Update THERMTRIP# control circuit.
D39
2 1
CH751H-40PT_SOD323-2
B
2
Q10
E
3 1
C
MMBT3904_SOT23-3
R41 10K_0402_5%@
1 2
R43 300_0402_5%
CPU_PROCHOT#_1.8
R88
80.6_0402_1%
1 2
+3VS
14
U20D
11
O
7
12
12
P
A
13
B
G
R35
1 2
0_0402_5% R36
1 2
0_0402_5%
@
B
2
E
3 1
MMBT3904_SOT23-3@
VID1 CPU_PRESENT# CPU_TEST26_BURNIN#
CPU_TEST21_SCANEN
LDT_RST#
+3V_SB
R490
Q11
1 2
C
1
PCIRST# <16,22>
MAINPWON <36,37,39> H_THERMTRIP# <16>
MP:Reserve pull up resistor R490 for H_PROCHOT#
10K_0402_5%
12
@
R42
0_0402_5%
@
R47 300_0402_5% R56 1K_0402_5% R57 300_0402_5%
R55 300_0402_5%
SB_PWRGD <16,30>
1 2 1 2 1 2
1 2
H_PROCHOT# <16>
+1.8V
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2007/5/4 2008/5/4
3
Deciphered Date
Title
Size Document Number Rev
Custom
2
Date: Sheet
Compal Electronics, Inc.
S1g1 CTRL
IALAA-Minnesota10A LA3631P
1A
645Wednesday, May 16, 2007
1
of
5
VDD(+CPU_CORE) decoupling.
+CPU_CORE
D D
1
+
C544
2
45level
820U_E9_2_5V_M_R745@
1
+
C576
820U_E9_2_5V_M_R745@
2
1
+
C560 330U_D2_2.5VY_R9M
2
Near CPU Socket
+CPU_CORE
1
C123 22U_0805_6.3V6M
2
+CPU_CORE
1
C143
0.22U_0603_16V4Z
C C
2
1
C146 22U_0805_6.3V6M
2
1
C138
0.22U_0603_16V4Z
2
1
C125 22U_0805_6.3V6M
2
+CPU_CORE +CPU_CORE
1
C144 22U_0805_6.3V6M
2
1
C129
0.01U_0402_25V4Z
2
VDDIO decoupling.
+1.8V
1
C153 22U_0805_6.3V6M
2
1
C152 22U_0805_6.3V6M
2
Under CPU Socket
B B
+1.8V
1
C163
0.22U_0603_16V4Z
2
+1.8V +1.8V
1
C159
0.01U_0402_25V4Z
2
A A
+1.8V
1
C183
4.7U_0805_10V4Z
2
Between CPU Socket and DIMM
1
C177
0.22U_0603_16V4Z
2
1
C160
0.01U_0402_25V4Z
2
1
C182
4.7U_0805_10V4Z
2
5
+1.8V
1
C155
0.22U_0603_16V4Z
2
1
C164
0.22U_0603_16V4Z
2
180PF Qt'y follow the distance between CPU socket and DIMM0. <2.5inch>
1
C157 180P_0402_50V8J
2
1
C162
4.7U_0805_10V4Z
2
1
C154
0.22U_0603_16V4Z
2
1
C172
0.22U_0603_16V4Z
2
1
C158 180P_0402_50V8J
2
A: Add C165 and C176 to follow AMD Layout review recommand for EMI
1
C161
4.7U_0805_10V4Z
2
4
1
+
C602 330U_D2_2.5VY_R9M
2
1
C122 22U_0805_6.3V6M
2
1
C136 180P_0402_50V8J
2
4
1
C124 22U_0805_6.3V6M
2
Under CPU Socket
1
C165 180P_0402_50V8J
2
1
C: Change to NBO CAP
+
C652 220U_Y_4VM
@
2
1
2
3
+CPU_CORE +CPU_CORE
AC4
VDD1
AD2
VDD2
G4
VDD3
H2
VDD4
J9
VDD5
J11
VDD6
J13
VDD7
K6
VDD8
K10
VDD9
K12
VDD10
K14
VDD11
L4
VDD12
L7
VDD13
L9
VDD14
L11
VDD15
L13
VDD16
M2
VDD17
M6
VDD18
M8
VDD19
M10
VDD20
N7
VDD21
N9
VDD22
N11
VDD23
1
C145 22U_0805_6.3V6M
2
1
C126 22U_0805_6.3V6M
2
1
C142 22U_0805_6.3V6M
2
VTT decoupling.
+0.9V
1
C556
4.7U_0805_10V4Z
2
C176 180P_0402_50V8J
+0.9V
1
C140
4.7U_0805_10V4Z
2
Near CPU Socket Left side.
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
C555
4.7U_0805_10V4Z
2
Near CPU Socket Right side.
1
C137
4.7U_0805_10V4Z
2
1
C548
0.22U_0603_16V4Z
2
1
C133
0.22U_0603_16V4Z
2
2007/5/4 2008/5/4
3
P8
VDD24
P10
VDD25
R4
VDD26
R7
VDD27
R9
VDD28
R11
VDD29
T2
VDD30
T6
VDD31
T8
VDD32
T10
VDD33
T12
VDD34
T14
VDD35
U7
VDD36
U9
VDD37
U11
VDD38
U13
VDD39
V6
VDD40
V8
VDD41
V10
VDD42
FOX_PZ63823-284S-41F
Athlon 64 S1 Processor Socket
+0.9V
1
C: Change to NBO CAP
+
2
1
C549
0.22U_0603_16V4Z
2
1
C134
0.22U_0603_16V4Z
2
Deciphered Date
JP27E
VDD43 VDD44 VDD45 VDD46 VDD47 VDD48 VDD49 VDD50 VDD51 VDD52 VDD53 VDD54
VDDIO1 VDDIO2 VDDIO3 VDDIO4 VDDIO5 VDDIO6 VDDIO7 VDDIO8 VDDIO9
VDDIO10
Power
VDDIO11 VDDIO12 VDDIO13 VDDIO14 VDDIO15 VDDIO16 VDDIO17 VDDIO18 VDDIO19 VDDIO20 VDDIO21 VDDIO22 VDDIO23 VDDIO24 VDDIO25 VDDIO26 VDDIO27
Near Power Supply
C577 220U_Y_4VM
2
V12 V14 W4 Y2 J15 K16 L15 M16 P16 T16 U15 V16
H25 J17 K18 K21 K23 K25 L17 M18 M21 M23 M25 N17 P18 P21 P23 P25 R17 T18 T21 T23 T25 U17 V18 V21 V23 V25 Y25
1
C559 1000P_0402_25V8J
2
1
C130 1000P_0402_25V8J
2
2
+1.8V
1
C554 1000P_0402_25V8J
2
1
C127 1000P_0402_25V8J
2
1
AA4
VSS1
AA11
VSS2
AA13
VSS3
AA15
VSS4
AA17
VSS5
AA19
VSS6
AB2
VSS7
AB7
VSS8
AB9
VSS9
AB23
VSS10
AB25
VSS11
AC11
VSS12
AC13
VSS13
AC15
VSS14
AC17
VSS15
AC19
VSS16
AC21
VSS17
AD6
VSS18
AD8
VSS19
AD25
VSS20
AE11
VSS21
AE13
VSS22
AE15
VSS23
AE17
VSS24
AE19
VSS25
AE21
VSS26
AE23
VSS27
B4
VSS28
B6
VSS29
B8
VSS30
B9
VSS31
B11
VSS32
B13
VSS33
B15
VSS34
B17
VSS35
B19
VSS36
B21
VSS37
B23
VSS38
B25
VSS39
D6
VSS40
D8
VSS41
D9
VSS42
D11
VSS43
D13
VSS44
D15
VSS45
D17
VSS46
D19
VSS47
D21
VSS48
D23
VSS49
D25
VSS50
E4
VSS51
F2
VSS52
F11
VSS53
F13
VSS54
F15
VSS55
F17
VSS56
F19
VSS57
F21
VSS58
F23
VSS59
F25
VSS60
H7
VSS61
H9
VSS62
H21
VSS63
H23
VSS64
J4
VSS65
FOX_PZ63823-284S-41F
Athlon 64 S1 Processor Socket
1
C552 180P_0402_50V8J
2
1
C147 180P_0402_50V8J
2
Title
Size Document Number Rev
Custom
Date: Sheet
Compal Electronics, Inc.
IALAA-Minnesota10A LA3631P
JP27F
J6
VSS66
J8
VSS67
J10
VSS68
J12
VSS69
J14
VSS70
J16
VSS71
J18
VSS72
K2
VSS73
K7
VSS74
K9
VSS75
K11
VSS76
K13
VSS77
K15
VSS78
K17
VSS79
L6
VSS80
L8
VSS81
L10
VSS82
L12
VSS83
L14
VSS84
L16
VSS85
L18
VSS86
M7
VSS87
M9
VSS88
M11
VSS89
M17
VSS90
N4
VSS91
N8
VSS92
N10
VSS93
N16
VSS94
N18
VSS95
P2
VSS96
P7
VSS97
P9
VSS98
P11
VSS99
P17
VSS100
R8
VSS101
R10
Ground
VSS102
R16
VSS103
R18
VSS104
T7
VSS105
T9
VSS106
T11
VSS107
T13
VSS108
T15
VSS109
T17
VSS110
U4
VSS111
U6
VSS112
U8
VSS113
U10
VSS114
U12
VSS115
U14
VSS116
U16
VSS117
U18
VSS118
V2
VSS119
V7
VSS120
V9
VSS121
V11
VSS122
V13
VSS123
V15
VSS124
V17
VSS125
W6
VSS126
Y21
VSS127
Y23
VSS128
N6
VSS129
1
C550 180P_0402_50V8J
2
1
C128 180P_0402_50V8J
2
S1g1 PWR & GND
745Monday, May 14, 2007
1
of
1A
5
DDR_A_D0 DDR_A_D1
DDR_A_DQS#0 DDR_A_DQS0
DDR_A_D2 DDR_A_D3
DDR_A_D8
D D
C C
B B
A A
DDR_CKE0_DIMMA<5> DDR_CS2_DIMMA#<5>
DDR_A_BS#2<5>
DDR_A_BS#0<5> DDR_A_WE#<5>
DDR_A_CAS#<5> DDR_CS1_DIMMA#<5>
DDR_A_ODT1<5>
SMB_CK_DAT0<9,13,17,24,28> SMB_CK_CLK0<9,13,17,24,28>
+3VS
DDR_A_D9 DDR_A_DQS#1
DDR_A_DQS1 DDR_A_D10
DDR_A_D11
DDR_A_D16 DDR_A_D17
DDR_A_DQS#2 DDR_A_DQS2
DDR_A_D18 DDR_A_D19
DDR_A_D24 DDR_A_D25
DDR_A_DM3
DDR_A_D26 DDR_A_D27
DDR_CKE0_DIMMA DDR_CS2_DIMMA#
DDR_A_BS#2 DDR_A_MA12
DDR_A_MA9 DDR_A_MA8
DDR_A_MA5 DDR_A_MA3 DDR_A_MA1
DDR_A_MA10 DDR_A_BS#0 DDR_A_WE#
DDR_A_CAS# DDR_CS1_DIMMA#
DDR_A_ODT1 DDR_A_D32
DDR_A_D33 DDR_A_DQS#4
DDR_A_DQS4 DDR_A_D34
DDR_A_D35 DDR_A_D40
DDR_A_D41 DDR_A_DM5 DDR_A_D42
DDR_A_D43 DDR_A_D48
DDR_A_D49
DDR_A_DQS#6 DDR_A_DQS6
DDR_A_D50 DDR_A_D51
DDR_A_D56 DDR_A_D57
DDR_A_DM7 DDR_A_D58
DDR_A_D59
C237
0.1U_0402_16V4Z
5
+DIMM_VREF +1.8V
JP31
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
DQ11
39
VSS
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
101
A1
103
VDD
105
A10/AP
107
BA0
109
WE#
111
VDD
113
CAS#
115
NC/S1#
117
VDD
119
NC/ODT1
121
VSS
123
DQ32
125
DQ33
127
VSS
129
DQS4#
131
DQS4
133
VSS
135
DQ34
137
DQ35
139
VSS
141
DQ40
143
DQ41
145
VSS
147
DM5
149
VSS
151
DQ42
153
DQ43
155
VSS
157
DQ48
159
DQ49
161
VSS
163
NC,TEST
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SDA
197
SCL
199
1
2
VDDSPD
P-TWO_A5692A-A0G16-N
VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7
VSS DQ12 DQ13
VSS
DM1
VSS
CK0
CK0#
VSS DQ14 DQ15
VSS
VSS DQ20 DQ21
VSS
DM2
VSS DQ22 DQ23
VSS DQ28 DQ29
VSS
DQS3#
DQS3
VSS DQ30 DQ31
VSS
NC/CKE1
VDD
NC/A15 NC/A14
VDD
A11
VDD
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
VSS DQ36 DQ37
VSS
DM4
VSS DQ38 DQ39
VSS DQ44 DQ45
VSS
DQS5#
DQS5
VSS DQ46 DQ47
VSS DQ52 DQ53
VSS
CK1
CK1#
VSS
DM6
VSS DQ54 DQ55
VSS DQ60 DQ61
VSS
DQS7#
DQS7
VSS DQ62 DQ63
VSS
SAO
SA1
4
NC
A7 A6
A4 A2 A0
NC
+1.8V+1.8V
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196
R121 0_0402_5%
198
R123 0_0402_5%
200
DDR_A_D4 DDR_A_D5
DDR_A_DM0 DDR_A_D6
DDR_A_D7 DDR_A_D12
DDR_A_D13 DDR_A_DM1
DDR_A_D14 DDR_A_D15
DDR_A_D20 DDR_A_D21
DDR_A_DM2 DDR_A_D22
DDR_A_D23 DDR_A_D28
DDR_A_D29 DDR_A_DQS#3
DDR_A_DQS3 DDR_A_D30
DDR_A_D31 DDR_CKE1_DIMMA DDR_A_MA15
DDR_A_MA14 DDR_A_MA11
DDR_A_MA7 DDR_A_MA6
DDR_A_MA4 DDR_A_MA2 DDR_A_MA0
DDR_A_BS#1 DDR_A_RAS# DDR_CS0_DIMMA#
DDR_A_ODT0 DDR_A_MA13
DDR_CS3_DIMMA# DDR_A_D36
DDR_A_D37 DDR_A_DM4 DDR_A_D38
DDR_A_D39 DDR_A_D44
DDR_A_D45 DDR_A_DQS#5
DDR_A_DQS5 DDR_A_D46
DDR_A_D47 DDR_A_D52
DDR_A_D53
DDR_A_DM6 DDR_A_D54
DDR_A_D55 DDR_A_D60
DDR_A_D61 DDR_A_DQS#7
DDR_A_DQS7 DDR_A_D62
DDR_A_D63
12 12
Security Classification
DDR_A_CLK1 <5> DDR_A_CLK#1 <5>
DDR_CKE1_DIMMA <5>
DDR_A_BS#1 <5> DDR_A_RAS# <5> DDR_CS0_DIMMA# <5>
DDR_A_ODT0 <5>
DDR_CS3_DIMMA# <5>
DDR_A_CLK2 <5> DDR_A_CLK#2 <5>
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
DDR_A_D[0..63]
DDR_A_DM[0..7] DDR_A_DQS[0..7] DDR_A_MA[0..15]
DDR_A_DQS#[0..7]
2007/5/4 2008/5/4
3
DDR_A_DM[0..7] <5>
DDR_A_DQS[0..7] <5>
DDR_A_MA[0..15] <5>
DDR_A_DQS#[0..7] <5>
1
C243
2
1000P_0402_25V8J
DDR_A_D[0..63] <5>
+1.8V+DIMM_VREF
1
C249
2
1 2
0.1U_0402_16V4Z
1 2
Deciphered Date
R148 1K_0402_1%
R132 1K_0402_1%
2
DDR_A_MA2 DDR_A_MA11 DDR_A_MA6 DDR_A_MA7
B: RP4 swap for Express Card.
DDR_CKE0_DIMMA DDR_CS2_DIMMA# DDR_A_BS#2
DDR_A_MA4 DDR_A_MA0 DDR_A_BS#1 DDR_CS0_DIMMA#
B: RP3 swap for Express Card.
DDR_A_MA12 DDR_A_MA9 DDR_A_MA8 DDR_A_MA5
DDR_A_MA3 DDR_A_MA1 DDR_A_MA10 DDR_A_BS#0
C: RP20 swap for DDR Shielding\.
DDR_A_CAS# DDR_A_WE# DDR_CS1_DIMMA# DDR_A_ODT1
DDR_CS3_DIMMA# DDR_A_ODT0 DDR_A_MA13 DDR_A_RAS#
DDR_A_MA14 DDR_A_MA15 DDR_CKE1_DIMMA
2
1
+0.9V
RP6
18 27 36
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
45
RP4
18 27 36 45
RP7
18 27 36 45
RP3
18 27 36 45
RP21
18 27 36 45
RP20
18 27 36 45
RP5
18 27 36 45
RP8
18 27 36 45
Title
DDRII SO-DIMM 0
Size Document Number Rev
Custom
IALAA-Minnesota10A LA3631P
Date: Sheet
1 2
C238 0.1U_0402_16V4Z
1 2
C204 0.1U_0402_16V4Z
1 2
C290 0.1U_0402_16V4Z
1 2
C655 0.1U_0402_16V4Z
1 2
C274 0.1U_0402_16V4Z
1 2
C654 0.1U_0402_16V4Z
1 2
C196 0.1U_0402_16V4Z
1 2
C244 0.1U_0402_16V4Z
1 2
C254 0.1U_0402_16V4Z
1 2
C199 0.1U_0402_16V4Z
1 2
C232 0.1U_0402_16V4Z
1 2
C213 0.1U_0402_16V4Z
1 2
C185 0.1U_0402_16V4Z
1 2
C218 0.1U_0402_16V4Z
1 2
C293 0.1U_0402_16V4Z
1 2
C258 0.1U_0402_16V4Z
1
845Monday, May 14, 2007
1A
of
+DIMM_VREF
1
C203
2
D D
C C
B B
A A
DDR_CKE0_DIMMB<5> DDR_CS2_DIMMB#<5>
DDR_B_BS#2<5>
DDR_B_BS#0<5> DDR_B_WE#<5>
DDR_B_CAS#<5> DDR_CS1_DIMMB#<5>
DDR_B_ODT1<5>
1000P_0402_25V8J
SMB_CK_DAT0<8,13,17,24,28> SMB_CK_CLK0<8,13,17,24,28>
5
DDR_B_D0 DDR_B_D1
DDR_B_DQS#0 DDR_B_DQS0
DDR_B_D2 DDR_B_D3
DDR_B_D8 DDR_B_D9
DDR_B_DQS#1 DDR_B_DQS1
DDR_B_D10 DDR_B_D11
DDR_B_D16 DDR_B_D17
DDR_B_DQS#2 DDR_B_DQS2
DDR_B_D18 DDR_B_D22 DDR_B_D19
DDR_B_D24 DDR_B_D25
DDR_B_DM3
DDR_B_D26 DDR_B_D27
DDR_CKE0_DIMMB DDR_CS2_DIMMB#
DDR_B_BS#2 DDR_B_MA12
DDR_B_MA9
DDR_B_MA5 DDR_B_MA3 DDR_B_MA1
DDR_B_MA10 DDR_B_BS#0 DDR_B_WE#
DDR_B_CAS# DDR_B_ODT0 DDR_CS1_DIMMB#
DDR_B_ODT1 DDR_B_D32
DDR_B_D33 DDR_B_DQS#4
DDR_B_DQS4 DDR_B_D34
DDR_B_D35 DDR_B_D40
DDR_B_D41 DDR_B_DM5 DDR_B_D42
DDR_B_D43 DDR_B_D47 DDR_B_D48
DDR_B_D49 DDR_B_D53
DDR_B_DQS#6 DDR_B_DQS6
DDR_B_D50 DDR_B_D51 DDR_B_D55
DDR_B_D56 DDR_B_D57
DDR_B_DM7 DDR_B_D58
DDR_B_D59
+3VS
C207
0.1U_0402_16V4Z
5
+1.8V
1
2
JP33
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
DQ11
39
VSS
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
101
A1
103
VDD
105
A10/AP
107
BA0
109
WE#
111
VDD
113
CAS#
115
NC/S1#
117
VDD
119
NC/ODT1
121
VSS
123
DQ32
125
DQ33
127
VSS
129
DQS4#
131
DQS4
133
VSS
135
DQ34
137
DQ35
139
VSS
141
DQ40
143
DQ41
145
VSS
147
DM5
149
VSS
151
DQ42
153
DQ43
155
VSS
157
DQ48
159
DQ49
161
VSS
163
NC,TEST
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SDA
197
SCL
199
VDDSPD
QTC_C111A-052SP31
4
VSS DQ4 DQ5
VSS DM0 VSS DQ6 DQ7 VSS
DQ12 DQ13
VSS DM1 VSS
CK0
CK0#
VSS
DQ14 DQ15
VSS
VSS
DQ20 DQ21
VSS DM2
VSS
DQ22 DQ23
VSS
DQ28 DQ29
VSS
DQS3#
DQS3
VSS
DQ30 DQ31
VSS
NC/CKE1
VDD
NC/A15 NC/A14
VDD
A11
VDD
VDD
BA1
RAS#
S0# VDD
ODT0
NC/A13
VDD VSS
DQ36 DQ37
VSS DM4 VSS
DQ38 DQ39
VSS
DQ44 DQ45
VSS
DQS5#
DQS5
VSS
DQ46 DQ47
VSS
DQ52 DQ53
VSS
CK1
CK1#
VSS DM6 VSS
DQ54 DQ55
VSS
DQ60 DQ61
VSS
DQS7#
DQS7
VSS
DQ62 DQ63
VSS SAO
SA1
4
3
+1.8V
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
42 44 46 48 50
NC
52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92
A7
94
A6
96 98
A4
100
A2
102
A0
104 106 108 110 112 114 116 118 120
NC
122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200
DDR_B_D4 DDR_B_D5
DDR_B_DM0 DDR_B_D6
DDR_B_D7 DDR_B_D12
DDR_B_D13 DDR_B_DM1
DDR_B_D14 DDR_B_D15
DDR_B_D20 DDR_B_D21
DDR_B_DM2
DDR_B_D23 DDR_B_D28
DDR_B_D29 DDR_B_DQS#3
DDR_B_DQS3 DDR_B_D30
DDR_B_D31 DDR_CKE1_DIMMB DDR_B_MA15
DDR_B_MA14 DDR_B_MA11
DDR_B_MA7 DDR_B_MA6DDR_B_MA8
DDR_B_MA4 DDR_B_MA2 DDR_B_MA0
DDR_B_BS#1 DDR_B_RAS# DDR_CS0_DIMMB#
DDR_B_MA13 DDR_CS3_DIMMB# DDR_B_D36
DDR_B_D37 DDR_B_DM4 DDR_B_D38
DDR_B_D39 DDR_B_D44
DDR_B_D45 DDR_B_DQS#5
DDR_B_DQS5 DDR_B_D46
DDR_B_D52
DDR_B_DM6 DDR_B_D54
DDR_B_D60 DDR_B_D61
DDR_B_DQS#7 DDR_B_DQS7
DDR_B_D62 DDR_B_D63
R423 4.7K_0402_5%
1 2
12
R427 0_0402_5%
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DDR_B_D[0..63]
DDR_B_DM[0..7] DDR_B_DQS[0..7] DDR_B_MA[0..15]
DDR_B_DQS#[0..7]
DDR_B_CLK1 <5> DDR_B_CLK#1 <5>
DDR_CKE1_DIMMB <5>
DDR_B_BS#1 <5> DDR_B_RAS# <5> DDR_CS0_DIMMB# <5>
DDR_B_ODT0 <5>
DDR_CS3_DIMMB# <5>
DDR_B_CLK2 <5> DDR_B_CLK#2 <5>
+3VS
2007/5/4 2008/5/4
3
DDR_B_D[0..63] <5>
DDR_B_DM[0..7] <5>
DDR_B_DQS[0..7] <5>
DDR_B_MA[0..15] <5>
DDR_B_DQS#[0..7] <5>
Deciphered Date
2
DDR_B_RAS# DDR_B_BS#1 DDR_B_MA0 DDR_B_MA2
DDR_B_MA11 DDR_B_MA7 DDR_B_MA6 DDR_B_MA4
DDR_CS2_DIMMB# DDR_B_BS#2 DDR_CKE0_DIMMB
DDR_B_MA5 DDR_B_MA8 DDR_B_MA9 DDR_B_MA12
DDR_B_MA3 DDR_B_MA1 DDR_B_MA10 DDR_B_BS#0
DDR_B_WE# DDR_B_CAS# DDR_CS1_DIMMB# DDR_B_ODT1
DDR_CS3_DIMMB# DDR_B_MA13 DDR_B_ODT0 DDR_CS0_DIMMB#
DDR_CKE1_DIMMB DDR_B_MA15 DDR_B_MA14
2
1
RP23
47_0804_8P4R_5%
RP13
47_0804_8P4R_5%
RP10
47_0804_8P4R_5%
RP9
47_0804_8P4R_5%
RP11
47_0804_8P4R_5%
RP12
47_0804_8P4R_5%
RP22
47_0804_8P4R_5%
RP14
47_0804_8P4R_5%
Custom
+0.9V
18 27 36 45
18 27 36 45
18 27 36 45
18 27 36 45
18 27 36 45
18 27 36 45
18 27 36 45
18 27 36 45
Title
DDRII SO-DIMM 1
Size Document Number Rev
IALAA-Minnesota10A LA3631P
Date: Sheet
12
C246 0.1U_0402_16V4Z
1 2
C245 0.1U_0402_16V4Z
12
C261 0.1U_0402_16V4Z
1 2
C267 0.1U_0402_16V4Z
12
C257 0.1U_0402_16V4Z
1 2
C268 0.1U_0402_16V4Z
12
C277 0.1U_0402_16V4Z
1 2
C695 0.1U_0402_16V4Z
12
C222 0.1U_0402_16V4Z
1 2
C241 0.1U_0402_16V4Z
12
C229 0.1U_0402_16V4Z
1 2
C273 0.1U_0402_16V4Z
12
C658 0.1U_0402_16V4Z
1 2
C256 0.1U_0402_16V4Z
12
C215 0.1U_0402_16V4Z
1 2
C235 0.1U_0402_16V4Z
+1.8V
1
1A
945Monday, May 14, 2007
of
5
PCIE_GTX_C_MRX_P[0..15]<15> PCIE_GTX_C_MRX_N[0..15]<15>
PCIE_GTX_C_MRX_P15 PCIE_GTX_C_MRX_N15 PCIE_GTX_C_MRX_P14 PCIE_GTX_C_MRX_N14 PCIE_GTX_C_MRX_P13
D D
C C
B B
PCIE_MRX_C_LANTX_P2<25> PCIE_MRX_C_LANTX_N2<25>
PCIE_MRX_C_WLANTX_P3<24> PCIE_MRX_C_WLANTX_N3<24>
PCIE_GTX_C_MRX_N13 PCIE_GTX_C_MRX_P12 PCIE_GTX_C_MRX_N12 PCIE_GTX_C_MRX_P11 PCIE_GTX_C_MRX_N11 PCIE_GTX_C_MRX_P10 PCIE_GTX_C_MRX_N10 PCIE_GTX_C_MRX_P9 PCIE_GTX_C_MRX_N9 PCIE_GTX_C_MRX_P8 PCIE_GTX_C_MRX_N8 PCIE_GTX_C_MRX_P7 PCIE_GTX_C_MRX_N7 PCIE_GTX_C_MRX_P6 PCIE_GTX_C_MRX_N6 PCIE_GTX_C_MRX_P5 PCIE_GTX_C_MRX_N5 PCIE_GTX_C_MRX_P4 PCIE_GTX_C_MRX_N4 PCIE_GTX_C_MRX_P3 PCIE_GTX_C_MRX_N3 PCIE_GTX_C_MRX_P2 PCIE_GTX_C_MRX_N2 PCIE_GTX_C_MRX_P1 PCIE_GTX_C_MRX_N1 PCIE_GTX_C_MRX_P0 PCIE_GTX_C_MRX_N0
SB_RX2P<16> SB_RX2N<16>
SB_RX3P<16> SB_RX3N<16>
SB_RX0P<16> SB_RX0N<16>
SB_RX1P<16> SB_RX1N<16>
PCIE_GTX_C_MRX_P[0..15] PCIE_GTX_C_MRX_N[0..15]
U5B
G5
GFX_RX0P
G4
GFX_RX0N
J8
GFX_RX1P
J7
GFX_RX1N
J4
GFX_RX2P
J5
GFX_RX2N
L8
GFX_RX3P
L7
GFX_RX3N
L4
GFX_RX4P
L5
GFX_RX4N
M8
GFX_RX5P
M7
GFX_RX5N
M4
GFX_RX6P
M5
GFX_RX6N
P8
GFX_RX7P
P7
GFX_RX7N
P4
GFX_RX8P
P5
GFX_RX8N
R4
GFX_RX9P
R5
GFX_RX9N
R7
GFX_RX10P
R8
GFX_RX10N
U4
GFX_RX11P
U5
GFX_RX11N
W4
GFX_RX12P
W5
GFX_RX12N
Y4
GFX_RX13P
Y5
GFX_RX13N
V9
GFX_RX14P
W9
GFX_RX14N
AB7
GFX_RX15P
AB6
GFX_RX15N
Y7
GPP_RX2P
AA7
GPP_RX2N
AB9
GPP_RX3P
AA9
GPP_RX3N
W11
GPP_RX0P(SB_RX2P)
W12
GPP_RX0N(SB_RX2N)
AA11
GPP_RX1P(SB_RX3P)
AB11
GPP_RX1N(SB_RX3N)
W14
SB_RX0P
W15
SB_RX0N
AB12
SB_RX1P
AA12
SB_RX1N
AA14
PCE_ISET(NC)
AB14
PCE_TXISET(NC)
216MQA6AVA11FG_FCBGA465_RS690MVGAR1@
PART 2 OF 5
PCIE I/F GPP
PCIE I/F SB
GND2 For IALAA Only-­Change Layer Bridge for HOST3 CADOP/N[0..7]
A A
5
4
GFX_TX0P GFX_TX0N GFX_TX1P GFX_TX1N GFX_TX2P GFX_TX2N GFX_TX3P GFX_TX3N GFX_TX4P GFX_TX4N GFX_TX5P GFX_TX5N GFX_TX6P GFX_TX6N GFX_TX7P GFX_TX7N GFX_TX8P GFX_TX8N GFX_TX9P
GFX_TX9N GFX_TX10P GFX_TX10N GFX_TX11P GFX_TX11N GFX_TX12P GFX_TX12N GFX_TX13P
PCIE GFX I/F
GFX_TX13N GFX_TX14P GFX_TX14N GFX_TX15P GFX_TX15N
GPP_TX2P GPP_TX2N
GPP_TX3P GPP_TX3N
GPP_TX0P(SB_TX2P) GPP_TX0N(SB_TX2N)
GPP_TX1P(SB_TX3P) GPP_TX1N(SB_TX3N)
SB_TX0P SB_TX0N
SB_TX1P SB_TX1N
PCE_PCAL(PCE_CALRP)
PCE_NCAL(PCE_CALRN)
1 2
C70 0.01U_0402_25V4Z@
1 2
C69 0.01U_0402_25V4Z@
4
PCIE_MTX_GRX_P15
J1
PCIE_MTX_GRX_N15
H2
PCIE_MTX_GRX_P14
K2
PCIE_MTX_GRX_N14
K1
PCIE_MTX_GRX_P13
K3
PCIE_MTX_GRX_N13
L3
PCIE_MTX_GRX_P12
L1
PCIE_MTX_GRX_N12
L2
PCIE_MTX_GRX_P11
N2
PCIE_MTX_GRX_N11
N1
PCIE_MTX_GRX_P10
P2
PCIE_MTX_GRX_N10
P1
PCIE_MTX_GRX_P9
P3
PCIE_MTX_GRX_N9
R3
PCIE_MTX_GRX_P8
R1
PCIE_MTX_GRX_N8
R2
PCIE_MTX_GRX_P7
T2
PCIE_MTX_GRX_N7
U1
PCIE_MTX_GRX_P6
V2
PCIE_MTX_GRX_N6
V1
PCIE_MTX_GRX_P5
V3
PCIE_MTX_GRX_N5
W3
PCIE_MTX_GRX_P4
W1
PCIE_MTX_GRX_N4
W2
PCIE_MTX_GRX_P3
Y2
PCIE_MTX_GRX_N3
AA1
PCIE_MTX_GRX_P2
AA2
PCIE_MTX_GRX_N2
AB2
PCIE_MTX_GRX_P1
AB1
PCIE_MTX_GRX_N1
AC1
PCIE_MTX_GRX_P0
AE3
PCIE_MTX_GRX_N0
AE4
PCIE_MTX_LANRX_P2
AD4
PCIE_MTX_LANRX_N2
AE5
PCIE_MTX_WLANRX_P3
AD5
PCIE_MTX_WLANRX_N3
AD6
SB_TX2P_C
AD8
SB_TX2N_C
AE8
SB_TX3P_C
AD7
SB_TX3N_C
AE7
SB_TX0P_C
AE9
SB_TX0N_C
AD10
SB_TX1P_C
AC8
SB_TX1N_C
AD9 AD11
AE11
3
PCIE_MTX_C_GRX_P[0..15]
PCIE_MTX_C_GRX_N[0..15]
C99 0.1U_0402_16V7KVGA@
C100 0.1U_0402_16V7KVGA@
1 2
C97 0.1U_0402_16V7KVGA@
1 2
C95 0.1U_0402_16V7KVGA@
1 2
C91 0.1U_0402_16V7KVGA@
1 2
C89 0.1U_0402_16V7KVGA@
1 2
C84 0.1U_0402_16V7KVGA@
1 2
C82 0.1U_0402_16V7KVGA@
1 2
C80 0.1U_0402_16V7KVGA@
1 2
C78 0.1U_0402_16V7KVGA@
1 2
C76 0.1U_0402_16V7KVGA@
1 2
C73 0.1U_0402_16V7KVGA@
1 2
C71 0.1U_0402_16V7KVGA@
1 2
C64 0.1U_0402_16V7KVGA@
1 2
C60 0.1U_0402_16V7KVGA@
1 2
C56 0.1U_0402_16V7KVGA@
1 2
C45 0.1U_0402_16V7KVGA@
1 2
C53 0.1U_0402_16V7K
1 2
C52 0.1U_0402_16V7K
1 2
C44 0.1U_0402_16V7KWLAN@
1 2
C43 0.1U_0402_16V7KWLAN@
1 2 1 2
1 2 1 2
1 2 1 2
1 2 1 2
1 2
C48 0.1U_0402_16V7K C49 0.1U_0402_16V7K
C51 0.1U_0402_16V7K C50 0.1U_0402_16V7K
C40 0.1U_0402_16V7K C39 0.1U_0402_16V7K
C42 0.1U_0402_16V7K C41 0.1U_0402_16V7K
R22 562_0402_1%
1 2
R23 2K_0402_1%
1 2
C1445 Near H_CADOP/N[2..4] and H_CLKOP/N0 near NB TOP Side
C1446 Near H_CADOP/N[5..7] and H_CTLOP/N0 near NB TOP Side
1 2
C98 0.1U_0402_16V7KVGA@
1 2
C96 0.1U_0402_16V7KVGA@
1 2
C94 0.1U_0402_16V7KVGA@
1 2
C90 0.1U_0402_16V7KVGA@
1 2
C88 0.1U_0402_16V7KVGA@
1 2
C83 0.1U_0402_16V7KVGA@
1 2
C81 0.1U_0402_16V7KVGA@
1 2
C79 0.1U_0402_16V7KVGA@
1 2
C77 0.1U_0402_16V7KVGA@
1 2
C74 0.1U_0402_16V7KVGA@
1 2
C72 0.1U_0402_16V7KVGA@
1 2
C68 0.1U_0402_16V7KVGA@
1 2
C63 0.1U_0402_16V7KVGA@
1 2
C59 0.1U_0402_16V7KVGA@
1 2
C46 0.1U_0402_16V7KVGA@
1 2
SB_TX2P <16> SB_TX2N <16>
SB_TX3P <16> SB_TX3N <16>
SB_TX0P <16> SB_TX0N <16>
SB_TX1P <16> SB_TX1N <16>
+VDDA12_PKG2
PCIE_MTX_C_LANRX_P2 <25> PCIE_MTX_C_LANRX_N2 <25>
PCIE_MTX_C_WLANRX_P3 <24>
PCIE_MTX_C_WLANRX_N3 <24>
GND1
H_CLKOP1<4> H_CLKON1<4>
H_CLKOP0<4> H_CLKON0<4>
H_CTLOP0<4> H_CTLON0<4>
R46 49.9_0402_1%
+VDDHT_PKG
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2007/5/4 2008/5/4
3
R40 49.9_0402_1%
PCIE_MTX_C_GRX_P[0..15] <15> PCIE_MTX_C_GRX_N[0..15] <15>
PCIE_MTX_C_GRX_P15 PCIE_MTX_C_GRX_N15 PCIE_MTX_C_GRX_P14 PCIE_MTX_C_GRX_N14 PCIE_MTX_C_GRX_P13 PCIE_MTX_C_GRX_N13 PCIE_MTX_C_GRX_P12 PCIE_MTX_C_GRX_N12 PCIE_MTX_C_GRX_P11 PCIE_MTX_C_GRX_N11 PCIE_MTX_C_GRX_P10 PCIE_MTX_C_GRX_N10 PCIE_MTX_C_GRX_P9 PCIE_MTX_C_GRX_N9 PCIE_MTX_C_GRX_P8 PCIE_MTX_C_GRX_N8 PCIE_MTX_C_GRX_P7 PCIE_MTX_C_GRX_N7 PCIE_MTX_C_GRX_P6 PCIE_MTX_C_GRX_N6 PCIE_MTX_C_GRX_P5 PCIE_MTX_C_GRX_N5 PCIE_MTX_C_GRX_P4 PCIE_MTX_C_GRX_N4 PCIE_MTX_C_GRX_P3 PCIE_MTX_C_GRX_N3 PCIE_MTX_C_GRX_P2 PCIE_MTX_C_GRX_N2 PCIE_MTX_C_GRX_P1 PCIE_MTX_C_GRX_N1 PCIE_MTX_C_GRX_P0 PCIE_MTX_C_GRX_N0
H_CADOP15 H_CADON15 H_CADOP14 H_CADON14 H_CADOP13 H_CADON13 H_CADOP12 H_CADON12 H_CADOP11 H_CADON11 H_CADOP10 H_CADON10
H_CADOP9 H_CADON9 H_CADOP8 H_CADON8
H_CADOP7 H_CADON7 H_CADOP6 H_CADON6 H_CADOP5 H_CADON5 H_CADOP4 H_CADON4 H_CADOP3 H_CADON3 H_CADOP2 H_CADON2 H_CADOP1 H_CADON1 H_CADOP0 H_CADON0
H_CTLON0
1 2 1 2
Deciphered Date
2
H_CADOP[0..15]<4> H_CADON[0..15]<4> H_CADIN[0..15] <4>
U5A
R19
HT_RXCAD15P
R18
HT_RXCAD15N
R21
HT_RXCAD14P
R22
HT_RXCAD14N
U22
HT_RXCAD13P
U21
HT_RXCAD13N
U18
HT_RXCAD12P
U19
HT_RXCAD12N
W19
HT_RXCAD11P
W20
HT_RXCAD11N
AC21
HT_RXCAD10P
AB22
HT_RXCAD10N
AB20
HT_RXCAD9P
AA20
HT_RXCAD9N
AA19
HT_RXCAD8P
Y19
HT_RXCAD8N
T24
HT_RXCAD7P
R25
HT_RXCAD7N
U25
HT_RXCAD6P
U24
HT_RXCAD6N
V23
HT_RXCAD5P
U23
HT_RXCAD5N
V24
HT_RXCAD4P
V25
HT_RXCAD4N
AA25
HT_RXCAD3P
AA24
HT_RXCAD3N
AB23
HT_RXCAD2P
AA23
HT_RXCAD2N
AB24
HT_RXCAD1P
AB25
HT_RXCAD1N
AC24
HT_RXCAD0P
AC25
HT_RXCAD0N
W21
HT_RXCLK1P
W22
HT_RXCLK1N
Y24
HT_RXCLK0P
W25
HT_RXCLK0N
P24
HT_RXCTLP
P25
HT_RXCTLN
A24
HT_RXCALP
C24
HT_RXCALN
216MQA6AVA11FG_FCBGA465_RS690MVGAR1@
2
1
H_CADON[0..15]
PART 1 OF 5
HT_TXCAD15P HT_TXCAD15N HT_TXCAD14P HT_TXCAD14N HT_TXCAD13P HT_TXCAD13N HT_TXCAD12P HT_TXCAD12N HT_TXCAD11P HT_TXCAD11N HT_TXCAD10P HT_TXCAD10N
HT_TXCAD9P HT_TXCAD9N HT_TXCAD8P HT_TXCAD8N
HT_TXCAD7P HT_TXCAD7N HT_TXCAD6P HT_TXCAD6N HT_TXCAD5P HT_TXCAD5N HT_TXCAD4P HT_TXCAD4N HT_TXCAD3P HT_TXCAD3N HT_TXCAD2P HT_TXCAD2N HT_TXCAD1P HT_TXCAD1N HT_TXCAD0P HT_TXCAD0N
HT_TXCLK1P
HT_TXCLK1N
HT_TXCLK0P
HT_TXCLK0N
HT_TXCTLP HT_TXCTLN
HT_TXCALP HT_TXCALN
H_CADIP[0..15]H_CADOP[0..15] H_CADIN[0..15]
P21 P22 P18 P19 M22 M21 M18 M19 L18 L19 G22 G21 J20 J21 F21 F22
N24 N25 L25 M24 K25 K24 J23 K23 G25 H24 F25 F24 E23 F23 E24 E25
L21 L22
J24 J25
H_CTLIP0H_CTLOP0
N23
H_CTLIN0
P23
R39 100_0402_1%
C25 D24
H_CADIP15 H_CADIN15 H_CADIP14 H_CADIN14 H_CADIP13 H_CADIN13 H_CADIP12 H_CADIN12 H_CADIP11 H_CADIN11 H_CADIP10 H_CADIN10
H_CADIP9
H_CADIN9
H_CADIP8
H_CADIN8
H_CADIP7
H_CADIN7
H_CADIP6
H_CADIN6
H_CADIP5
H_CADIN5
H_CADIP4
H_CADIN4
H_CADIP3
H_CADIN3
H_CADIP2
H_CADIN2
H_CADIP1
H_CADIN1
H_CADIP0
H_CADIN0
1 2
H_CADIP[0..15] <4>
H_CLKIP1 <4> H_CLKIN1 <4>
H_CLKIP0 <4> H_CLKIN0 <4>
H_CTLIP0 <4>
H_CTLIN0 <4>
HYPER TRANSPORT I/F
Title
Size Document Number Rev
Custom
Date: Sheet
RX690/RS690MC HT/VMEM
IALAA-Minnesota10A LA3631P
10 45Monday, May 14, 2007
1
of
1A
+1.8VS
1
1
0.1U_0402_16V4Z
+1.8VS +AVDDQ
1 2
MBC1608121YZF_0603
2.2U_0603_6.3V4Z
+1.8VS +NB_PLLVDD
1 2
MBK2012221YZF 0805
2.2U_0603_6.3V4Z
+1.8VS +NB_HTPVDD
1 2
MBC1608121YZF_0603
+1.2V_HT +PLLVDD12
1 2
MBC1608121YZF_0603
L15
2.2U_0603_6.3V4Z
C515
2
2
L12
1
C113
2
GND to A22
L13
1
C114
L52
10U_0805_10V4Z@
1
C522 1U_0402_6.3V4Z
2
2
GND to B10
1
C514
2
1
C117
2
+3VS
R64 4.7K_0402_5%UMA@ R62 4.7K_0402_5%UMA@
1 2
R70 10K_0402_5%
1 2
R63 10K_0402_5%@
POWER PLAY HI: 1.2V LOW: 1.0V Won't Support in IALAA
AVDDI=250mA
C519
2.2U_0603_6.3V4Z
GND to B20
AVDDQ=200mA
1
C523
1U_0402_6.3V4Z
2
PLLVDD18=625mA
+3VS
1 2
R68 24K_0402_5%HDMI@
1 2
R61 24K_0402_5%HDMI@
HTPVDD=200mA
1
C520 1U_0402_6.3V4Z
2
GND to B25
PLLVDD12=70mA
1
C110 1U_0402_6.3V4Z
2
C:Set to UMA@
12 12
UMA_LCD_CLK UMA_LCD_DAT
NB_STRAP_DATA
LDT_STOP#<6,16>
+3VS
FBM-L11-201209-300LMA30T_0805
1 2
R317 150_0402_1%
1 2
R316 150_0402_1%
1 2
R299 150_0402_1%UMA@
1 2
R297 150_0402_1%UMA@
1 2
R295 150_0402_1%UMA@
UMA_CRT_SCL UMA_CRT_SDA
R298 3K_0402_5%@ R301 3K_0402_5%@ R59 3K_0402_5%@ R67 3K_0402_5%@ R60 3K_0402_5%@ R66 3K_0402_5%@
L11
1 2
0.1U_0402_16V4Z
UMA_TV_CRMA UMA_TV_LUMA UMA_CRT_R UMA_CRT_G UMA_CRT_B
UMA_CRT_VSYNC<14> UMA_CRT_HSYNC<14>
UMA_LCD_DAT<15>
+3VS
+1.8VS
+AVDDQ
UMA_TV_CRMA<14> UMA_TV_LUMA<14>
1 2
R300 75_0402_1%@
UMA_CRT_R<14> UMA_CRT_G<14> UMA_CRT_B<14>
R58 715_0402_1%
1 2
UMA_CRT_SCL<14>
UMA_CRT_SDA<14>
+NB_PLLVDD
+NB_HTPVDD
NB_RST#<15,17,24,25,28,30,34>
NB_PWRGD<30>
ALLOW_LDTSTOP<16>
R45 10K_0402_5%
HTREFCLK<13>
R65 10K_0402_5%
NB_REFCLK<13> +PLLVDD12
GFX_PCIE<13>
GFX_PCIE#<13> SBLINKCLK<13>
SBLINKCLK#<13>
12 12 12 12 12 12
BMREQ#<16>
UMA_LCD_CLK<15>
R71 4.7K_0402_5%@ R72 4.7K_0402_5%
1 2
+1.8VS
1 2
B
2
Q12
E
3 1
MMBT3904_SOT23-3
+AVDD
C108
12
NB_STRAP_DATA
R79
10K_0402_5%
C
AVDD=100mA
1
1
2
2
UMA_TV_CRMA UMA_TV_LUMA UMA_TV_COMPS
UMA_CRT_R UMA_CRT_G UMA_CRT_B
UMA_CRT_SCL UMA_CRT_SDA
NB_PWRGD NB_LDTSTOP#
12
12
DFT_GPIO0 DFT_GPIO1 DFT_GPIO2 DFT_GPIO3 DFT_GPIO4 DFT_GPIO5
UMA_LCD_CLK UMA_LCD_DAT
+3VS
12
R69
1K_0402_5%
NB_LDTSTOP#
C115
2.2U_0603_6.3V4Z U5C
B14 B15 B13 A13 H14 G14 D17 E17
A15 B16 C17 C18 B17 A17 A18 B18
E15
TXCLK_LP
D15
TXCLK_LN
H15
TXCLK_UP
G15
TXCLK_UN
D14
LPVDD
E14
LPVSS
A12 B12 C12 C13
A16
LVSSR1
A14
LVSSR3
D12
LVSSR5
C19
LVSSR6
C15
LVSSR7
C16
LVSSR8
F14
LVSSR12
F15
LVSSR13
E12 G12 F12
AD14 AD15 AE15 AD16 AE16 AC17 AD18 AE19 AD19 AE20 AD20 AE21
AD13 AC13 AE13 AE17 AD17
RS690 RS690 only
DFT_GPIO1 DFT_GPIO[4:2] DFT_GPIO5
Bypass the loading of EEPROM straps and use Hardware default values
DEFAULT
I2C Master can load strap values from EEPROM if connected, or use default values if not connected
UMA_TXOUT0+ <15> UMA_TXOUT0- <15> UMA_TXOUT1+ <15> UMA_TXOUT1- <15> UMA_TXOUT2+ <15> UMA_TXOUT2- <15>
UMA_TZOUT0+ <15>
UMA_TZOUT0- <15>
UMA_TZOUT1+ <15>
UMA_TZOUT1- <15>
UMA_TZOUT2+ <15>
UMA_TZOUT2- <15>
UMA_TXCLK+ <15> UMA_TXCLK- <15>
UMA_TZCLK+ <15>
UMA_TZCLK- <15>
+LPVDD
+LVDDR18D +LVDDR33A
LVDS_ENVDD LVDS_ENBKL
PCIE_MTX_DVDRX_P0 PCIE_MTX_DVDRX_N0
PCIE_MRX_C_DVDTX_P0 <24> PCIE_MRX_C_DVDTX_N0 <24>
PCIE_MTX_NEWRX_N1 PCIE_MTX_NEWRX_P1
PCIE_MRX_C_NEWTX_N1 <28> PCIE_MRX_C_NEWTX_P1 <28>
R488 2K_0402_5%
MP:Add R488 and R489 for LCD flash issue
R489 2K_0402_5%
C:Set to DVD@
C409 0.1U_0402_16V7KDVD@
1 2
C414 0.1U_0402_16V7KDVD@
1 2
C62 0.1U_0402_16V7KNEW@
1 2
C61 0.1U_0402_16V7KNEW@
1 2
These pin straps are used to configure PCI-E GPP mode: 111: register defined (register default to Config E)
110: 4-0-0-0-0 Config A 101: 4-4 Config B 100: 4-2-2 Config C 011: 4-2-1-1 Config D 010: 4-1-1-1-1 Config E others: register defined ( register defa ult to Config E)
Deciphered Date
G17
G19
AA15 AB15
B22 C22
H17 A20 B20
A21 A22
C21 C20 D19
E19 F19
B21
A10 B10
B24 B25
C10 C11
C23 B23
B11 A11
C14
C6 A5
B6 A6
C5 B5
C2
F2 E1
G1 G2
D6 D7 C8 C7 B8 A8
B2 A2 B4
B3 C3 A3
PART 3 OF 5
AVDD1 AVDD2 AVSSN1 AVSSN2 AVDDDI AVSSDI
AVDDQ AVSSQ
C Y COMP
RED GREEN BLUE DACVSYNC DACHSYNC
RSET DACSCL
DACSDA PLLVDD(PLLVDD18)
PLLVSS HTPVDD
HTPVSS SYSRESET#
POWERGOOD LDTSTOP# ALLOW_LDTSTOP
HTTSTCLK HTREFCLK
TVCLKIN OSCIN
OSCOUT(PLLVDD12) GFX_CLKP
GFX_CLKN SB_CLKP
SB_CLKN DFT_GPIO0
DFT_GPIO1 DFT_GPIO2 DFT_GPIO3 DFT_GPIO4 DFT_GPIO5
BMREQ# I2C_CLK I2C_DATA THERMALDIODE_P THERMALDIODE_N
TMDS_HPD DDC_DATA TESTMODE STRP_DATA
216MQA6AVA11FG_FCBGA465_RS690MVGAR1@
PULL HIGH (internally pulled high)
PULL LOW
CRT/TVOUT
PLL PWR
PMCLOCKs
MIS.
TXOUT_L0P TXOUT_L0N TXOUT_L1P TXOUT_L1N TXOUT_L2P TXOUT_L2N TXOUT_L3P
TXOUT_L3N TXOUT_U0P
TXOUT_U0N
TXOUT_U1P
TXOUT_U1N
TXOUT_U2P
TXOUT_U2N
TXOUT_U3P
TXOUT_U3N
LVDDR18D_1
LVTM
LVDDR18D_2 LVDDR18A_1(LVDDR33_1) LVDDR18A_2(LVDDR33_2)
LVDS_DIGON
LVDS_BLON LVDS_BLEN
DVO_D0(GPP_TX0P) DVO_D1(GPP_TX0N)
DVO_D2(DEBUG6)
DVO_D3(GPP_RX0P)
DVO_D4(GPP_RX0N)
DVO_D5(DEBUG9)
DVO_D6(DEBUG10)
DVO_D7(GPP_TX1N)
DVO_D8(GPP_TX1P)
DVO_D9(GPP_RX1N)
DVO_D10(GPP_RX1P)
DVO
DVO_D11(DEBUG15)
DVO_VSYNC(DEBUG0)
DVO_DE(DEBUG2) DVO_HSYNC(DEBUG1) DVO_IDCKP(DEBUG14) DVO_IDCKN(DEBUG13)
DFT_GPIO0
Memory side port not available
DEFAULT
Memory side port available
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SE CRET INFO RMATI ON. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2007/5/4 2008/5/4
LVDDR33=180mA
LVDS_ENBKL
1 2
UMA@
NB_PWRGD
LVDS_ENVDD
1 2
UMA@
+LPVDD
1
C504
0.1U_0402_16V4Z
2
GND to E14
+LVDDR18D
C109
0.1U_0402_16V4Z
GND to A14, D12
+LVDDR33A
C505
0.1U_0402_16V4Z
GND to C15
+3VS
14
4
P
A
5
B
G
7
PCIE_MTX_C_DVDRX_P0 <24> PCIE_MTX_C_DVDRX_N0 <24>
MBC1608121YZF_0603
1
C513
2.2U_0603_6.3V4Z
2
1
2
1
2
+3VS
14
1
A
2
B
7
U20B
6
O
SN74LVC08APW_TSSOP14
PCIE_MTX_C_NEWRX_N1 <28> PCIE_MTX_C_NEWRX_P1 <28>
DEFAULT
L50
1 2
MBC1608121YZF_0603
L14
1 2
1
C116
2.2U_0603_6.3V4Z
2
MBC1608121YZF_0603
L54
1 2
1
C537
4.7U_0805_10V4Z
2
C499
0.1U_0402_16V4Z
U20A
P
3
O
G
SN74LVC08APW_TSSOP14
UMA_ENVDD <15>
Enable debug bus via the memory IO pads, if available in the package
use default values
use the memory data bus to output the debug bus
Title
Size Document Number Rev
Custom
Date: Sheet
RX690/RS690MC VIDEO_IF/CLOCK GEN
IALAA-Minnesota10A LA3631P
+1.8VS
+1.8VS
+3VS
UMA_ENBKL <30>
DEFAULT
of
11 45Wednesday, May 16, 2007
1A
5
4
3
2
1
+1.2V_HT
12
+
C57 330U_D2E_2.5VM@ C54 C55
D D
+1.2V_HT +VDDA12
C C
+1.2V_HT
B B
C442 1U_0402_6.3V4Z C456 1U_0402_6.3V4Z C465 1U_0402_6.3V4Z C445 1U_0402_6.3V4Z C432 1U_0402_6.3V4Z
+1.8VS
FBMA-L11-201209-221LMA30T_0805
C448 C493 1U_0402_6.3V4Z
1 2
C470 1U_0402_6.3V4Z
1 2
C490 1U_0402_6.3V4Z
1 2
C486 1U_0402_6.3V4Z
1 2
1 2
C511 2.2U_0603_6.3V4Z C498 0.1U_0402_16V4Z
C433 1U_0402_6.3V4Z C446 1U_0402_6.3V4Z C430 1U_0402_6.3V4Z
1 2
MBC1608121YZF_0603
4.7U_0805_10V4Z
10U_0805_10V4Z 10U_0805_10V4Z
1 2 1 2 1 2 1 2 1 2
C492 1U_0402_6.3V4Z
1 2
C489 1U_0402_6.3V4Z
1 2
L45
12
10U_0805_10V4Z
12
+1.8VS
12 12 12
L49
+3VS
C516
VDDA_12=2.5A
VDDR3=70mA
+NB_VDDPLL
1
2
2
1
GND to F9, G9.
VDD_HT(I/O only)=800mA
VDD_18=2mA
VDDPLL=50mA
C501 1U_0402_6.3V4Z
+VDDA12
+NB_VDDPLL
+VDDHT_PKG +VDDA12_PKG1 +VDDA12_PKG2
+VDDA12_PKG1
1
2
AA17 AB17 AB19 AC18 AC19 AC20 AD21 AD22 AD23 AD24 AE23 AE24 AE25
W17
Y17
AB3 AB4 AC3 AD2 AE1 AE2
D11 E11
AC12 AD12 AE12
D22
AC11
C484
4.7U_0805_10V4Z
U5D
PART 4 OF 5
VDD_HT1 VDD_HT2 VDD_HT3 VDD_HT4 VDD_HT5 VDD_HT6 VDD_HT7 VDD_HT8 VDD_HT9 VDD_HT10 VDD_HT11 VDD_HT12 VDD_HT13 VDD_HT14 VDD_HT15
J14
VDD18_1
J15
VDD18_2 VDDA18_1(VDDA12_13)
VDDA18_2(VDDA12_14) VDDA18_3(VDDA12_15) VDDA18_4(VDDA12_16) VDDA18_5(VDDA12_17) VDDA18_6(VDDA12_18)
U7
VDDA18_7(VDDA12_19) VDDA18_8(VDDA12_20)W7VDDC_14
VDDR3_1 VDDR3_2
VDD_DVO1(VDDR_1) VDD_DVO2(VDDR_2) VDD_DVO3(VDDR_3)
E7
VDDA12(VDDPLL_1)
F7
VDDA12(VDDPLL_2)
F9
VSSA12(VSSPLL_1)
G9
VSSA12(VSSPLL_2) VDDHT_PKG
M1
VDDA12_PKG1 VDDA12_PKG2
216MQA6AVA11FG_FCBGA465_RS690MVGAR1@
POWER
VDDA12_1 VDDA12_2 VDDA12_3 VDDA12_4 VDDA12_5 VDDA12_6 VDDA12_7 VDDA12_8
VDDA12_9 VDDA12_10 VDDA12_11 VDDA12_12
VDDC_1 VDDC_2 VDDC_3 VDDC_4 VDDC_5 VDDC_6 VDDC_7 VDDC_8
VDDC_9 VDDC_10 VDDC_11 VDDC_12 VDDC_13
VDDC_15 VDDC_16 VDDC_17 VDDC_18 VDDC_19 VDDC_20 VDDC_21 VDDC_22 VDDC_23 VDDC_24 VDDC_25 VDDC_26 VDDC_27 VDDC_28 VDDC_29 VDDC_30 VDDC_31 VDDC_32
VDDA_12=2.5A
B1 C1 D1 D2 D3 E2 E3 F4 E6 G7 L9 M9
A4 A7 A9 A19 B9 B19 C9 D9 D20 G20 H11 J11 J19 L11 L13 L15 L17 M12 M14 N11 N13 N15 P12 P14 P17 R11 R13 R15 U11 U12 U14 U15
FBMA-L11-201209-221LMA30T_0805
1
1
C4910.1U_0402_16V4Z
C4800.1U_0402_16V4Z
2
2
1
C4830.1U_0402_16V4Z
2
+VDDA12
+1.2V_HT +NB_VDDC
1
C5100.1U_0402_16V4Z
2
L43
1 2
C447 C58
C521
C500 1U_0402_6.3V4Z
1 2
C441 1U_0402_6.3V4Z
1 2
C453 1U_0402_6.3V4Z
1 2
C512 1U_0402_6.3V4Z
1 2 1 2 1 2
1 2 1 2
VDD_CORE=5A
1
1
C4710.1U_0402_16V4Z
C4790.1U_0402_16V4Z
2
2
1
C4740.1U_0402_16V4Z
2
C506 1U_0402_6.3V4Z C463 1U_0402_6.3V4Z
L41 FBMA-L11-201209-221LMA30T_0805 L44
FBMA-L11-201209-221LMA30T_0805
1
C4850.1U_0402_16V4Z
2
10U_0805_10V4Z 10U_0805_10V4Z
10U_0805_10V4Z
1
1
C5020.1U_0402_16V4Z
C52910U_0805_10V4Z
2
2
+1.2V_HT
330U_D2E_2.5VM
1
C424
1
C53010U_0805_10V4Z
+
2
2
A25 D23 G11
Y23 P11 R24
AE18
M15 G23
M11 M20 M23 M25 N12 N14
P13 P20 P15 R12 R14 R20
W23
Y25
AD25
U20 H25
W24
Y22
AC23
D25 G24
AC14 AC22
R23
AE22
AE14
R17 H23 M17 A23
AC15
M13
AC16
H12
U5E
VSS1
F11
E9
J22 J12
L12 L14 L20 L23
L24
C4
T23 T25
F17
D4
B7
VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23
VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42
VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57
VSS59 VSS60 VSS61 VSS62
PAR 5 OF 5
GROUND
216MQA6AVA11FG_FCBGA465_RS690MVGAR1@
VSSA2 VSSA3 VSSA4 VSSA5 VSSA6 VSSA7 VSSA8
VSSA9 VSSA10 VSSA11
VSSA13 VSSA15
VSSA16 VSSA17 VSSA18 VSSA19 VSSA20 VSSA21 VSSA22
VSSA24 VSSA25 VSSA26 VSSA27 VSSA28
VSSA30 VSSA32
VSSA33 VSSA34 VSSA35 VSSA36 VSSA93 VSSA94 VSSA95 VSSA37 VSSA38 VSSA39 VSSA40 VSSA41 VSSA42 VSSA43 VSSA44 VSSA45 VSSA46 VSSA47 VSSA48 VSSA49 VSSA50 VSSA51
V12 V11 V14 F3 V15 A1 H1 G3 J2 H3
J6 F1
L6 M2 M6 J3 P6 T1 N3
R6 U2 T3 U3 U6
Y1 W6
AC2 Y3 Y9 Y11 Y12 Y14 AA3 R9 AD1 AC5 AC6 AC7 AD3 AC9 AC10 G6 Y15 AC4 P9 AE6 AE10 M3
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2007/5/4 2008/5/4
3
Deciphered Date
Title
Size Document Number Rev
Custom
2
Date: Sheet
RX690/RS690MC Power/GND
IALAA-Minnesota10A LA3631P
12 45Monday, May 14, 2007
1
of
1A
A
B
C
D
E
F
G
H
+3VS
Need to link "SM010007E00"
L57
1 2
CHB2012U121_0805
VDD_48=50mA
L56
1 1
+3VS
+3VS
1 2
MBC1608121YZF_0603
2.2U_0603_6.3V4Z
L58
1 2
MBC1608121YZF_0603
2.2U_0603_6.3V4Z
C588
C599
2
C596
0.1U_0402_16V4Z
1
2
C597
0.1U_0402_16V4Z
1
+3VS_CLK_VDD48
+3VS_CLK_ V DDREF
1
2
1
2
10U_0805_10V4Z@
1
C592
2
+3VS_CLK_VDD48
+3VS_CLK_ V DDREF
+3VS_CLK
1
C590
2
10U_0805_10V4Z
+3VS_CLK
0.1U_0402_16V4Z
C595
VDD_REF=50mA
C603
33P_0402_50V8J
1 2
1 2
C631
33P_0402_50V8J
12
14.31818MHZ_20P_6X1430004201
Y3
R390
1M_0402_5%@
1 2
SMB_CK_CLK0<8,9,17,24,28> SMB_CK_DAT0<8,9,17,24,28>
2 2
+3VS_CLK
1 2
R378 10K_0402_5%
3 3
CLK_RESET
XTALIN_CLK CLK_PCIE_VGA_R
XTALOUT_CLK
CLK_RESET
1 2
R394 475_0402_1%
PLACE CLOSE TO U62 WITHIN 0.5 INCH
EXT CLK FREQUENCY SELECT TABLE(MHZ)
FS2
0 0 0 0 0 1
0 1 0 0 1 1 1 0 0 1 0 1
1 1 1
4 4
CPUFS1
Hi-Z X
180.00
220.00
100.00
133.33
200.00
SRCCLK
[2:1]
100.00
100.00
100.00
100.00
100.00
100.00
HTTFS0 PCI
Hi-Z Hi-Z100.00 Reserved
36.56 73.12
66.66 33.33
66.66 33.33
66.66 33.33 Norma l A T H L O N64 o p er a ti o n
USB
COMMENT
48.00
48.00
48.00
48.00
48.00
48.00
Reserved Reserved Reserved Reserved Reserved
X/6X/3
30.0060.00
48.00
VDD=500mA
1
1
C593
2
2
0.1U_0402_16V4Z
54 14 23 28 44
5
39
2
60 53
15 22 29 45
8
38
1
58
3 4
11 61
9
10
48
FS0 FS1 FS2
0.1U_0402_16V4Z
1
C170
2
U25
VDDCPU VDDSRC VDDSRC VDDSRC VDDSRC VDD48 VDDATIG VDDREF VDDHTT
GNDCPU GNDSRC GNDSRC GNDSRC GNDSRC GND48 GNDATIG GNDREF GNDHTT
X1 X2
RESET_IN# NC
SMBCLK SMBDAT
IREF
ICS951462AGLFT_TSSOP64
0.1U_0402_16V4Z
1
C636
2
0.1U_0402_16V4Z
CPUCLK8T0 CPUCLK8C0 CPUCLK8T1 CPUCLK8C1
ATIGCLKC0 ATIGCLKC1 ATIGCLKC2 ATIGCLKC3
C167
VDDA
GNDA
SRCCLKT6 SRCCLKC6 ATIGCLKT0
ATIGCLKT1 ATIGCLKT2 ATIGCLKT3
SRCCLKT5 SRCCLKC5
SRCCLKT4 SRCCLKC4
SRCCLKT3 SRCCLKC3
SRCCLKT2 SRCCLKC2
SRCCLKT0 SRCCLKC0
SRCCLKT1 SRCCLKC1
SRCCLKT7 SRCCLKC7
CLKREQA# CLKREQB# CLKREQC#
48MHz_1 48MHz_0
FS1/REF1 FS0/REF0 FS2/REF2
HTTCLK0
R104
R108
1
2
0.1U_0402_16V4Z
12
2.2K_0402_5%
12
2.2K_0402_5%
@
0.1U_0402_16V4Z
1
C594
2
50 49
CPUCLK0
56
CPUCLK0#
55 52 51
SBLINKCLK_R
16
SBLINKCLK#_R
17
GFX_PCIE_R
41
GFX_PCIE_R#
40 37 36 35 34 30 31
SBSRCCLK_R
18
SBSRCCLK_R#
19 20
CLK_PCIE_VGA_R#
21 24 25 26 27
CLK_NEW_R
47
CLK_NEW_R#
46
CLK_PCIE_LAN_R
43
CLK_PCIE_LAN_R#
42
CLK_WLAN_R
12
CLK_WLAN_R#
13
CLKREQ_WLAN#
57
CLKREQ_DVD#
32
CLKREQ_NEW#
33
CLK_CBCLKIREF
7
CLK_USB
6
FS1
63
FS0
64
FS2
62
CLK_HTREFCLK
59
12
R105
2.2K_0402_5%
12
R109
2.2K_0402_5%
@
+3VS_CLK
CLK_DVD_R CLK_DVD_R#
+3VS_CLK
12
R106
12
R110
@
VDDA=50mA
1
C171
2
2.2K_0402_5%
2.2K_0402_5%
+3VS_CLK_VDDA
C168
0.1U_0402_16V4Z
R99 47.5_0402_1%
1 2
R100 47.5_0402_1%
1 2
R366 33_0402_5% R365 33_0402_5% R397 33_0402_5% R396 33_0402_5%
R360 33_0402_5% R359 33_0402_5%
R373 33_0402_5%VGA@ R372 33_0402_5%VGA@
C:Set R377 and R376 with DVD@
R377 33_0402_5%DVD@ R376 33_0402_5%DVD@ R404 33_0402_5%NEW@ R403 33_0402_5%NEW@ R402 33_0402_5% R401 33_0402_5% R368 33_0402_5%WLAN@ R367 33_0402_5%WLAN@
R369 FBMA-11-100505-900T R379 33_0402_5%
R95 33_0402_5% R94 33_0402_5% R96 33_0402_5% R97 33_0402_5%
1 2 1 2 1 2 1 2
1 2 1 2 1 2 1 2
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
CLKREQ_WLAN# <24> CLKREQ_DVD# <24> CLKREQ_NEW# <28>
1 2 1 2
1 2 1 2
12
1 2
1
1
C169
2
C179
2
10U_0805_10V4Z
@
SBLINKCLK SBLINKCLK# GFX_PCIE GFX_PCIE# GFX_PCIE
MP:Chg. R369 from 33Ohm to 90Ohm Bead.
HTREFCLK
CLKREQ_WLAN# CLKREQ_DVD# CLKREQ_NEW#
1
2
10U_0805_10V4Z
12
SBSRCCLK
SBSRCCLK# CLK_PCIE_VGA CLK_PCIE_VGA#
CLK_DVD CLK_DVD#
CLK_NEW
CLK_NEW# CLK_PCIE_LAN CLK_PCIE_LAN#
CLK_WLAN
CLK_WLAN#
1 2
R398 100K_0402_5%
1 2
R386 100K_0402_5%
1 2
R395 100K_0402_5%
L17
1 2
MBC1608121YZF_0603
R101 261_0402_1%
SBLINKCLK <11> SBLINKCLK# <11> GFX_PCIE <11> GFX_PCIE# <11>
SBSRCCLK <16> SBSRCCLK# <16> CLK_PCIE_VGA <15> CLK_PCIE_VGA# <15>
CLK_DVD <24> CLK_DVD# <24>
CLK_NEW <28> CLK_NEW# <28> CLK_PCIE_LAN <25> CLK_PCIE_LAN# <25>
CLK_WLAN <24> CLK_W LAN# <24>
C:Set R370 and R371 with DVD@
CLK_48M_CB <22> USBCLK_EXT <17>
CLK_14M_SIO <34> SB_OSC_INT <17>
NB_REFCLK <11>
HTREFCLK <11>
+3VS
CPUCLK0_H <6>
CPUCLK0_L <6>
+3VS
SBLINKCLK SBLINKCLK#
GFX_PCIE#
SBSRCCLK SBSRCCLK# CLK_PCIE_VGA CLK_PCIE_VGA# CLK_PCIE_LAN CLK_PCIE_LAN# CLK_NEW CLK_NEW# CLK_DVD CLK_DVD# CLK_WLAN CLK_WLAN#
HTREFCLK
1 2
1 2 1 2 1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
VGA@ VGA@
NEW@ NEW@ DVD@ DVD@ WLAN@ WLAN@
1 2
R356 49.9_0402_1%
1 2
R355 49.9_0402_1%
1 2
R92 49.9_0402_1%
1 2
R93 49.9_0402_1%
R354 49.9_0402_1% R353 49.9_0402_1% R352 49.9_0402_1% R351 49.9_0402_1% R102 49.9_0402_1% R103 49.9_0402_1% R407 49.9_0402_1% R406 49.9_0402_1% R371 49.9_0402_1% R370 49.9_0402_1% R362 49.9_0402_1% R361 49.9_0402_1%
1 2
R107 49.9_0402_1%
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D
2007/5/4 2008/5/4
Deciphered Date
E
Title
Size Document Number Rev
Custom
F
Date: Sheet
G
Clock Generator IALAA-Minnesota10A LA3631P
13 45Wednesday, May 16, 2007
of
H
1A
A
B
C
D
E
12
1
2
JP24
ACES_85201-1205UMA@
+CRT_VCC
12
R18
UMA@
19.1K_0402_1%
CRT_DDC_DAT
CRT_DDC_CLK
1
C24
@
2
470P_0402_50V8J
1 2 3 4 5 6 7 8 9 10 11 12
CRT CONNECTOR
UMA_CRT_R<11>
1 1
2 2
UMA_CRT_G<11>
UMA_CRT_B<11>
1 2
C428 0.1U_0402_16V4Z
UMA@
UMA_CRT_HSYNC<11>
UMA_CRT_VSYNC<11>
CRT_HSYNC HSYNC
CRT_VSYNC
CRT_G
CRT_B
12
R20
UMA@
+CRT_VCC
C426
UMA@
150_0402_1%
1
5
P
4
OE#
A2Y
G
U16
UMA@
3
SN74AHCT1G125GW_SOT353-5
1 2
UMA@
0.1U_0402_16V4Z
R19
12
R16
UMA@
150_0402_1%
+CRT_VCC
12
150_0402_1%
1
5
P
OE#
A2Y
G
U17
UMA@
3
SN74AHCT1G125GW_SOT353-5
1
C17
UMA@
2
12
R282 10K_0402_5%
UMA@
D_CRT_HSYNC
D_CRT_VSYNC
4
1
C25
UMA@
2
6P_0402_50V8K
6P_0402_50V8K
C37
UMA@
L6
1 2
FCM2012C-800_0805
UMA@
L4
1 2
FCM2012C-800_0805
UMA@
L3
1 2
FCM2012C-800_0805
UMA@
1
2
6P_0402_50V8K
B:As EMI request L3,L4,L6 need to link SM010009L00
1 2
L40 10_0402_5%UMA@
1 2
L42 10_0402_5%UMA@
C21
1
2
22P_0402_50V8J
C16
C425
UMA@
CRT_R_LCRT_R
CRT_G_L
CRT_B_L
1
2
1
2
22P_0402_50V8J
C427
UMA@
10P_0402_50V8J
C13
1
2
MP:Update D29 to meet CRT.
+5VS +R_CRT_VCC +CRT_VCC
D29
2 1
RB491D_SOT23
C:EMI solution to add C13,C16,C21 in BOM with
1
22P value.
2
22P_0402_50V8J
UMA_CRT_SDA<11>
UMA_CRT_SCL<11>
F2
21
1A_6VDC_MINISMDC110
0.1U_0402_16V4Z@
G
2
S
C:Chg. PN to SB770020010.
VSYNC
10P_0402_50V8J
+CRT_VCC
1
C422
2
+3VS
G
2
Q4
13
D
S
2N7002_SOT23-3
UMA@
Q5
13
D
2N7002_SOT23-3
UMA@
CRT_DDC_CLK
CRT_DDC_DAT VSYNC HSYNC CRT_R_L
CRT_G_L CRT_B_L
A: Follow AMD command.
R21
UMA@
19.1K_0402_1%
C38
@
470P_0402_50V8J
TV-OUT CONNECTOR
3 3
+3VS
C524
1 2
22P_0402_50V8J
VGA_TV_LUMA<15> UMA_TV_LUMA<11>
VGA_TV_CRMA<15> UMA_TV_CRMA<11>
4 4
1 2
R288 0_0402_5%VGA@
1 2
R287 0_0402_5%UMA@
1 2
R290 0_0402_5%VGA@
1 2
R289 0_0402_5%UMA@
R307
150_0402_1%
TV_LUMA
TV_CRMA
12
12
R310 150_0402_1%
1
C533
100P_0402_25V8K
2
L51 MBK1608121YZF_0603
L53 MBK1608121YZF_0603
1
C517
100P_0402_25V8K
2
@
1 2
1 2
1 2
22P_0402_50V8J@
C528
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2007/5/4 2008/5/4
C
D4
DAN217_SC59@
2
1
C536
2
100P_0402_25V8K
Deciphered Date
1
D5
3
1
C535
2
100P_0402_25V8K
DAN217_SC59@
1
2
3
TV_CRMA_L TV_LUMA_L
JP26
4
4
3
3
2
2
1
ALLTO_C10877-104A1-L_4P
1
D
6 5
TV-OUT Conn.
1. Y ground
2. C ground
3. Y (luminance+sync)
4. C (crominance)
Compal Electronics, Inc.
Title
TV-OUT, LVDS CONNECTOR
Size Document Number Rev
IALAA-Minnesota10A LA3631P 1A
B
Monday, May 14, 2007
Date: Sheet
E
14 45
of
Loading...
+ 31 hidden pages
Buy Points How it Works FAQ Contact Us Questions and Suggestions Privacy Policy Cookie Policy Terms of Use