Toshiba 27WLT56B Service Manual

TOSHIBA

27WLT56B

SERVICE MANUAL

TABLE OF CONTENTS

INTRODUCTION ...................................................................................................................................... 1

2. TUNER......................................................................................................................................................1

3. IF PART (TDA9886) .................................................................................................................................1

4. MULTI STANDARD SOUND PROCESSOR............................................................................................ 2

5. VIDEO SWITCH TEA6415 ....................................................................................................................... 2

6. AUDIO AMPLIFIER STAGE WITH TPA3002D2 ...................................................................................... 2

7. MAIN POWER SUPPLY (SMPS) AND POWER INTERFACE BOARD ..................................................3

8. MICROCONTROLLER ............................................................................................................................. 3

9. SERIAL ACCESS CMOS 4K x 8 (32K bit) EEPROM 24C32A................................................................. 3

10. CLASS AB STEREO HEADPHONE DRIVER TDA1308 ......................................................................... 3

11. SAW FILTERS..........................................................................................................................................3

12. IC DESCRIPTIONS AND INTERNAL BLOCK DIAGRAM .......................................................................4

12.1. TDA9886 ...........................................................................................................................................5

12.2. TEA6415C ......................................................................................................................................... 6

12.3. 24C32A.............................................................................................................................................. 7

12.4. SAA5264 ...........................................................................................................................................8

12.5. LM317.............................................................................................................................................. 10

12.6. ST24LC21 .......................................................................................................................................10

12.7. TLC7733..........................................................................................................................................11

12.8. 74LVC257A .....................................................................................................................................12

12.9. 74LVC14A .......................................................................................................................................12

12.10. LM1117............................................................................................................................................ 13

12.11. IRF7314- IRF7316........................................................................................................................... 14

12.12. MC34063A....................................................................................................................................... 15

12.13. LM2576- 52kHz Simple 3A Buck Regulator....................................................................................16

12.14. DS90C385 ....................................................................................................................................... 17

12.15. MSP34X1G...................................................................................................................................... 19

12.16. TPA3002D ....................................................................................................................................... 22

12.17. TDA1308 .........................................................................................................................................22

12.18. PI5V330...........................................................................................................................................23

12.19. MST9883 ......................................................................................................................................... 23

12.20. SAA7118E ....................................................................................................................................... 25

12.21. TPS72501........................................................................................................................................ 30

12.22. TSOP1136.......................................................................................................................................32

12.23. PCF8591 .........................................................................................................................................32

12.24. PW1231...........................................................................................................................................33

12.25. PW181.............................................................................................................................................34

12.26. SIL1169 ........................................................................................................................................... 35

12.27. SDRAM 4M x 16 (MT48LC4M16A2TG-75)..................................................................................... 36

12.28. FLASH 16MBit.................................................................................................................................38

12.29. ASM3P2814 ....................................................................................................................................39

12.30. 74LX1G86 .......................................................................................................................................40

12.31. 74HCT4053 .....................................................................................................................................41

13. IC DESCRIPTIONS (FOR DIGITAL) ...................................................................................................... 42

13.1. STI5518 ........................................................................................................................................... 42

13.2. MAX232_SMD.................................................................................................................................42

13.3. 74HCU04.........................................................................................................................................43

13.4. TSH22 .............................................................................................................................................44

13.5. CS4334............................................................................................................................................ 44

13.6. AMIC A43L2616 .............................................................................................................................. 45

13.7. MX29LV160T................................................................................................................................... 47

13.8. 24C32 .............................................................................................................................................. 48

13.9. STV0360.......................................................................................................................................... 49

13.10. MAX809...........................................................................................................................................52

13.11. TDCC2345TV39A............................................................................................................................ 53

13.12. STV0700.......................................................................................................................................... 53

27” TFT TV Service Manual 05/09/2005

14.

SERVICE MENU SETTINGS ................................................................................................................. 58

14.1. display menu ...................................................................................................................................58

14.2. calibration menu ..............................................................................................................................60

14.3. deinterlacer menu............................................................................................................................ 62

14.4. factory settings menu ......................................................................................................................64

15. BLOCK DIAGRAMS ...............................................................................................................................65

16. CIRCUIT DIAGRAMS.............................................................................................................................67

27” TFT TV Service Manual 05/09/2005

1. INTRODUCTION

27” TFT IDTV is a progressive TV control system with built-in de-interlacer and scaler. It uses a

1280*720 panel with 16:9 aspect ratio.The TV is capable of operation in PAL, SECAM, NTSC (playback) colour standards and multiple transmission standards as B/G, D/K, I/I’, and L/L’ including German and NICAM stereo. Sound system output is supplying 2x8W (10%THD) for stereo 8 speakers. The chassis is equipped with many inputs and outputs allowing it to be used as a center of a media system.

It supports following peripherals: 2 SCART’s with all of them supporting full SCART features including RGB input 1 AV input. (CVBS+ Stereo Audio) 1 SVHS iput 1 Stereo Headphone output 1 D-Sub 15 PC input 1 DVI input (supports HDCP) 1 Audio line out 1 Stereo audio input for PC/DVI 2 CI (Common Interface) slots

Other features include, 10 pg Teletext, Picture-In-Picture (PIP) , Picture-And-Picture (PAP) , PictureAnd-Text (PAT).

2. TUNER

The tuners used in the design are combined VHF, UHF tuners suitable for CCIR systems B/G, H, L, L’, I/I’, and D/K. The tuning is available through the digitally controlled I

C bus (PLL). Below you will find

info on one of the Tuners in use.

General description of UV1316:

The UV1316 tuner belongs to the UV 1300 family of tuners, which are designed to meet a wide range of applications. It is a combined VHF, UHF tuner suitable for CCIR systems B/G, H, L, L’, I and I’. The low IF output impedance has been designed for direct drive of a wide variety of SAW filters with sufficient suppression of triple transient.

Features of UV1316:

1. Member of the UV1300 family small sized UHF/VHF tuners

2. Systems CCIR: B/G, H, L, L’, I and I’; OIRT: D/K

3. Digitally controlled (PLL) tuning via I

C-bus

4. Off-air channels, S-cable channels and Hyperband

5. World standardised mechanical dimensions and world standard pinning

6. Compact size

7. Complies to “CENELEC EN55020” and “EN55013”

Pinning:

1. Gain control voltage (AGC) : 4.0V, Max: 4.5V

2. Tuning voltage

3. I²C-bus address select : Max: 5.5V

4. I²C-bus serial clock : Min:-0.3V, Max: 5.5V

5. I²C-bus serial data : Min:-0.3V, Max: 5.5V

6. Not connected

7. PLL supply voltage : 5.0V, Min: 4.75V, Max: 5.5V

8. ADC input

9. Tuner supply voltage : 33V, Min: 30V, Max: 35V

10. Symmetrical IF output 1

11. Symmetrical IF output 2

3. IF PART (TDA9886)

The TDA9886 is an alignment-free multistandard (PAL, SECAM and NTSC) vision and sound IF signal PLL Both devices can be used for TV, VTR, PC and set-top box applications. The following figure shows the simplified block diagram of the integrated circuit. The integrated circuit comprises the following functional blocks:

27” TFT TV Service Manual 05/09/2005

VIF amplifier, Tuner and VIF-AGC, VIF-AGC detector, Frequency Phase-Locked Loop (FPLL) detector, VCO and divider, Digital acquisition help and AFC, Video demodulator and amplifier, Sound carrier trap, SIF amplifier, SIF-AGC detector, Single reference QSS mixer, AM demodulator, FM demodulator and acquisition help, Audio amplifier and mute time constant, voltage stabilizer.

I²C-bus transceivers and MAD (module address), Internal

4. MULTI STANDARD SOUND PROCESSOR

The MSP34x1G family of single-chip Multistandard Sound Processors covers the sound processing of all analog TV-Standards worldwide, as well as the NICAM digital sound standards. The full TV sound processing, starting with analog sound IF signal-in, down to processed analog AF-out, is performed on a single chip. These TV sound processing ICs include versions for processing the multichannel television sound (MTS) signal conforming to the standard recommended by the Broadcast Television Systems Committee (BTSC). The DBX noise reduction, or alternatively, Micronas Noise Reduction (MNR) is performed alignment free. Other processed standards are the Japanese FM-FM multiplex standard (EIA-J) and the FM Stereo Radio standard. Current ICs have to perform adjustment procedures in order to achieve good stereo separation for BTSC and EIA-J. The MSP34x1G has optimum stereo performance without any adjustments.

5. VIDEO SWITCH TEA6415

In case of three or more external sources are used, the video switch IC TEA6415 is used. The main function of this device is to switch 8 video-input sources on the 6 outputs. Each output can be switched on only one of each input. On each input an alignment of the lowest level of the signal is made (bottom of sync. top for CVBS or black level for RGB signals). Each nominal gain between any input and output is 6.5dB.For D2MAC or Chroma signal the alignment is switched off by forcing, with an external resistor bridge, 5VDC on the input. Each input can be used as a normal input or as a MAC or Chroma input (with external Resistor Bridge). All the switching possibilities are changed through the BUS. Driving 75ohm load needs an external resistor. It is possible to have the same input connected to several outputs.

6. AUDIO AMPLIFIER STAGE WITH TPA3002D2

The TPA3002D2 is a 9-W (per channel) efficient, Class-D audio amplifier for driving bridged-tied stereo speakers. The TPA3002D2 can drive stereo speakers as low as 8 . The high efficiency of the TPA3002D2 eliminates the need for external heatsinks when playing music.

27” TFT TV Service Manual 05/09/2005

7. MAIN POWER SUPPLY (SMPS) AND POWER INTERFACE BOARD

The DC voltages required at various parts of the chassis and inverters are provided by an main power supply unit and power interface board. The main power supply unit is designed for 24V and 12V DC supply. Power interface board generates +12V for audio amplifier, 5V and 3.3V stand by voltage and 8V, 12V, 5V and 3V3 supplies for other different parts of the chassis. An optocoupler is used to control the regulation of line voltage and stand-by power consumption. There is a regulation circuit in secondary side. During the switch on period of the transistor, energy is stored in the transformer. During the switch off period energy is fed to the load via secondary winding. By varying switch-on time of the power transistor, it controls each portion of energy transferred to the second side such that the output voltage remains nearly independent of load variations.

8. MICROCONTROLLER

The microprocessor is embedded inside PW181 chip which also handles scaling, frame rate conversion and OSD generation. The on-chip 16-bit microprocessor is a Turbo x86-compatible processor core with on-chip peripherals (timers, interrupt controller, 2-wire serial master/slave interface, UART, I/O ports, and more). Special peripherals such as Infrared (IR) pulse decoders and a digital pulse width modulator (PWM) are also included. There are two independent 2-wire serial master/slave interface modules that can be multiplexed to control up to five 2-wire serial ports. The slave 2-wire interface is designed for HDCP use only (and requires the use of HDCP Image Processors). On-chip RAM of up to 64 Kbytes is available. A complete microprocessor system can be implemented simply by adding external ROM. The on-chip processor can be disabled to allow external processor control of all internal functions.

9. SERIAL ACCESS CMOS 4K x 8 (32K bit) EEPROM 24C32A

The Microchip Technology Inc. 24C32A is a 4K x 8 (32K bit) Serial Electrically Erasable PROM. It has been developed for advanced, low power applications such as personal communications or data acquisition. The 24C32A also has a page-write capability of up to 32 bytes of data. The 24C32A is capable of both random and sequential reads up to the 32K boundary. Functional address lines allow up to eight 24C32A devices on the same bus, for up to 256K bits address space. Advanced CMOS technology and broad voltage range make this device ideal for low-power/low-voltage, non-volatile code and data applications.

10. CLASS AB STEREO HEADPHONE DRIVER TDA1308

The TDA1308 is an integrated class AB stereo headphone driver contained in a DIP8 plastic package. The device is fabricated in a 1 mm CMOS process and has been primarily developed for portable digital audio applications.

11. SAW FILTERS

K9656M: Standard:

• B/G

• D/K

• I

• L/L’

Features

• TV IF audio filter with two channels

• Channel 1 (L’) with one pass band for sound carriers at 40,40 MHz (L’) and 39,75 MHz (L’- NICAM)

• Channel 2 (B/G,D/K,L,I) with one pass band for sound carriers between 32,35 MHz and 33,40 MHz

Terminals

• Tinned CuFe alloy

Pin configuration

1 Input 2 Switching input 3 Chip carrier - ground 4 Output 5 Output

27” TFT TV Service Manual 05/09/2005

K3953M:

Standard:

• B/G

• D/K

• I

• L/L’

Features

TV IF video filter with Nyquist slopes at 33,90 MHz and 38,90 MHz Constant group delay Suitable for CENELEC EN 55020

Terminals

Tinned CuFe alloy

Pin configuration

1 Input 2 Input - ground 3 Chip carrier - ground 4 Output 5 Output

12. IC DESCRIPTIONS AND INTERNAL BLOCK DIAGRAM

TDA9886 TEA6415C 24C32 SAA5264 LM317T ST24LC21 TLC7733 74LVC257A

74LVC14A

LM1117 IRF7314 IRF7316 MC34063A LM2576 DS90C385 MSP3411G TPA3002D TDA1308 PI5V330 MST9883 SAA7118E TPS72501 TSOP1136 PCF8591 PW1231 PW181 SIL1169 SDRAM 4M x 16 (MT48LC4M16A2TG-75) FLASH ASM3P2814 74LX1G86 74HCT4053

27” TFT TV Service Manual 05/09/2005

12.1. TDA9886

12.1.1. General Description

The TDA9885 is an alignment-free single standard (without positive modulation) vision and sound IF signal PLL.

12.1.2. Features

•

5 V supply voltage

• Gain controlled wide-band Vision Intermediate Frequency (VIF) amplifier (AC-coupled)

• Multistandard true synchronous demodulation with active carrier regeneration (very linear demodulation,

good intermodulation figures, reduced harmonics, excellent pulse response)

• Gated phase detector for L/L accent standard

• Fully integrated VIF Voltage Controlled Oscillator (VCO), alignment-free; frequencies switchable for all

negative and positive modulated standards via I

• Digital acquisition help, VIF frequencies of 33.4, 33.9, 38.0, 38.9, 45.75 and 58.75 MHz

• 4 MHz reference frequency input [signal from Phase-Locked Loop (PLL) tuning system] or operating as

crystal oscillator

• VIF Automatic Gain Control (AGC) detector for gain control, operating as peak sync detector for negative

modulated signals and as a peak white detector for positive modulated signals

• Precise fully digital Automatic Frequency Control (AFC) detector with 4-bit digital-to-analog converter; AFC

bits via I

• TakeOver Point (TOP) adjustable via I

C -bus readable

C-bus or alternatively with potentiometer

• Fully integrated sound carrier trap for 4.5, 5.5, 6.0 and 6.5 MHz, controlled by FM-PLL oscillator

• Sound IF (SIF) input for single reference Quasi Split Sound (QSS) mode (PLL controlled)

• SIF AGC for gain controlled SIF amplifier; single reference QSS mixer able to operate in high performance

single reference QSS mode and in intercarrier mode, switchable via I

• AM demodulator without extra reference circuit

• Alignment-free selective FM-PLL demodulator with high linearity and low noise

• I

C-bus control for all functions

• I

C-bus transceiver with pin programmable Module Address (MAD).

C-bus

12.1.3. Pinning

SYMBOL PIN DESCRIPTION

VIF1 1

VIF2 OP1 FMPLL DEEM AFD DGND AUD TOP SDA SCL SIOMA n.c. TAGC REF VAGC CVBS AGND VPLL

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

VP 20

AFC

VIF differential input 1 VIF differential input 2 output 1 (open-collector) FM-PLL for loop filter de-emphasis output for capacitor AF decoupling input for capacitor digital ground audio output tuner AGC TakeOver Point (TOP) I2C-bus data input/output I2C-bus clock input sound intercarrier output and MAD select not connected tuner AGC output 4 MHz crystal or reference input VIF-AGC for capacitor; note 1 video output analog ground VIF-PLL for loop filter supply voltage (+5 V) AFC output

27” TFT TV Service Manual 05/09/2005

OP2 SIF1 SIF2

22 23 24

output 2 (open-collector) SIF differential input 1 SIF differential input 2

12.2.

TEA6415C

12.2.1. General Description

The main function of the IC is to switch 8 video input sources on 6 outputs. Each output can be switched on only one of each input. On each input an alignment of the lowest level of the signal is made (bottom of synch. top for CVBS or black level for RGB signals). Each nominal gain between any input and output is 6.5dB. For D2MAC or Chroma signal the alignment is switched off by forcing, with an external resistor bridge, 5 V

DC on the input. Each input can be used as a normal input or as a MAC or

Chroma input (with external resistor bridge). All the switching possibilities are changed through the BUS. Driving 75 load needs an external transistor. It is possible to have the same input connected to several outputs. The starting configuration upon power on (power supply: 0 to 10V) is undetermined. In this case, 6 words of 16 bits are necessary to determine one configuration. In other case, 1 word of 16 bits is necessary to determine one configuration.

12.2.2. Features

• 20MHz Bandwidth

• Cascadable with another TEA6415C (Internal address can be changed by pin 7 voltage)

• 8 Inputs (CVBS, RGB, MAC, CHROMA,...)

• 6 Outputs

• Possibility of MAC or chroma signal for each input by switching-off the clamp with an external resistor bridge

• Bus controlled

• 6.5dB gain between any input and output

• 55dB crosstalk at 5mHz

• Fully ESD protected

12.2.3. Pinning

1. Input : Max : 2Vpp, Input Current: 1mA, Max : 3mA

2. Data : Low level : -0.3V Max: 1.5V, High level : 3.0V Max : Vcc+0.5V

3. Input : Max : 2Vpp, Input Current: 1mA, Max : 3mA

4. Clock : Low level : -0.3V Max: 1.5V, High level : 3.0V Max : Vcc+0.5V

5. Input : Max : 2Vpp, Input Current: 1mA, Max : 3mA

6. Input : Max : 2Vpp, Input Current: 1mA, Max : 3mA

7. Prog

8. Input : Max : 2Vpp, Input Current: 1mA, Max: 3mA

9. Vcc : 12V

10. Input : Max : 2Vpp, Input Current: 1mA, Max : 3mA

11. Input : Max : 2Vpp, Input Current: 1mA, Max : 3mA

12. Ground

13. Output : 5.5Vpp, Min : 4.5Vpp

14. Output : 5.5Vpp, Min : 4.5Vpp

15. Output : 5.5Vpp, Min : 4.5Vpp

16. Output : 5.5Vpp, Min : 4.5Vpp

17. Output : 5.5Vpp, Min : 4.5Vpp

18. Output : 5.5Vpp, Min : 4.5Vpp

19. Ground

20. Input : Max : 2Vpp, Input Current : 1mA, Max : 3mA

27” TFT TV Service Manual 05/09/2005

12.3.

24C32A

12.3.1. Features

• Voltage operating range: 4.5V to 5.5V

- Maximum write current 3 mA at 5.5V

- Standby current 1 mA typical at 5.0V

• 2-wire serial interface bus, I

2CTM

compatible

• 100 kHz and 400 kHz compatibility

• Self-timed ERASE and WRITE cycles

• Power on/off data protection circuitry

• Hardware write protect

• 1,000,000 Erase/Write cycles guaranteed

• 32-byte page or byte write modes available

• Schmitt trigger filtered inputs for noise suppression

• Output slope control to eliminate ground bounce

• 2 ms typical write cycle time, byte or page

• Up to eight devices may be connected to the same bus for up to 256K bits total memory

• Electrostatic discharge protection > 4000V

• Data retention > 200 years

• 8-pin PDIP and SOIC packages

• Temperature ranges

- Commercial (C): 0°C to 70°C

- Industrial (I): -40°C to +85°C

- Automotive (E): -40°C to +125°C

12.3.2. Description

12.3.3. Pin Function table

Name Function

A0, A1, A2 User Configurable Chip Selects Vss Ground SDA Serial Address/Data I/O SCL Serial Clock WP Write Protect Input Vcc +4.5V to 5.5V Power Supply

27” TFT TV Service Manual 05/09/2005

12.3.4. Functional Descriptions

The 24C32A supports a Bi-directional 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. The bus must be controlled by a master device which generates the Serial Clock (SCL), controls the bus access, and generates the START and STOP conditions, while the 24C32A works as slave. Both master and slave can operate as transmitter or receiver but the master device determines which mode is activated.

12.4.

SAA5264

12.4.1. Features

The following features apply to both SAA5264 and SAA5265:

• Complete 625 line teletext decoder in one chip reduces printed circuit board area and cost

• Automatic detection of transmitted fastext links or service information (packet 8/30)

• On-Screen Display (OSD) for user interface menus using teletext and dedicated menu icons

• Video Programming System (VPS) decoding

• Wide Screen Signalling (WSS) decoding

• Pan-European, Cyrillic, Greek/Turkish and French/Arabic character sets in each chip

• High-level command interface via I

C-bus gives easy control with a low software overhead

• High-level command interface is backward compatible to Stand-Alone Fastext And Remote Interface

(SAFARI)

• 625 and 525 line display

• RGB interface to standard colour decoder ICs, current source

• Versatile 8-bit open-drain Input/Output (I/O) expander, 5 V tolerant

• Single 12 MHz crystal oscillator

• 3.3 V supply voltage.

SAA5264 features

• Automatic detection of transmitted pages to be selected by page up and page down

• 8 Page fastext decoder

• Table Of Pages (TOP) decoder with Basic Top Table (BTT) and Additional Information Tables (AITs)

• 4 Page user-defined list mode.

12.4.2. General Description

The SAA5264 is a single-chip ten page 625-line World System Teletext decoder with a high-level command interface, and is SAFARI compatible. The device is designed to minimize the overall system cost, due to the high-level command interface offering the benefit of a low software overhead in the TV microcontroller. The SAA5264 has the following functionality:

• 10 page teletext decoder with OSD, Fastext, TOP, default and list acquisition modes

• Automatic channel installation support

• Closed caption acquisition and display

• Violence Chip (VChip) support.

12.4.3. Pin Connections and Short Descriptions

SYMBOL PIN TYPE DESCRIPTION

Port 2: 8-bit programmable bidirectional port with alternative functions

P2.0/PWM 1 I/O P2.1/PWM0 2 I/O P2.2/PWM1 3 I/O P2.3/PWM2 4 I/O P2.4/PWM3 5 I/O P2.5/PWM4 6 I/O P2.6/PWM5 7 I/O P2.7/PWM6 8 I/O

Port 3: 8-bit programmable bidirectional port with alternative functions P3.0/ADC0 P3.1/ADC1

9 I/O 10 I/O

output for 14-bit high precision Pulse Width Modulator (PWM) outputs for 6-bit PWMs 0 to 6

inputs for the software Analog-to-Digital-Converter (ADC) facility

27” TFT TV Service Manual 05/09/2005

P3.2/ADC2 P3.3/ADC3 P3.4/PWM7

SSC

11 I/O 12 I/O 30 I/O 13 I/O

output for 6-bit PWM7 core ground

Port 0: 8-bit programmable bidirectional port

SCL(NVRAM) SDA(NVRAM) P0.2 P0.3 P0.4 P0.5

14 I 15 I/O 16 I/O 17 I/O 18 I/O 19 I/O

I2C-bus Serial Clock input to Non-Volatile RAM I2C-bus Serial Data input/output (Non-Volatile RAM) input/output for general use input/output for general use input/output for general use 8 mA current sinking capability for direct drive of Light Emitting

Diodes (LEDs) P0.6 P0.7

22 -

SSA

CVBS0

20 I/O 21 I/O

23 I

input/output for general use

analog ground

Composite Video Baseband Signal (CVBS) input; a positive-going

1V CVBS1 SYNC_FILTER

24 I 25 I sync-pulse-filter input for CVBS; this pin should be connected to V

(peak-to-peak) input is required; connected via a 100 nF capacitor

via a 100 nF capacitor IREF

26 I

reference current input for analog circuits; for correct operation a 24

κΩ resistor should be connected to FRAME

27 O

Frame de-interlace output synchronized with the VSYNC pulse to

produce a non-interlaced display by adjustment of the vertical

deflection circuits TEST COR

28 I not available; connect this pin to V 29 O

contrast reduction: open-drain, active LOW output which allows

selective contrast reduction of the TV picture to enhance a mixed

mode display

31 -

DDA

VDS

HSYNC

30 I/O

32 O

33 O

34 O

35 O

36 I

P3.4/PWM7 (described above)

analog supply voltage (3.3 V)

Blue colour information pixel rate output

Green colour information pixel rate output

Red colour information pixel rate output

video/data switch push-pull output for pixel rate fast blanking

horizontal sync pulse input: Schmitt triggered for a Transistor

Transistor Level (TTL) version; the polarity of this pulse is

programmable by register bit TXT1.H POLARITY VSYNC

37 I

vertical sync pulse input; Schmitt triggered for a TTL version; the

polarity of this pulse is programmable by register bit TXT1.V

POLARITY

SSP

DDC

OSCGND

XTALIN

XTALOUT

RESET

38 -

39 -

40 -* 41 I 42 O 43 I

periphery ground

core supply voltage (+3.3 V)

crystal oscillator ground

12 MHz crystal oscillator input

12 MHz crystal oscillator output

reset input; if this pin is HIGH for at least 2 machine cycles (24

oscillator periods) while the oscillator is running, the device resets;

this pin should be connected to

DDP

44 -

periphery supply voltage (+3.3 V)

Port 1: 8-bit programmable bidirectional port P1.0

P1.1 P1.2 P1.3 SCL

45 I/O 46 I/O 47 I/O 48 I/O 49 I

input/output for general use

I2C-bus Serial Clock input from application

SSA

via a capacitor

DDP

SSA

27” TFT TV Service Manual 05/09/2005

SDA P1.4 P1.5

50 I/O 51 I/O 52 I/O

I2C-bus Serial Data input from (application)

input/output for general use

12.5.

LM317

12.5.1. General Description

The LM117/LM217/LM317 are monolithic integrated circuit in TO-220, ISOWATT220, TO-3 and D

PAK packages intended for use as positive adjustable voltage regulators. They are designed to supply more than 1.5A of load current with an output voltage adjustable over a

1.2 to 37V range. The nominal output voltage is selected by means of only a resistive divider, making the device exceptionally easy to use and eliminating the stocking of many fixed regulators.

12.5.2. Features

• Output voltage range : 1.2 To 37V

• Output current In excess of 1.5A

• 0.1% Line and Load Regulation

• Floating Operation for High Voltages

• Complete Series of Protections : Current Limiting, Thermal Shutdown And Soa Control

12.6.

ST24LC21

12.6.1. Description

The ST24LC21 is a 1K bit electrically erasable programmable memory (EEPROM), organized by 8 bits. This device can operate in two modes: Transmit Only mode and I

C bidirectional mode. When powered, the device is in Transmit Only mode with EEPROM data clocked out from the rising edge of the signal applied on VCLK. The device will switch to the I applied on SCL pin. The ST24LC21 can not switch from the I

C bidirectional mode upon the falling edge of the signal

C bidirectional mode to the Transmit Only

mode (except when the power supply is removed). The device operates with a power supply value as

low as 2.5V. Both Plastic Dual-in-Line and Plastic Small Outline packages are available.

12.6.2. Features

• 1 million Erase/Write cycles

• 40 years data retention

• 2.5V To 5.5V single supply voltage

• 400k Hz compatibility over the full range of supply voltage

• Two wire serial interface I

C bus compatible

• Page Write (Up To 8 Bytes)

• Byte, random and sequential read modes

• Self timed programming cycle

• Automatic address incrementing

• Enhanced ESD/Latch up

• Performances

27” TFT TV Service Manual 05/09/2005

12.6.3. Pin connections

DIP Pin connections CO Pin connections

NC: Not connected

Signal names

SDA Serial data Address Input/Output SCL Serial Clock (I2C mode) Vcc Supply voltage Vss Ground VCLK Clock transmit only mode

12.7.

TLC7733

12.7.1. Description

The TLC77xx family of micropower supply voltage supervisors are designed for reset control, primarily in microcomputer and microprocessor systems. During power-on, RESET is asserted when V

reaches 1 V. After minimum V

(. 2 V) is established,

the circuit monitors SENSE voltage and keeps the reset outputs active as long as SENSE voltage (V inactive state to ensure proper system reset. The delay time, t t

) remains below the threshold voltage. An internal timer delays return of the output to the

I(SENSE)

, is determined by an external capacitor:

= 2.1 x 10 4 x CT

where C

is in farads

is in seconds

The TLC77xx has a fixed SENSE threshold voltage set by an internal voltage divider. When SENSE voltage drops below the threshold voltage, the outputs become active and stay in that state until SENSE voltage returns above threshold voltage and the delay time, t

, has expired.

In addition to the power-on-reset and undervoltage-supervisor function, the TLC77xx adds power-down control support for static RAM. When CONTROL is tied to GND, RESET will act as active high. The voltage monitor contains additional logic intended for control of static memories with battery backup during power failure. By driving the chip select (CS) of the memory circuit with the RESET output of the TLC77xx and with the CONTROL driven by the memory bank select signal (CSH1) of the microprocessor (see Figure 10), the memory circuit is automatically disabled during a power loss. (In this application the TLC77xx power has to be supplied by the battery.) The TLC77xxQ is characterized for operation over a temperature range of –40°C to 125°C, and the TLC77xxI is characterized for operation over a temperature range of –40°C to 85°C.

27” TFT TV Service Manual 05/09/2005

12.8.

74LVC257A

12.8.1. Features

Wide supply voltage range of 1.2 to 3.6 V In accordance with JEDEC standard no. 8-1A CMOS lower power consumption Direct interface with TTL levels Output drive capability 50 _ transmission lines at 85°C 5 Volt tolerant inputs/outputs, for interfacing with 5 Volt logic

12.8.2. Description

The 74LVC257A is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3V or 5.0V devices. In 3-State operation, outputs can handle 5V. This feature allows the use of these devices as translators in a mixed 3.3V/5V environment. The 74LVC257A is a quad 2-input multiplexer with 3-state outputs, which select 4 bits of data from two sources and are controlled by a common data select input (S). The data inputs from source 0 (1l 0 to 4l 0 ) are selected when input S is LOW and the data inputs from source 1 (1l 1 to 4l 1 ) are selected when S in HIGH. Data appears at the outputs (1Y to 4Y) in true (non-inverting) form from the selected inputs. The 74LVC257A is the logic implementation of a 4-pole, 2-position switch, where the position of the switch is determined by the logic levels applied to S. The outputs are forced to a high impedance OFF-state when OE is HIGH.

12.8.3. Pin Description

PIN NUMBER SYMBOL DESCRIPTION

1 S Common data select input 2, 5, 11, 14 3, 6, 10, 13

1| 1|

to 4|

Data inputs from source 0

Data outputs from source 1

4,7,9,12 1Y to 4Y 3-State multiplexer outputs 8 GND Ground (0V) 15 OE 3-State output enable input (active LOW) 16 Vcc Positive supply voltage

12.9. 74LVC14A

12.9.1. Features

• Wide supply voltage range of 1.2 to 3.6 V

• In accordance with JEDEC standard no. 8-1A

• Inputs accept voltages up to 5.5 V

• CMOS low power consumption

• Direct interface with TTL levels

12.9.2. Applications

• Wave and pulse shapers for highly noisy environments

• Astable multivibrators

• Monostable multivibrators

12.9.3. Description

The 74LVC14A is a high-performance, low power, low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V/5 V environment. The 74LVC14A provides six inverting buffers with Schmitt-trigger action. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.

27” TFT TV Service Manual 05/09/2005

12.9.4. Pin Description

PIN NUMBER SYMBOL DESCRIPTION

1, 3, 5, 9, 11, 13 1A – 6A Data inputs 2, 4, 6, 8, 10, 12 1Y – 6Y Data outputs 7 GND Ground (0V) 14 Vcc Positive supply voltage

12.10. LM1117

12.10.1. General Description

The LM1117 is a series of low dropout voltage regulators with a dropout of 1.2V at 800mA of load current. It has the same pin-out as National Semiconductor’s industry standard LM317. The LM1117 is available in an adjustable version, which can set the output voltage from 1.25V to 13.8V with only two external resistors. In addition, it is also available in five fixed voltages, 1.8V, 2.5V, 2.85V, 3.3V, and 5V. The LM1117 offers current limiting and thermal shutdown. Its circuit includes a zener trimmed bandgap reference to as-sure output voltage accuracy to within ±1%. The LM1117 series is available in SOT223, TO-220, and TO-252 D-PAK packages. A minimum of 10µF tantalum capacitor is required at the

output to improve the transient response and stability.

12.10.2. Features

• Available in 1.8V, 2.5V, 2.85V, 3.3V, 5V, and Adjustable Versions

• Space Saving SOT-223 Package

• Current Limiting and Thermal Protection

• Output Current 800mA

• Line Regulation 0.2% (Max)

• Load Regulation 0.4% (Max)

• Temperature Range — LM1117 0°C to 125°C

— LM1117I -40°C to 125°C

12.10.3. Applications

• 2.85V Model for SCSI-2 Active Termination

• Post Regulator for Switching DC/DC Converter

• High Efficiency Linear Regulators

• Battery Charger

• Battery Powered Instrumentation

12.10.4. Connection Diagrams

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12.11.

IRF7314- IRF7316

Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications.

The SO-8 has been modified through a customized leadframe for enhanced thermal characteristics and multiple-die capability making it ideal in a variety of power applications. With these improvements, multiple devices can be used in an application with dramatically reduced board space. The package is designed for vapor phase, infra red, or wave soldering techniques.

IRF7314 IRF7316

Absolute Maximum Ratings ( TA = 25°C Unless Otherwise Noted) (IRF7314)

Drain-Source Voltage VDS -20 Gate-Source Voltage VGS ± 12

Continuous Drain Current

Pulsed Drain Current

Continuous Source Current (Diode Conduction) IS -2.5

Maximum Power Dissipation

Single Pulse Avalanche Energy EAS 150 mJ Avalanche Current

Repetitive Avalanche Energy EAR 0.20 mJ Peak Diode Recovery dv/dt dv/dt -5.0 V/ ns

Junction and Storage Temperature Range TJ, TSTG -55 to + 150 °C

TA= 25°C -5.3 TA= 70°C

TA= 25°C

Symbol Maximum Units

-4.3

-21

2.0

1.3

-2.9 A

Absolute Maximum Ratings ( TA = 25°C Unless Otherwise Noted) (IRF7316)

Drain-Source Voltage VDS -30 Gate-Source Voltage

Continuous Drain Current

Pulsed Drain Current

Continuous Source Current (Diode Conduction) IS -2.5

Maximum Power Dissipation

Single Pulse Avalanche Energy EAS 140 mJ Avalanche Current

Repetitive Avalanche Energy Peak Diode Recovery dv/dt dv/dt -5.0 V/ ns

TA= 25°C TA= 70°C

TA= 25°C 2.0 TA= 70°C

Symbol Maximum Units

± 20

-4.9

-3.9

-30

1.3

-2.8 A

0.20 mJ

27” TFT TV Service Manual 05/09/2005

Junction and Storage Temperature Range TJ, TSTG -55 to + 150 °C

12.12.

MC34063A

1.5 A, Step-Up/Down/Inverting Switching Regulators

The MC34063A Series is a monolithic control circuit containing the primary functions required for DCtoDC converters. These devices consist of an internal temperature compensated reference, comparator, controlled duty cycle oscillator with an active current limit circuit, driver and high current output switch. This series was specifically designed to be incorporated in StepDown and StepUp and VoltageInverting applications with a minimum number of external components. Refer to Application Notes AN920A/D and AN954/D for additional design information.

Features:

• Operation from 3.0 V to 40 V Input

• Low Standby Current

• Current Limiting

• Output Switch Current to 1.5 A

• Output Voltage Adjustable

• Frequency Operation to 100 kHz

• Precision 2% Reference

• PbFree Packages are Available

27” TFT TV Service Manual 05/09/2005

12.13.

The LM2576 series of monolithic integrated circuits provide all the active functions for a step-down (buck) switching regulator. Fixed versions are available with a 3.3V, 5V, or 12V fixed output. Adjustable versions have an output voltage range from 1.23V to 37V. Both versions are capable of driving a 3A load with excellent line and load regulation. These regulators are simple to use because they require a minimum number of external components and include internal frequency compensation and a fixed-frequency oscillator. The LM2576 series offers a high efficiency replacement for popular three-terminal adjustable linear regulators. It substantially reduces the size of the heat sink, and in many cases no heat sink is required. A standard series of inductors available from several different manufacturers are ideal for use with the LM2576 series. This feature greatly simplifies the design of switch-mode power supplies. The feedback voltage is guaranteed to ±2% tolerance for adjustable versions, and the output voltage is guaranteed to ±3% for fixed versions, within specified input voltages and output load conditions. The oscillator frequency is guaranteed to ±10%. External shutdown is included, featuring less than 200⎧A standby current. The output switch includes cyclebycycle current limiting and thermal shutdown for full protection under fault conditions.

• 3.3V, 5V, 12V, and adjustable output versions

• Voltage over specified line and load conditions: Fixed version: ±3% max. output voltage Adjustable version: ±2% max. feedback voltage

• Guaranteed 3A output current

• Wide input voltage range: 4V to 40V

LM2576- 52kHz Simple 3A Buck Regulator

12.13.1. General Description

12.13.2. Features

27” TFT TV Service Manual 05/09/2005

• Wide output voltage range

1.23V to 37V

• Requires only 4 external components

• 52kHz fixed frequency internal oscillator

• Low power standby mode I

Q typically < 200⎧A

• 80% efficiency (adjustable version typically > 80%)

• Uses readily available standard inductors

• Thermal shutdown and current limit protection

• 100% electrical thermal limit burn-in

12.13.3. Pin Configurations

12.14.

DS90C385

12.14.1. General Description

The DS90C385 transmitter converts 28 bits of LVCMOS/LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. At a transmit clock frequency of 85 MHz, 24 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 595 Mbps per LVDS data channel. Using an 85 MHz clock, the data throughput is 297.5 Mbytes/sec. Also available is the DS90C365 that converts 21 bits of LVCMOS/LVTTL data into three LVDS (Low Voltage Differential Signaling) data streams. Both transmitters can be programmed for Rising edge strobe or falling edge strobe through a dedicated pin. A Rising edge or Falling edge strobe transmitter will interoperate with a Falling edge strobe Receiver (DS90CF386/DS90CF366) without any translation logic. The DS90C385 is also offered in a 64 ball, 0.8mm fine pitch ball grid array (FBGA) package which provides a 44 % reduction in PCB footprint compared to the TSSOP package. This chipset is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces.

12.14.2. Features

• 20 to 85 MHz shift clock support

• Best–in–Class Set & Hold Times on TxINPUTs

• Tx power consumption <130 mW (typ) @85MHz Grayscale

• Tx Power-down mode <200µW (max)

• Supports VGA, SVGA, XGA and Dual Pixel SXGA.

• Narrow bus reduces cable size and cost

27” TFT TV Service Manual 05/09/2005

• Up to 2.38 Gbps throughput

• Up to 297.5 Megabytes/sec bandwidth

• 345 mV (typ) swing LVDS devices for low EMI

• PLL requires no external components

• Compatible with TIA/EIA-644 LVDS standard

• Low profile 56-lead or 48-lead TSSOP package

• DS90C385 also available in a 64 ball, 0.8mm fine pitch ball grid array (FBGA) package

12.14.3. Pin Description

DS90C385 MTD56 (TSSOP) Package Pin Description-FPD Link Transmitter Pin Name I/O No. Description

TxIN

TxOUT+ TxOUT- TxCLKIN R_FB TxCLK OUT+ TxCLK OUT- PWR DOWN

Vcc GND PLL Vcc PLL GND LVDS Vcc LVDS GND

I 28

O 4 O 4 I 1 I 1 O 1 O 1 I 1

I 3 I 4 I 1 I 2 I 1 I 3

TTL level input. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines —FPLINE, FPFRAME and DRDY (also referred to as HSYNC, VSYNC, Data Enable). Positive LVDS differentiaI data output.

Negative LVDS differential data output. TTL Ievel clock input. Pin name TxCLK IN.

Programmable strobe select Positive LVDS differential clock output.

Negative LVDS differential clock output. TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at

power down. Power supply pins for TTL inputs.

Ground pins for TTL inputs.

Power supply pin for PLL. Ground pins for PLL. Power supply pin for LVDS outputs.

Ground pins for LVDS outputs.

Pin Name I/O No. Description

TxIN TxOUT+ TxOUT- TxCLKIN R_FB TxCLK OUT+ TxCLK OUT- PWR DOWN

Vcc GND PLL Vcc PLL GND LVDS Vcc LVDS GND NC

I 28 O 4 O 4 I 1 I 1 O 1 O 1 I 1

I 3 I 5 I 1 I 2 I 2 I 4 6

TTL level input. Positive LVDS differentiaI data output. Negative LVDS differential data output. TTL Ievel clock input. The rising edge acts as data strobe. Pin name TxCLK IN. Programmable strobe select. HIGH = rising edge, LOW = falling edge. Positive LVDS differential clock output. Negative LVDS differential clock output. TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low

current at power down. Power supply pins for TTL inputs.

Ground pins for TTL inputs.

Power supply pin for PLL. Ground pins for PLL. Power supply pin for LVDS outputs.

Ground pins for LVDS outputs. Pins not connected.

27” TFT TV Service Manual 05/09/2005

12.15.

MSP34X1G

MSP3411G

Multistandard Sound Processor Family

12.15.1. Introduction

The MSP 34x1G family of single-chip Multistandard Sound Processors covers the sound processing of all analog TV-Standards worldwide, as well as the NICAM digital sound standards. The full TV sound processing, starting with analog sound IF signal-in, down to processed analog AF-out, is performed on a single chip. Figure shows a simplified functional block diagram of the MSP 34x1G. The MSP 34x1G has all functions of the MSP 34x0G with the addition of a virtual surround sound feature. Surround sound can be reproduced to a certain extent with two loudspeakers. The MSP 34x1G includes the Micronas virtualizer algorithm “3D-PANORAMA” which has been approved by the Dolby

Laboratories for with the "Virtual Dolby Surround" technology. In addition, the MSP 34x1G includes the “PAN-ORAMA” algorithm. These TV sound processing ICs include versions for processing the multichannel television sound (MTS) signal conforming to the standard recommended by the Broadcast Television Systems Committee (BTSC). The DBX noise reduction, or alternatively, Micronas Noise Reduction (MNR) is performed alignment free. Other processed standards are the Japanese FM-FM multiplex standard (EIA-J) and the FM Stereo Radio standard. Current ICs have to perform adjustment procedures in order to achieve good stereo separation for BTSC and EIA-J. The MSP 34x1G has optimum stereo performance without any adjustments. The MSP 34x1G has built-in automatic functions: The IC is able to detect the actual sound standard automat-ically (Automatic Standard Detection). Furthermore, pilot levels and identification signals can be evaluated internally with subsequent switching between mono/stereo/bilingual; no I

2 C interaction is

necessary (Automatic Sound Selection).

Source Select

S bus interface consists of five pins:

1. I

S_DA_IN1, I2S_DA_IN2: For input, four channels (two channels per line, 2*16 bits) per sampling

cycle (32 kHz) are transmitted.

2. I

S _DA_OUT: For output, two channels (2*16 bits) per sampling cycle (32 kHz) are transmitted.

3. I

S _CL: Gives the timing for the transmission of I2S serial data (1.024 MHz).

4. I

S _WS: The I2S _WS word strobe line defines the left and right sample.

27” TFT TV Service Manual 05/09/2005

12.15.2. Features

• 3D-PANORAMA virtualizer (approved by Dolby Laboratories) with noise generator

• PANORAMA virtualizer algorithm

• Standard Selection with single I

C transmission

• Automatic Sound Selection (mono/stereo/bilingual),

• Automatic Carrier Mute function

• Interrupt output programmable (indicating status change)

• Loudspeaker / Headphone channel with volume, balance, bass, treble, loudness

• AVC: Automatic Volume Correction

• Subwoofer output with programmable low-pass and complementary high-pass filter

• 5-band graphic equalizer for loudspeaker channel

• Spatial effect for loudspeaker channel, processing of all deemphasis filtering

• Two selectable sound IF (SIF) inputs

• Four Stereo SCART (line) inputs, one Mono input; two Stereo SCART outputs

• Complete SCART in/out switching matrix

• Two I

S inputs; one I2S output

• Automatic Standard Detection of terrestrial TV standards

• Demodulation of the BTSC multiplex signal and the SAP channel

• Alignment free digital DBX noise reduction

• BTSC stereo separation (MSP 3441G also EIA-J) significantly better than specification

• SAP and stereo detection for BTSC system

• Demodulation of the FM-Radio multiplex signal

12.15.3. Pin connections

NC = not connected; leave vacant LV = if not used, leave vacant OBL = obligatory; connect as described in circuit diagram DVSS: if not used, connect to DVSS AHVSS: connect to AHVSS

Pin No. Pin Name Type

PLCC 68-pin

1 16 14 9 8 ADR_WS OUT LV ADR word strobe 2 - - - - NC LV Not connected 3 15 13 8 7 ADR_DA OUT LV ADR Data Output 4 14 12 7 6 I2S_DA_IN1 IN LV I2S1 data input 5 13 11 6 5 I2S_DA_OUT OUT LV I2S data output 6 12 10 5 4 I2S_WS IN/OUT LV I2S word strobe 7 11 9 4 3 I2S_CL IN/OUT LV I2S clock 8 10 8 3 2 I2C_DA IN/OUT OBL I2C data 9 9 7 2 1 I2C_CL IN/OUT OBL I2C clock 10 8 - 1 64 NC LV Not connected 11 7 6 80 63 STANDBYQ IN OBL Stand-by (low-active) 12 6 5 79 62 ADR_SEL IN OBL I2C bus address select 13 5 4 78 61 D_CTR_I/O_0 IN/OUT LV D_CTR_I/O_0 14 4 3 77 60 D_CTR_I/O_1 IN/OUT LV D_CTR_I/O_1 15 3 - 76 59 NC LV Not connected 16 2 - 75 58 NC LV Not connected 17 - - - - NC LV Not connected

18 1 2 74 57 AUD_CL_OUT OUT LV

19 64 1 73 56 TP LV Test pin 20 63 52 72 55 XTAL_OUT OUT OBL Crystal oscillator 21 62 51 71 54 XTAL_IN IN OBL Crystal oscillator 22 61 50 70 53 TESTEN IN OBL Test pin

23 60 49 69 52 ANA_IN2+ IN

24 59 48 68 51 ANA_IN- IN

25 58 47 67 50 ANA_IN1+ IN LV IF input 1

PSDIP 64-pin

PSDIP 52-pin

PQFP 80-pin

PLQFP 64-pin

Connection (if not used)

AVSS via 56 pF/LV

Short Description

Audio clock output (18.432 MHz)

IF Input 2 (can be left vacant, only if IF input 1 is also not in use) IF common (can be left vacant, only if IF input 1 is also not in use)

27” TFT TV Service Manual 05/09/2005

26 57 46 66 49 AVSUP OBL Analog power supply 5V

- - - 65 - AVSUP OBL Analog power supply 5V

- - - 64 - NC LV Not connected

- - - 63 - NC LV Not connected 27 56 45 62 48 AVSS OBL Analog ground

- - - 61 - AVSS OBL Analog ground 28 55 44 60 47 MONO_IN IN LV Mono input

- - - 59 - NC LV Not connected

29 54 43 58 46 VREFTOP OBL

30 53 42 57 45 SC1_IN_R IN LV SCART 1 input, right 31 52 41 56 44 SC1_IN_L IN LV SCART 1 input, left 32 51 - 55 43 ASG1 AHVSS Analog Shield Ground 1 33 50 40 54 42 SC2_IN_R IN LV SCART 2 input, right 34 49 39 53 41 SC2_IN_L IN LV SCART 2 input, left 35 48 - 52 40 ASG2 AHVSS Analog Shield Ground 2 36 47 38 51 39 SC3_IN_R IN LV SCART 3 input, right 37 46 37 50 38 SC3_IN_L IN LV SCART 3 input, left 38 45 - 49 37 ASG4 AHVSS Analog Shield Ground 4 39 44 - 48 36 SC4_IN_R IN LV SCART 4 input, right 40 43 - 47 35 SC4_IN_L IN LV SCART 4 input, left 41 - - 46 - NC LV or AHVSS Not connected 42 42 36 45 34 AGNDC OBL Analog reference voltage 43 41 35 44 33 AHVSS OBL Analog ground

- - - 43 - AHVSS OBL Analog ground

- - - 42 - NC LV Not connected

- - - 41 - NC LV Not connected 44 40 34 40 32 CAPL_M OBL Volume capacitor MAIN 45 39 33 39 31 AHVSUP OBL Analog power supply 8V 46 38 32 38 30 CAPL_A OBL Volume capacitor AUX 47 37 31 37 29 SC1_OUT_L OUT LV SCART output 1, left 48 36 30 36 28 SC1_OUT_R OUT LV SCART output 1, right 49 35 29 35 27 VREF1 OBL Reference ground 1 50 34 28 34 26 SC2_OUT_L OUT LV SCART output 2, left 51 33 27 33 25 SC2_OUT_R OUT LV SCART output 2, right 52 - - 32 - NC LV Not connected 53 32 - 31 24 NC LV Not connected 54 31 26 30 23 DACM_SUB OUT LV Subwoofer output 55 30 - 29 22 NC LV Not connected 56 29 25 28 21 DACM_L OUT LV Loudspeaker out, left 57 28 24 27 20 DACM_R OUT LV Loudspeaker out, right 58 27 23 26 19 VREF2 OBL Reference ground 2 59 26 22 25 18 DACA_L OUT LV Headphone out, left 60 25 21 24 17 DACA_R OUT LV Headphone out, right

- - - 23 - NC LV Not connected

- - - 22 - NC LV Not connected 61 24 20 21 16 RESETQ IN OBL Power-on-reset 62 23 - 20 15 NC LV Not connected 63 22 - 19 14 NC LV Not connected 64 21 19 18 13 NC LV Not connected 65 20 18 17 12 I2S_DA_IN2 IN LV I2S2-data input 66 19 17 16 11 DVSS OBL Digital ground

- - - 15 - DVSS OBL Digital ground

- - - 14 - DVSS OBL Digital ground 67 18 16 13 10 DVSUP OBL Digital power supply 5V

- - - 12 - DVSUP OBL Digital power supply 5V

- - - 11 - DVSUP OBL Digital power supply 5V 68 17 15 10 9 ADR_CL OUT LV ADR clock

Reference voltage IF A/D converter

27” TFT TV Service Manual 05/09/2005

12.16.

The TPA3002D2 is a 9-W (per channel) efficient, Class-D audio amplifier for driving bridged-tied stereo speakers. The TPA3002D2 can drive stereo speakers as low as 8 &. The high efficiency of the TPA3002D2 eliminates the need for external heatsinks when playing music.

FEATURES

- 9-W/Ch Into an 8- Load From 12-V Supply

- Efficient, Class-D Operation Eliminates Heatsinks and Reduces Power Supply Requirements

- 32-Step DC Volume Control From –40 dB to 36 dB

- Line Outputs For External Headphone

- Amplifier With Volume Control

- Regulated 5-V Supply Output for Powering TPA6110A2

- Space-Saving, Thermally-Enhanced PowerPAD Packaging

- Thermal and Short-Circuit Protection

TPA3002D

12.16.1. Description

12.16.2. Pin Connection

12.17.

The TDA1308 is an integrated class AB stereo headphone driver contained in an SO8 or a DIP8 plastic package. The device is fabricated in a 1 mm CMOS process and has been primarily developed for portable digital audio applications. It gets its input from two analog audio outputs (DACA_L and DACA_R) of MSP 34x0G. The gain of the output is adjustable by the feedback resistor between the inputs and outputs.

•

Wide temperature range

• No switch ON/OFF clicks

• Excellent power supply ripple rejection

• Low power consumption

• Short-circuit resistant

• High performance

• high signal-to-noise ratio

27” TFT TV Service Manual 05/09/2005

TDA1308

12.17.1. General Description

12.17.2. Features

High slew rate

•

• Low distortion

• Large output voltage swing.

12.17.3. Pinning

SYMBOL PIN DESCRIPTION

OUTA 1 Output A INA(neg) 2 Inverting input A INA(pos) 3 Non-inverting input A VSS 4 Negative supply INB(pos) 5 Non-inverting input B INB(neg) 6 Inverting input B OUTB 7 Output B VDD 8 Positive supply

12.18. PI5V330

12.18.1. General Description

The PI5V330 is well suited for video applications when switching composite or RGB analog. A picturein-picture application will be described in this brief. The pixel-rate creates video overlays so two or more pictures can be viewed at the same time. An inexpensive NTSC titler can be implemented by superimposing the output of a character generator on a standard composite video background.

12.19.

MST9883

12.19.1. General Description

The MST9883C is a fully integrated analog interface for digitizing high-resolution RGB graphics signals from PC’s and workstations. With a sampling rate capability of up to 140 MHz, it can accurately support display resolutions up to 1280x1024 (SXGA) at 75 Hz. The clamped input circuits provide sufficient bandwidth to accurately digitize each pixel.

12.19.2. Features

• Triple ADC with 12 - 140 MHz Sampling Rate

• Integrated line locked PLL generates pixel clock from HSYNC

• Integrated clamp with timing generator

• Integrated Brightness & Contrast controls

• Pin Compatible with AD9883A

• 4:2:2 and 4:4:4 Output Format Mode

• BT656 output format mode*

• Black and mid-level precision clamp and calibration

27” TFT TV Service Manual 05/09/2005

12.19.3. Pin Descriptions

27” TFT TV Service Manual 05/09/2005

12.20.

SAA7118E

12.20.1. General Description

The SAA7118E is a video capture device for applications at the image port of VGA controllers. Philips X-VIP is a new multistandard comb filter video decoder chip with additional component processing, providing high quality, optionally scaled, video. The SAA7118E is a combination of a four-channel analog preprocessing circuit including source selection, anti-aliasing filter and ADC, an automatic clamp and gain control, a Clock Generation Circuit (CGC), a digital multistandard decoder containing two-dimensional chrominance/luminance separation by an adaptive comb filter and a high performance scaler, including variable horizontal and vertical up and downscaling and a brightness, contrast and saturation control circuit. It is a highly integrated circuit for desktop video and similar applications. The decoder is based on the principle of line-locked clock decoding and is able to decode the colour of PAL, SECAM and NTSC signals into ITU 601 compatible colour component values. The SAA7118E accepts CVBS or S-video (Y/C) as analog inputs from TV or VCR sources, including weak and distorted signals as well as baseband component signals Y-P

-PR or RGB. An expansion port (X-port) for digital video

(bidirectional half duplex, D1 compatible) is also supported to connect to MPEG or video phone codec. At the so called image port (I-port) the SAA7118E supports 8 or 16-bit wide output data with auxiliary reference data for interfacing to VGA controllers. The target application for the SAA7118E is to capture and scale video images, to be provided as digital video stream through the image port of a VGA controller, for capture to system memory, or just to provide digital baseband video to any picture improvement processing.

12.20.2. Features

Video acquisition/clock

• Up to sixteen analog CVBS, split as desired (all of the CVBS inputs optionally can be used to convert e.g. Vestigial Side Band (VSB) signals)

• Up to eight analog Y + C inputs, split as desired

• Up to four analog component inputs, with embedded or separate sync, split as desired

• Four on-chip anti-aliasing filters in front of the Analog-to-Digital Converters (ADCs)

• Automatic Clamp Control (ACC) for CVBS, Y and C (or VSB) and component signals

• Switchable white peak control

• Four 9-bit low noise CMOS ADCs running at twice the oversampling rate (27 MHz)

• Fully programmable static gain or Automatic Gain Control (AGC), matching to the particular signal properties

• On-chip line-locked clock generation in accordance with “ITU 601”

• Requires only one crystal (32.11 or 24.576 MHz) for all standards

• Horizontal and vertical sync detection.

Video decoder

• Digital PLL for synchronization and clock generation from all standards and non-standard video sources e.g. consumer grade VTR

• Automatic detection of any supported colour standard

• Luminance and chrominance signal processing for PAL B, G, D, H, I and N, combination PAL N, PAL M, NTSC M, NTSC-Japan, NTSC 4.43 and SECAM

• Adaptive 2/4-line comb filter for two dimensional chrominance/luminance separation, also with VTR signals – Increased luminance and chrominance bandwidth for all PAL and NTSC standards – Reduced cross colour and cross luminance artefacts

• PAL delay line for correcting PAL phase errors

• Brightness Contrast Saturation (BCS) adjustment, separately for composite and baseband signals

• User programmable sharpness control

• Detection of copy-protected signals according to the macrovision standard, indicating level of protection

• Independent gain and offset adjustment for raw data path.

Component video processing

• RGB component inputs

• Y-P

-PR component inputs

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• Fast blanking between CVBS and synchronous component inputs

• Digital RGB to Y-C

-CR matrix.

Video scaler

• Horizontal and vertical downscaling and upscaling to randomly sized windows

• Horizontal and vertical scaling range: variable zoom to 1/64 (icon) (note: H and V zoom are restricted by the transfer data rates)

• Anti-alias and accumulating filter for horizontal scaling

• Vertical scaling with linear phase interpolation and accumulating filter for anti-aliasing (6-bit phase accuracy)

• Horizontal phase correct up and downscaling for improved signal quality of scaled data, especially for compression and video phone applications, with 6-bit phase accuracy (1.2 ns step width)

• Two independent programming sets for scaler part, to define two ‘ranges’ per field or sequences over frames

• Fieldwise switching between decoder part and expansion port (X-port) input

• Brightness, contrast and saturation controls for scaled outputs.

Vertical Blanking Interval (VBI) data decoder and slicer

• Versatile VBI-data decoder, slicer, clock regeneration and byte synchronization e.g. for World Standard Teletext (WST), North-American Broadcast Text System (NABTS), close caption, Wide Screen Signalling (WSS) etc.

Audio clock generation

• Generation of a field-locked audio master clock to support a constant number of audio clocks per video field

• Generation of an audio serial and left/right (channel)

Digital I/O interfaces

• Real-time signal port (R port), inclusive continuous line-locked reference clock and real-time status information supporting RTC level 3.1 (refer to document “RTC Functional Specification” for details)

• Bidirectional expansion port (X-port) with half duplex functionality (D1), 8-bit Y-C

-CR

– Output from decoder part, real-time and unscaled – Input to scaler part, e.g. video from MPEG decoder (extension to 16-bit possible)

• Video image port (I-port) configurable for 8-bit data (extension to 16-bit possible) in master mode (own clock), or slave mode (external clock), with auxiliary timing and handshake signals

• Discontinuous data streams supported

• 32-word ´ 4-byte FIFO register for video output data

• 28-word ´ 4-byte FIFO register for decoded VBI-data output

• Scaled 4 :2 :2, 4 :1 :1, 4 :2 :0, 4 :1 :0 Y-C

-CR output

• Scaled 8-bit luminance only and raw CVBS data output

• Sliced, decoded VBI-data output.

Miscellaneous

• Power-on control

• 5 V tolerant digital inputs and I/O ports

• Software controlled power saving standby modes supported

• Programming via serial I 2 C-bus, full read back ability by an external controller, bit rate up to 400 kbits/s

• Boundary scan test circuit complies with the “IEEE Std. 1149.b1 - 1994”

• BGA156 package.

12.20.3.

Pinning

SYMBOL PIN TYPE DESCRIPTION

XTOUT A2 O crystal oscillator output signal; auxiliary signal XTALO A3 O 24.576 MHz (32.11 MHz) crystal oscillator output; not

connected if TTL clock input of XTALI is used

A4 P ground for crystal oscillator

SS(xtal)

TDO A5 O test data output for boundary scan test; note 2 XRDY A6 O task flag or ready signal from scaler, controlled by XRQT XCLK A7 I/O clock I/O expansion port

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XPD0 A8 I/O LSB of expansion port data XPD2 A9 I/O MSB - 5 of expansion port data XPD4 A10 I/O MSB - 3 of expansion port data XPD6 A11 I/O MSB - 1 of expansion port data TEST1 A12 I/pu do not connect, reserved for future extensions and for testing:

scan input

TEST2 A13 I/pu do not connect, reserved for future extensions and for testing:

scan input AI41 B1 I analog input 41 TEST3 B2 O do not connect, reserved for future extensions and for testing V

B3 P supply voltage for crystal oscillator

DD(xtal)

XTALI B4 I input terminal for 24.576 MHz (32.11 MHz) crystal oscillator

or connection of external oscillator with TTL compatible

square wave clock signal TDI B5 I/pu test data input for boundary scan test; note 2 TCK B6 I/pu test clock for boundary scan test; note 2 XDQ B7 I/O data qualifier for expansion port XPD1 B8 I/O MSB - 6 of expansion port data XPD3 B9 I/O MSB - 4 of expansion port data XPD5 B10 I/O MSB - 2 of expansion port data XTRI B11 I X-port output control signal, affects all X-port pins (XPD7 to

XPD0, XRH, XRV, XDQ and XCLK), enable and active

polarity is under software control (bits XPE in subaddress

83H) TEST4 B12 O do not connect, reserved for future extensions and for testing:

scan output TEST5 B13 NC do not connect, reserved for future extensions and for testing TEST6 B14 NC do not connect, reserved for future extensions and for testing VSSA4 C1 P ground for analog inputs AI4x

AGND C2 P analog ground TEST7 C3 NC do not connect, reserved for future extensions and for testing TEST8 C4 NC do not connect, reserved for future extensions and for testing V

C5 P digital supply voltage 1 (peripheral cells)

DDD1

TRST C6 I/pu test reset input (active LOW), for boundary scan test (with

internal pull-up); notes 2, 3 and 4 XRH C7 I/O horizontal reference I/O expansion port V

C8 P digital supply voltage 2 (core)

DDD2

C9 P digital supply voltage 3 (peripheral cells)

DDD3

C10 P digital supply voltage 4 (core)

DDD4

XPD7 C11 I/O MSB of expansion port data TEST9 C12 NC do not connect, reserved for future extensions and for testing TEST10 C13 NC do not connect, reserved for future extensions and for testing TEST11 C14 I/pu do not connect, reserved for future extensions and for testing:

scan input AI43 D1 I analog input 43 AI42 D2 I analog input 42 AI4D D3 I differential input for ADC channel 4 (pins AI41 to AI44) V

D4 P analog supply voltage for analog inputs AI4x (3.3 V)

DDA4

D5 P digital ground 1 (peripheral cells)

SSD1

TMS D6 I/pu test mode select input for boundary scan test or scan test;

note 2 V

D7 P digital ground 2 (core; substrate connection)

SSD2

XRV D8 I/O vertical reference I/O expansion port V

D9 P digital ground 3 (peripheral cells)

SSD3

D10 P digital ground 4 (core)

SSD4

D11 P digital ground 5 (peripheral cells)

SSD5

D12 P digital supply voltage 5 (peripheral cells)

DDD5

TEST12 D13 I/pu do not connect, reserved for future extensions and for testing:

scan input HPD0 D14 I/O LSB of host port data I/O, extended CB -CR input for

expansion port, extended C

-CR output for image port

AI44 E1 I analog input 44 V

E2 P analog supply voltage for analog inputs AI4x (3.3 V)

DDA4A

AI31 E3 I analog input 31

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E4 P ground for analog inputs AI3x

SSA3

HPD1 E11 I/O MSB - 6 of host port data I/O, extended CB -CR input for

expansion port, extended C

-CR output for image port

HPD3 E12 I/O MSB - 4 of host port data I/O, extended CB -CR input for

expansion port, extended C

-CR output for image port

HPD2 E13 I/O MSB - 5 of host port data I/O, extended CB -CR input for

expansion port, extended C

-CR output for image port

HPD4 E14 I/O MSB - 3 of host port data I/O, extended CB -CR input for

expansion port, extended C

-CR output for image port

AI3D F1 I/O differential input for ADC channel 3 (pins AI31 to AI34) AI32 F2 I analog input 32 AI33 F3 I analog input 33 V

F4 P analog supply voltage for analog inputs AI3x (3.3 V)

DDA3

F11 P digital ground 6 (core)

SSD6

F12 P digital supply voltage 6 (core)

DDD6

HPD5 F13 I/O MSB - 2 of host port data I/O, extended CB -CR input for

expansion port, extended C

-CR output for image port

HPD6 F14 I/O MSB - 1 of host port data I/O, extended CB -CR input for

expansion port, extended C

-CR output for image port

AI34 G1 I analog input 34 V

G2 P analog supply voltage for analog inputs AI3x (3.3 V)

DDA3A

AI22 G3 I analog input 22 AI21 G4 I analog input 21 V

G11 P digital ground 7 (peripheral cells)

SSD7

IPD1 G12 O MSB - 6 of image port data output HPD7 G13 I/O MSB of host port data I/O, extended CB -CR R input for

expansion port, extended C

-CR output for image port

IPD0 G14 O LSB of image port data output AI2D H1 I differential input for ADC channel 2 (pins AI24 to AI21) AI23 H2 I analog input 23 V

H3 P ground for analog inputs AI2x

SSA2

H4 P analog supply voltage for analog inputs AI2x

DDA2

IPD2 H11 O MSB - 5 of image port data output V

H12 P digital supply voltage 7 (peripheral cells)

DDD7

IPD4 H13 O MSB - 3 of image port data output IPD3 H14 O MSB - 4 of image port data output V

J1 P analog supply voltage for analog inputs AI2x

DDA2A

AI11 J2 I analog input 11 AI24 J3 I analog input 24 V

J4 P ground for analog inputs AI1x

SSA1

J11 P digital ground 8 (core)

SSD8

J12 P digital supply voltage 8 (core)

DDD8

IPD6 J13 O IPD5 J14 O

MSB − 1 of image port data output

MSB − 2 of image port data output AI12 K1 I analog input 12 AI13 K2 I analog input 13 AI1D K3 I differential input for ADC channel 1 (pins AI14 to AI11) V

K4 P analog supply voltage for analog inputs AI1x (3.3 V)

DDA1

IPD7 K11 O MSB of image port data output IGPH K12 O multi purpose horizontal reference output signal; image port

(controlled by subaddresses 84H and 85H) IGP1 K13 O general purpose output signal 1; image port (controlled by

subaddresses 84H and 85H) IGPV K14 O multi purpose vertical reference output signal; image port

(controlled by subaddresses 84H and 85H) V

L1 P analog supply voltage for analog inputs AI1x (3.3 V)

DDA1A

AGNDA L2 P analog signal ground AI14 L3 I analog input 14 V

L4 P digital ground 9 (peripheral cells)

SSD9

L5 P digital ground 10 (core)

SSD10

ADP6 L6 O MSB - 2 of direct analog-to-digital converted output data

(VSB) ADP3 L7 O MSB - 5 of direct analog-to-digital converted output data

(VSB)

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L8 P digital ground 11 (peripheral cells)

SSD11

L9 P digital ground 12 (core)

SSD12

RTCO L10 O/st/pd real-time control output; contains information about actual

system clock frequency, field rate, odd/even sequence,

decoder status, subcarrier frequency and phase and PAL

sequence; the RTCO pin is enabled via I

C-bus bit RTCE;

see notes 5, 6 V

L11 P digital ground 13 (peripheral cells)

SSD13

ITRI L12 I/(O) image port output control signal, affects all input port pins

inclusive ICLK, enable and active polarity is under software

control (bits IPE in subaddress 87H); output path used for

testing: scan output IDQ L13 O output data qualifier for image port (optional: gated clock

output) IGP0 L14 O general purpose output signal 0; image port (controlled by

subaddresses 84H and 85H) AOUT M1 O analog test output (do not connect) V

M2 P ground for internal Clock Generation Circuit (CGC)

SSA0

M3 P analog supply voltage (3.3 V) for internal clock generation

DDA0

circuit V

M4 P

DDD9

M5 P

DDD10

ADP7 M6 O

ADP2 M7 O

M8 P

DDD11

M9 P

DDD12

RTS0 M10 O

M11 P

DDD13

AMXCLK M12 I FSW M13 I/pd

ICLK M14 I/O

digital supply voltage 9 (peripheral cells)

digital supply voltage 10 (core)

MSB − 1 of direct analog-to-digital converted output data

(VSB)

MSB − 6 of direct analog-to-digital converted output data

(VSB)

digital supply voltage 11 (peripheral cells)

digital supply voltage 12 (core)

real-time status or sync information, controlled by

subaddresses 11H and 12H

digital supply voltage 13 (peripheral cells)

audio master external clock input

fast switch (blanking) with internal pull-down inserts

component inputs into CVBS signal

clock output signal for image port, or optional

asynchronous back-end clock input

TEST13 N1 NC do not connect, reserved for future extensions and for testing TEST14 N2 I/pu do not connect, reserved for future extensions and for testing TEST15 N3 I/pd do not connect, reserved for future extensions and for testing CE N4 I/pu chip enable or reset input (with internal pull-up) LLC2 N5 O line-locked 1 ¤2 clock output (13.5 MHz nominal) CLKEXT N6 I external clock input intended for analog-to-digital conversion

of VSB signals (36 MHz) ADP5 N7 O MSB - 3 of direct analog-to-digital converted output data

(VSB) ADP0 N8 O LSB of direct analog-to-digital converted output data (VSB) SCL N9 I serial clock input (I 2 C-bus) RTS1 N10 O real-time status or sync information, controlled by

subaddresses 11H and 12H ASCLK N11 O audio serial clock output ITRDY N12 I target ready input for image port data TEST16 N13 NC do not connect, reserved for future extensions and for testing TEST17 N14 NC do not connect, reserved for future extensions and for testing TEST18 P2 I/O do not connect, reserved for future extensions and for testing EXMCLR P3 I/pd

external mode clear (with internal pull-down)

LLC P4 O line-locked system clock output (27 MHz nominal) RES P5 O reset output (active LOW) ADP8 P6 O MSB of direct analog-to-digital converted output data (VSB) ADP4 P7 O MSB - 4 of direct analog-to-digital converted output data

(VSB) ADP1 P8 O MSB - 7 of direct analog-to-digital converted output data

(VSB) INT_A P9 O/od I2C-bus interrupt flag (LOW if any enabled status bit has

changed)

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SDA P10 I/O/od serial data input/output (I 2 C-bus) AMCLK P11 O audio master clock output, up to 50% of crystal clock ALRCLK P12 O/st/pd audio left/right clock output; can be strapped to supply via a

3.3 kW resistor to indicate

that the default 24.576 MHz crystal (ALRCLK = 0; internal

pull-down) has been replaced

by a 32.110 MHz crystal (ALRCLK = 1); see notes 5 and 7 TEST19 P13 I/pu do not connect, reserved for future extensions and for testing:

scan input

Notes

1. I = input, O = output, P = power, NC = not connected, st = strapping, pu = pull-up, pd = pull-down, od = open-drain.

2. In accordance with the “IEEE1149.1” standard the pads TDI, TMS, TCK and TRST are input pads with an internal pull-up transistor and TDO is a 3-state output pad.

3. For board design without boundary scan implementation connect the TRST pin to ground.

4. This pin provides easy initialization of the Boundary Scan Test (BST) circuit. TRST can be used to force the Test Access Port (TAP) controller to the TEST_LOGIC_RESET state (normal operation) at once.

5. Pin strapping is done by connecting the pin to the supply via a 3.3 κΩ resistor. During the power-up reset sequence the corresponding pins are switched to input mode to read the strapping level. For the default setting no strapping resistor is necessary (internal pull-down).

6. Pin RTCO operates as I 2 C-bus slave address pin; RTCO = 0 slave address 42H/43H (default); RTCO = 1 slave address 40H/41H.

7. Pin ALRCLK: 0 = 24.576 MHz crystal (default; Philips order number 4322 143 05291); 1 = 32.110 MHz crystal

12.21. TPS72501

12.21.1. General Description

The TPS725xx family of 1-A low-dropout (LDO) linear regulators has fixed voltage options available that are commonly used to power the latest DSPs, FPGAs, and microcontrollers. An adjustable option ranging from 1.22 V to 5.5 V is also available. The integrated supervisory circuitry provides an active low RESET signal when the output falls out of regulation. The no capacitor/any capacitor feature allows the customer to tailor output transient performance as needed. Therefore, compared to other regulators capable of providing the same output current, this family of regulators can provide a stand alone power supply solution or a post regulator for a switch mode power supply. These regulators are ideal for higher current applications. The family operates over a wide range of input voltages (1.8 V to 6 V) and has very low dropout (170 mV at 1-A). Ground current is typically 210 µA at full load and drops to less than 80 µA at no load. Standby current is less than 1 µA. Each regulator option is available in either a SOT223–5, D (TPS72501 only), or DDPAK package. With a low input voltage and properly heatsinked package, the regulator dissipates more power and achieves higher efficiencies than similar regulators requiring 2.5 V or more minimum input voltage and higher quiescent currents. These features make it a viable power supply solution for portable, battery powered equipment. Although an output capacitor is not required for stability, transient response and output noise are improved with a 10-µF output capacitor. Unlike some regulators that have a minimum current requirement, the TPS725 family is stable with no output load current. The low noise capability of this family, coupled with its high current operation and

27” TFT TV Service Manual 05/09/2005

ease of power dissipation, make it ideal for telecom boards, modem banks, and other noise sensitive applications.

12.21.2. Features

• 1-A Output Current

• Available in 1.5-V, 1.6-V, 1.8-V, 2.5-V Fixed-Output and Adjustable Versions (1.2-V to 5.5-V)

• Input Voltage Down to 1.8 V

• Low 170-mV Dropout Voltage at 1 A (TPS72525)

• Stable With Any Type/Value Output Capacitor

• Integrated Supervisor (SVS) With 50-ms RESET Delay Time

• Low 210-µA Ground Current at Full Load (TPS72525)

• Less than 1-µA Standby Current

• ±2% Output Voltage Tolerance Over Line, Load, and Temperature (–40C to 125C)

• Integrated UVLO

• Thermal and Overcurrent Protection

• 5-Lead SOT223–5 or DDPAK and 8–Pin SOP (TPS72501 only) Surface Mount Package

27” TFT TV Service Manual 05/09/2005

12.22.

TSOP1136

12.23.

PCF8591

12.23.1. General Description

The PCF8591 is a single-chip, single-supply low power 8-bit CMOS data acquisition device with four analog inputs, one analog output and a serial I Three address pins A0, A1 and A2 are used for programming the hardware address, allowing the use of up to eight devices connected to the I

C-bus without additional hardware. Address, control and data to

and from the device are transferred serially via the two-line bidirectional I

C-bus interface.

C-bus. The functions of the device include analog input multiplexing, on-chip track and hold function, 8-bit analog-to-digital conversion and an 8-bit digital-to-analog conversion. The maximum conversion rate is given by the maximum speed of the I

C-bus.

12.23.2. Features

• Single power supply

• Operating supply voltage 2.5 V to 6 V

• Low standby current

• Serial input/output via I 2 C-bus

• Address by 3 hardware address pins

• Sampling rate given by I 2 C-bus speed

• 4 analog inputs programmable as single-ended or differential inputs

• Auto-incremented channel selection

•

Analog voltage range from VSS to VDD

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On-chip track and hold circuit

•

• 8-bit successive approximation A/D conversion

• Multiplying DAC with one analog output.

12.23.3. Pinning

SYMBOL PIN DESCRIPTION

AINO 1 analog inputs (A/D converter) AIN1 2 AIN2 3 AIN3 4 A0 5 hardware address A1 6 A2 7 V

8 negative supply voltage

SDA 9 I2C-bus data input/output SCL 10 I2C-bus clock input OSC 11 oscillator input/output EXT 12 external/internal switch for oscillator input AGND 13 analog ground V

14 voltage reference input

REF

AOUT 15 analog output (D/A converter) VDD 16 positive supply voltage

12.24.

PW1231

12.24.1. General Description

The PW1231 is a high-quality, digital video signal processor that incorporates Pixelworks’ patented deinterlacing, scaling, and video enhancement algorithms. The PW1231 accepts industry-standard video formats and resolutions, and converts the input into any desired output format. The video algorithms are highly efficient, providing excellent quality video. The PW1231 Video SignalProcessor combines many functions into a single device, including memory controller, auto-configuration, and others. This high level of integration enables simple, flexible, costeffective solutions featuring fewer required components.

12.24.2. Features

• Built-In Memory Controller

• Motion-Adaptive Deinterlace Processor

• Intelligent Edge Deinterlacing

• Digital Color/Luminance Transient Improvement (DCTI/DLTI)

• Interlaced Video Input Options, including NTSC and PAL

• Independent horizontal and vertical scaling

• Copy Protection

• Two-Wire Serial Interface

12.24.3. Applications

For use with Digital Displays

• Flat-Panel (LCD, DLP) TVs

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• Rear Projection TVs

• Plasma Displays

• LCD Multimedia Monitors

• Multimedia Projectors

12.25.

The PW181 ImageProcessor is a highly integrated “system-on-a-chip” that interfaces computer graphics and video inputs in virtually any format to a fixed-frequency flat panel display. Computer and video images from NTSC/PAL to WUXGA at virtually any refresh rate can be resized to fit on a fixed-frequency target display device with any resolution up to WUXGA. Video data from 4:3 aspect ratio NTSC or PAL and 16:9 aspect ratio HDTV or SDTV is supported. Multi-region, nonlinear scaling allows these inputs to be resized optimally for the native resolution of the display. Advanced scaling techniques are supported, such as format conversion using multiple programmable regions. Three independent image scalers coupled with frame locking circuitry and dual programmable color lookup tables create sharp images in multiple windows, without user intervention. Embedded SDRAM frame buffers and memory controllers perform frame rate conversion and enhanced video processing completely on-chip. A separate memory is dedicated to storage of onscreen display images and CPU general purpose use. Advanced video processing techniques are supported using the internal frame buffer, including motion adaptive, temporal deinterlacing with film mode detection. When used in combination with the new third-generation scaler, this advanced video processing technology delivers the highest quality video for advanced displays. Both input ports support integrated DVI 1.0 content protection using standard DVI receivers. A new advanced OSD Generator with more colors and larger sizes supports more demanding OSD applications, such as on-screen programming guides. When coupled with the new, faster, integrated microprocessor, this OSD Generator supports advanced OSD animation techniques. Programmable features include the user interface, custom start-up screen, all automatic imaging features, and special screen effects.

PW181

12.25.1. General Description

12.25.2. Features

• Third-generation, two-dimensional filtering techniques

• Third-generation, advanced scaling techniques

• Second-generation Automatic Image Optimization

• Frame rate conversion

• Video processing

• On-Screen Display (OSD)

• On-chip microprocessor

• JTAG debugger and boundary scan

• Picture-in-picture (PIP)

• Multi-region, non-linear scaling

• Hardware 2-wire serial bus support

12.25.3. Applications

• Multimedia Displays

• Plasma Displays

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• Digital Television

12.26.

The SiI 1169 receiver uses PanelLink Digital technology to support high-resolution digital displays for PC and HDTV applications. The SiI 1169 device features High-bandwidth Digital Content Protection HDCP) for secure delivery of high-definition video, and comes with integrated, pre-programmed HDCP eys to simplify manufacturing and provide the highest level of security.

• Integrated 25-165MHz PanelLink DVI 1.0 compliant core supports VGA to UXGA resolutions

• Supports HDTV resolutions (720p/1080i/1080p)

• Integrated HDCP decryption engine for viewing protected content

• Pre-programmed HDCP keys provide highest level of key security, simplify manufacturing

• Backwards compatible with SiI 161B, SiI 169, SiI 1161, SiI 163B, and TFP401

• Flexible low power modes with automatic power down when input clock is inactive

• Cost-reducing 5V-tolerant DDC I2C interface

• Universal Pb-free package

SIL1169

12.26.1. General Description

12.26.2. Features

12.26.3. Pin Connections

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12.27.

The Micron ® 64Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 67,108,864 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’s 16,777,216-bit banks is orga-nized as 4,096 rows by 1,024 columns by 4 bits. Each of the x8’s 16,777,216-bit banks is organized as 4,096 rows by 512 columns by 8 bits. Each of the x16’s 16,777,216- bit banks is organized as 4,096 rows by 256 columns by 16 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A11 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. The SDRAM provides for programmable READ or WRITE burst lengths of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. An auto precharge function may be enabled to provide a selftimed row precharge that is initiated at the end of the burst sequence. The 64Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation. This

architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column

address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, random-access operation. The 64Mb SDRAM is designed to operate in 3.3V memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible. SDRAMs offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks in order to hide precharge time and the capability to randomly change column addresses on each clock cycle during a burst access.

SDRAM 4M x 16 (MT48LC4M16A2TG-75)

12.27.1. General Description

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12.27.2. Features

• PC66-, PC100-, and PC133-compliant

• Fully synchronous; all signals registered on positive edge of system clock

• Internal pipelined operation; column address can be changed every clock cycle

• Internal banks for hiding row access/precharge

• Programmable burst lengths: 1, 2, 4, 8, or full page

• Auto Precharge, includes CONCURRENT AUTO PRECHARGE, and Auto Refresh Modes

• Self Refresh Modes: standard and low power

• 64ms, 4,096-cycle refresh

• LVTTL-compatible inputs and outputs

• Single +3.3V ±0.3V power supply

12.27.3. Pin Descriptions

PIN NUMBERS SYMBOL TYPE DESCRIPTION

38 CLK Input Clock: CLK is driven by the system clock. All SDRAM input

signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers.

37 CKE Input Clock Enable: CKE activates (HIGH) and deactivates (LOW)

the CLK signal. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), ACTIVE POWER-DOWN (row active in any bank) or CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous except after the device enters power-down and self refresh modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CLK, are disabled during power-down and self refresh modes, providing low standby power. CKE may be tied HIGH.

19 CS# Input Chip Select: CS# enables (registered LOW) and disables

(registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code.

16, 17, 18 WE#, CAS#,

RAS#

39 x4, x8: DQM

15, 39 x16: DQML,

DQMH

20, 21 BA0, BA1 Input Bank Address Inputs: BA0 and BA1 define to which bank the

23-26, 29-34, 22, 35

2, 4, 5, 7, 8, 10, 11, 13, 42, 44, 45, 47, 48, 50, 51, 53 2, 5, 8, 11, 44, 47, 50, 53 5, 11, 44, 50 DQ0-DQ3 x4: I/O Data Input/Output: Data bus for x4.

40 NC – No Connect: These pins should be left unconnected.

A0-A11 Input Address Inputs: A0-A11 are sampled during the ACTIVE

DQ0-DQ15 x16: I/O Data Input/Output: Data bus for x16 (4, 7, 10, 13, 42, 45, 48,

DQ0-DQ7 x8: I/O Data Input/Output: Data bus for x8 (2, 8, 47, 53 are NCs for

Input Command Inputs: WE#, CAS#, and RAS# (along with CS#)

define the command being entered.

Input Input/Output Mask: DQM is an input mask signal for write

accesses and an output enable signal for read accesses. Input data is masked when DQM is sampled HIGH during a WRITE cycle. The output buffers are placed in a High-Z state (twoclock latency) when DQM is sampled HIGH during a READ cycle. On the x4 and x8, DQML (Pin 15) is a NC and DQMH is DQM. On the x16, DQML corresponds to DQ0-DQ7 and DQMH corresponds to DQ8-DQ15. DQML and DQMH are considered same state when referenced as DQM.

ACTIVE, READ, WRITE or PRECHARGE command is being applied.

command (row-address A0-A11) and READ/WRITE command (column-address A0-A9 [x4]; A0-A8 [x8]; A0-A7 [x16]; with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10[HIGH]) or bank selected by BA0, BA1 (A1[LOW]). The address inputs also provide the op-code during a LOAD MODE REGISTER command.

and 51 are NCs for x8; and 2, 4, 7, 8, 10, 13, 42, 45, 47, 48, 51, and 53 are NCs for x4).

x4).

27” TFT TV Service Manual 05/09/2005

36 NC – Address input (A12) for the 256Mb and 512Mb devices 3, 9, 43, 49 VDDQ Supply DQ Power: Isolated DQ power on the die for improved noise

immunity.

6, 12, 46, 52 VSSQ Supply DQ Ground: Isolated DQ ground on the die for improved noise

immunity. 1, 14, 27 VDD Supply Power Supply: +3.3V ±0.3V. 28, 41, 54 VSS Supply Ground.

12.28.

FLASH 16MBit

12.28.1. Description

The M29W160E is a 16 Mbit (2Mb x8 or 1Mb x16) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (2.7 to 3.6V) supply. On power-up the memory defaults to its Read mode where it can be read in the same way as a ROM or EPROM. The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. Each block can be protected independently to prevent accidental Program or Erase commands from modifying the memory. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards. The blocks in the memory are asymmetrically arranged, ee Figures 5 and 6, Block Addresses. he first or last 64 KBytes have been divided into our additional blocks. The 16 KByte Boot Block can be used for small initialization code to start the microprocessor, the two 8 KByte Parameter Blocks can be used for parameter storage and the remaining 32K is a small Main Block where the application may be stored. Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory. They allow simple connection to most microprocessors, often without additional logic. The memory is offered TSOP48 (12 x 20mm) and TFBGA48 (0.8mm pitch) packages. The memory is supplied with all the bits erased (set to ’1’).

12.28.2. FEATURES SUMMARY

■ SUPPLY VOLTAGE

– V

CC = 2.7V to 3.6V for Program, Erase and Read

■ ACCESS TIMES: 70, 90ns

■ PROGRAMMING TIME

– 10µs per Byte/Word typical

■ 35 MEMORY BLOCKS

– 1 Boot Block (Top or Bottom Location) – 2 Parameter and 32 Main Blocks

■ PROGRAM/ERASE CONTROLLER

– Embedded Byte/Word Program algorithms

■ ERASE SUSPEND and RESUME MODES

– Read and Program another Block during Erase Suspend

■ UNLOCK BYPASS PROGRAM COMMAND

– Faster Production/Batch Programming

■ TEMPORARY BLOCK UNPROTECTION MODE

■ COMMON FLASH INTERFACE

– 64 bit Security Code

■ LOW POWER CONSUMPTION

– Standby and Automatic Standby

■ 100,000 PROGRAM/ERASE CYCLES per BLOCK

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 0020h – Top Device Code M29W160ET: 22C4h – Bottom Device Code M29W160EB: 2249h

27” TFT TV Service Manual 05/09/2005

12.29.

12.29.1. Description

The ASM3P28XX devices are versatile spread spectrum frequency modulators designed specifically for a wide range of input clock frequencies from 10MHz to 40MHz. The ASM3P28XX reduces electromagnetic interference (EMI) at the clock source, allowing system wide reduction of EMI of down stream clock and data dependent signals. The ASM3P28XX modulates the output of a single PLL in order to “spread” the bandwidth of a synthesized clock, and more importantly, decreases the peak amplitudes of its harmonics. This results in significantly lower system EMI compared to the typical narrow band signal produced by oscillators and most frequency generators. Lowering EMI by increasing a signal’s bandwidth is called ‘spread spectrum clock generation’. The ASM3P28XX uses the most efficient and optimized modulation profile approved by the FCC and is implemented in a proprietary all-digital method.

12.29.2. Features

• FCC approved method of EMI attenuation.

• Provides up to 15dB EMI reduction.

• Generates a 1X, 2X and 4X low EMI spread spectrum clock of the input frequency.

• Optimized for input frequency range from 10MHz to 40 MHz.

• Selectable spread options: Down Spread and Center Spread.

• Low inherent cycle-to-cycle jitter.

12.29.3. Pin Descriptions

ASM3P2814

27” TFT TV Service Manual 05/09/2005

12.30.

74LX1G86

12.30.1. Features

• 5V TOLERANT INPUTS

• HIGH SPEED: t

= 5ns (MAX.) at VCC = 3V

• LOW POWER DISSIPATION: ICC = 1A (MAX.) at TA = 25°C

• POWER DOWN PROTECTION ON INPUTS AND OUTPUTS

• SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) at VCC = 3V

 t

• BALANCED PROPAGATION DELAYS: t

• OPERATING VOLTAGE RANGE: V

(OPR) = 1.65V to 5.5V (1.2V Data Retention)

PLH

PHL

• IMPROVED LATCH-UP IMMUNITY

12.30.2. Description

The 74LX1G86 is a low voltage CMOS SINGLE EXCLUSIVE OR GATE fabricated with sub-micron silicon gate and double-layer metal wiring C

MOS technology. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. All inputs and outputs are equipped with protection circuits against static discharge.

12.30.3. Pin Connections and Descriptions

27” TFT TV Service Manual 05/09/2005

12.31.

74HCT4053

12.31.1. General Description

74HCT4053 is a high-speed Si-gate CMOS device, which has a triple 2-channel analogue multiplexer / demultiplexer with a common enable input. V

and GND are the supply voltage pins for the digital control inputs The VCC to GND ranges are 4.5 to

5.5 V for HCT. The analog inputs/outputs (nY0 and nY1, and nZ) can swing between V limit and V

as a negative limit. VCC - V

may not exceed 10.0 V.

as a positive

12.31.2. Pin Description

27” TFT TV Service Manual 05/09/2005

13. IC DESCRIPTIONS (FOR DIGITAL)

STI5518 24C32

MAX232_SMD STV0360

74HCU04 MAX809

TSH22 TDCC2345TV39A

CS4334 STV0700

AMIC A43L2616

MX29LV160T

13.1.

The STi5518 is a highly integrated single-chip decoder, designed for use in feature-rich mass-market set-top boxes. It integrates a high-performance 32-bit CPU, a dedicated block for DVB/DirecTV transport demultiplexing and descrambling, modules for MPEG-2 video and audio decoding with 3Dsurround and MP3 support, advanced display and graphics features, a digital video encoder and all of the system peripherals required in a typical low-cost interactive receiver. To cover the needs of DVD-capable set-top boxes, STi5518 integration options include a CSS decryption block, a Dolby Digital audio decoder and Macrovision copy protection. An ATAPI interface is built-in, supporting the glueless connection of standard Hard Disk Drives. In this way, the STi5518 is ideal for set-top boxes featuring trick modes such as live TV recording, pausing and time-shifting. The STi5518 is backward compatible with the popular STi5500 set-top box decoder, allowing easy migration from the previous generation. The high level of integration in a single PQFP-208 package makes the STi5518 ideally suited for lowcost, high-volume set-top box applications.

13.2.

The MAX220–MAX249 family of line drivers/receivers is intended for all EIA/TIA-232E and V.28/V.24 communications interfaces, particularly applications where ±12V is not available. These parts are especially useful in battery-powered systems, since their low-power shutdown mode reduces power dissipation to less than 5µW. The MAX225, MAX233, MAX235, and MAX245/MAX246/MAX247 use no external components and are recommended for applications where printed circuit board space is critical.

STI5518

13.1.1. General Description

MAX232_SMD

13.2.1. General Description

13.2.2. Features

• Operate from Single +5V Power Supply (+5V and +12V—MAX231/MAX239)

• Low-Power Receive Mode in Shutdown (MAX223/MAX242)

• Meet All EIA/TIA-232E and V.28 Specifications

• Multiple Drivers and Receivers

• 3-State Driver and Receiver Outputs

• Open-Line Detection (MAX243)

27” TFT TV Service Manual 05/09/2005

13.3.

74HCU04

13.3.1. General Description

The M54/74HCU04 is a high speed CMOS HEX INVERTER (SINGLE STAGE) fabricated in silicon gate

MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. As the internal circuit is composed of a single stage inverter, it can be used in crystal oscillator. All inputs are equipped with circuits against static discharge and transient excess voltage.

13.3.2. Pin Description

27” TFT TV Service Manual 05/09/2005

13.4.

The TSH22 is a dual bipolar operational amplifier offering a single supply operation from 3V to 30V with very good performances: medium speed (25MHz), unity gain stability and low noise. The TSH 22 is therefore an enhanced replacement of standard dual operational amplifiers.

TSH22

13.4.1. General Description

13.4.2. Pin Connections

13.5.

The CS4334 family members are complete, stereo digital-to-analogue output systems including interpolation, 1-bit D/A conversion and output analogue filtering in an 8-pin package. The CS4334/5/6/7/8/9 support all major audio data interface formats and the individual devices differ only in the supported interface format. The CS4334 family is based on delta-sigma modulation, where the modulator output controls the reference voltage input to an ultra-linear analogue low-pass filter. This architecture allows for infinite adjustment of sample rate between 2 kHz and 100 kHz simply by changing the master clock frequency. The CS4334 family contains on-chip digital de-emphasis, operates from a single +5V power supply, and requires minimal support circuitry. These features are ideal for portable CD players and other portable playback systems.

• Complete Stereo DAC System: Interpolation, D/A, Output Analogue Filtering

• 24-Bit Conversion

• 96 dB Dynamic Range

• Low Distortion

• Low Clock Jitter Sensitivity

• Single 5 V Power Supply

• Filtered Line Level Outputs

• On-Chip Digital De-emphasis

• Soft Ramp to Quiescent Output Voltage

• Functionally Compatible with CS4330/31/33

CS4334

13.5.1. General Description

13.5.2. Features

27” TFT TV Service Manual 05/09/2005

13.6.

The A43L2616-PH is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 X 1,048,576 words by 16 bits, fabricated with AMIC’s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications.

• JEDEC standard 3.3V power supply

• LVTTL compatible with multiplexed address

• Four banks / Pulse RAS

• MRS cycle with address key programs

• All inputs are sampled at the positive going edge of the system clock

• Clock Frequency: 166MHz @ CL=3

143MHz @ CL=3

• Burst Read Single-bit Write operation

• DQM for masking

• Auto & self refresh

• 64ms refresh period (4K cycle)

• 54 Pin TSOP (II)

AMIC A43L2616

13.6.1. General Description

13.6.2. Features

13.6.3. Pin Description

27” TFT TV Service Manual 05/09/2005

13.7.

The MX29LV160T/B & MX29LV160AT/AB is a 16-megabit Flash memory organized as 2M bytes of 8 bits or 1M words of 16 bits. MXIC's Flash memories offer the most cost-effective and reliable read/write non-volatile random access memory. The MX29LV160T/B & MX29LV160AT/AB is packaged in 44-pin SOP, 48-pin TSOP and 48-ball CSP. It is designed to be reprogrammed and erased in system or in standard EPROM programmers. The standard MX29LV160T/B & MX29LV160AT/AB offers access time as fast as 70ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the MX29LV160T/B &MX29LV160AT/AB has separate chip enable (CE) and output enable (OE) controls. MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The MX29LV160T/B & MX29LV160AT/AB uses a command register to manage this functionality. The command register allows for 100% TTL level control inputs and fixed power supply levels during erase and programming, while maintaining maximum EPROM compatibility. MXIC Flash technology reliably stores memory contents even after 100,000 erase and program cycles. The MXIC cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and program operations produces reliable cycling. The MX29LV160T/B & MX29LV160AT/AB uses a 2.7V~3.6V VCC supply to perform the High Reliability Erase and auto Program/Erase algorithms. The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latchup protection is proved for stresses up to 100 milliamps on address and data pin from -1V to VCC + 1V.

• Extended single - supply voltage range 2.7V to 3.6V

• 2,097,152 x 8/1,048,576 x 16 switchable

• Single power supply operation

• Fast access time: 70/90ns

• Low power consumption

• Command register architecture

• Auto Erase (chip & sector) and Auto Program

• Erase Suspend/Erase Resume

• Status Reply

• Ready/Busy pin (RY/BY)

• Sector protection

• CFI (Common Flash Interface) compliant (for MX29LV160AT/AB)

• 100,000 minimum erase/program cycles

• Latch-up protected to 100mA from -1V to VCC+1V

• Boot Sector Architecture

• Low VCC write inhibit is equal to or less than 1.4V

• Compatibility with JEDEC standard

MX29LV160T

13.7.1. General Description

13.7.2. Features

13.7.3. Pin Description

27” TFT TV Service Manual 05/09/2005

13.8.

24C32

13.8.1. General Description

The AT24C32/64 provides 32,768/65,536 bits of serial electrically erasable and programmable read only memory (EEPROM) organized as 4096/8192 words of 8 bits each. The device’s cascadable feature allows up to 8 devices to share a common 2-wire bus. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. The AT24C32/64 is available in space saving 8-pin JEDEC PDIP, 8-pin JEDEC SOIC, 8-pin EIAJ SOIC, and 8-pin TSSOP (AT24C64) packages and is accessed via a 2-wire serial interface. In addition, the entire family is available in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 5.5V) versions.

13.8.2. Features

• Low-Voltage and Standard-Voltage Operation

• Low-Power Devices (I

= 2 µA at 5.5V) Available

• Internally Organized 4096 x 8, 8192 x 8

• 2-Wire Serial Interface

• Schmitt Trigger, Filtered Inputs for Noise Suppression

• Bidirectional Data Transfer Protocol

• 100 kHz (1.8V, 2.5V, 2.7V) and 400 kHz (5V) Clock Rate

• Write Protect Pin for Hardware Data Protection

• 32-Byte Page Write Mode (Partial Page Writes Allowed)

• Self-Timed Write Cycle (10 ms max)

• High Reliability

• Automotive Grade and Extended Temperature Devices Available

• 8-Pin JEDEC PDIP, 8-Pin JEDEC SOIC, 8-Pin EIAJ SOIC, and 8-pin TSSOP Packages

13.8.3. Pin Description

SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open collector devices. DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs that are hard wired or left not connected for hardware compatibility with AT24C16. When the pins are hardwired, as many as eight 32K/64K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section). When the pins are not hardwired, the default

, A1, and A0 are zero.

WRITE PROTECT (WP): The write protect input, when tied to GND, allows normal write operations. When WP is tied high to V

, all write operations to the upper quadrant (8/16K bits) of memory are

inhibited. If left unconnected, WP is internally pulled down to GND.

27” TFT TV Service Manual 05/09/2005

13.9.

The STV0360 is a single-chip COFDM (coded orthogonal frequency division multiplex) demodulator that performs IF to MPEG-2 block processing of OFDM carriers. It is intended for digital terrestrial receivers for compressed video, sound and data services. The chip implements all the functions from the tuner IF output up to the MPEG-2 transport stream input. The STV0360 is fully compliant with the DVB-T specification (ETS 300 744) and handles 2K/8K modes. The STV0360 integrates an A/D converter that delivers the required performance to handle up to 64 QAM carriers in a direct IF sampling architecture, thus eliminating the need for an external downconverter. The chip also integrates an internal programmable gain amplifier (PGA) to compensate for SAW filter level degradation, thus eliminating the need for external IF amplifiers. A 10-bit ADC, intended for RF signal strength indication, eliminates the need for external components when using wide-band AGC tuners. In addition to all the demodulation and FEC (forward error correction) functions required for recovery of the QAM modulated bit streams with very low BER, it also includes several features that give easy and immediate access to various quality monitoring parameters or lock status. The STV0360 also provides output such as delayed AGC or noise-free I²C bus dedicated to tuner control, which facilitates the design of high quality integrated receiver decoders. The STV0360 outputs error-corrected MPEG-2 transport streams and complies with the DVB common interface format, with programmable data clock frequency. It also interfaces seamlessly with the packet de-multiplexers embedded in the STi55xx Omega family of single-chip decoders.

• Decodes DVB-T (ETS300744) and NorDig II

• TPS decoded or automatic FEC mode detection

• Embeds PGA for IF level adaptation

• Generates system clock on-chip from 20 to 27-MHz crystal quartz

• Four I²C addresses available

• Low power consumption (< 500 mW)

• Small footprint: TQFP64 (10 X 10 mm)

• 1.8 V operation, CMOS technology

STV0360

13.9.1. General Description

13.9.2. Features

13.9.3. Pin Description

27” TFT TV Service Manual 05/09/2005

13.10.

MAX809

13.10.1. General Description

The MAX803/MAX809/MAX810 are microprocessor (µP) supervisory circuits used to monitor the power supplies in µP and digital systems. They provide excellent circuit reliability and low cost by eliminating external components and adjustments when used with +5V, +3.3V,+3.0V, or +2.5V powered circuits. These circuits perform a single function: they assert a reset signal whenever the V declines below a preset threshold, keeping it asserted for at least 140ms after V

supply voltage

has risen above the reset threshold. Reset thresholds suitable for operation with a variety of supply voltages are available. The MAX803 has an open-drain output stage, while the MAX809/MAX810 have push-pull outputs. The MAX803’s open-drain RESET output requires a pull-up resistor that can be connected to a voltage higher than V active-high RESET output. The reset comparator is designed to ignore fast transients on V outputs are guaranteed to be in the correct logic state for V

. The MAX803/MAX809 have an active-low RESET output, while the MAX810 has an

down to 1V. Low supply current makes

, and the

the MAX803/MAX809/MAX810 ideal for use in portable equipment. The MAX803 is available in a 3-pin SC70 package, and the MAX809/MAX810 are available in 3-pin SC70 or SOT23 packages.

13.10.2. Features

• 1 Precision Monitoring of +2.5V, +3V, +3.3V, and +5V Power-Supply Voltages

• Fully Specified Over Temperature

• Available in Three Output Configurations

Open-Drain RESET Output (MAX803) Push-Pull RESET Output (MAX809) Push-Pull RESET Output (MAX810)

• 140ms min Power-On Reset Pulse Width

• 12µA Supply Current

• Guaranteed Reset Valid to V

= +1V

• Power Supply Transient Immunity

• No External Components

• 3-Pin SC70 and SOT23 Packages

13.10.3. Pin Description

27” TFT TV Service Manual 05/09/2005

13.11.

• Receiving System : Designed to cover all bands in VHF and UHF including digital terrestrial

• Receiving Channel : 47 MHz ~ 862 MHz

• Intermediate Frequency : Digital (center) 36.125 MHz

• Input Impedance : 75, Unbalanced.

• IF Output Impedance : 75, Balanced.

• Loop through RF output Impedance : 75, Unbalanced.

• Band Change-Over System : PLL system

• Tuning System : PLL system

• Pin-out for the port to control the switchable saw

TDCC2345TV39A

13.11.1. General Description

channels for DVB-T system.

13.11.2. Pin Description

13.12.

The STV0700 controller contributes to offer an optimized, homogeneous and complete solution for digital TV receiver and Set Top Box manufacturers that want to quickly implement the Common Interface. The STV0700 includes the necessary I/Os to interface to the MPEG Transport stream generated by the receiver demodulator and daisy chain it through two independent Common Interface modules and back to the demultiplexer. The STV0700 interfaces with major digital TV receiver microprocessors. An I Signal Generator (UCSG) maps CPU control bus into Command Interface control signals. To minimize pin count, host address and data buses transit through external buffers that are driven by the STV0700. The STV0700 includes a memory mode that allows the use any of the Common Interface slots to read and write an 8-bit PC Card Memory card. This feature gives the receiver memory extension capability for software upgrade or better performance.

27” TFT TV Service Manual 05/09/2005

STV0700

13.12.1. General description

C bus is used for initialization and module selection, while a Universal Control

13.12.2. Features

• Module Interface

• 2 independent module capability

• Common Interface Standard compliant

o DVB_CI (CENELEC EN-50221) o NRSS-B (SCTE IS-679 Part B) o DAVIC v1.2 (CA0 interface)

• Memory PCMCIA compliance (R2)

o 8-bit data access o 26-bit address Memory Card

• Attribute Memory access (CIS, Tupple)

• High speed capability

o Up to 20Mbits/s on Command Interface o Up to 100Mbits/s on Transport Stream

• Polling and Interrupt modes

• Hot Insertion (Automatic and Reset VCC handling)

• 3.3V (5V tolerant) I/O buffers

• IEEE 1149.1 Boundary Scan Compliant Test Access Port

• Host microprocessor Interface

• Universal Control Signal Generator(UCSG)

o PC Card control signals generation o Supports PowerPC, ARM, ST20,68xxx, TMS, LSI 64008, TC81220F,IDTR3041 host

• I

microprocessors

C port

o STV0700 Set-up o Slot selection o Cascade mode management (up to 4STV0700)

• Chip Select bank and Interrupt facilities

• 3.3V (5V tolerant) I/O buffers

• Digital Video Stream Interface

• MPEG II Transport Stream compliant(serial/parallel configurable interface)

• 3.3V (5V tolerant) I/O buffer for direct interface with FEC and DEMUX ICs

13.12.3. Pin Description

27” TFT TV Service Manual 05/09/2005

14. SERVICE MENU SETTINGS

All system, geometry and white balance alignments are performed in production service mode. Before starting the production mode alignments, make sure that all manual adjustments are done correctly. To

start production mode alignments enter the MENU by pressing “MENU” button and then press the digits

4, 7, 2 and 5 respectively. The following menu appears on the screen.

blank colo

panel

power on time

backlight on time

scart prescale

nicam prescale

There are 4 submenus in service menu. These are display, calibration, deinterlacer and factory settings menus. Press “/” buttons to select a menu title and then “/” buttons to select a menu item and “/” or “OK” buttons to set the menu item to the desired option. To exit the service menu press “MENU” button.

Entire service menu parameters of Plasma TV are listed below.

display

black

Vestel V1.0.10 Release Build

red

down to change display settings

green blue

: 23 30

14.1. display menu

By pressing “/” buttons select the first icon. display menu appears on the screen.

blank color

panel

power on time

backlight on time

scart prescale

nicam prescale

display

blac

Vestel V1.0.10 Release Build

red

green blue

: 23 30

down to change display settings

blank color By pressing c/d button, select blank color. Press e/f button to set the blank color. The options are: black, red, green and blue.

panel

Displays panel resolution.

power on time

Displays total working time of the set.

backlight on time

Displays total backlight on time of the set. (Not used for plasma displays)

27” TFT TV Service Manual 05/09/2005

scart prescale

By pressing c/d button, select scart prescaler. Press e/f button to set the scart prescaler. Scart

prescale can be adjusted between 0 and 127.

nicam prescale

By pressing c/d button, select nicam prescaler. Press e/f button to set the nicam prescaler. Nicam

prescale can be adjusted between 0 and 127.

display

fm/am prescale

subwoofer corne

subwoofer level

agc adjustment

carrier mute

virtual dolby

virtual dolby hardware

enable disable enable disable enable disable

right/left to adjust item

fm/am prescale

By pressing c/d button, select fm/am prescaler. Press e/f button to set the fm/am prescaler. Fm/am

prescale can be adjusted between 0 and 127.

subwoofer corner

By pressing c/d button, select subwoofer corner. Press e/f button to set the subwoofer corner.

Subwoofer corner can be adjusted between 0 and 7.

subwoofer level

By pressing c/d button, select subwoofer level. Press e/f button to set the subwoofer level.

Subwoofer level can be adjusted between 0 and 32.

agc adjustment

Adjustment for automatic gain control of tuner. By pressing c/d button, select agc adjustment. Press

e/f button to set the agc adjustment. Agc adjustment can be adjusted between 0 and 31.

carrier mute

By pressing c/d button, select carrier mute. Press

e/f button to enable or disable the sound carrier

mute feature.

virtual dolby

By pressing c/d button, select virtual dolby. Press e/f button to enable or disable the virtual dolby

feature in the audio menu of the TV.

virtual dolby hardware

By pressing c/d button, select virtual dolby hardware. Press e/f button to enable or disable the

virtual dolby hardware feature of the TV.

27” TFT TV Service Manual 05/09/2005

14.2. calibration menu

By pressing “/” buttons select the second icon. calibration menu appears on the screen.

initial APS

burn-in mode

color temp

video format

calibration

5500K

6500

7500K 9300K use

of of

6500K

auto

down to change cal. settings, scrolling menu

initial APS

By pressing c/d button, select initial APS. Initial APS can be selected on or off. If initial aps is

switched on, then the TV will display initial APS menu only for the first time it is switched on.

burn-in mode By pressing c/d button, select burn-in mode. Press e/f button to set it on or off.

color temp

By pressing c/d button, select color temp. Press e/f button to set the color temperature. The options are: 5500K, 6500K, 7500K, 9300K and user.

R/G/B If color temp is set as “user”, then R/G/B settings can be adjusted. By pressing c/d button, select Red, Green or Blue. Press f button to increase the color value. Press e button to decrease the color

value. R/G/B values can be adjusted between 0 and 63.

video format

By pressing c/d button, select video format. Press

e/f button to set the video format. The options

are: auto, ntsc, pal, secam and ntsc japan.

colorspace

test pattern

color components

solid field level

factory reset

main tune

pip tune

teletext language

calibration

none

RGB

solid color vert bars

all

red green blue

<ok> to activate

Tuner 1

right/left to adjust item

27” TFT TV Service Manual 05/09/2005

color space Displays the current color space used. RGB, YPbPr SMPTE240, YPbPr REC709 and YCbCr REC601.

test pattern By pressing c/d button, select test pattern. Press e/f button to set the test pattern. The options are: none, solid color and vert bars.

color components

By pressing c/d button, select color components. Press e/f button to set the color components. The options are: all, red, green and blue.

solid field level

By pressing c/d button, select solid field level. Press f button to increase or e button to decrease

the solid field level. Solid field level can be adjusted between 0 and 64.

factory reset By pressing c/d button, select factory reset. Press “OK” button to return to the factory setting values.

main tuner By pressing c/d button, select main tuner. Press e/f button to set a tuner as main tuner.

pip tuner

By pressing c/d

button, select pip tuner. Press e/f button to set a tuner as pip tuner.

teletext language

By pressing c/d button, select teletext language. Press e/f button to set it on or off. When it is

turned on, the teletext language option can be seen in the TV menu.

27” TFT TV Service Manual 05/09/2005

14.3. deinterlacer menu

By pressing “/” buttons select the third icon. deinterlacer menu appears on the screen.

black expansion

dcti

dlti

luminance peaking

film mode

film mode speed

deinterlace

131

down for deinterlacer settings, scrolling menu

black expansion

By pressing c/d button, select black expansion. Black expantion can be set to on or off by pressing

e/f button.

dcti

Digital colour transition improvement: By pressing c/d button, select dcti. DCTI can be adjusted between 0 and 255 by pressing e/f button.

dlti

Digitial luma transition improvement: By pressing c/d button, select dlti. DLTI can be adjusted between 0 and 255 by pressing e/f button.

luminance peaking

By pressing c/d button, select luminance peaking. Luminance peaking can be set to on or off by

pressing e/f button.

film mode By pressing c/d button, select film mode. Film mode speed can be set to

on or off by pressing e/f

button.

bad cut

nr threshold

noise reduction

lai level

sharpness

sparkle

deinterlace

of of

low

high

255

right/left to adjust item

27” TFT TV Service Manual 05/09/2005

film mode speed

By pressing c/d button, select film mode speed. Film mode speed can be set to 0, 1, 2 or 3 by

pressing e/f button.

vof video on film. By pressing c/d button, select vof. VOF can be set to on or off by pressing e/f button.

bad cut By pressing c/d button, select vof. Bad cut can be set to on or off by pressing e/f button.

nr threshold

By pressing c/d button, select nr threshold. Nr threshold can be set to low or high by pressing e/f

button.

noise reduction

By pressing c/d button, select noise reduction. Noise reduction can be adjusted between 0 and 255

by pressing e/f button.

lai level

By pressing c/d button, select

lai level. Lai level can be set to 0, 1 or 2 by pressing e/f button.

sharpness

By pressing c/d button, select sharpness. Sharpness can be adjusted between 0 and 255 by

pressing e/f button.

sparkle

By pressing c/d button, select sparkle. Sparkle can be adjusted between 0 and 255 by pressing e/f

button.

27” TFT TV Service Manual 05/09/2005

14.4. factory settings menu

By pressing “/” buttons select the fourth icon. Factory settings menu appears on the screen.

brightness

contrast

sharpness

colo

volume

hp volume

factory settings

down to change factory settings

Brightness, contrast, sharpness, color, volume and headphone volume factory settings can be

seen in this menu. When factory reset is selected in the calibration menu, the values in the factory settings menu will be seen in the TV menus.

27” TFT TV Service Manual 05/09/2005

15. BLOCK DIAGRAMS

SC1_AUDIO_L/R_IN

Saw Filter

Sound

QSS Main

TUNER

(Main)

Video

Saw Filter

TUNER

(Pip)

SC1_R SC1_G SC1_B SC1_FB

SC2_R

SC2_G SC2_B

SC2_FB

2-/+ 1-/+

DVI_RX

0-/+ C-/+

PI5V330

(RGB Switch)

S Video_Y_IN S Video_C_IN

SiI1169

(TMDS Rx)

Video

Saw Filter

RGB_SW (PW181A)

PC_B PC_G PC_R

VGA

DDC_DATA_PC

DDC_CLK_PC

MST9883

PC_HS

PC_VS

VS HS

FAV_IN

74LVC14A

(Inv. Schmitt

Trigger)

TDA

9886

Sound

TDA

9886

R, G, B, FB

Vx to Pip

S Video_C_IN

S Video_Y_IN

Digital Video

From PING08

Vx to Main

GCOAST(PW181A)

Vx to Main

Vx to Pip

FAV_IN

SDA

SCL

PCF8591

(8-Bit A/D, D/A

Converter)

SC1_PIN8 SC2_PIN8

Sound

Main_CVBS

Pip_CVBS

SAA7118

(Pip Picture)

SAA7118

(Main

Picture)

TXT R, G, B, FB

Pip_CVBS

TEA6415

(Video Switch)

SC1_V_OUT

Scart1 Scart2

MSP 34XX

QSS Pip

Main_CVBS

SC1_V_IN

CVBS from PING08

AUDIO_L/R_IN

74HCT4053

RGB 48

YUV 16

TXT_CVBS

SC2_V_OUT

SC2_V_IN

SC2_AUDIO_L/R_IN

IDTV_AUDIO_L/R_IN

LINE_L/R_OUT

SC2_L/R_OUT SC1_L/R_OUT

RGB 24

MAIN_AUDIO_L/R

HP_L/R

FAV_AUDIO_L/R_IN

PC_AUDIO_L/R_IN

YUV 16

PW1231

A0-A13

MT48LC4M16A2

(SDRAM)

27” TFT TV Service Manual 05/09/2005

UART with PING08

RGB 24

D0-D15

TXT R, G, B, FB

TXT_CVBS

TPA3002

(Class D Amp)

TDA1308

(Headphone

Amp)

(GRGB)

(VRGB)

SAA5264

(TXT Decoder)

HP_L/R

ASM3P2814

(SSC IC)

SPREADED DISPLAY CLOCK

PW181A

A0-A19

MT28F800B3W

(Flash Memory)

D0-D15

SCL

SDA

Headphone

24C32

(E2PROM)

IC33

8 Ohms

12W

8 Ohms

12W

DRE 8 DGE 8 DBE 8

DEN DHS DVS

DCLK

Reset

(HSyncs of SiI151 and

AD9883 ICs)

GHS

GDECD

GAFEDE

GHSSIL

HDSOG

STBY_3V3

VGA

DVI

SCL

SDA

DDC_DATA_PC

DDC_CLK_PC

DDC_V PC_VS

DDC_DATA_DVI

DDC_CLK_DVI

ANA_VS_DVI

DVI_VDDC

DS90C385 (LVDS TX)

74LVC257A

(MUX)

TLC7733

(Reset IC)

24LC32A

(E2PROM)

IC24

Reset

ST24LC21 (E2PROM)

IC113

ST24LC21 (E2PROM)

IC111

TXEOUT0-/+

TXEOUT1-/+

TXEOUT2-/+

TXEOUT3-/+

TXCLKOUT-/+

BLOCK DIAGRAM - IDTV PART

DIGITAL

TUNER

DIGITAL

FRONTEND

ST0360

I2C

FROM

POWER

SUPPLY

+12V

+5V

3.3V

2.5V

1.8V S+5V

S3.3V S2.5V S1.8V

FC_DATA(0-7) FC_CLK FC_SYNC FC_VALID

CARD

INTERFACE

STV0700

I2C

CI CONNECTOR

I2C

MA_A(0-14)

MDOA_D(0-7)

MDIA_D(0-7)

ADR&DATA

CMD(0-7) CMD_CLK CMD_SYNC CMD_VALID

LATCH

ADR (0-14) CPU_ DATA

(0-7)

FLASH

EMI DRAM

CONTROLLER

MPEG DECODER

STi5518

PCM/I2S

I2C

SMI DRAM

Serial Interface RX,TX,IRQ

BT-601 8-bit, HS,VS

I2C

PROM

TO SDA 5550 CONTROLLER

TO GM6015 PORT B

AUDIO

L/R

AUDIO

SWITCH

PCM DAC

CVBS

TO VIDEO

MATRIX

27” TFT TV Service Manual 05/09/2005

16. CIRCUIT DIAGRAMS

27” TFT TV Service Manual 05/09/2005

27” TFT TV Service Manual

Toshiba 27WLT56B Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual