THOMSON MK68590 Technical Manual
i I
a.)M~i']~1
COMPONENTS
COMMUNICATIONS PRODUCTS
~-~~--------
-----~------------------------
MOSTEK
TECHNICAL
MANUAL
MK68590
CONTROLLER FOR ETHERNET
LOCAL AREA NETWORK
1·91
1-92
SECTION
TABLE
OF
CONTENTS
Chapter 1
General Description
PAGE
1.0
Introduction
1,1 Overview
........................................................................
1-1
1.2
Functional Capabilities
.............................................................
1-2
1.3
Functional Description
.............................................................
1-5
1.3.1
Serial
Data
Handling
........................................................
1-5
1.3.2
Collision Detection and Implementation
.........................................
1-5
1.3.3
Buffer Management
........................................................
1-5
1.3.4
Microprocessor Interface
....................................................
1-6
1.3.5
Pin
Description
............................................................
1-8
1.3.6
Lance Interface Description-Bus Master Mode
..................................
1-11
1.3.6.1
Read
Sequence
..................................................
1-12
1.3.6.2
Write Sequence
..................................................
1-13
1.3.7
Lance Interface Description-Bus Slave
Mode
...................................
1-13
2.0
Introduction
1.3.7.1
Read
Sequence
..................................................
1-13
1.3.7.2
Write Sequence
..................................................
1-14
1.3.7.3
Reference Documents
.............................................
1-15
Chapter 2
Programming Specifications
2.1
Programming Specifications
........................................................
2-1
2.2 Programming the LANCE
..........................................................
2-1
2.3
Control and Status Registers
.......................................................
2-1
2.3.1
Accessing the Control and Status Registers
...................
'
..................
2-1
2.3.1.1
Register
Data
Port
(RDP)
...........................................
2-2
2.3.1.2
Register Address
Port
(RAP)
...........................
:
.............
2-2
2.3.2
Control and Status Register Definition
.........................................
2-3
2.3.2.1
Control
and
Status Register 0
(CSRO)
.................................
2-3
2.3.2.2
Control
and
Status Register 1
(CSR1)
.................................
2-5
2.3.2.3
Control and Status Register 2
(CSR2)
.................................
2-5
2.3.2.4
Control
and
Status Register 3
(CSR3)
.................................
2-6
2.4 Initialization
......................................................................
2-7
2.4.1
Initialization Block
..........................................................
2-7
2.4.1.1
Mode
...........................................................
2-8
2.4.1.2
Physical Address
.................................................
2-10
2.4.1.3
Logical Address Filter
.............................................
2-10
2.4.1.4
Receive Descriptor Ring Pointer
.....................................
2-12
2.4.1.5
Transmit Descriptor Ring Pointer
.....................................
2-13
2.5
Buffer Management
..............................................................
2-14
2.5.1
Descriptor Rings
..........................................................
2-14
2.5.1.1
Receive Message Descriptor Entry
...................................
2-14
2.5.1.1.1
Receive Message Descriptor 0
(RMDO)
......................
2-14
2.5.1.1.2
Receive Message Descriptor 1
(RMD1)
.......................
2-14
2.5.1.1.3
Receive Message Descriptor 2
(RMD2)
......................
2-16
2.5.1.1.4
Receive Message Descriptor 3
(RMD3)
......................
2-16
2.5.1.2
Transmit Message Descriptor Entry
..................................
2-17
2.5.1.2.1
Transmit Message Descriptor 0
(TMDO)
......................
2-17
2.5.1.2.2
Transmit Message Descriptor 1
(TMD1)
.......................
2-17
2.5.1.2.3
Transmit Message Descriptor 2 (TMD2)
......................
2-18
2.5.1.2.4
Transmit Message Descriptor 3 (TMD3)
......................
2-18
1-93
3.0
Introduction
Chapter 3
Functional Specifications
3.1
Functional Description
.............................................................
3-1
3.2
Logic
...........................................................................
3·1
3.2.1
Clock
....................................................................
3-1
3.2.2
Microsequencer
............................................................
3·1
3.2.3
Control
Data
Path
..........................................................
3·1
3.2.4
Message
Byte
Count
........................................................
3·1
3.2.5
Ring
End
Finders
..........................................................
3·1
3.3
Bus
Control
.....................................................................
3·2
3.3.1
Bus
Address
Register
.......................................................
3·2
3.3.2
Memory
Data
Register
......................................................
3-2
3.3.3
Bus
Master
Control
.........................................................
3·2
3.3.4
Memory
Timeout
...........................................................
3·2
3.3.5
Bus
Slave
Control
..........................................................
3·2
3.3.6
Discrete User Apparent
Registers
.............................................
3·2
3.4
Transceiver
Data
Path
.............................................................
3·2
3.4.1
Serial
Data
Output
.........................................................
3·2
3.4.2
Serial
Data
Input
...........................................................
3-3
3.4.3
SILO
....................................................................
3-3
3.4.4
SILO·
Memory
Byte
Alignment
...............................................
3-4
3.4.5
Cyclic Redundancy
Check
...................................................
3-4
3.5
Transmission
.....................................................................
3·5
3.5.1
Interpacket
Delay
..........................................................
3-5
3.5.2
Collision Detection
and
Collision
Jam
..........................................
3·5
3.5.3
Collision Backoff
...........................................................
3-6
3.5.4
Collision • Microcode Interaction
..............................................
3·6
3.5.5
Time
Domain
Reflectometry
..................................................
3·6
3.5.6
Heartbeat. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3·6
3.6
Reception
.......................................................................
3·6
3.6.1
Station
Address
Detection
...................................................
3·7
3.6.1.1
Physical
Address
Register
...........................................
3-7
3.6.1.2
Logical
Address
Filter Register
.......................................
3·7
3.6.1.3
Promiscuous
Mode
................................................
3-7
3.6.1.4
Broadcast
Address
Detection
........................................
3·7
3.6.2
Runt
Packet
Filtration
.......................................................
3·7
3.7
Loopback
.......................................................................
3-8
3.8
Microprogram Overview
.......................•....................................
3·8
3.8.1
Switch
Routine
............................................................
3·8
3:8.2
Initialization Routine
........................................................
3·8
3.8.3
Polling
Routine
............................................................
3·8
3.8.4
Receive
Polling
Routine
.....................................................
3·9
3.8.5
Receive
Routine
...........................................................
3-9
3.8.6
Receive
DMA
Routine
......................................................
3·9
3.8.7
Transmit
Polling
Routine
....................................................
3·10
3.8.8
Transmit
Routine
..........................................................
3·10
3.8.9
Transmit
DMA
Routine
.....................................................
3·10
3.8.10
Collision
Trap
Routine
......................................................
3·11
3.8.11
CSR
Trap
Routine
...................................................
,
.....
3·11
3.8.12
Memory Timeout
Trap
Routine
...............................................
3·11
3.8.13
Retry
Trap
Routine
.........................................................
3·11
3.8.14
Data
Chain
...............................................................
3·11
Chapter 4
Electrical Specifications
4.0
Electrical Specifications
...............................................................
,4·1
1-94
FIGURE
NUMBER
LIST
OF ILWSTRATIONS
TITLE
PAGE
1 LANCE Block Diagram
.............................................................
1-1
2 Ethernet and LANCE
Packet
Format
.................................................
1-2
3 Ethernet and LANCE Packet Bit Transmission Sequence
.................................
1-2
4 Ethernet Local Area Network System Block Diagram
....................................
1-3
5 Lance Conceptual View
............................................................
1-4
6 LANCE Memory Management
...................................................
,
...
1-6
7 LANCE
Pin
Assignment
............................................................
1-7
8 Multiplexed Bus Interface
..........................................................
1-11
9 Demultiplexed
Bus
Interface
........................................................
1-12
10
Bus Master Timing
...............................................................
1-13
11
Bus
Slave
Read
Timing for
CSRO,
RAp,
and
CSR3
.....................................
1-14
12
Bus
Slave Write Timing for
CSRO,
RAP,
and
CSR3
.....................................
1-14
13
Mapping of Logical Address
to
Filter Mask
...........................................
2-12
14
Output
Load
Diagram
.............................................................
4-5
15
Serial Link Timing Diagram
........................................................
4-5
16
Bus Master Timing Diagram
........................................................
4-6
17
LANCE
Bus
Slave Timing Diagram
..................................................
4-7
1-95
iii
1-96
1.0 INTRODUCTION
1.1
OVERVIEW
CHAPTER 1
GENERAL
DESCRIPTION
The MK68590 LANCE (Local Area Network Controller for Ethernet)
is
a 48-pin VLSI device designed
to
simplify greatly the interfacing of a microcomputer or a minicomputer to an Ethernet Local Area Net-
work. This chip is intended to operate
in
a local environment that includes a closely coupled memory
and microprocessor. The LANCE uses
scaled N-channel MOS technology and
is
compatible with several
microprocessors. A block diagram of the chip is shown
in
Figure
1.
LANCE
is
a
trademark
of
Mostek
Corporation.
LANCE BLOCK DIAGRAM
Figure 1
BUFFER
CONTROL
TENA.-
A(B)
AX------------.---~~
CLSN
DAln6)
M
U
x
16
BIT INTERNAL BUS
1-97
f-----------~~H0I5
~---------
HLDA
---------.-
DALci
MASTER
f-------------I~
i3AiJ
CNTR
BUS
f---~~~----I~A~/As
f-----+-
...
__
--I~
i5As
~--+-~_r~~~
~---------Cs
~READ
~BM(21
_.5
...-GNO(2)
1·1
1.2 FUNCTIONAL CAPABILITIES
The Local Area Network Controller for Ethernet (LANCE) interfaces to a microprocessor bus characterized
by time
multiplexed address and data lines. Typically, data transfers are
16
bits wide, but byte transfers
occur if the buffer memory address boundaries are odd. The address bus is
24
bits wide.
The Ethernet packet format consists
of
a 64·bit preamble, a 48·bit destination address, a 48·bit source
address, a 16·bit type
field, and a 46 to 1500 byte data field terminated with a 32·bit CRC as shown
in Figure 2 and Figure
3.
The variable widths of the packets accommodate both short status, command
and
terminal traffic packets, and long data packets to printers and disks (1024 byte disk sectors for ex·
ample).
Packets are spaced a minimum of
9.6
p.Sec
apart to allow one node time enough to receive back·
to·back packets.
ETHERNET AND
LANCE PACKET FORMAT
FIgure 2
r-------PACKET--------j
I---
MINIMUM
PACKET SPACING (96 BIT TIMES,
*last
Byte
is
Start
of
Frame Synchronization Byte--1 01 01 011
ETHERNET AND LANCE PACKET
BIT
TRANSMISSION SEQUENCE
Figure 3
1·2
r-'
BYTE---1
PHYSICAl/MULTICAST
BIT
-....
.J
SBYrES
BBYrES
2 BYTES
46·1600
BYTES
4 BYTES
DESTINATION
SOURCE
TVPE
DATA
fRAME
CHECK
SEQUENCE
OCTETS
WITHIN
FRAME
TRANSMITTED
m'r"
LSBIIIIIIIIIMSB
L
BITS
WITHIN
OCTET TRANSMITTED
.......
LEFT-TO-RIGHT
1-98
The LANCE
is
intended to operate
in
a minimal configuration that requires close coupling between local
memory and a processor. Figure 5 shows the relationship between the chip and local memory. The local
memory provides packet buffering for the chip and serves as a communication link between the chip
and the processor. During initialization, the control processor loads into LANCE the starting address
of the initialization block plus the operating mode of the chip via two control registers.
It is only during
this initial phase that the host processor talks directly to LANCE. All further communications are handled
via a DMA machine under microword control contained within the LANCE. Figure 4
is
a block diagram
of the LANCE and
SIA device used to create an Ethernet interface for a computer system.
ETHERNET LOCAL AREA
NETWORK
SYSTEM BLOCK DIAGRAM
Figure 4
c
o
M
P
U
T
E
R
S
... -__
Y
S
T
E
M
B
U
S
MICROPROCESSOR
·
MK68200
·
MK68000
·
8086
·
28000
·
LSI·11
·
T·11
16·0ATA
--.
24·ADDRESS
LOCAL
MEMORY
LOCAL
AREA
NETWORK
7
SERIAL
f-h
CONTROLLER FOR
+--f--
INTERFACE
ETHERNET
ADAPTER
(SIA)
( LANCE I
POWER
---f-
NETWORK
INTERFACE
MODULE
1-99
8
TRANSCEIVER
CABLE
NETWORK
CABLE
1-3
LANCE CONCEPTUAL VIEW
Figure 5
r---wC"E---
--,
I
"'"
~
I
CSR1
(AO-15)
I
r-
I CSR2 (A16-23) I
r--
~
I
CSR3
I
I
DATA
I
.
~
~
I
SILO
I-
r-
I
r
I
I
I
I
I
I
I
I
RCVR
XMTR
I
I
L_~
----t-..J
'--
~
r---
-
~
DATA
~
..
~
1-4
1-100
MEMORY
MODE
PHYSICAL ADDRESS
LOGICAL ADDRESS
POINTER
10
RECEIVE RINGS
RECEIVE RING
LENGTH
POINTER
10
TRANSMIT RINGS
TRANSMIT RING
LENGTH
RCV_
BUFFER LO-ADDRESS
STATUS'
HI-ADDRESS
BUFFER BYTE LENGTH
RECEIVED MESSAGE LENGTH
RCV.
BUFFER LO-ADDRESS
STATUS'
HI-ADDRESS
BUFFER BYTE LENGTH
RECEIVED MESSAGE LENGTH
XMT. BUFFER
LO-ADDRESS
STATUS'
HI-ADDRESS
BUFFER BYTE LENGTH
BUFFER
STATUS
'TDR
XMT. BUFFER LO-ADDRESS
STATUS'
HI-ADDRESS
BUFFER BYTE LENGTH
BUFFER
STATUS'
TDR
RCV.
DATA
PACKET(S)
RCV.
DATA
PACKET(S)
XMT.
DATA
PACKET(S)
XMT. DATA
PACKET(S)
}
INITIALIZATION
BLOCK
RECEIVE
DESCRIPTOR
RING(S)
TRANSMIT
DESCRIPTOR
RING(S)
}
RECEIVE
DATA
BUFFER(S)
TRANSMIT
DATA
BUFFER(S)
1.3 FUNCTIONAL DESCRIPTION
1.3.1
SERIAL
DATA
HANDLING
The basic operation of the chip set to provide the Ethernet interface
is
as
follows.
In
the transmit
mode (since there is
only one transmission path, Ethernet is a half duplex system), the LANCE
reads data from a transmit buffer
by
using Direct Memory Access (DMA) and appends the pream-
ble,
sync pattern (two ones after alternating ones and zeros
in
the preamble), and calculates
and appends the complement of the 32-bit
CRC.
The first eight words of the transmit buffer
must contain the destination address, source address,
ar<1
type field as detailed
in
the Ethernet
specification.
In
the receive mode, the destination address, source address, type, data, and
eRe
fields are transferred to memory via DMA cycles. The
eRC
is
calculated as the data and transmit-
ted CRC are received.
At
the end of the packet, if this calculated CRC does not agree with a
constant,
an
error bit is set and
in
RMD1
of the receiver descriptor rings.
In
the receive mode,
packets will
be
accepted by the LANCE under four modes of operation. The first mode
is
a full
comparison of the 48·bit destination address
in
the packet with the node address that
was
programmed into the LANCE during an initialization cycle. There are two types of logical address.
One
is
a group type mask where the 48-bit address
in
the packet is put through a hash filter
in
order to map the 48-bit physical addresses into 1 of 64 logical groups. This mode can be
useful if sending packets to all of one type of a device simultaneously or the network
(i.e.
sending a packet to all file servers or all printer servers). The second logical address is the broadcast address where all nodes
on
the network receive the packet. The last receive mode of
operation is the
so
called "promiscuous mode"
in
which a node will accept all packets on
the network cable regardless of their destination address.
1.3.2 COLLISION DETECTION AND IMPLEMENTATION
The Ethernet CSMAlCD network access algorithm
is
implemented completely within the LANCE.
In
addition to listening for a clear network cable before transmitting, Ethernet handles collisions
in
a predetermined
way.
Should two transmitters attempt to seize the network cable at the same
time, they
will collide, and the data on the network cable will be garbled. LANCE is constantly
monitoring the
CLSN (Collision) pin. This signal
is
generated by the transceiver when the signal
level
on
the network cable indicates the presence of signals from two or more transmitters. If
LANCE
is
transmitting when CLSN
is
asserted, it will continue to transmit the preamble, (nor·
mally collisions will
occur while the preamble is being transmitted) then will
"jam"
the network
for 32 bit times (3.2 microseconds). This jamming ensures that
all nodes have enough time to
detect the
collision. The transmitting nodes then delay a random amount of time according to
the
"truncated binary backoff" algorithm defined
in
the Ethernet specification to minimize the
probability of the
colliding nodes having multiple collisions with each other. After
16
abortive
attempts to transmit a packet,
LANCE will report a RTRY error due to excessive collisions and
step over the transmit buffer. During reception, the detection of a collision causes that reception
to be aborted. Depending on when the
collision occurred, LANCE will treat this packet
as
an
error packet if the packet has
an
address mismatch, as a runt packet (a packet that has less
than 64 bytes), or as a legal length packet with a CRC error. Extensive error reporting is provided by the LANCE through a microprocessor interrupt and error bits
in
a status register. The
following are the significant error conditions: CRC error on received data; transmitter on longer
than
1518
bytes; missed packet error (meaning a packet on the network cable was missed
because there were no empty buffers
in
memory), and memory error,
in
which the memory did
not respond (handshake)
to
a memory cycle request.
1.3.3
BUFFER MANAGEMENT
A key feature of the LANCE and its
on
board DMA channel is the flexibility and speed of communication between the LANCE and the host microprocessor through common memory loca·
tions. The basic organization of the buffer management is a circular queue of tasks
in
memory
called descriptor rings, as shown
in
Figure
6.
There are separate descriptor rings to describe
transmit and receive operations. Up to
128
tasks may be queued up on a descriptor ring awaiting
execution by the LANCE. Each entry
in
a descriptor ring holds a pointer to a data memory buf·
fer and
an
entry for the length of the data buffer. Data buffers can be chained or cascaded in
order to handle a long packet
in
multiple data buffer areas. The LANCE searches the descriptor
1·101
1-5
rings in a
"look
ahead manner" to determine the next empty buffer
in
order to chain buffers
together or to
handle back to back packets.
As
each buffer is filled, an "own" bit is reset, signal-
ing the host processor to empty this buffer. The minimum buffer size is
64
bytes for receive
buffers and
100 bytes for transmit buffers.
1.3.4
MICROPROCESSOR INTERFACE
The parallel interface of the LANCE has been designed to be "friendly" or easy to interface
to a variety of popular 16-bit microprocessors. These microprocessors include the following:
MK68000,
Z8000,
8086,
LSI-11,
T-11,
and
MK68200. (The MK68200
is
a 16-bit single chip microcom-
puter being
sampled by Mostek with
an
architecture modeled after the MK68000). The LANCE
has a wide 24-bit
linear address space when it is in the Bus Master Mode, allowing it to DMA
directly into the entire address space of the above microprocessors. No segmentation or paging
methods are used within the LANCE, and as such the addressing is
closest to that used by
the
MK68000 but is compatible with the others. When the LANCE is a bus master, a program-
mable
mode of operation allows byte addressing either by employing a ByteiWord control signal,
much like that used on the 8086 or the Z8000, or by using an Upper Data Strobe/Lower Data
strobe much like that used
on
the MK68000,
LSI-11,
and MK68200 microprocessors. A program-
LANCE MEMORY MANAGEMENT
Figure 6
1·6
LANCE
eSA
REGISTERS
~
POINTER
TO
INITIAUZAnON
I
. I BLOCK
tNtTiAUZAnON
BLOCK
~
MODE
OF
OPERATlON
PHYSICAL
ADDRESS
LOGICAL
ADDRESS
FILTER
RECEIVE BUFFER
r--oA"TA
,,-:~A_EC_E_'V_E_D_ES_C_A'_PT_O_A_A_'N_G_S_-....
~
PACKET 0
~
AODAESSOFAECE,vEBUFFEAO
~
~
~.-/
BUFFEAOSTATUS
...
::>::::
BUFFEAOBYTECOUNT _
~
~~
,
f----------
PA~KET
n;:
:
•
•
•
----
.
__
r-;;;r;-
~v
~~
r:~
~v
f-P-OIN-T-EA-TO-A-EC-E-'VE'-A-'N-GS----If-~
N
~~------N~------~
N
PACKET
N
NUMBER
OF
RECEIVE
ENTRIES
POINTER
TO
TRANSMIT
RINGS
NUMBER
OF
TRANSMIT
ENTRIES
TRANSMIT
DESCRIPTOR
RINGS
TRANSMIT
BUFFE
v.~
~~
V PACKET 0
V~
ADORESS
OF
TRANSMIT
BUFFERS 0
~
BUFFER 0 STATUS
~
BUFFER 0
BYTE
COUNT
~
:
::::-::::
'
~
--
PACKET
,
~
@§
• .
~A-----N----~_
:
•
•
~
v
/:::::::..t.-=--=--:::...~;;-_-_-_-_-
_-
-j-l---_.......Jr---
..........
/7
N - OATA
N
PACKET
N
1-102
mabie polarity on the Address Strobe signal eliminates the need for external logic. The LANCE
interfaces with both
multiplexed and demultiplexed data buses and features control signals for
address/data bus transceivers.
Interrupts to the microprocessor are generated by the LANCE upon completion of its initializa-
tion routine, the reception
of
a packet, the transmission of a packet, transmitter timeout error,
a missed packet, or a memory error.
The cause of the interrupt is ascertained by reading the
control status register
(CSRO).
Bit (06)
of
CSRO,
INEA, enables
or
disables interrupts to the microprocessor.
In
a polling mode, BIT
(07)
of
CSRO
is sampled to determine when
an
interrupt causing condition occurred.
LANCE
PIN ASSIGNMENT
Figure 7
v
••
-
1
DAL07-
2
DAL08-
3
DALOS-
4
DAL04-
5
DAL03-
8
DAL02-
7
DAL01-
8
DALOO-
9
READ-10
iiii'i'lf-11
DALi-
12
DA'CO
_
13
DAS_14
'Biili/BYTE _ 15
iiii1/iiiiSAK6
-
33
HOLD/BUSRQ _ 17
ALE/AS_
18
HiJ5i
_19
Cs
_20
ADR
_21
READY_22
RESET
_23
Vas
- 24
48
-
vee
47-DAL08
48-DAL09
45-DAL
10
44-DAL
11
43-
DAL12
4Z-DAL
13
41-DAL
14
40-DAL
15
39
-A
18
38
-A
17
37
-A
18
38
-A
19
35
-A20
34
-A21
18
-A22
32
-A23
31_
RX
30_
RENA
29
_
TX
28_
CLSN
27-
RCLK
28
_ TENA
25_
TCLK
1-103
1-7
1-8
1.3.5 PIN DESCRIPTION
DALOO-DAL15
(Data/Address Bus)
Input/Output Tri-State. Pins 2-9 and
40-47.
The time multiplexed Address/Data bus. During the
address portion of a memory transfer, DAL <
15:00> contains the lower
16
bits of the memory
address. The upper 8 bits of address are contained
in
A < 23:16
>.
During the data portion of
a memory transfer, DAL <
15:00 > contains the read or write data, depending on the type of
transfer. The LANCE drives these lines both as a Bus Master and as a Bus
Slave.
READ
Input/Output Tri-State. Pin
10.
Read indicates the type of operation the bus controller is performing during a bus transaction. When it is a Bus Master, LANCE drives READ. Read is valid during the entire bus transaction and is tri-stated
at
all other times.
LANCE as Bus
Slave:
High - The chip places data on the DAL lines.
Low
- The chip takes data off the DAL lines.
LANCE as Bus Master:
High - The chip takes data off the DAL lines.
Low
- The chip places data on the DAL lines.
INTR
(Interrupt)
Output Open
Drain. Pin
11.
INTERRUPT is an attention interrupt line that indicates that one
or more of the following
CSRO
status flags
is
set: BABL, MISS, MERR,
RINT,
TINT OR IDON.
Interrupt is enabled by
CSRO
< 6
>,
INEA =
1.
i5A[j
(Data/Address Line In)
Output
Tri-State. Pin
12.
DAL
IN
is
an
external bus transceiver control line. LANCE drives
5A[j
only while it
is
the Bus Master. When LANCE reads the
DAL
lines during the data portion of
a READ transfer, DALI is asserted.
i5AiJ
is not asserted during a WRITE transfer.
i5ACO
(Data/Address
Line
Out)
Output Tri-Staie.
Pin
13.
DAL
OUT
is
an
external bus transceiver control line. LANCE drives 5A[(5
only when it is a Bus Master. When LANCE drives the DAL lines during the address portion
of a READ transfer or for the duration of a
WRITE transfer,
i5ALO
is asserted.
DAS
(Data/Strobe)
Input/Output Tri-State. Pin
14.
Data Strobe defines the data portion of the bus transaction. By
definition, data
is
stable and valid at the low to high transition of
iSAS.
When it is the Bus Master,
LANCE drives this signal.
At
all other times, the signal is tri-stated.
BMO,
BM1
or
BYTE, BUSAKO
(Byte Mask)
Output' Tri-State. Pins
15
and
16
are programmable through CSR3.
CSR3<00>
BCON = 0
PIN
15 = BMO
(Output Tri-State)
PIN
16 = BM1
(Output Tri-State)
Byte Mask <
1:0>
Indicates the byte(s) on the DAL to
be
read or written during this bus
transaction. LANCE drives these lines only as a Bus Master. LANCE ignores the BM lines when
it
is
a Bus Slave and assumes word transfers. Byte selection follows:
BM1
LOW
LOW
HIGH
HIGH
LOW
HIGH
LOW
HIGH
1-104
Whole Word
Byte < DAL 15:08 >
Byte < DAL
07:00 >
None
CSR3<00>
BCON = 1
PIN
15
= BYTE (Output Tri-State)
PIN
16
= BUSAKO (Output)
Byte selection occurs
by
using the BYTE line and DAL
<00>
latched during the address por-
tion of the bus transaction. LANCE drives BYTE only
as
a Bus Master and ignores it when
operating
as
a Bus Slave. Byte selection occurs as follows:
BYTE
DAL<OO>
(During Address Portion)
LOW LOW
WHOLE WORD
LOW
HIGH ILLEGAL CONDITION
HIGH
LOW
LOWER BYTE
HIGH HIGH UPPER BYTE
BUSAKO is a bus request daisy chain output. If LANCE is not requesting the bus and it receives
HLDA, BUSAKO is driven
low.
If LANCE is requesting the bus when it receives HLDA, BUSAKO
remains high.
HOLD/BUSRQ
(Bus Hold Request)
Input/Output Open Drain. Pin
17.
This pin is programmable through
CSR3.
CSR3<00>
BCON = 0
PIN
17
= HOLD
LANCE
asserts the HOLD request when it requires a DMA cycle regardless of the HOLD pin
state.
HOLD is held
LOW
for the entire bus transaction.
CSR3<00>
BCON = 1
PIN
17
= BUSRQ
LANCE
asserts BUSRQ when it requires a DMA cycle if the prior state of the BUSRQ pin
was high.
BUSRQ is held low for the entire bus transaction.
ALE/AS
(Address
Latch Enable)
Output
Tri-State. Pin
18.
The active level of Address Strobe is programmable through CSR3.
The address portion of a bus transfer occurs while this signal is at its asserted level. LANCE
drives this signal while it is the Bus Master.
At
all other times, the signal is tri-stated.
CSR3<01>
ACON = 0
PIN
18
= ALE
Address Latch
Enable is used
to
demultiplex the DAL lines and define the address portion of
the transfer.
As
ALE, the signal transitions from high
to
low during the address portion of the
transfer and remains
low during the data portion. A slave device can use
ALE
to control a latch
on
the bus address lines. When ALE is high, the latch should be open and when
ALE
goes
low,
the latch should be closed.
CSR3<01>
ACON = 1
PIN
18 = AS
As
AS,
the signal pulses low during the address portion of the bus transfer. The low
to
high
transition of
AS
can be used
by
a slave device to strobe the address into a register.
HLDA
(Hold Acknowledge)
Input.
Pin
19.
Hold Acknowledge is the response
to
HOLD. When HLDA is low
in
response to
LANCE's assertion of
HOLD,
the LANCE is the Bus Master. HLDA should be deasserted after
LANCE releases HOLD.
1-105
1-9
1-10
CS
(Chip Select)
Input. Pin 20. When
low,
CS indicates LANCE is the slave device for the data transfer. CS must
be
valid throughout the data portion of the transaction.
ADR
(Register Address Port
Select)
Input. Pin
21.
Address selects the Register Address Port or the Register Data Port. It must
be
valid throughout the data portion of the transfer and the chip only uses it when CS is
low.
READY
ADR
LOW
HIGH
PORT
Register Data Port
Register Address Port
Input/Output Open
Drain.
Pin
22. When LANCE is a Bus Master, READY
is
an
asynchronous
acknowledgement from the bus memory that memory will accept data
in
a WRITE cycle or that
memory has put data on the
DAL
lines
in
a READ cycle.
As
a Bus Slave, LANCE asserts READY
when it has put data on the DAL lines during a READ cycle or is about
to
take data off the DAL
lines during a WRITE cycle. READY
is
a response to
DAS
and
is
negated after
DAS
is negated.
CS and
DAS
must remain asserted until READY
is
asserted or READY will not be asserted.
RESET
(Bus Reset Signal.)
Input. Pin
23.
Causes LANCE to cease operation, clear its internal logic and enter an idle state
with the
STOP
bit of
CSRO
set.
TLCK
(Transmit
Clock)
Input. Pin
25. A crystal-controlled
10
MHz clock. This clock is the primary LANCE clock as well
as the Transmit clock.
(A
0.01
% clock as specified
in
the Ethernet Specification.)
TENA
(Transmit
Enable)
Output. Pin
26. A high level signal asserted w:th the transmit output serial bit stream, TX, to
enable the external transmit logic.
RCLK
(Receive
Clock)
Input.
Pin
27.
The
10
MHz clock that
is
synchronous with the received data and is used for transfer-
ring the received data into the LANCE.
CLSN
Collision)
Input.
Pin
28. A logical input that indicates, when high, that a collision
is
occurring on the channel.
TX
(Transmit)
Output. Pin 29. Transmit Output Bit Stream.
RENA
(Receive Enable)
Input. Pin 30. A logical input that indicates, when high, the presence of data
on
the channeL
RX
(Receive)
Input. Pin
31.
The input for the serial receive data. The data
is
synchronous with the receive clock.
1-106
A16-A23
(High-Order Address Bus)
Output, Three
State pins 32 thru
39.
Address bits
<23:16>
used
in
conjunction with DAL
< 15:00 > to produce a 24-bit address. LANCE drives these lines only as a Bus Master.
Vcc
Power supply pin
48.
+5
VDC
±5%.
It is recommended that a power supply filter be used be-
tween
Vee
(Pin
48)
and V ss (Pins 1 and
24).
This filter should consist of two capacitors
in
parallel
having the values of
1O",F
and
.047",F
respectively.
Vss
Ground pins 1 and
24.
0 VDC
1.3.6 LANCE INTERFACE DESCRIPTION--BUS MASTER MODE
All data transfers from the LANCE
in
the Bus Master mode are timed by ALE,
DAS,
and
READY.
The automatic adjustment of the LANCE cycle
by
the
READY
Signal allows synchronization with
variable cycle time memory due either to memory refresh or to dual port access. Bus cycles
are a minimum of 600 nsec
in
length and can
be
increased
in
100
nsec increments. Figure 8
and Figure 9 show
generalized interfaces to both multiplexed and demultiplexed bus
microprocessors, and Figure
10,
the Bus Master Timing modes.
MULTIPLEXED BUS INTERFACE
Figure 8
DATA
AND
ADDRESS CONTROL
ADDRESS
BITS
16·23
SIGNALS
BITS
0·15
---,v,-----'
MICROPROCESSOR BUS
A16·
A23
A
<23:16>
~----------~~ADR
LANCE
1-107
TO
SIA
1-11
DEMULT!!l'tEXED BUS INTERFACE
Figure 9
DATA
BITS CONTROL ADDRESS BITS
0-15
SIGNALS
0-23
""
~
'"
;::..
./':,.
'--
I---
~
I---
1
'I
A
'I
....
?
...
7
------~v~------~
MICROPROCESSOR BUS
1.3.6.1
1-12
r-~
AO.
15
L
A
'I
T
C
H
'---
A'6_23
AO
r-
0
.J\
E
A
O
_
23
C
0
V
0
E
T
5AS
READ SEQUENCE
"
\
DAL
<15:00>
~
ALE
A
<23:16>
AOR
LANCE
CS
SIA
.1
BUS
\
"
V
TO
SIA
At
the beginning of a read cycle, valid addresses are placed on DAL < 15:00 > and
A
< 23:16 >. The BYTE Mask signals
(BMO
and
i3"M1)
become valid
at
the beginning
of this
cycle as does READ, indicating the type of cycle. The trailing edge of ALE
or
AS is used to strobe in the addresses A < 15:00> into the external latches. Ap-
proximately a hundred nanoseconds
later,
DAL
< 15:00> go into a tristate mode. There
is a fifty nanosecond delay to allow for transceiver turnaround, then
BAS
falls low
to signal the beginning of the data portion of the cycle. At this point in the cycle, the
LANCE waits for the memory device to assert
READY.
Upon assertion of
READY,
DAS
makes a transition from a zero to a one, latching memory data.
(DAS)
is low
for a minimum of 200 nsec).
The bus transceiver
controls,
DALI
and
DALO,
are used to control the bus transceivers.
The DALI
signal is used to strobe data toward the LANCE and the DALO signal is
used to strobe data or addresses away from the LANCE. During a read
cycle, DALO
goes inactive before DALI goes active to avoid the
"spiking"
of the bus transceivers.
1-108
BUS MASTER TIMING
Figure
10
A16-A21 READ
iiMD,
BM1
DAL
<15:00>
(READ)
DAL
<15:00>
(WRITE)
ALE
AS
(DOTTED)
DAS
REAi:iY
DALO (READ)
DAD
(READ)
DAi:O
(WRITE)
"'"
i5ALi
(WRITE)
..
TCYCLE
I
50 I '00 I '50 I 200 I 250 I 300 I 350 I 400 I 450 I 500 I 550 I 600
I
X
__________________________
x
r--------~
ADDRESS
- - - -
--<
MEMORY
DATA >- -
--
________
J
ADDRESS
DATA
TO
MEMORY
---"'"
"
'---
___
--J/
,,~-------/
"
~------------------------~/
1,3.6.2
WRITE SEQUENCE
The write
cycle begins exactly like a read cycle with the READ line remaining inac-
tive. After ALE or
AS
pulse, the DAL < 15:00> change from addresses to data.
DAS
goes active when the DAL < 15:00> lines are stable. This data will remain valid on
the bus
until the memory device asserts
READY.
At this
pOint,
DAS
goes inactive
latching data into the memory device. Data is held for 75 nanoseconds after the
deassertion of
DAS.
1.3.7 LANCE INTERFACE DESCRIPTION··BUS SLAVE MODE
The LANCE enters the Bus Slave Mode whenever CS becomes active. This mode must be
entered whenever writing or reading the four status
control registers
(CSRO,
CSR1,
CSR2, and
CSR3) and the register address painter (RAP). RAP and
CSRO
may
be
read or written to at
any time, but the
LANCE must be stopped for CSR1, CSR2, and CSR3 to be written to or read.
1.3.7.1
READ SEQUENCE
CS,
READ,
and
DAS
are asserted
at
the beginning of a read cycle. ADR also must
be valid
at
this time. (If ADR is a "1", the contents of RAP are placed
on
the DAL
lines. Otherwise the contents of the
CSR register addressed by RAP are placed on
the DAL
line~fter
the data
on
the DAL lines become valid, LANCE asserts
READY.
CS,
READ,
DAS,
and ADR must remain stable throughout the read cycle. Refer to
Figure l1.
1·109
1-13
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