TEXAS INSTRUMENTS UC1827-1, UC1827-2, UC2827-1, UC2827-2, UC3827-1 Technical data

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R

D

QS

20

DELAY

23

GND

11

VCC

REF

15

RT

17

CT

18

SYNC

19

CSA−

9

CSA+

8

SS

4

CSAO

7

CEA−

13

VEA−

16

VEA+

14

22

24

3

2

1

RAMPCEA+12CEAOVEAO

10

PULL

PGND

PUSH

SRC

BUCK

V+

DELAY

DELAY

T

Q

Q

REF

&

UVLO

SS

INHBT

UV

OSC

500 kHz

MAX

6 5

21

Current Sense
Amplifier

ILIM Comparator

+3 V

Current Error
Amplifier

PWM Comparator0.7 V

Flying
Driver

Push/Pull

Drivers

OSC

UVLO

Voltage Error

Amplifier

+

查询UC1827供应商

BUCK CURRENT/VOLTAGE FED PUSH-PULL

FEATURES DESCRIPTION

• Ideal for Multiple Output and/or High

Voltage Output Voltage Converters

• Up to 500 kHz Operation

• High Voltage, High Current Floating

Driver for Buck Converter Stage

• UC3827-1 Current Fed Controller has

Push-Pull Drivers with Overlapping
Conduction Periods

• UC3827-2 Voltage Fed Controller has

Push-Pull Drivers with Nonoverlapping
Conduction Periods

• Average Current Mode, Peak Current

Mode or Voltage Mode with Input
Voltage Feedforward Control for Buck
Power Stage

• Wide Bandwidth, Low Offset,

Differential Current Sense Amplifier

• Precise Short Circuit Current Control

UC1827-1, UC1827-2
UC2827-1, UC2827-2
UC3827-1, UC3827-2

SLUS365A – APRIL 1999 – REVISED AUGUST 2005

PWM CONTROLLERS

The UC3827 family of controller devices provides an
integrated control solution for cascaded buck and
push-pull converters. These converters are known as
current fed or voltage fed push-pull converters and
are ideally suited for multiple output and/or high
voltage output applications. In both current fed and
voltage fed modes, the push-pull switches are driven
at 50% nominal duty cycles and at one half the
switching frequency of the buck stage. In the current
fed mode, the two switches are driven with a speci­fied over-lap period to prevent ringing and voltage
stress on the devices. In the voltage fed mode, the
two switches are driven with a specified gap time
between the switches to prevent shorting the trans­former across the energy storage capacitor and to
prohibit excessive currents flowing through the de­vices.

The converter's output voltage is regulated by pulse
width modulation of the buck switch. The UC3827
contains complete protection and PWM control func­tions for the buck converter. Easy control of the
floating switch is accomplished by the floating drive
circuitry. The gate drive waveform is level shifted to
support an input voltage up to 72 V

BLOCK DIAGRAM

.

DC

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright © 1999–2005, Texas Instruments Incorporated

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UC1827-1, UC1827-2
UC2827-1, UC2827-2
UC3827-1, UC3827-2

SLUS365A – APRIL 1999 – REVISED AUGUST 2005

DESCRIPTION (CONTINUED)

The UC3827 can be set up in traditional voltage mode control using input voltage feedforward technique or in
current mode control. Using current mode control prevents potential core saturation of the push-pull transformer
due to mismatches in timing and in component tolerances. With average current mode control, precise control of
the inductor current feeding the push-pull stage is possible without the noise sensitivity associated with peak
current mode control. The UC3827 average current mode loop can also be connected in parallel with the voltage
regulation loop to assist only in fault conditions.

Other valuable features of the UC3827 include bidirectional synchronization capability, user programmable
overlap time (UC3827-1), user programmable gap time (UC3827-2), a high bandwidth differential current sense
amplifier, and soft start circuitry.

ORDERING INFORMATION

TA= T

J

-55°C to 125°C

-40°C to 85°C

0°C to 70°C

(1) The DW and Q packages are also available taped and reeled. Add a TR suffix to the device type (i.e., UC2827DWTR-1).

PUSH-PULL TOPOLOGY

Current Fed UC1827J-1 UC1827J-1
Voltage Fed UC1827J-2 UC1827J-2
Current Fed UC2827DW-1 UC2827N-1 ­Voltage Fed UC2827DW-2 UC2827N-2 ­Current Fed UC3827DW-1 UC3827N-1 UC3827Q-1
Voltage Fed UC3827DW-2 UC3827N-2 -

SOIC-24 PDIP-24 PLCC-28

(1)

PACKAGES

DISSIPATION RATINGS

PACKAGE ( θJA) JUNCTION-TO-AMBIENT ( θJC) JUNCTION-TO-WHAT?

24-pin (N) 60

24-pin (J) 70 to 90 28

28-pin (DW) 71 to 83

28-pin (QLCC) 40-65

(1) Specified θJA(junction-to-ambient) refers to devices mounted to 5-in

range is given, the lower values refer to a 5-in
trace widths for power packages and 1.3 mm trace widths for non-power packages with a 100 × 100 mil probe land area at the end of
each trace.

(2) Specified θJC(junction-to-what?) data values stated were derived from MIL-STD-1835B which states " The baseline values shown are

worst case (mean + 2s) for a 60 x 60 mil microcircuit device silicon die and applicable for devices with die sizes up to 14400 mils
device sizes greater than 14400 mils
array, 10 °C/W."

(3) Modeled data. If there is a value range given for θJA, the lower value refers to a 3 x 3 in., 1-oz, internal copper ground plane. The higher

value refers to a 1 x 1 in. ground plane. All model data assumes only one trace for each non-fused lead.

2

2

aluminum PC board. The test PWB is 0.062 inches thick and typically used 0.635 mm

use the following values; dual-in-line, 11 °C/W; flat pack, 10 °C/W; pin grid array, 10 °C/W pin grid

TEMPERATURE (°C/W) TEMPERATURE (°C/W)

(1)

(3)

(1)

2

FR4 PC board with 1 oz. copper where noted. When a resistance

30

24

30

(2)
(3)

2

. For

2

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1
2
3
4
5
6
7
8
9
10
11
12

24
23
22
21
20
19
18
17
16
15
14
13

V+

BUCK

SRC

SS
RAMP
CEAO
CSAO

CSA+
CSA−

VEAO

GND

CEA+

PUSH
VCC
PULL
PGND
DELAY
SYNC
CT
RT
VEA−
REF
VEA+
CEA−

N, J OR DW PACKAGES

(TOP VIEW)

3 2 1

13 14

5
6
7
8
9
10
11

PGND
NC
NC
DELAY
SYNC
CT
RT

SS

RAMP

CEAO
CSAO

CSA+
CSA−

VEAO

4

15 16 17 18

CEA+

CEA−

VEA+

REF

NC

VEA−

SRC

BUCKNCV+

Q PACKAGE

(TOP VIEW)

28 27 26

25
24
23
22
21
20
19

12

GND

PUSH

VCC

PULL

NC − No internal connection

UC1827-1, UC1827-2
UC2827-1, UC2827-2
UC3827-1, UC3827-2

SLUS365A – APRIL 1999 – REVISED AUGUST 2005

ABSOLUTE MAXIMUM RATINGS

Supply voltage, VCC 20

CEAO, CEA+, CEA-, CSAO, CSA+, CSA-, CT, DELAY, PUSH, PULL,

Input voltage range

BUCK driver

PUSH/PULL driver

Storage temperature –65 to 150
Junction temperature –55 to 150 °C
Lead temperature (soldering, 10 sec) 300

(1) Voltages are referenced to ground. Currents are positive into, negative out of the specified terminal. Consult Packaging section of

databook for thermal limitations and considerations of packages.

RAMP, RT, SS, SYNC, VEA+, VEAO,
V+ and BUCK 90
SRC 90-VCC
I/O continuous ±250 mA
I/O peak ±1 A
I/O continuous ±200 mA
I/O peak ±0.8 A

(1)

UC2827-1
UC2827-2
UC3827-1
UC3827-2

–0.3 to 5

UNITS

V

CONNECTION DIAGRAMS

PLCC-28 (Q PACKAGE)

(TOP VIEW)

DIL-24 (N or J, DW PACKAGES)

(TOP VIEW)

3

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f

OSC



0.77

RRT C

CT

(Hz)

t

DELAY



R

DELAY

200

 109(s)

I

RT



2.5 V
R

RT

UC1827-1, UC1827-2
UC2827-1, UC2827-2
UC3827-1, UC3827-2

SLUS365A – APRIL 1999 – REVISED AUGUST 2005

Terminal Functions

TERMINAL

NAME Q

BUCK 2 3 O gate of an N-channel MOSFET. The peak sink and source currents are 1 A. V

CEA+ 12 13 I Non-inverting input of the current error amplifier.
CEA- 13 14 I Inverting input of the current error amplifier

CEAO 6 7 O
CSA+ 8 9 I Noninverting input of the current sense amplifier.

CSA– 9 10 I Inverting input of the current sense amplifier.

CSAO 7 8 O

CT 18 20 I

DELAY 20 22 I dead time of the PUSH and PULL outputs of the UC3827-2. The minimum value of the resistor, R

GND 11 12 -

PGND 21 25 - on the printed circuit board. This is imperative to prevent large, high frequency switching currents

PULL 22 26 O the two switches of the push-pull converter with complementary signals at close to a 50% duty cycle.

PUSH 24 28 O the two switches of the push-pull converter with complementary signals at close to a 50% duty cycle.

RAMP 5 6 I

REF 15 16 O

RT 17 19 I to keep CT's discharge peak current less than 20 mA, which is CT's maximum practical discharge value.

SRC 3 4 I must be lower than 90 V–V

N or

DW

I/O DESCRIPTION

Output of the buck PWM controller. The BUCK output is a floating driver, optimized for controlling the
disables BUCK to an off condition (low).

Output of the current error amplifier and the inverting input of the PWM comparator of the buck
converter.

Output of the current sense amplifier and the noninverting input of the current limit comparator. When
the signal level on this pin exceeds the 3V threshold of the current limit comparator, the buck gate drive
pulse is terminated. This feature is useful to implement cycle-by-cycle current limiting for the buck
converter.

Provides for the timing capacitor which is connected between CT and GND. The oscillator frequency is
set by CT and a resistor RT, connected between pin RT and GND. The CT discharge current is
approximately 40 x the bias current through the resistor connected to RT. A practical maximum value for
the discharge current is 20 mA. The frequency of the oscillator is given by equation

A resistor to GND programs the overlap time of the PUSH and PULL outputs of the UC3827-1 and the
is 18 k Ω . The delay or overlap time is given by equation

Ground reference for all sensitive setup components not related to driving the outputs. They include all
timing, voltage sense, current sense, and bypass components.

Ground connection for the PUSH and PULL outputs. PGND must be connected to GND at a single point
flowing through the ground metalization inside the device.

Ground referenced output to drive an N-channel MOSFET. The PULL and the PUSH outputs are driving
Any undervoltage faults will disable PULL to an off condition (low).

Ground referenced output to drive an N-channel MOSFET. The PULL and the PUSH outputs are driving
Any undervoltage faults disables PUSH to an off condition (low).

The RAMP voltage, after a 700 mV internal level shift, is fed to the noninverting input of the buck PWM
comparator. A resistor to VINand a capacitor to GND provide an input voltage feedforward signal for the
buck controller in voltage mode control. In peak current mode control, the RAMP pin receives the
current signal of the buck converter. In an average current mode setup, the RAMP pin has a linearly
increasing ramp signal. This waveform may be generated either by connecting RAMP directly to CT, or
by connecting both a resistor from VCC to RAMP and a capacitor from RAMP to GND.

The output of the +5V on board reference. Bypass this pin with a capacitor to GND. The reference is off
when the chip is in undervoltage lockout mode.o

A resistor to GND programs the charge current of the timing capacitor connected to CT. The charge
current approximately equals that shown in equation

The discharge time, which sets the maximum duty cycle, is set internally and is influenced by the charge
current.

The source connection for the floating buck switch. The voltage on the SRC pin can exceed VCC but
can go to –2V.

. Also, during turn-off transients of the buck switch, the voltage at SRC

VCC

(2)

(3)

. The charge current should be less than 500 µA

CC

undervoltage faults

(1)

,

DELAY

(1)

(2)

(3)
4

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UC1827-1, UC1827-2
UC2827-1, UC2827-2
UC3827-1, UC3827-2

SLUS365A – APRIL 1999 – REVISED AUGUST 2005

Terminal Functions (continued)

TERMINAL

NAME Q

N or

DW

SS 4 5 O clamped to the soft-start capacitor voltage which is slowly charged by an internal current source. In

SYNC 19 21 I

VCC 23 27 I
VEA+ 14 15 I Non-inverting input of the voltage error amplifier

VEA- 16 18 I Inverting input of the voltage error amplifier
VEAO 10 11 O Output of the voltage error amplifier

V+ 1 1 I

I/O DESCRIPTION

5Soft-start pin requires a capacitor to GND. During soft-start the output of the voltage error amplifier is
UVLO, SS is held low.

A bidirectional pin for the oscillator., used to synchronize several chips to the fastest oscillator. Its input
synchronization threshold is 1.4 V. The SYNC voltage is 3.6 V when the oscillator capacitor, CT, is
discharged. Otherwise it is 0 V. If the recommended synchronization circuit is not used, a 1 k Ω or lower
value resistor from SYNC to GND may be needed to increase the fall time of the signal at SYNC.

A voltage source connected to this pin supplies the power for the UC3827. It is recommended to bypass
this pin to both GND and PGND ground connections with good quality high frequency capacitors

Supply voltage for the buck output. The floating driver of the UC3827 uses the bootstrap technique
which requires a reservoir capacitor to store the required energy for the on time of the buck switch. A
diode must be connected from VCC to V+ to charge the reservoir capacitor. This diode must be able to
withstand VIN. The reservoir capacitor must be connected between V+ and SRC.

ELECTRICAL CHARACTERISTICS

Unless otherwise spsecified, V
V

= V

PUSH

SUPPLY

I

VCC

I

VCC

VOLTAGE ERROR AMPLIFIER

IB 0.5 3 µA
VIO 10 mV
AVOL 80 95 dB

(1)

GBW
V

OL

V

OH

CURRENT SENSE AMPLIFIER

IB –1 –5 µA
VIO 5 mV
AVOL 80 110 dB

(1)

GBW
V

OL

V

OH

CMRR Common mode range

CURRENT ERROR AMPLIFIER

IB –1 –5 µA
VIO 10 mV
AVOL 80 110 dB

outputs no load, TJ= T

PULL

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VCC UVLO, Turn-on 8.3 8.8 9.5 V
Hysteresis 0.9 1.2 1.5 V
Supply current start V
Supply current run 32 45 mA
IV+buck high 0.2 1 2 mA

Gain bandwidth 1 4 MHz
Low-level output voltage I
High-level output voltage I

Gain bandwidth 15 29 MHz
Low-level output voltage I
High-level output voltage I

VCC

= 15 V, V

(1)

= 14.3 V, C

V+

A

= 340 pF, R

CT

= 8 V 1000 µA

VCC

= 0 µA (No load) 0.3 0.5 V

VEAO

= 0 µA (No load) 2.85 3 3.20 V

VEAO

= 0 µA (No load) 0.25 0.5 V

CEAO

= 0 µA (No load) 3 3.3 V

CEAO

= 10 k Ω , R

RT

DELAY

= 24.3 k Ω , V

SRC

= V

= V

GND

-0.3 2 V

=

BUCK

(1) Ensured by design. Not production tested.

5