
15
12
3
6
5
7
9
1
2
8
10
Reference
Regulator
16 4
OSC
50 m
A
13
14
11
13
11
14
COMP
S
S
R
+VIN
GROUND
SYNC
RT
CT
DISCHARGE
COMPENSATION
INV INPUT
NI INPUT
SOFTSTART
SHUTDOWN OUTPUT B
OUTPUT A
VC
OUTPUT B
OUTPUT A
VC
NOR
NOR
OR
OR
V
REF
Error
Amp
VREF
OSC
OUT
To Internal
Circutry
UVLO
Lockout
Flip
Flop
PWM
Latch
3 kW
5 kW
UC1527A
Output Stage
UC1525A
Output Stage
www.ti.com
REGULATING PULSE WIDTH MODULATORS
1
FEATURES
• 8-V to 35-V Operation
• 5.1-V Reference Trimmed to 1%
• 100-Hz to 500-kHz Oscillator Range
• Separate Oscillator Sync Terminal
• Adjustable Deadtime Control
• Internal Soft-Start
• Pulse-by-Pulse Shutdown
• Input Undervoltage Lockout With Hysteresis
• Latching PWM to Prevent Multiple Pulses
• Dual Source/Sink Output Drivers
UC1525A, UC1527A
UC2525A, UC2527A
UC3525A, UC3527A
SLUS191C – FEBRUARY 1997 – REVISED JANUARY 2008
DESCRIPTION
The UC1525A/1527A series of pulse width modulator
integrated circuits are designed to offer improved
performance and lowered external parts count when
used in designing all types of switching power
supplies. The on-chip +5.1-V reference is trimmed to
1% and the input common-mode range of the error
amplifier includes the reference voltage, eliminating
external resistors. A sync input to the oscillator allows
multiple units to be slaved or a single unit to be
synchronized to an external system clock. A single
resistor between the C
provides a wide range of dead-time adjustment.
These devices also feature built-in soft-start circuitry
with only an external timing capacitor required. A
shutdown terminal controls both the soft-start circuitry
and the output stages, providing instantaneous turn
off through the PWM latch with pulsed shutdown, as
well as soft-start recycle with longer shutdown
commands.
and the discharge terminals
T
BLOCK DIAGRAM
1
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 1997 – 2008, Texas Instruments Incorporated

UC1525A, UC1527A
UC2525A, UC2527A
UC3525A, UC3527A
SLUS191C – FEBRUARY 1997 – REVISED JANUARY 2008
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (continued)
These functions are also controlled by an undervoltage lockout which keeps the outputs off and the soft-start
capacitor discharged for sub-normal input voltages. This lockout circuitry includes approximately 500 mV of
hysteresis for jitter- free operation. Another feature of these PWM circuits is a latch following the comparator.
Once a PWM pulse has been terminated for any reason, the outputs will remain off for the duration of the period.
The latch is reset with each clock pulse. The output stages are totem-pole designs capable of sourcing or sinking
in excess of 200 mA. The UC1525A output stage features NOR logic, giving a LOW output for an OFF state. The
UC1527A utilizes OR logic which results in a HIGH output level when OFF.
ABSOLUTE MAXIMUM RATINGS
+V
IN
V
C
(1) Values beyond which damage may occur.
(2) See Thermal Characteristics table.
Supply voltage 40
Collector supply voltage 40
Logic inputs – 0.3 to +5.5
Analog inputs – 0.3 to +V
Output current, source or sink 500
Reference output current 50 mA
Oscillator charging current 5
Power dissipation at TA= +25 ° C
Power dissipation at TC= +25 ° C
Operating junction temperature – 55 to 150
Storage temperature range – 65 to 150 ° C
Lead temperature (soldering, 10 seconds) 300
(1)
(2)
(2)
RECOMMENDED OPERATING CONDITIONS
+V
IN
V
C
(1) Range over which the device is functional and parameter limits are assured.
Input voltage 8 35
Collector supply voltage 4.5 35
Sink/source load current (steady state) 0 100
Sink/source load current (peak) 0 400 mA
Reference load current 0 20
Oscillator frequency range 100 400 Hz
Oscillator timing resistor 2 150 k Ω
Oscillator timing capacitorm 0.001 0.01 µ F
Dead time resistor range 0 500 Ω
Operating ambient temperature range UC2525A, UC2527A – 25 85 ° C
UCx52xA UNIT
V
IN
1000
2000
(1)
MIN MAX UNIT
UC1525A, UC1527A – 55 125
UC3525A, UC3527A 0 70
mW
V
2 Submit Documentation Feedback Copyright © 1997 – 2008, Texas Instruments Incorporated
Product Folder Link(s): UC1525A, UC1527A UC2525A, UC2527A UC3525A, UC3527A

THERMAL CHARACTERISTICS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
INV Input
NI Input
SYNC
OSC Output
C
T
R
T
Discharge
Soft Start
V
REF
+V
IN
Output B
V
C
Ground
Output A
Shutdown
Compensation
J or N PACKAGE
(TOP VIEW)
3 2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
Output B
V
C
NC
Ground
Output A
SYNC
OSC Output
NC
C
T
R
T
Q AND L PACKAGES
(TOP VIEW)
NI Input
INV Input
NC
Compensation
Shutdown
V
+V
Discharge
Soft Start
NC
IN
REF
NC − No internal connection
over operating free-air temperature range (unless otherwise noted)
PACKAGE θ
J-16 80-120 28
N-16 90 45
DW-16 45-90 25
PLCC-20 43-75 34
LCC-20 70-80 20
UC1525A, UC1527A
UC2525A, UC2527A
UC3525A, UC3527A
SLUS191C – FEBRUARY 1997 – REVISED JANUARY 2008
JA
θ
JC
CONNECTION DIAGRAMS
PLCC-20, LCC-20
DIL-16
Copyright © 1997 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): UC1525A, UC1527A UC2525A, UC2527A UC3525A, UC3527A

f +
1
C
T
ǒ
0.7RT) 3R
D
Ǔ
UC1525A, UC1527A
UC2525A, UC2527A
UC3525A, UC3527A
SLUS191C – FEBRUARY 1997 – REVISED JANUARY 2008
ELECTRICAL CHARACTERISTICS
+V
= 20 V, and over operating temperature, unless otherwise specified, TA= T
IN
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
REFERENCE
Output voltage TJ= 25 ° C V
UC152xA, UC252xA 5.05 5.10 5.15
Line regulationg VIN= 8 V to 35 V 10 20
Load regulationg IL= 0 mA to 20 mA 20 50 mV
Temperature stability
Total output variation
Shorter circuit current V
Output noise Voltage
Long term stability
OSCILLATOR SECTION
Initial accuracy
Voltage stability
Temperature stability
(1)
(1)
(1)
(1)
(2)
(1) (2)
(1) (2)
(1)
Over operating range 20 50
Line, load, and temperature V
= 0, TJ= 25 ° C 80 100 mA
REF
UC152xA, UC252xA 5.0 5.2
10 Hz ≤ 10 kHz, TJ= 25 ° C 40 200 µ Vrms
TJ= 125 ° C 20 50 mV
TJ= 25 ° C 2% 6%
VIN= 8 V to 35 V
UC152xA, UC252xA 0.3% 1%
Over operating range 3% 6%
Minimum frequency RT= 200 k Ω , CT= 0.1 µ F 120 Hz
Maximum frequency RT= 2 k Ω , CT= 470 pF 400 kHz
Current mirror IRT= 2 mA 1.7 2.0 2.2 mA
Clock amplitude
Clock width
Syncronization threshold
(1) (2)
(1) (2)
(1) (2)
TJ= 25 ° C 0.3 0.5 1.0 µ s
Sync input current Sync voltage = 3.5 V 1.0 2.5 mA
ERROR AMPLIFIER SECTION (V
Input offset voltage
= 5.1 V)
CM
UC152xA, UC252xA 0.5 5 mV
Input bias current 1 10
Input offset current 1
DC open loop gain RL≥ 10 M Ω 60 75 dB
Gain-bandwidth product
DC transconductanc
(1)
(1) (3)
AV= 0 dB, TJ= 25 ° C 1 2 MHz
TJ= 25 ° C, 30 k Ω ≤ RL≤ 1 M Ω 1.1 1.5 mS
Low-level output voltage 0.2 0.5
High-level output voltage 3.8 5.6
Common mode rejection V
= 1.5 V to 5.2 V 60 75
CM
Supply voltage rejection VIN= 8 V to 35 V 50 60
(1) These parameters, although ensured over the recommended operating conditions, are not 100% tested in production.
(2) Tested at f
OSC
= 40 kHz (R
= 3.6 k Ω , CT= 0.01 µ F, RD= 0. Approximate oscillator frequency is defined by:
T
J
UC352xA 5.0 5.1 5.2
UC352xA 4.95 5.25
UC352xA 1% 2%
3.0 3.5 V
1.2 2.0 2.8 V
UC352xA 2 10
µ A
V
dB
(3) DC transconductance (gM) relates to DC open-loop voltage gain (AV) according to the following equation: AV= gMRLwhere RLis the
resistance from pin 9 to ground. The minimum gMspecification is used to calculate minimum AVwhen the error amplifier output is
loaded.
4 Submit Documentation Feedback Copyright © 1997 – 2008, Texas Instruments Incorporated
Product Folder Link(s): UC1525A, UC1527A UC2525A, UC2527A UC3525A, UC3527A

+V
IN
15
Q3
Q4
Q2Q1
1
2
Inv Input
NI Input
200 mA 100 mA
5.8 V
100 W
Comp
9
to PWM
Comparator
UC1525A, UC1527A
UC2525A, UC2527A
UC3525A, UC3527A
SLUS191C – FEBRUARY 1997 – REVISED JANUARY 2008
ELECTRICAL CHARACTERISTICS (continued)
+V
= 20 V, and over operating temperature, unless otherwise specified, TA= T
IN
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PWM COMPARATOR
Minimum duty-cycle 0%
Maximum duty-cycle 45% 49%
Input threshold
Input bias current
(4)
(4)
Zero duty-cycle 0.7 0.9
Maximum duty-cycle 3.3 3.6
SHUTDOWN
Soft-start current V
Soft-start low level V
Shutdown threshold To outputs, V
Shutdown input current V
Shutdown Delay
(5)
OUTPUT DRIVERS (each output) (V
Low-level output voltage
High-level output voltage
Undervoltage lockout V
VCOFF Current
Rise Time
Fall Time
(6)
(5)
(5)
= 0 V, V
SD
= 2.5 V 0.4 0.7
SD
= 2.5 V 0.4 1.0 mA
SD
V
= 2.5 V, TJ= 25 ° C 0.2 0.5 µ s
SD
= 20 V)
C
I
= 20 mA 0.2 0.4
SINK
I
= 100 mA 1.0 2.0
SINK
I
SOURCE
I
SOURCE
COMP
= 0 V 25 50 80 µ A
SS
= 5.1 V, TJ= 25 ° C 0.6 0.8 1.0
SS
= 20 mA 18 19 V
= 100 mA 17 18
and V
= High 6 7 8
SS
VC= 35 V 200 µ A
CL= 1 nF, TJ= 25 ° C 100 600
CL= 1 nF, TJ= 25 ° C 50 300
TOTAL STANDBY CURRENT
Supply Current VIN= 35 V 14 20 mA
(4) Tested at f
(5) These parameters, although ensured over the recommended operating conditions, are not 100% tested in production.
OSC
= 40 kHz (R
= 3.6 k Ω , CT= 0.01 µ F, RD= 0 Ω .
T
(6) Collector off-state quiescent current measured at pin 13 with outputs low for UC1525A and high for UC1527A.
J
0.05 1.0 µ A
V
V
ns
UC1525A Error Amplifier
Copyright © 1997 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): UC1525A, UC1527A UC2525A, UC2527A UC3525A, UC3527A

13
+V
IN
Q5
Q4
+V
REF
Q6
Q3Q2Q1
5 kW
10 kW 10 kW
Clock F/F PWM
11
14
Output
2 kW
Q8
Q9
Q7
Q10
Q11
Q6 Ommitted
In UC1527A
+V
C
+V
SUPPLY
Q1
To Output Filter
R2
R1
13
11
14
12
+V
C
A
B
UC1525A
GND
Return
UC1525A, UC1527A
UC2525A, UC2527A
UC3525A, UC3527A
SLUS191C – FEBRUARY 1997 – REVISED JANUARY 2008
PRINCIPLES OF OPERATION AND TYPICAL CHARACTERISTICS
Figure 1. UC1525A Output Circuit (1/2 circuit shown)
For single-ended supplies, the driver outputs are grounded. The V
totem-pole source transistors on alternate oscillator cycles.
6 Submit Documentation Feedback Copyright © 1997 – 2008, Texas Instruments Incorporated
Figure 2. Grounded Driver Outputs For Single-Ended Supplies
Product Folder Link(s): UC1525A, UC1527A UC2525A, UC2527A UC3525A, UC3527A
termainal is switched to ground by the
C

+15 V
13
11
14
12
D1
D2
Return
30 W
30 W
Q2
Q1
T1
D1, D2: UC3611
+V
C
A
B
UC1525A
GND
Source = VO − V
OH
Sink = V
OL
VIN = 20 V,
TA = 25°C
4
3
2
1
0
0.1 .1 .2 1
Saturation Voltage − V
Output Current, Source or Sink − A
13
11
14
12
Q2
Q1
+V
C
A
B
UC1525A
GND
+V
SUPPLY
Return
R1
C1
R2
C2
R3
T1
UC1525A, UC1527A
UC2525A, UC2527A
UC3525A, UC3527A
SLUS191C – FEBRUARY 1997 – REVISED JANUARY 2008
PRINCIPLES OF OPERATION AND TYPICAL CHARACTERISTICS (continued)
Figure 3. Output Drivers With Low Source Impedance
The low source impedance of the output drivers provides rapid charging of power FET input capacitance while
minimizing external components.
In conventional push-pull bipolar designs, forward base drive is controlled by R1 – R3. Rapid turn-off times for the
power devices are achieved with speed-up capacitors C1 and C2.
Copyright © 1997 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 7
Figure 4. UC1525A Output Saturation Characteristics.
Product Folder Link(s): UC1525A, UC1527A UC2525A, UC2527A UC3525A, UC3527A
Figure 5. Conventional Push-Pull Bipolar Design

13
12
Q2
Q1
+V
C
A
B
UC1525A
GND
+V
SUPPLY
Return
R1
30 W
R2
C1
T1
11
14
D1, D2: UC3611
C2
V
REF
R
T
C
T
16
Q1
Q5 Q8
7.4 kW
Q36
5
Q6 Q9
2 kW
14 kW
Ramp To PWM
Blanking To Outout
Q12
Q10 Q11
Q13
3 kW 250 kW
Clock
Q14
25 kW
1 kW
2 kW
400 mA
5 pF
Q7
Q4
Q2
1 kW
3
7
12
SYNC
DISCHARGE
GND
23 kW
UC1525A, UC1527A
UC2525A, UC2527A
UC3525A, UC3527A
SLUS191C – FEBRUARY 1997 – REVISED JANUARY 2008
PRINCIPLES OF OPERATION AND TYPICAL CHARACTERISTICS (continued)
Figure 6. Low Power Transformers
Low power transformers can be driven by the UC1525A. Automatic reset occurs during dead time, when both
ends of the primary winding are switched to ground.
Figure 7. UC1525A Oscillator Schematic
8 Submit Documentation Feedback Copyright © 1997 – 2008, Texas Instruments Incorporated
Product Folder Link(s): UC1525A, UC1527A UC2525A, UC2527A UC3525A, UC3527A

RD = 0
CT = .01 µF
CT = .02 µF
CT = .05 µF
CT = 0.1 µF
CT = 1 nF
CT = 5 nF
CT = 2 nF
6 5 7
R
T
R
D
C
T
200
100
50
20
10
5
2
− Timing Resistance − kR
T
Ω
1 2 5 10 20 50100 200 1ms 2ms 5ms10ms
Charge Time − ms
500
400
300
200
100
0
0.2 0.5 1 2 5 10 20 50 100 200
− Dead Time Resistance −R
D
Ω
Charge Time − ms
CT = 1 nF
CT = 2 nF
CT = 5 nF
CT = .01 µF
CT = .05 µF
CT = 0.1 µF
CT = .02 µF
125°C
25°C
−55°C
Max RD For a Given RT,
Min RT For a Given R
D
500
400
300
200
100
0
2 4 6 8 10 12
Minimum Recommended R
T
− kW
Maximum recommended RD
RL = ∞
RL = 1 MΩ
RL = 300 kΩ
RL = 100 kΩ
RL = 30 kΩ
Voltage Gain
Phase
80
60
40
20
0
100 1 k 10 k 100 k 1 M 10 M
f − Frequency − Hz
Open-Loop Voltage Gain − dB
−360°
−270°
−180°
Open-Loop Phase
VIN = 20 V,
TJ = 25°C
UC1525A, UC1527A
UC2525A, UC2527A
UC3525A, UC3527A
SLUS191C – FEBRUARY 1997 – REVISED JANUARY 2008
PRINCIPLES OF OPERATION AND TYPICAL CHARACTERISTICS (continued)
Shutdown Options (See Block Diagram)
Since both the compensation and soft-start terminals (Pins 9 and 8) have current source pull-ups, either can
readily accept a pull-down signal which only has to sink a maximum of 100 A to turn off the outputs. This is
subject to the added requirement of discharging whatever external capacitance may be attached to these pins.
An alternate approach is the use of the shutdown circuitry of Pin 10 which has been improved to enhance the
available shutdown options. Activating this circuit by applying a positive signal on Pin 10 performs two functions;
the PWM latch is immediately set providing the fastest turn-off signal to the outputs; and a 150-A current sink
begins to discharge the external soft-start capacitor. If the shutdown command is short, the PWM signal is
terminated without significant discharge of the soft-start capacitor, thus, allowing, for example, a convenient
implementation of pulse-by-pulse current limiting. Holding Pin 10 high for a longer duration, however, will
ultimately discharge this external capacitor, recycling slow turn-on upon release.
Pin 10 should not be left floating as noise pickup could conceivably interrupt normal operation. All transitions of
the voltage on pin 10 should be within the time frame of one clock cycle and not repeated at a frequency higher
than 10 clock cycles.
Oscillator Charge Time vs RTand C
Figure 8. Figure 9.
Maximum Value RDvs Minimum Value R
T
T
Error Amplifier Voltage Gain and Phase vs Frequency
Oscillator Discharge Time vs RTC
T
Copyright © 1997 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 9
Figure 10. Figure 11.
Product Folder Link(s): UC1525A, UC1527A UC2525A, UC2527A UC3525A, UC3527A

V
REF
PWM
Adj.
3 kW
10 kW
1.5 kW
3.6 kW
.009
0.1
1 = VOS
2 = I(+)
3 = I(−)
V/I Meter
−
+
Clock
SYNC
R
T
Deadtime
Ramp
100 W
.001
Comp
10 kW
0.1
0.1
Oscillator
16
4
3
6
7
5
9
1
2
15
13
11
14
12
8
10
Reference
Regulator
Flip/
Flop
PWM
E/A
D.U.T.
A
B
+V
IN
0.1
V
C
0.1
Out A
1 k, 1 W
(2)
Out B
Gnd
Soft-Start
5 mF
50 mA
5 kW
5 kW
5 kW
V
REF
Shutdown
1
2
3
1
2
3
3
1
2
1
2
3
UC1525A, UC1527A
UC2525A, UC2527A
UC3525A, UC3527A
SLUS191C – FEBRUARY 1997 – REVISED JANUARY 2008
PRINCIPLES OF OPERATION AND TYPICAL CHARACTERISTICS (continued)
Figure 12. Lab Test Fixture
10 Submit Documentation Feedback Copyright © 1997 – 2008, Texas Instruments Incorporated
Product Folder Link(s): UC1525A, UC1527A UC2525A, UC2527A UC3525A, UC3527A

PACKAGE MATERIALS INFORMATION
www.ti.com
TAPE AND REEL INFORMATION
11-Mar-2008
*All dimensions are nominal
Device Package
Type
UC2525ADWTR SOIC DW 16 2000 330.0 16.4 10.85 10.8 2.7 12.0 16.0 Q1
UC3525ADWTR SOIC DW 16 2000 330.0 16.4 10.85 10.8 2.7 12.0 16.0 Q1
Package
Drawing
Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm)W(mm)
Pin1
Quadrant
Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
UC2525ADWTR SOIC DW 16 2000 346.0 346.0 33.0
UC3525ADWTR SOIC DW 16 2000 346.0 346.0 33.0
Pack Materials-Page 2

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