TEXAS INSTRUMENTS TVP7001 Technical data

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TRIPLE 8/10-BIT, 165/110 MSPS, VIDEO

AND GRAPHICS DIGITIZER WITH ANALOG PLL

FEATURES APPLICATIONS

• Analog Channels

– -6 dB to 6 dB Analog Gain
– Analog Input MUXs
– Auto Video Clamp
– Three Digitizing Channels, Each With

Independently Controllable Clamp, PGA,
and ADC

– Clamping: Selectable Clamping Between

Bottom Level and Mid-level

– Offset: 1024-Step Programmable RGB or

YPbPr Offset Control
– PGA: 8-Bit Programmable Gain Amplifier
– ADC: 8/10-Bit 165/110 MSPS A/D Converter
– Automatic Level Control Circuit
– Composite Sync: Integrated Sync-on-Green

Extraction From GreenLuminance Channel
– Support for DC and AC-Coupled Input

Signals

• PLL

– Fully Integrated Analog PLL for Pixel Clock

Generation
– 12-165 MHz Pixel Clock Generation From

HSYNC Input
– Adjustable PLL Loop Bandwidth for

Minimum Jitter
– 5-Bit Programmable Subpixel Accurate

Positioning of Sampling Phase

• Output Formatter
– Support for RGB/YCbCr 4:4:4 and YCbCr TVP7001 also contains a complete analog PLL block

4:2:2 Output Modes to Reduce Board Traces

– Dedicated DATACLK Output for Easy

Latching of Output Data

• System
– Industry-Standard Normal/Fast I2C Interface

With Register Readback Capability
– Space-Saving TQFP-100 Pin Package
– Thermally-Enhanced PowerPAD™ Package

for Better Heat Dissipation

TVP7001

SLES164 – FEBBRUARY 2006

• LCD TV/Monitors/Projectors

• DLP TV/Projectors

• PDP TV/Monitors

• PCTV Set-Top Boxes

• Digital Image Processing

• Video Capture/Video Editing

• Scan Rate/Image Resolution Converters

• Video Conferencing

• Video/Graphics Digitizing Equipment

DESCRIPTION

TVP7001 is a complete solution for digitizing video
and graphic signals in RGB or YPbPr color spaces.
The device supports pixel rates up to 165 MHz.
Therefore, it can be used for PC graphics digitizing
up to the VESA standard of UXGA (1600 × 1200)
resolution at 60 Hz screen refresh rate, and in video
environments for the digitizing of digital TV formats,
including HDTV up to 1080p. TVP7001 can be used
to digitize CVBS and S-video signal with 10-bit ADCs.

The TVP7001 is powered from 3.3-V and 1.8-V
supply and integrates a triple high-performance A/D
converter with clamping functions and variable gain,
independently programmable for each channel. The
clamping timing window is provided by an external
pulse or can be generated internally. The TVP7001
includes analog slicing circuitry on the Y or G input to
support sync-on-luminance or sync-on-green
extraction. In addition, TVP7001 can extract discrete
HSYNC and VSYNC from composite sync using a
sync slicer.

to generate a pixel clock from the HSYNC input. Pixel
clock output frequencies range from 12 MHz to 165
MHz.

All programming of the part is done via an
industry-standard I2C interface, which supports both
reading and writing of register settings. The TVP7001
is available in a space-saving TQFP 100-pin
PowerPAD package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Copyright © 2006, Texas Instruments Incorporated

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Output

Formatter

ROUT[9:0]

GOUT[9:0]

Host

Interface

Timing Processor

and Clock generation

RIN_1

SCL

SDA

I2CA

GIN_1

BIN_1

Clamp

Clamp

Clamp

PGA

PGA

PGA

10−bit

ADC

10−bit

ADC

10−bit

ADC

HSYNC_A

VSYNC_A

COAST
CLAMP

FILT1

SOGIN_1

RESETB

PWDN

BOUT[9:0]

SOGOUT
HSOUT
VSOUT

DATACLK

RIN_2

GIN_2

BIN_2

EXT_CLK

SOGIN_2

HSYNC_B

VSYNC_B

FILT2

RIN_3

GIN_3
GIN_4

SOGIN_3

BIN_3

TVP7001

SLES164 – FEBBRUARY 2006

T

A

0 ° C to 70 ° C

ORDERING INFORMATION

PACKAGED DEVICES

100-PIN PLASTIC FLATPACK PowerPAD™

TVP7001PZP Tray

TVP7001PZPR Reel

FUNCTIONAL BLOCK DIAGRAM

PACKAGE OPTION

2

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TVP7001

100−Pin TQFP Package

(Top View)

SOGIN_1

GIN_1
A18GND
A18VDD
A18GND
A18VDD
A18VDD
A18GND

RIN_3

RIN_2

RIN_1
A33GND
A33VDD
A33VDD
A33GND

BIN_3
BIN_2

BIN_1
A18VDD
A18GND

NSUB

TEST
VSOUT
HSOUT

SOGOUT

IOVDD

IOGND

B_9

B_8

B_7

B_6

B_5

B_4

B_3

B_2

B_1

B_0

DVDD

GND

IOVDD

IOGND

G_9

G_8

G_7

G_6

G_5

G_4

G_3

G_2

SDA
SCL
I2CA
TMS
RESETB
PWDN
DVDD
GND
IOGND
IOVDD
R_0
R_1
R_2
R_3
R_4
IOGND
R_5
R_6
R_7
R_8
R_9
IOGND
IOVDD
G_0
G_1

GIN_2

SOGIN_2

GIN_3

SOGIN_3

GIN_4

A33GND

A33VDD

A33VDD

A33GND

NSUB

PLL_A18GND

PLL_F

FILT2

FILT1

PLL_A18GND

PLL_A18VDD

PLL_A18VDD

PLL_A18GND

HSYNC_B

HSYNC_A

EXT_CLK

VSYNC_B

VSYNC_A

COAST

CLAMP

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

100

9998979695949392919089888786858483828180797877

76

26272829303132333435363738394041424344454647484950

TVP7001

SLES164 – FEBBRUARY 2006

TERMINAL ASSIGNMENTS

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TVP7001

SLES164 – FEBBRUARY 2006

TERMINAL FUNCTIONS

TERMINAL

NAME NO.

ANALOG VIDEO

RIN_1 11 I Analog video input for R/Pr 1
RIN_2 10 I Analog video input for R/Pr 2
RIN_3 9 I Analog video input for R/Pr 3
GIN_1 2 I Analog video input for G/Y 1
GIN_2 100 I Analog video input for G/Y 2
GIN_3 98 I Analog video input for G/Y 3
GIN_4 96 I Analog video input for G/Y 4
BIN_1 18 I Analog video input for B/Pb 1
BIN_2 17 I Analog video input for B/Pb 2
BIN_3 16 I Analog video input for B/Pb 3

CLOCK SIGNALS

DATACLK 28 O Data clock output
EXT_CLK 80 I External clock input for free running mode
TEST 22 O Internal 5 MHz clock output, coast output, high-Z, or SOG output

DIGITAL VIDEO

ROUT [9:0] 55–59, 61–65 O Digital video output of R/Cr, ROUT [9] is MSB.
GOUT [9:0] 43-52 O Digital video output of G/Y, GOUT [9] is MSB.
BOUT [9:0] 29-38 O Digital video output of B/Cb, BOUT [9] is MSB. For a 4:2:2 mode BOUT outputs CbCr data.

MISCELLANEOUS SIGNALS

PWDN 70 I Power down input. 1: Power down 0: Normal mode
RESETB 71 I Reset input, active low
TMS 72 I Connect to ground
FILT1 87 O External filter connection for PLL. The recommended capacitor is 0.1 µ F. see Figure 4
FILT2 88 O External filter connection for PLL. The recommended capacitor is 4.7 nF. See Figure 4

HOST INTERFACE

I2C A 73 I I2C Address input
SCL 74 I I2C Clock input
SDA 75 I/O I2C Data bus

POWER SUPPLIES

NSUB 21, 91 I Substrate ground. Connect to analog ground.
A33VDD 13, 14, 93, 94 I Analog power. Connect to 3.3 V.
A33GND 12, 15, 92, 95 I Analog 3.3 V return. Connect to Ground.
A18GND 3, 5, 8, 20 I Analog 1.8V return. Connect to Ground
A18VDD 4, 6, 7, 19 I Analog power. Connect to 1.8 V.
PLL_A18VDD 84, 85 I PLL analog power. Connect to 1.8 V.
PLL_F 89 I PLL filter internal supply connection
PLL_A18GND 83, 86, 90 I PLL analog power return. Connect to Ground.
GND 40, 68 I Digital return. Connect to Ground.
DVDD 39, 69 I Digital power. Connect to 1.8 V

IOGND I
IOVDD 26, 41, 53, 66 I Digital power. Connect to 3.3 V or less for reduced noise.

SYNC SIGNALS

CLAMP 76 I External Clamp input. Unused inputs can be connected to ground.
COAST 77 I External PLL COAST signal input. Unused inputs can be connected to ground

27, 42, 54, 60, Digital power return. Connect to Ground.

67

I/O DESCRIPTION

The inputs must be AC coupled. The recommended coupling capacitor is 0.1 µ F. Unused analog
inputs should be connected to ground using a 10 nF capacitor.

Unused outputs can be left unconnected.

4

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TERMINAL FUNCTIONS (continued)

TERMINAL

NAME NO.

VSYNC_A 78 I Vertical sync input A
VSYNC_B 79 I Vertical sync input B. Unused inputs can be connected to ground.

HSYNC_A 81 I Horizontal Sync input A
HSYNC_B 82 I Horizontal Sync input B. Unused inputs can be connected to ground.

SOGIN1 1 I Sync-on-green input 1
SOGIN2 99 I Sync-on-green input 2
SOGIN3 97 I Sync-on-green input 3. Unused inputs should be connected to ground using a 10 nF capacitor.

VSOUT 23 O Vertical sync output
HSOUT 24 O Horizontal sync output
SOGOUT 25 O Sync-on-green slicer output

I/O DESCRIPTION

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

IOVDD to IOGND –0.5 V to 4.5 V

Supply voltage range

Digital input voltage range VI to GND –0.5 V to 4.5 V
Analog input voltage range AI to A33GND –0.2 V to 2.3 V

Digital output voltage range VO to GND –0.5 V to 4.5 V
TA Operating free-air temperature 0 ° C to 70 ° C
Tstg Storage temperature –65 ° C to 150 ° C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

DVDD to GND –0.5 V to 2.3 V
PLL_A18VDD to PLL_A18GND and A18VDD to A18GND –0.5 V to 2.3 V
A33VDD to A33GND – 0.5 V to 4.5 V

(1)

UNIT

TVP7001

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range, TA= 0 ° C to 70 ° C (unless otherwise noted)

MIN NOM MAX UNIT

IOVDD Digital I/O supply voltage 3.0 3.3 3.6 V
DVDD Digital supply voltage 1.70 1.8 2.0 V
PLL_A18VDD Analog PLL supply voltage 1.8 1.9 2.0 V
A18VDD Analog supply voltage 1.8 1.9 2.0 V
A33VDD Analog supply voltage 3.0 3.3 3.6 V
V

I(P–P)

V

IH

V

IL

I

OH

I

OL

I

OH_DATACLK

I

OL_DATACLK

T

A

Analog input voltage (ac–coupling necessary) 0.5 2.0 V
Digital input voltage high 0.7 IOVDD V
Digital input voltage low 0.3 IOVDD V
High–level output current 2 mA
Low–level output current –2 mA
DATACLK high–level output current 4 mA
DATACLK low–level output current –4 mA
Operating free–air temperature 0 70 ° C

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TVP7001

SLES164 – FEBBRUARY 2006

ELECTRICAL CHARACTERISTICS

IOVDD = 3.3 V, DVDD = 1.8 V, PLL_A18VDD = 1.9 V, A18VDD = 1.9 V, A33VDD = 3.3 V, TA= 25 ° C

PARAMETER TEST CONDITIONS MIN TYP

POWER SUPPLY

I

A33VDD

I

IOVDD

I

A18VDD

I

PLL_18VDD

I

DVDD

P

TOT

I

A33VDD

I

IOVDD

I

A18VDD

I

PLL_18VDD

I

DVDD

P

TOT

P

DOWN

(1) SMPTE color bar RGB input pattern used.
(2) Worst case vertical line RGB input pattern used.

3.3-V supply current 78.75 MHz 60 60 mA

3.3-V supply current 78.75 MHz 32 78 mA

1.8-V supply current 78.75 MHz 225 225 mA

1.8-V supply current 78.75 MHz 14 14 mA

1.8-V supply current 78.75 MHz 7 9 mA
Total power dissipation, normal mode 78.75 MHz 746 901 mW

3.3-V supply current 162 MHz 95 95 mA

3.3-V supply current 162 MHz 44 125 mA

1.8-V supply current 162 MHz 230 230 mA

1.8-V supply current 162 MHz 20 20 mA

1.8-V supply current 162 MHz 17 20 mA
Total power dissipation, normal mode 162 MHz 936 1200 mW
Total power dissipation, power–down mode 1 mW

(1)

(2)

MAX

UNIT

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TVP7001

SLES164 – FEBBRUARY 2006

ELECTRICAL CHARACTERISTICS

IOVDD = 3.3 V, DVDD = 1.8 V ± 0.1, PLL_A18VDD = 1.9 V ± 0.1, A18VDD = 1.9 V ± 0.1, A33VDD = 3.3 V, TA= 0 ° C to 70 ° C
(unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ANALOG INTERFACE

Input voltage range By design 0.5 1.0 2.0 Vpp

Z

I

DIGITAL LOGIC INTERFACE

C

I

Z

I

V

OH

V

OL

V

OH_SCLK

V

OL_SCLK

V

IH

V

IL

A/D CONVERTERS

DNL DC differential nonlinearity LSB

INL DC integral nonlinearity LSB

SNR Signal-to-noise ratio 10 MHz, 1.0 V

PLL

Input impedance, analog video inputs By design 500 k Ω

Input capacitance By design 10 pF
Input impedance By design 500 k Ω
Output voltage high IOH= 2 mA 0.8 IOVDD V
Output voltage low IOL= –2 mA 0.2 IOVDD V
DATACLK output voltage high IOH= 4 mA 0.8 IOVDD V
DATACLK output voltage low IOH= –2 mA 0.2 IOVDD V
High-level input voltage By design 0.7 IOVDD V
Low-level input voltage By design 0.3 IOVDD V

Conversion rate 12 165 MSPS

10 bit, 110 MHz -1 ± 0.5 +1
8 bit, 162 MHz -1 ± 0.5 +1
10 bit, 110 MHz -4 ± 1 +4
8 bit, 162 MHz -4 ± 1 +4

Missing code 8 bit, 162 MHz none

at 110 52 dB

MSPS

P–P

Analog bandwidth By design 500 MHz

Clock jitter 500 ps
Phase adjustment 11.6 degree
VCO frequency range 12 165 MHz

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DATACLK

t1

t2

t3

Valid DataR, G, B, HSOUT Valid Data

TVP7001

SLES164 – FEBBRUARY 2006

TIMING REQUIREMENTS

PARAMETER TEST CONDITIONS

CLOCKS, VIDEO DATA, SYNC TIMING

Duty cycle DATACLK 50%
t
t
t

(1) Measured with a load of 15 pF.

DATACLK rise time 10% to 90% 1 ns

1

DATACLK fall time 90% to 10% 1 ns

2

Output delay time 1.5 3.5 ns

3

(1)

MIN TYP MAX UNIT

Figure 1. Clock, Video Data, and Sync Timing

8

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TIMING REQUIREMENTS

SDA

t1

t6

t7

t2

t8

t3

t4

t6

SCL

Data

Stop Start Stop

t5

I2C HOST PORT TIMING

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

C

b

f

12C

TVP7001

SLES164 – FEBBRUARY 2006

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Bus free time between STOP and START Specified by design 1.3 µ s

Setup time for a (repeated) START condition Specified by design 0.6 µ s

Hold time (repeated) START condition Specified by design 0.6 µ s

Setup time for a STOP condition Specified by design 0.6 ns

Data setup time Specified by design 100 ns

Data hold time Specified by design 0 0.9 µ s

Rise time SDA and SCL signal Specified by design 250 ns

Fall time SDA and SCL signal Specified by design 250 ns

Capacitive load for each bus line Specified by design 400 pF

I2C clock frequency Specified by design 400 kHz

Figure 2. I2C Host Port Timing

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TVP7001

SLES164 – FEBBRUARY 2006

FUNCTIONAL DESCRIPTION

Analog Channel

The TVP7001 contains three identical analog channels that are independently programmable. Each channel
consists of a clamping circuit, a programmable gain amplifier, automatic offset control and an A/D converter.

Analog Input Switch Control

TVP7001 has 3 analog channels that accept up to 10 video inputs. The user can configure the internal analog
video switches via the I2C interface. The 10 analog video inputs can be used for different input configurations
some of which are:

• Up to 10 selectable individual composite video inputs

• Up to 2 selectable RGB graphics inputs

• Up to 3 selectable YPbPr video HD/SD inputs

The input selection is performed by the input select register at I2C subaddress 0 × 19 and 0 × 1A (see Input Mux
Select 1 and Input Mux Select 2)

Analog Input Clamping

An internal clamping circuit restores the AC-coupled video/graphic signal to a fixed DC level. The clamping circuit
provides line-by-line restoration of the signal black level to a fixed DC reference voltage. The selection between
bottom and mid level clamping is performed by I2C subaddress 0 × 10 (see Sync On_Green Threshold). Fine
clamps must also be enabled in the I2C register 2Ah for proper operation.

The internal clamping time can be adjusted by I2C clamp start and width registers at subaddress 0 × 05 and 0 × 06
(see Clamp Start and Clamp Width).

Programmable Gain Amplifier (PGA)

The TVP7001 PGA can scale a signal with a voltage-input compliance of 0.5-Vpp to 2-Vpp to a full-scale 10-bit
A/D output code range. A 4-bit code sets the coarse gain (Red Coarse Gain, Green Coarse Gain, Blue Coarse
Gain) with individual adjustment per channel. Minimum gain corresponds to a code 0 × 0 (2-Vpp full-scale input,
–6 dB gain) while maximum gain corresponds to code 0 × F (0.5-Vpp full-scale, +6 dB gain). TVP7001 also has
8-bit fine gain control (Red Fine Gain, Green Fine Gain, Blue Fine Gain) for RGB independently ranging from 1
to 2. For a normal PC graphics input, the fine gain will be used mostly.

Programmable Offset Control and Automatic Level Control (ALC)

The TVP7001 supports a programmable offset control for RGB independently. A 6-bit code sets the coarse offset
(Red Coarse Offset, Green Coarse Offset, Blue Coarse Offset) with individual adjustment per channel. The
coarse offset ranges from –32 LSB to +31 LSB. The coarse offset registers apply before the ADC. A 10-bit fine
offset registers (Red Fine Offset, Green Fine Offset, Blue Fine Offset) apply after the ADC. The fine offset ranges
from –512 LSB to +511 LSB.

ALC circuit maintains the level of the signal to be set at a value which is programmed at fine offset I2C register. It
consists of pixel averaging filter and feedback loop. This ALC function can be enabled or disabled by I2C register
address at 0 × 26. ALC circuit needs a timing pulse generated internally but user should program the position
properly. The ALC pulse must be positioning after the clamp pulse. The position of ALC pulse is controlled by
ALC placement I2C register at address 0 × 31. This is available only for internal ALC pulse timing. For external
clamp, the timing control of clamp is not applicable so the ALC pulse control is also not applicable. Therefore it is
suggested to keep the external clamp pulse as long as possible. ALC is applied as same position of external
clamp pulse.

A/D Converters

All ADCs have a resolution of 10-bits and can operate up to 165 MSPS. All A/D channels receive an identical
clock from the on-chip phase-locked loop (PLL) at a frequency between 12 MHz and 165 MHz. All ADC
reference voltages are generated internally. Also the external sampling clock can be used.

10

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