TEXAS INSTRUMENTS TVP6000C Technical data

现货库存、技术资料、百科信息、热点资讯，精彩尽在鼎好!

TVP6000C

Data Manual

NTSC/PAL Digital Video Encoder

SLAS184 July 1998

Printed on Recycled Paper

IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.

CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Contents

Section Title Page

1 Introduction 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1 Features 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 Applications 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 Functional Block Diagram 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4 Terminal Assignments 1–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.5 Ordering Information 1–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.6 Terminal Functions 1–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Detailed Description 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 Initialization 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 I

2.3 Data Manager 2–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4 Scaling Processor 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5 Video Encoder 2–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6 Closed Caption 2–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7 Clock Generation 2–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.8 Analog Output 2–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.9 Video Port Interface 2–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.10 Modes of Operation 2–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11 Register Descriptions 2–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C Interface 2–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.1 Luminance Encoding 2–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.2 Luminance Low-Pass and Interpolation Filter 2–6. . . . . . . . . . . . . . . . . . . . . .

2.5.3 Cross Color Reduction Filter 2–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.4 Chrominance Encoding 2–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.9.1 RCV1 2–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.9.2 RCV2 2–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.9.3 RCM1 2–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.9.4 RCM2 2–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.10.1 Master Mode 2–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.10.2 Slave Mode 2–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.10.3 Demand Mode 2–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.10.4 Genlock Mode 2–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 1.1 DEV_ID 2–17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 1.2 REV_ID 2–17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 1.3 STA TUS 2–17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 1.4 F_CONTROL 2–18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 1.5 C_PHASE 2–19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 1.6 GAIN_U 2–19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 1.7 GAIN_V 2–19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 1.8 BLACK_LEVEL 2–19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 1.9 BLANK_LEVEL 2–20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

iii

Contents (Continued)

Section Title Page

2.11.10 GAIN_Y 2–20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 1.1 1 X_COLOR 2–20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 1.12 M_CONTROL 2–21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 1.13 BST AMP 2–21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.14 S_CARR1, 2, 3, 4 2–22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 1.15 LINE21_O0 2–23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 1.16 LINE21_O1 2–23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 1.17 LINE21_E0 2–23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 1.18 LINE21_E1 2–23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 1.19 LN_SEL 2–23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 1.20 SYN_CTRL0 2–24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 1.21 RCM_L21 2–26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 1.22 HTRIGGER0 2–28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 1.23 HTRIGGER1 2–28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 1.24 VTRIGGER 2–28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 1.25 BMRQ 2–29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 1.26 EMRQ 2–29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 1.27 BEMRQ 2–29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 1.28 BRCV 2–29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 1.29 ERCV 2–30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 1.30 BERCV 2–30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 1.31 FLEN 2–30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 1.32 FAL 2–30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 1.33 LAL 2–31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 1.34 FLAL 2–31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 1.35 SYN_CTRL1 2–31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 1.36 SCM 2–32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 1.37 SLPF 2–32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 1.38 SPPL 2–33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 1.39 SLPH 2–33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 1.40 DLPF 2–33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 1.41 DPPL 2–33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 1.42 DLPH 2–34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 1.43 VDT AL 2–34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 1.44 VDT AH 2–34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 1.45 HDT AL 2–34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 1.46 HDT AH 2–35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 1.47 VOFS 2–35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 1.48 HOFS 2–35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 1.49 NLR 2–35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.50 TEST1, TEST2, TEST3 2–35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents (Continued)

Section Title Page

3 Electrical Characteristics 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range 3–1. . . . .

3.2 Recommended Operating Conditions 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 DC Electrical Characteristics, T

3.4 AC Electrical Characteristics, T

3.5 Timing Requirements 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6 Demand Mode Timing 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.7 Switching Characteristics 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A Example Register Settings A–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B Mechanical Data B–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

= 25°C, DVDD = AVDD = 5 V 3–1. . . . . . . . . . . . . . .

= 25°C, DVDD = AVDD = 5 V 3–2. . . . . . . . . . . . . . .

List of Illustrations

Figure Title Page

1–1 Terminal Assignments 1–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–1 Block Diagram 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–2 I

C Start and Stop Conditions 2–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–3 I

C Access Cycles 2–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–4 I

C Write Cycle 2–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–5 I

C Read Cycle 2–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–6 Luma Path Frequency Response 2–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–7 Luma Cross Color Reduction Filter 2–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–8 Chroma Path Frequency Response 2–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–9 NTSC CCIR601 Rate Closed Caption Line 2–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–10 PAL CCIR601 Pixel Rate Closed Caption Line 2–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–11 NTSC Square Pixel Rate Closed Caption Line 2–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–12 PAL Square Pixel Rate Closed Caption Line 2–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–13 Output Filter 2–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–14 Transmission Timing 2–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–1 Data Setup and Hold Timing 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–2 Demand Mode Timing 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

List of Tables

Table Title Page

2–1 16-Bit Video Port YUV 4:2:2 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–2 8-Bit Multiplexed Video Port CCIR656 YUV 4:2:2 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–3 100/100 Color Bar in Twos Complement 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–4 Master Mode 2–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–5 Crystal Frequencies 2–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–6 Slave Mode Signals 2–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–7 Base Addresses 2–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–8 Register Bit Allocation Map 2–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–9 Input Format and Data Sampling 2–18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–10 Chroma Channel Delays 2–20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–11 Total Horizontal Pixel Selection 2–22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–12 S_CARR Values 2–22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–13 RCV1 Pin Configurations 2–25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–14 RCV1 Symbols and Signal Descriptions 2–25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–15 RCV2 Pin Configurations 2–25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–16 RCV2 Symbols and Signal Descriptions 2–26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–17 RCM1 Output Signals 2–27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–18 RCM2 Pin Configurations 2–27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–19 Encoding Setting 2–27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–20 Phase Reset Modes 2–28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–21 Active Video Modes 2–32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1 Introduction

The TVP6000 is a digital video encoder designed for multimedia systems requiring high-quality flicker free display of computer graphics, video, and internet content.

The TVP6000 provides advanced horizontal and vertical scaling for overscan compensation. It features a 3 tap antiflicker filter. The encoder has different filters in the luma and the chroma channels. Additionally, the output is interpolated to twice the pixel frequency . All of these features combine to produce a high-quality display of non-interlaced data on a traditional interlaced TV.

The TVP6000 converts Y Cb Cr video data to base-band analog video output. The input can come from a video decoder (such as the TI TVP5010/TVP5020), a 3D graphics controller (such as the TI 4020), or a MPEG decoding device. Simultaneous composite and S-video (Y , C separated) provides high-quality video output.

1.1 Features

• Digital Input Formats: – YUV 4:2:2 on a 16-Bit Port – CCIR-656 YUV 4:2:2 on an 8-Bit Port – YUV 4:2:2 on an 8-Bit Port

• CCIR601 or Square Pixel Operation

• Analog Output Formats:

– NTSC-M – PAL-B,D,G,H,I – PAL-M – PAL-N – PAL-Nc

• Simultaneous S-Video and CVBS (Composite Baseband Video) Output

• 2x Over-Sampling

• 3-Tap Antiflicker Filter

• Triple 10-Bit DACs

• Overscan Compensation

• Programmable Video Port Interface

• Supports Master, Slave, CCIR656 and Demand Mode Video Port Interface

• Programmable Blank Level, Black Level, and Color Burst Amplitude

• Programmable Luminance and Chrominance Gains

• Programmable Subcarrier Frequency

• Programmable SCH

• Subcarrier Genlock Capability

1–1

• Programmable Luminance Delay

C Serial Interface

• I

• On Chip Color Bar Generation

• Closed Caption Support

• Software Detection of TV Connection

• On Chip Voltage Reference

• Cross Color Reduction Filter

• Power Down Mode

• 80-pin TQFP Package

• 5-V Operation

• Supports PC98 Hardware Design Specification

• SMPTE 170M NTSC Composite Video Specification Compliant

• CCIR624/CCIR601 PAL Composite Video Specification Compliant

1.2 Applications

• Digital Entertainment/ Set Top Box

• Internet PC

• Internet Appliance

• PC-to-TV Appliance

• Digital Video Disk (DVD)

• Digital Video Camera

1.3 Functional Block Diagram

VP1(0–7) VP2(0–7)

SDA SCL

XTAL1 XTAL2

1–2

Data

Manager

Serial

Interface

Clock

Generation

RCM1

Scaling Filter

Timing and

Synchronization

RCM2

RCV1 RCV2

Closed

Caption

Modulator

and Gain

Control

Cross Color

Reduction

REF

CVBS

COMP

FSADJ

1.4 Terminal Assignments

PFP PACKAGE

(TOP VIEW)

NC NC NC

XDAC

CCIR

NTSQ

PASQ

DVDD VP1[7] DGND VP1[6] VP1[5] DGND VP1[4]

DVDD VP1[3] VP1[2] VP1[1] VP1[0]

VP2[0]

VP2[1]

59 58 57 56 5560 54

61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

VP2[2]

VP2[3]

5678

VP2[4]

VP2[5]

VP2[6]

VP2[7]

52 51 5053

VSUB

DVDD

49 48

10 11 12 13

DGND

DVDD

47 46 45 44

14 15 16 17

INVGND

REFV

REFGND

FSADJ

DREF

43 42 41

18 19 20

COMP

VREF

40 39 38 37 36 35 34 33 32 31 30 29 27 27 26 25 24 23 22 21

NC AVDD CVBS AGND AVDD Y AGND AVDD C AGND NC NC NC NC NC NC NC NC NC NC

RCV1

RCM1

RCV2

RCM2

CREF

DGND

LLC

RES

DVDD

GLCI DGND

SDEN

TST

Figure 1–1. Terminal Assignments

XT AL1

XT AL2

SCL

SDA

CDIR

DGND

DVDD

1–3

1.5 Ordering Information

I/O

DESCRIPTION

Device TVP6000CPFP PFP: Plastic Flat Pack With Power Pad

1.6 Terminal Functions

TERMINAL

NAME NO.

AGND 31,34,37 Analog ground AVDD 33,36,39 Analog power supply C 32 O Chrominance analog output signal for S-video output

External clock source select. CCIR can be programmed to select different external

CCIR 65 O

CDIR 18 I

COMP 41 I/O CREF 5 I/O Clock reference signal

CVBS 38 O Composite video output signal DGND DREF 43 I/O T est pin. For normal applications no connect. DVDD

FSADJ 44 I/O GLCI 10 I Genlock control input. GLCI is used for communicating with TVP5xxx decoder series.

INVGND 47 INVGND should be connected to AGND for normal applications. LLC 7 I/O

NTSQ 66 O

PASQ 67 O

6,19,48,

51,70,73

8,20,49,

52,68,75

21–30,40,

61–63,80

clock sources. When CCIR = 1, the encoder is set to CCIR601 mode. For detailed programming information, refer to Table 2–11.

Clock direction input. When CDIR = 0, LLC and CREF are outputs. When CDIR = 1, LLC and CREF are inputs.

Compensation pin for the internal reference amplifier. A 0.1-µF capacitor should be connected between COMP and A VDD.

Digital ground

Digital power supply Full scale adjust control. A 264-Ω resistor should be connected between FSADJ and

AGND to control the full-scale output current on the analog outputs.

Line locked clock. One of the 24.54 MHz, 27.00 MHz, or 29.5 MHz clocks for different standards and pixel rates.

No connect External clock source select. NTSQ can be programmed to select different external

clock sources. When NTSQ = 1, the encoder is set to NTSC square pixel mode. For detailed programming information, refer to Table 2–11.

External clock source select. PASQ can be programmed to select different external clock sources. When PASQ = 1, the encoder is set to PAL square pixel mode. For detailed programming information, refer to Table 2–11.

1–4

1.6 Terminal Functions (Continued)

I/O

DESCRIPTION

TERMINAL

NAME NO.

RCM1 1 O

RCM2 3 I/O

RCV1 2 I/O

RCV2 4 I/O

VREF 42 I/O REFGND 45 Reference ground of output DACs. REFGND should be connected to AGND.

REFV

RES 9 I Reset input, active low SA 15 I I2C slave address select SCL 16 I/O I2C serial clock input. Maximum clock rate of 400 kHz. SDA 17 I/O I2C serial data line SDEN 11 I Test pin. For normal applications connect to DGND. TST 12 I T est pin. For normal applications connect to DGND.

VP1[7:0]

VP2[7:0] 53–60 I VSUB 50 VSUB should be connected to AGND.

XDAC 64 I

XTAL1 13 I Crystal or oscillator input. CMOS input levels XTAL2 14 I Crystal input. Crystal is connected between XTAL1 and XTAL2. Y 35 O Luminance analog output signal for S-video output

46 Reference power supply of the DACs. REFVDD should be connected to AVDD.

69,71,72, 74,76–79

Programmable video vertical timing signal. For detailed programming information, see the RCM_L21 register definition.

Programmable video horizontal timing signal (can also be programmed for horizontal active video signal. For detailed programming information, see RCM_L21 register definition.

Programmable video vertical timing signal. For programming infromation, see SYN_CTRL0 register definition.

Programmable video horizontal timing signal (can also be programmed for horizontal active video signal). For detailed programming infromation, see SYN_CTRL0 register definition.

Test pin. VREF can be used for bandgap voltage output. For normal operation no connection.

Y input port in 16-bit mode. For 8-bit multiplexed mode, VP1[7:0] is either the YUV

multiplexed port or should be left unconnected based on the FMT(2) register bit. UV input port in 16-bit mode. For 8-bit multiplexed mode, VP2[7:0] is either the YUV

multiplexed port or should be left unconnected based on the FMT(2) register bit.

XDAC sets the initial mode of operation for the output DACs immediately after reset. If XDAC = GND the DACs will be in normal operation mode after reset. If XDAC = VDD, the DACs will be in power down mode.

1–5

1–6

2 Detailed Description

The TVP6000 is a digital video encoder designed for systems requiring high-quality display of computer graphics, video, video conferencing, and Internet content. It is designed to convert a digital video input data stream into NTSC or P AL composite video output. Digital input formats include 8 or 16 bit YUV 4:2:2 or 8 bit CCIR–656 YUV. Analog output formats are NTSC and PAL.

The encoder provides picture quality enhancement features such as overscan compensation, which allows up to a 12.5% down scaling of pixels (horizontal) and lines (vertical) to allow fitting a VGA frame on a NTSC. A 3-tap antiflicker filter greatly reduces annoying flicker associated with displaying progressive scan graphics data or text on an interlace display , like TV. The output has simultaneous S-video and composite baseband video (CVBS) via three 10-bit DACs. Programmable features such as blank levels, color burst amplitude, luminance and chrominance gains, subcarrier frequency, luminance delay allow for easy optimization of picture quality and subcarrier genlock capability when used with a compatible video decoder provides accurate color reproduction even with nonstandard or unstable video sources such as a VCR.

See Figure 2–1 for an overview of the major functional blocks of the TVP6000.

2.1 Initialization

Upon power up, the TVP6000 is initialized by the internal logic to display a color bar. With this feature, the TVP6000 is able to demonstrate basic functionality while using only a 27-MHz clock signal at the LLC pin or the XTAL1 and XTAL2 crystal pins. No software programming is required for this initial operation. This serves as a quick diagnostic tool during the initial debug of a system.

The DACs can also be optionally turned off immediately after reset by connecting the XDAC pin (pin 64) to

if the initial color bar display is not desired. In this case, video is not output after reset. See Section 2.1 1,

for details about the default values immediately after power up.

2–1

DAC

10-Bit

Filter

Reduction

Cross Color

CVBS

10-Bit

DAC

10-Bit

COMP

DAC

42 44

VREF FSADJ

sin

Closed

Caption

Generator

Scaling

Processor

and

Filters

LowPass

Interpolation

76–79

69,71,72,74

(5.7 MHz)

Data

Manager

Modulator

and

LowPass

Unit

Cr/Cb

53–60

and

Gain Control

Filters

(1.3 MHz)

Interpolation

Cr/Cb

cos

sin

SCL

L.U.T.

SIN/COS

Generator

Sync. Clock

Logic

I2C Control

SDA

2–2

Figure 2–1. Block Diagram

2.2 I2C Interface

The I2C interface is used to access the internal registers of the TVP6000 encoder. This two pin interface consists of one clock line, SCL, and one serial data line, SDA. The basic I2C access cycles are shown in Figure 2–3.

SDA

SCL

Start Condition (S) Stop Condition (P)

Figure 2–2. I2C Start and Stop Conditions

The basic access cycle consists of the following:

1. A start condition

2. A slave address cycle

3. A subaddress cycle

4. Any number of data cycles

5. A stop condition

The start and stop conditions are shown in Figure 2–2. The high-to-low transition of SDA while SCL is high, defines the start condition. The low-to-high transition of SDA while SCL is high, defines the stop condition. Each cycle, data or address, consists of 8 bits of serial data followed by one acknowledge bit generated by the receiving device. Thus, each data/address cycle contains nine bits as shown in Figure 2–3.

123456789123456789123456789

SCL

SDA

MSB

Slave Address Subaddress Data

Acknowledge Acknowledge Acknowledge

Stop

Figure 2–3. I2C Access Cycles

As indicated in Figure 2–3, following a start condition, each I

C device decodes the slave address. The TVP6000 responds with an acknowledge by pulling the SDA line low during the ninth clock cycle, if it decodes the address as its address. During subsequent subaddress and data cycles, the TVP6000 responds with an acknowledge as shown in Figure 2–3. The subaddress is auto-incremented after each data cycle.

The transmitting device must not drive the SDA signal during the acknowledge cycle so that the receiving device may drive the SDA signal low. The not acknowledge, A

, condition is indicated by the master by keeping the SDA signal high just before it asserts the stop, P, condition. This sequence terminates a read cycle as shown in Figure 2–5.

2–3

The slave address consists of 7 bits of address along with 1 bit of read/write information as shown in Figures 2–4 and 2–5. For the TVP6000, the possible slave addresses (including the read/write bit) are 0x40 or 0x42 for write cycles or 0x41 and 0x43. Refer to Table 2–7 for additional base address information.

From Receiver

S Slave Address W Sub Address A Data A PA Data A

= No Acknowledge (SDA High)

A A = Acknowledge S = Start Condition P = Stop Condition W = Write

S Slave Address W A PA S Slave Address R A PA Data A Data

A = No Acknowledge (SDA High) A = Acknowledge S = Start Condition P = Stop Condition W = Write R = Read

From Transmitter

Figure 2–4. I2C Write Cycle

Receiver

Transmitter

Sub Address

Transmitter

Receiver

Figure 2–5. I2C Read Cycle

2.3 Data Manager

The data manager resides at the very beginning of the processing pipeline. It receives the Y Cb Cr pixel data from the pixel bus and converts it to its internal YUV representation. Register F_CONTROL at subaddress 3A and the SCN bit of the SCM register at subaddress 90 define the function of the data manager.

The data manager can receive data on either an 8-bit or 16-bit video port. In the 8-bit format, it receives data at port VP1 or VP2 (both 8-bits wide) depending on register bit FMT2, at every rising edge of LLC if scan conversion is disabled, and at every (rising and falling) edge of LLC if scan conversion is enabled. In the 16-bit format, it receives luminance information on the VP1 port and chrominance information on the VP2 port, at alternate rising edges of LLC (qualified by CREF) if scan conversion is disabled, or at every rising edge of LLC if scan conversion is enabled. Additionally , the data manager can generate pixels internally for a 100/100 color bar if the CBAR bit is set. The Y, U, and V values for this color bar are shown in T able 2–3.

2–4

Table 2–1. 16-Bit Video Port YUV 4:2:2

TIME 0 1 2 3 4 5 6 7

VP1[7:0] Y0 Y1 Y2 Y3 VP2[7:0] Cb0 Cb1 Cb2 Cb3

Luma pixel number 0 1 2 3

Chroma pixel number 0 2

Table 2–2. 8-Bit Multiplexed Video Port CCIR656 YUV 4:2:2

TIME 0 1 2 3 4 5 6 7

VP1[7:0] or VP2[7:0] Cb0 Y0 Cr0 Y1 Cb2 Y2 Cr2 Y3

Luma pixel number 0 1 2 3

Chroma pixel number 0 2

Table 2–3. 100/100 Color Bar in Twos Complement

COLOR Y (hex) Cb (hex) Cr (hex)

White 6B 00 00

Yellow 52 90 12

Cyan 2A 26 90

Green 11 B6 A2

Magenta EA 4A 5E

Red D1 DA 70

Blue A9 70 EE

Black 90 00 00

The SCN bit in the SCM register enables or disables scan conversion. When scan conversion is disabled (SCN = 0), the input scan lines are interlaced at a field rate of 60 Hz for 525-line systems or 50 Hz for 625-line systems. When scan conversion is enabled (SCN = 1), the input scan lines are non-interlaced at a frame rate of 60 Hz or 50 Hz.

2.4 Scaling Processor

The scaling processor scales down the input image in both horizontal and vertical directions. In addition to scaling, the scaling processor filters the image in the vertical direction and removes annoying flickers, which are common when a computer-generated graphics or text, especially a static image, is displayed on TV . The scaling processor uses a 3-tap adaptive filter, whose coef ficients are dynamically adjusted on a line-by-line basis to maintain optimal performance.

The scaling processor is enabled by setting the SCN register bit to 1. When scan conversion is enabled, the data manager receives non-interlaced pixel data via the demand mode interface and passes pixel data on to the scaling processor for overscan-compensation processing. The output of the scaling processor feeds the video encoder core for encoding. See Section 2.5,

Video Encoder

When the scaling processor is disabled, SCN reset to 0, the data manager receives pixel data via master or slave mode and passes pixel data directly to the video encoder core, bypassing the scaling processor.

The scaling processor, when enabled, is controlled by the following registers: SPPL, DPPL, SLPF, and DLPF . These registers define the size of the image before and after scaling. The SPPL register defines the number of active pixels per line before scaling and the DPPL register defines the number of active pixels per line after scaling. The SLPF register defines the number of active lines before scaling and the DLPF register defines the number of active lines after scaling. Refer to Section 2.11, additional information on these registers.

for a detailed description.

for

2–5

Vertical and horizontal over-scan compensation ratios are independently controlled by two pairs of registers. The VDTAH and VDTAL register pair define the vertical scaling ratio and the HDTAH and HDTAL register pair define the horizontal scaling ratio. The scaling ratio equations are given in the register description section. An over-scan compensation ratio up to 12.5% in both vertical and horizontal directions is supported.

When enabled, three modes of vertical scaling and two modes of horizontal scaling are provided for optimal performance of the target application. For computer graphics and text intensive static images, mode 2 vertical scaling (VSC[1:0] = 2) should be used for maximum flicker reduction. For DVD playback, mode 3 (VSC[1:0] =3) should be used for sharpness. The nearest neighbor mode is provided only for comparison and diagnostic purposes, and should not be used for normal applications.

Finally, the scaled image can be placed on the TV screen at a location defined by the VOFS and HOFS registers. VOFS and HOFS define the location of the upper left corner of the output image. See the definitions of the VOFS and HOFS registers for details.

Note that the SWPF bit is provided for test and diagnostic purposes. For normal applications, this bit must be set to 0 at all times.

2.5 Video Encoder

2.5.1 Luminance Encoding

Programmable gain is first applied to the luminance data output from the data manger or scaling processor depending on whether the TVP6000 is in regular or scan-conversion mode. The luminance gain is defined by the GAIN_Y register at subaddresses 5F and 60. The horizontal sync, vertical sync, and setup insertion are then performed. Both black level and blank level are programmable through the BLACK_LEVEL and BLANK_LEVEL registers at subaddresses 5D and 5E, respectively.

All of the transition edges of the luminance signal such as the sync edges and active video edges are properly shaped and filtered to limit the bandwidth within the standards.

2.5.2 Luminance Low-Pass and Interpolation Filter

After all of the necessary components of the luminance signal have been added, the resultant signal is low-passed and interpolated to a 2x pixel rate. This 2x interpolation simplifies the external analog reconstruction filter design and improves the signal-to-noise ratio. Refer to Figure 2–6 for the filter frequency response.

2–6

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