Texas Instruments TVP5020CPFP Datasheet

TVP5020

NTSC/P AL VIDEO DECODER

Data Manual

May 2000 Mixed-Signal Products

SLAS186B

IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.

CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICA TIONS IS UNDERSTOOD T O
BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
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party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Copyright  2000, Texas Instruments Incorporated

iii

Contents

Section Title Page

1 Introduction 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1 Features 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 Applications 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 Functional Block Diagram 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4 Terminal Assignments 1–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.5 Ordering Information 1–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.6 Terminal Functions 1–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Detailed Description 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 Analog Video Processors and A/D Converter 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.1 Video Input Selection 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.2 Analog Input Clamping and Automatic Gain Control Circuits 2–1. . . . . . . . . . .

2.1.3 A/D Converter 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 Digital Processing 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.1 Y/C Separation 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.2 Luminance Processing 2–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.3 Chrominance Processing 2–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.4 Clock Circuits 2–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 Video Output Format 2–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.1 Sampling Frequencies and Patterns 2–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.2 Video Port 16-Bit 4:2:2 Output Format Timing 2–8. . . . . . . . . . . . . . . . . . . . . . . .

2.3.3 Video Port 12-Bit 4:1:1 Output Format Timing 2–9. . . . . . . . . . . . . . . . . . . . . . . .

2.3.4 Video Port 8-Bit 4:2:2 and ITU-R BT.656 Output Format Timing 2–9. . . . . . . .

2.4 Synchronization Signals 2–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5 I

2

C/VIP/VMI Host Interface 2–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6 I2C Interface 2–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6.1 I2C Host Port Select 2–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6.2 I2C Write Operation 2–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6.3 I2C Read Operation 2–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6.4 I

2

C Microcode Write Operation 2–16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6.5 I2C Microcode Read Operation 2–17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7 VIP Host Interface Port 2–19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7.1 VIP Host Port Terminal Description 2–20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7.2 VIP Phases 2–20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7.3 Command Byte 2–21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7.4 VIP Microcode Write Operation 2–26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7.5 VIP Microcode Read Operation 2–26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.8 Video Module Interface (VMI) Host Interface 2–26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.9 Host Port – Mode A Timing 2–27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.10 Host Port – Mode B Timing 2–28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11 Host Port – Mode C Timing (PPC) 2–28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

iv

2.11.1 VMI Register Mapping 2–29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.2 VMI Microcode Write Operation 2–30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.3 VMI Microcode Read Operation 2–31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.12 Genlock Control 2–31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.13 VBI Data Processor 2–32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.13.1 Teletext Data Byte Order 2–32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.13.2 Teletext as Ancillary Data in Video Stream 2–33. . . . . . . . . . . . . . . . . . . . . . . . .

2.14 Reset 2–36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.15 Internal Control Registers 2–37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.15.1 Register Definitions 2–38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.15.2 Vendor ID 2–38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.15.3 Device ID 2–39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.15.4 Subsystem Vendor ID 2–39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.15.5 Subsystem Device ID 2–39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.15.6 Subsystem Revision ID 2–39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.15.7 Analog Input Source Selection 2–40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.15.8 Analog Channel Controls 2–41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.15.9 Operation Mode Controls 2–42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.15.10 Miscellaneous Controls 2–43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.15.11 Color Killer Threshold Control 2–44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.15.12 Luminance Processing Control 1 2–45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.15.13 Luminance Processing Control 2 2–46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.15.14 Brightness Control 2–47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.15.15 Color Saturation Control 2–47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.15.16 Hue Control 2–47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.15.17 Contrast Control 2–48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.15.18 Outputs and Data Rates Select 2–48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.15.19 Horizontal Sync (HSYN) Start 2–49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.15.20 Vertical Blanking Start 2–49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.15.21 Vertical Blanking Stop 2–50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.15.22 Chrominance Control 2–51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.15.23 Digital Channel Selection 2–52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.15.24 Firmware Version 2–52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.15.25 Status Register 1 2–53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.15.26 Status Register 2 2–54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.15.27 AGC Gain 2–54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.15.28 TXF Filter #1 Parameters 2–55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.15.29 TXF Filter #2 Parameters 2–56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.15.30 TXF Error Filtering Enables 2–57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.15.31 TXF Transaction Processing Enables 2–57. . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.15.32 TTX Control Register 2–58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.15.33 Line Enable Registers 2–58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.15.34 Sync Pattern Register 2–59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.15.35 Teletext FIFO 2–59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.15.36 Closed Caption Data 2–59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.15.37 Buffer Status 2–60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.15.38 Interrupt Threshold 2–60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

v

2.15.39 Interrupt Line Number 2–60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.15.40 FIFO Control 2–61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.15.41 Interrupt Status Register 2–62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.15.42 Interrupt Enable Register 2–63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.15.43 Interrupt Configuration Register 2–63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.15.44 Interrupt Status Register 2–63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 Electrical Specifications 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1 Absolute Maximum Ratings† 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 Recommended Operating Conditions 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 Electrical Characteristics 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3.1 Analog Processing and Analog-to-Digital Converter 3–2. . . . . . . . . . . . . . . . . .

3.3.2 DC Electrical Characteristics 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4 Timing 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4.1 Clocks, Video Data, Sync Timing 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4.2 I

2

C Host Bus Timing 3–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4.3 VIP Host Port Timing 3–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4.4 VMI Host Port Timing (Mode A) 3–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4.5 VMI Host Port Timing (Mode B) 3–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 Mechanical Data 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

vi

List of Illustrations

Figure Title Page

2–1 Analog Video Processors and A/D Converter 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–2 Digital Video Signal Processing Block Diagram 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–3 Chroma Trap Filter Frequency Response for 13.5 MHz Sampling 2–3. . . . . . . . . . . . . . . .

2–4 Chroma Trap Filter Frequency Response for Square-Pixel Sampling 2–3. . . . . . . . . . . . .

2–5 Luminance Edge-Enhancer 2–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–6 Peaking Filter Response, 13.5 MHz Sampling 2–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–7 Peaking Filter Response, NTSC AND PAL-M SQUARE PIXEL 2–5. . . . . . . . . . . . . . . . . . .

2–8 Peaking Filter Response, PAL Square Pixel 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–9 Transfer Curve of Coring Circuit 2–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–10 Clock Circuit Diagram 2–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–11 Reference Clock Configurations 2–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–12 4:2:2 Sampling 2–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–13 4:1:1 Sampling 2–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–14 16-Bit 4:2:2 Output Format 2–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–15 12-bit 4:1:1 Output Format 2–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–16 8-Bit 4:2:2 and ITU-R BT.656 Output Formats 2–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–17 Vertical Synchronization Signals 2–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–18 Horizontal Synchronization Signals 2–1 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–19 Host Interface 2–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–20 I

2

C Data Transfer Example 2–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–21 VIP Transfer Example 2–20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–22 Functional Timing Reading From TVP (Example) 2–22. . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–23 Functional Timing Writing to TVP (Example) 2–23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–24 Functional Timing Reading From FIFO (Example) 2–23. . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–25 Functional Timing Example of Slave Termination 2–24. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–26 VMI Host Port Mode A Timing 2–27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–27 Host Port Mode B Timing 2–28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–28 Host Port Mode C Timing 2–28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–29 VMI Address Register Map 2–29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–30 GLCO Timing 2–32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–31 Video Input Source Selection 2–40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–1 Clock, Video and Sync Timing 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–2 I

2

C Bus Timing 3–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–3 VIP Host Port Timing 3–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–4 VMI Host Port Timing (Mode A) 3–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–5 VMI Host Port Timing (Mode B) 3–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

vii

List of Tables

Table Title Page

2–1 Summary of the Line Frequencies, Data Rates, and Pixel Counts 2–7. . . . . . . . . . . . . . . .

2–2 Host Port Select 2–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–3 I2C Host Port Terminal Description 2–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–4 VIP Host Port Terminal Description 2–20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–5 VIP Host Port Phase Description 2–21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–6 Condensed Table Command/Address 2–21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–7 VMI Host Port Select 2–26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–8 VMI Host Port Terminal Definitions 2–27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–9 Teletext Byte Order 2–32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–10 NABTS 525/625-Line Ancillary Data Sequence 2–34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–11 WST 525-Line Ancillary Data Sequence 2–35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–12 WST 625-Line Ancillary Data Sequence 2–35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–13 Dummy Timing Ancillary Data Sequence 2–36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–14 Ancillary Data ID 2–36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–15 Power-Up Reset Sequence 2–36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–16 Registers Summary 2–37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–17 Analog Channel and Video Mode Selection 2–40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–18 YUV Output Controls 2–43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

viii

1–1

1 Introduction

The TVP5020 is a high-quality single-chip digital video decoder that converts base-band analog NTSC and
PAL video signals into digital component video. Sampling is square-pixel or ITU-R BT.601 (13.5 MHz) and
is line-locked for correct pixel alignment. The output formats can be 8-bit or 16-bit 4:2:2, 12-bit 4:1:1, or 8-bit
ITU-R BT.656. The TVP5020 uses TI patented technology for locking to weak, noisy, or unstable signals.
A genlock control output is generated for synchronizing downstream video encoders.

Two-line (1-H delay) comb filtering is available for both the luma and chroma data paths to reduce both
cross-luma and cross-chroma artifacts; a chroma trap filter is also available. Video characteristics including
hue, contrast, and saturation are programmable using one of five supported host port interfaces. The
TVP5020 generates synchronization, blanking, field, lock, and clock signals in addition to digital video
outputs.

The TVP5020 includes advanced vertical blanking interval (VBI) data retrieval. The VBI data processor
slices, parses, and performs error checking on teletext data in several formats. A built-in FIFO stores up to
14 lines of teletext data and, with proper host port synchronization, full-field teletext retrieval is possible. The
VBI data processor also retrieves closed-caption data.

The main blocks of TVP5020 include:

• Analog processors and A/D converter

• Y/C separation

• Chrominance processor

• Luminance processor

• Clock/Timing processor and power-down control

• Output formatter

• Host port interface

• VBI data processor

1.1 Features

• NTSC (M) and PAL (B, D, G, H, I, M, N) composite video

• Two analog video inputs for up to two composite inputs

• Single built-in-analog signal processing channels with clamping and AGC

• Single high speed 8-bit A/D converter

• Patented architecture for locking to weak, noisy, or unstable signals

• Comb filters for both cross-color and cross-luminance noise reductions

• Line locked clock and sampling

• Programmable data rates:

– 12.2727 MHz square-pixel (NTSC)
– 14.7500 MHz square-pixel (PAL)
– 13.5 MHz ITU-R BT.601 (NTSC and PAL)

• Programmable output formats: 16-bit or 8-bit 4:2:2 YCbCr, 12-Bit 4:1:1 YCbCr and ITU-R BT.656
with embedded syncs

1–2

• Teletext (NABTS, WST) and closed caption decode with FIFO

• ITU-R BT.601 or extended coding range

• Programmable host port options including I

2

C, VMI (3 modes), and VIP

• 80-terminal TQFP package

1.2 Applications

• Digital image processing

• Video conferencing

• Multimedia

• Digital video

• Desktop video

• Video capture

• Video editing

1.3 Functional Block Diagram

A/D

AGC

Luma/Chroma

Separation

Luminance
Processing

Chrominance

Processing

Output

Formatter

Line

and

Chroma

PLL’s

Sync

Processor

VI1A
VI1B

XTAL1
XTAL2

SCLK
PCLK
PREF

GLCO

Y (7:0)
UV (7:0)

OEB

HSYN
VSYN
FID

PALI
GPCL

RSTINB

VMI Interface

VBI

D (7:0)

A0

VC (0–3)

INTREQ

M
U
X

Channel 1

I2C Interface

A1

M
U
X

1–3

1.4 Terminal Assignments

TQFP PACKAGE

(TOP VIEW)

22 23

UV7
UV6
UV5
DGND
UV4
UV3
DVDD
UV2
UV1
UV0
Y7
Y6
Y5
DGND
Y4
Y3
DVDD
Y2
Y1
Y0

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41

24

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

NC
NC

CH1_AGND

VI_1B
VI_1A

CH1_AVDD

REFM

REFP
AVDD

NC
NC

AGND

NC
NC
NC

AFE_GND

NSUB

AFE_VDD

DTO_AVDD

DTO_AGND

25 26 27 28

D5

79 78 77 76 7580 74

VC1

VC2

VC3

DVDDA1A0

D7

GLCO

FID

RSTINB

DGND

PLL_AVDD

GPCL

AVID

PLL_BYP

VSYN

72 71 7073

29 30 31 32 33

69 68

21

DGND

DGND

67 66 65 64

34 35 36 37

DVDD

XTAL1

XTAL2

DGND

D3D2DVDD

D1

INTREQ

VC0

SCLK

PREF

38 39 40

D0

OEB

63 62 61

D4

EXT_DATA_8

DGND

PALI

PCLK

HSYN

D6

1.5 Ordering Information

DEVICE: TVP5020CPFP
PFP: Plastic flat-pack with PowerPAD

1–4

1.6 Terminal Functions

TERMINAL

NAME NO.

I/O

DESCRIPTIONS

Analog video

VI_1A
VI_1B

5
4

I Analog video inputs. Up to two composite inputs. The inputs must be AC coupled. The

recommended coupling capacitor is 0.1 µF.

Clock Signals

PCLK 40 O Pixel clock output. The frequency is 12.2727 MHz for square-pixel NTSC,

14.75 MHz for square-pixel PAL, and 13.5 MHz for ITU-R BT.601 sampling modes.

PREF 39 O Clock phase reference signal. This signal qualifies clock edges when SCLK is used to

clock data that is changing at the pixel clock rate.
SCLK 38 O System clock output with twice the frequency of the pixel clock (PCLK).
XTAL1

XTAL2

35
36

I External clock reference. The user may connect XTAL1 to a TTL-compatible

oscillator or to one terminal of a crystal oscillator. The user may connect XT AL2 to the

other terminal of the crystal oscillator or not connect XTAL2 at all. Square pixel

sampling uses an oscillator frequency of 26.800 MHz. ITU-R BT.601 sampling uses

an oscillator frequency of 24.576 MHz.

Digital Video

EXT_DATA_8 61 I Bit [8] of a 9-or 10-bit digital composite video input
UV[0:7] 51, 52,

53, 55,
56, 58,

59, 60

I/O Digital chrominance outputs. These terminals may be configured to output data from

the channel 2 A/D converter. A vendor modifiable subsystem ID may be initialized by

configuring the UV [7:0] terminals with pull-up/pull-down resistors.

Y[0:7] 41, 42,

43, 45,
46, 48,

49, 50

O Digital luminance outputs, or multiplexed luminance and chrominance outputs.

These terminals may be configured to output data from the channel 1 A/D converter.

HOST PORT-bus VMI I2C VIP

A[0:1] 73, 74 I VMI address port
D[0:7] 63, 64

66, 67
69, 70
71, 72

I/O VMI data port – bit [7:0].

INTREQ 80 O Interrupt request (INTREQ) Interrupt request (VIRQ)
VC0 79 I/O VMI port data ack. or ready

signal (DTACK)

Serial clock (SCL) Hardware address

bit-0 (HAD[0])

VC1 78 I/O VMI Port Read-Write or

Write (RW/WR)

Serial data (SDA) Hardware address bit-1

HAD[1]

VC2 77 I/O VMI port data strobe or read

signal (DS/RD)

Hardware control (HCTL)

VC3 76 I VMI port chip select. (VC) Slave address select

(I2CA)

VIPCLK

1–5

1.6 Terminal Functions (Continued)

TERMINAL

NAME NO.

I/O

DESCRIPTIONS

Miscellaneous signals

GPCL 26 I/O General-purpose control logic. This terminal has three functions:

1. General-purpose output. In this mode the state of GPCL is directly
programmed via the host port.

2. Vertical blank output. In this mode the GPCL terminal is used to indicate
the vertical blanking interval of the output video. The beginning and end
times of this signal are programmable via the host port control.

3. Sync lock control input. In this mode when GPCL is high, the output clock
frequencies and sync timing are forced to nominal values.

GLCO 31 I/O This serial output carries color PLL information. A slave device can decode the

information to allow genlocking to the TVP5020. Data is transmitted at the SCLK
rate. Additionally, this terminal, in conjunction with PALI and FID, is used to
determine the host port mode configuration during initial power up.

OEB 62 I Output enable for Y and UV terminals. Output enable is also controllable via the

host port.
PLL_BYP 28 Connect a 0.1 µF capacitor between this terminal and PLL_AVDD
RSTINB 23 I Reset input, active low
NC 1, 2, 13,

14, 15

Not connected

Power Supplies

AFE_GND 16 Analog ground
AFE_VDD 18 Analog supply, connect to 5 V
CH1_AGND

AGND

3

12

Analog grounds

CH1_AVDD
AVDD

6
9

Analog supply , connect to 5 V

DGND 21, 22, 24,

37, 47, 57,

68

Digital grounds

DTO_AGND 20 DTO ground, connect to analog ground
DTO_A VDD 19 DTO supply , connect to 5 V analog
DVDD 34, 44, 54,

65, 75

Digital supply, connect to 3.3 V

NSUB 17 Substrate ground, connect to analog ground
PLL_AVDD 25 PLL supply connect to 3.3 V
REFP 8 A/D reference supply, connect to 5 V analog
REFM 7 A/D reference ground, connect to analog ground

1–6

1.6 Terminal Functions (Continued)

TERMINAL

NAME NO.

I/O

DESCRIPTIONS

Sync Signals

AVID 27 O Active video indicator. This signal is high during the horizontal active time of the

video output on the Y and UV terminals. AVID continues to toggle during vertical
blanking intervals.

FID 33 I/O Odd/even field indicator or vertical lock indicator. For odd/even indicator, a logic 1

indicates the odd field. For vertical lock indicator, a logic 1 indicates the internal
vertical PLL is in a locked state. Additionally, this terminal in conjunction with GLCO
and PALI is used to determine the host port mode configuration during initial power

up and reset.
HSYN 30 O Horizontal sync signal. The rising edge time is programmable via the host.
PALI 32 I/O PAL line indicator or horizontal lock indicator. For PAL line indicator, a logic 1

indicates a noninverted line, and a logic 0 indicates an inverted line. For horizontal

lock indicator, a logic 1 indicates the internal horizontal PLL is in a locked state.

Additionally , this terminal in conjunction with GLCO and FID is used to determine the

host port mode configuration during initial power up.
VSYN 29 O Vertical sync signal

2–1

2 Detailed Description

2.1 Analog Video Processors and A/D Converter

Figure 2–1 is a functional diagram of the TVP5020 analog video processors and A/D converter. This block
accepts up to two inputs and performs analog signal conditioning (i.e., video clamping, video amplifying),
and carries out analog-to-digital conversion.

2.1.1 Video Input Selection

Two high-impedance video inputs are sources for a single internal analog channel in the TVP5020. The user
can connect the two analog video inputs to two selectable individual composite video inputs.

2.1.2 Analog Input Clamping and Automatic Gain Control Circuits

The internal clamp circuit restores the ac-coupled video signals to a fixed dc level before A/D conversion.
The clamping circuit provides line-by-line restoration of the video sync level to a fixed dc reference voltage.
The circuit has two modes of clamping, coarse and fine. In coarse mode, the most negative portion of the
signal (typically the sync tip) is clamped to a fixed dc level. The circuit uses fine mode to prevent spurious
level shifting caused by noise that is more negative than the sync tip on the input signal. When fine mode
is enabled, after the sync position is detected, clamping is only enabled during the sync period.

Input video signal amplitudes may vary significantly from the nominal level of 1 Vpp. An automatic gain
control (AGC) circuit adjusts the signal amplitude to use the maximum range of the A/D converter without
clipping.

The AGC circuit adjusts the signal amplitude based on the detected amplitude of the sync portion of the input
signal. Signal peaks may be present on nonstandard signals that cause clipping at the A/D converter after
gain adjustment based only on sync amplitude. In these cases, the signal will be attenuated before A/D
conversion.

Clamp

Clamp and AGC

Control Logic

Sync Processor

Amplifier

Input Multiplexer

A/D

VI_1A

VI_1B

Analog Input Video

Digitized Video
Channel 1 (0–7)

Figure 2–1. Analog Video Processors and A/D Converters

2.1.3 A/D Converter

The TVP5020 contains one 8-bit A/D converter which digitizes the selected analog video signal input. To
prevent high frequencies which are above half of the sampling rate from entering into the system, video
inputs may require external anti-aliasing low pass filters.

2.2 Digital Processing

Figure 2–2 is a block diagram of the TVP5020 digital video processing. This block receives digitized
composite or signals from the A/D converter, and performs Y/C separation, chroma demodulation, and
Y -signal enhancements. It also generates the horizontal and vertical syncs. The YUV digital output may be
programmed into various formats: 16-bit or 8-bit 4:2:2, 12-bit 4:1:1 and ITU-R BT.656 parallel interface
standard. The circuit uses comb filters to reduce the cross-chroma and cross-luma noise.

2–2

Input

Interface

Chrominance
Demodulator

Gain

Control

Comb

Filter

Output

Formatter

and

Interface

Digital Control

Oscillator

Loop Filter

Burst Gate

Accumulator

Notch Filter

Comb Filter

Luminance Signal

Processing and Coring

Delay

Adjustment

Lowpass Filter
Sync Detector

Phase

Detector

Loop
Filter

Line-Locked

Clock

PLL

Power-Down

Mode Control

CLOCK

Crystal

Clock

Generator

Digital

Control

Oscillator

DAC

Clock

Generation

Circuit

Vertical

Sync

Processor

Horizontal

Sync

Processor

Counter

CH1

From A/D Converter

CHROMINANCE

LUMINANCE CIRCUITS

SYNCHRONIZATION

OEB

UV (0–7)

Y (0–7)

AVID

PREF
SCLK

PCLK

XTL1
XTL2

HSYN

PALI

(HPLL)

VSYN

FID

(VLK)

Figure 2–2. Digital Video Signal Processing Block Diagram

2.2.1 Y/C Separation

Luma/chroma separation may be done using either 2-line (1–H delay) comb filtering or a chroma trap filter.
Comb filtering is available for both the luminance and the chrominance portion of the data path. The
characteristics of the chroma trap filter are shown in Figures 2–3 and 2–4.

2–3

PAL-B,
D,G,H,I

NTSC,

PAL-M,N

–20

–25

–35

–40

0 0.5 1 1.5 2 2.5 3

Amplitude – dB

–10

–5

f – Frequency – MHz

0

4.5 5 5.5 6.5

–15

–30

3.5

46

Figure 2–3. Chroma T rap Filter Frequency Response for 13.5 MHz Sampling

NTSC,
PAL-M

PAL-N

PAL-B,
D,G,H.I

–20

–30

–35

–40

0 0.5 1 1.5 2 3 3.5

Amplitude – dB

–10

–5

f – Frequency – MHz

0

4.5 5 5.5 6.5

–15

–25

2.5 4 6

Figure 2–4. Chroma T rap Filter Frequency Response for Square-Pixel Sampling

2.2.2 Luminance Processing

The digitized composite video signal from the output of the A/D converter passes through a luminance comb
filter or a chroma trap filter that removes the chrominance signal from the composite signal to generate the
luminance signal. The luminance signal is then fed to the input of luminance signal peaking and coring
circuits. Figure 2–5 illustrates the functions of the luminance data path. High frequency components of the
luminance signal are enhanced further by the peaking filter (edge enhancer). Figures 2–6, 2–7, and 2–8
show the characteristic of the peaking filter at maximum gain. The coring circuit reduces low-level, high

2–4

-frequency noise. Figure 2–9 shows the transfer curve of the coring function. The peaking frequency,
peaking gain, and coring threshold are programmable.

Peaking

Coring

KPK

Peaking
Frequency

Coring
Threshold

COR

Delay

Digital Y

Signal

Aperture

Factor

Y

Figure 2–5. Luminance Edge-Enhancer

8

6

2

0

0 0.5 1 1.5 2 2.5 3

Amplitude – dB

12

14

f – Frequency – MHz

16

3.5 4 5.5 6.5

10

4

4.5 5

6

Figure 2–6. Peaking Filter Response, 13.5 MHz Sampling

2–5

8

6

2

0

0 0.5 1 1.5 2 3 3.5

Amplitude – dB

12

14

f – Frequency – MHz

16

4.5 5 5.5 6.5

10

4

2.5

46

Figure 2–7. Peaking Filter Response, NTSC AND PAL-M SQUARE PIXEL

8

6

2

0

0 0.5 1 1.5 2 3 3.5

Amplitude – dB

12

14

f – Frequency – MHz

16

4.5 5 5.5 6.5

10

4

2.5

46

Figure 2–8. Peaking Filter Response, PAL Square Pixel

2–6

Input Signal

Output Signal

V

I

V

O

Coring Threshold

t

Figure 2–9. Transfer Curve of Coring Circuit

2.2.3 Chrominance Processing

A quadrature demodulator removes the U and V components from the composite signal in composite video
mode. The U/V signals then pass through the gain control stage for chroma saturation adjustment. The U
and V components pass through a comb filter to eliminate cross-chrominance noise. Phase shifting the
digitally-controlled oscillator controls hue. The block includes an automatic color killer (ACK) circuit that
suppresses the chroma output when the color burst of the video signal is weak or not present.

2.2.4 Clock Circuits

An internal line-locked PLL generates the system and pixel clocks. Figure 2–10 shows a simplified clock
circuit diagram. The digital control oscillator (DCO) generates the reference signal for the horizontal PLL.
The DCO outputs a signal that is fed to the D/A converter. The D/A converter outputs a line-locked clock
signal (LCLK). The DCO requires a 26.8 or a 24.576 MHz clock as an input. The input for the DCO may be
connected to terminal XTAL1 or a 26.8 or 24.576 MHz crystal may be connected across terminals XTAL1
and XTAL2. Figure 2–11 shows the various reference clock configurations.

Lowpass Filter

Sync Detector

Phase

Detector

Loop
Filter

Line-Locked
Clock
PLL

Digital

Control

Oscillator

Crystal

Clock

Generator

DAC

Clock

Generator

Circuit

SCLK

PCLK

XTL1

XTL2

Digitized

Video

Figure 2–10. Clock Circuit Diagram

2–7

TVP5020

XTAL1

XTAL2

35

36

TVP5020

XTAL1

XTAL2

35

36

26.8 MHz or

24.576 MHz
Crystal

26.8 MHz or

24.576 MHz
TTL Clock

Figure 2–11. Reference Clock Configurations

The TVP5020 generates three signals PCLK, SCLK, and PREF used for clocking data. PCLK is the pixel
clock at the sampling frequency. PCLK can be used for clocking data in the 16-bit 4:2:2 and the 12-bit 4:1:1
output formats. SCLK is at twice the sampling frequency and may be used for clocking data in the 8-bit 4:2:2
and ITU-R BT .656 formats. PREF is used as a clock qualifier with SCLK to clock data in the 16-bit 4:2:2 and
the 12-bit 4:1:1 formats

2.3 Video Output Format

The TVP5020 supports both square-pixel and ITU-R BT .601 sampling formats and multiple output formats:

• 16-bit 4:2:2

• 12-bit 4:1:1

• 8-bit 4:2:2

• ITU-R BT.656

2.3.1 Sampling Frequencies and Patterns

The sampling frequencies that control the number of pixels per line differ depending on the video format and
standards. Table 2–1 shows a summary of the sampling frequencies.

Table 2–1. Summary of the Line Frequencies, Data Rates, and Pixel Counts

STANDARDS

HORIZONTAL

LINE RATE

(kHz)

PIXELS

PER LINE

ACTIVE PIXELS

PER LINE

PCLK (MHz) SCLK (MHz)

NTSC, square-pixel 15.73426 780 640 12.2727 24.54
NTSC, ITU-R BT.601 15.73426 858 720 13.5 27.0
PAL (B,D,G,H,I), square-pixel 15.625 944 768 14.75 29.5
PAL (B,D,G,H,I), ITU-R BT.601 15.625 864 720 13.5 27.0
PAL(M), square-pixel 15.73426 780 640 12.2727 24.54
PAL(M), ITU-R BT.601 15.73426 858 720 13.5 27.0
PAL(N), square-pixel 15.625 944 768 14.75 29.5
PAL(N), ITU-R BT.601 15.625 864 720 13.5 27.0

Depending on the output format chosen, The TVP5020 outputs data in the 4:2:2 or 4:1:1 sampling pattern.
The patterns differ in the number of chrominance samples derived from the original samples. For the 4:2:2
pattern, every second sample is both a luminance and a chrominance sample; the remainder are
luminance-only samples. For the 4:1:1 pattern, every fourth sample is both a luminance and a chrominance
sample; the remainder are luminance-only samples.

2–8

U2

Y4

V2

U0

Y0

V0

Numbering Shown is for 13.5 MHz Sampling.

= Luminance–Only Sample

Y1U1Y2V1Y3

U358

Y716

V358

Y717

U359

Y718

V359

= Luminance and Chrominance Sample

Y719Y5

Figure 2–12. 4:2:2 Sampling

U1

Y4

V1

U0

Y0

V0

Numbering Shown is for 13.5 MHz Sampling.

= Luminance–Only Sample

Y1 Y2 Y3

U179

Y716

V179

Y717 Y718

= Luminance and Chrominance Sample

Y719Y5

Figure 2–13. 4:1:1 Sampling

2.3.2 Video Port 16-Bit 4:2:2 Output Format Timing

Y717

V358

PCLK

SCLK

PREF

Y7:0

Y0 Y1 Y2 Y3 Y4 Y5 Y716 Y718 Y719

UV7:0

U0 V0 U1 V1 U2 V2 U358 U359 V359

Numbering Shown is for 13.5 MHz Sampling.

Figure 2–14. 16-Bit 4:2:2 Output Format

2–9

2.3.3 Video Port 12-Bit 4:1:1 Output Format Timing

PCLK

SCLK

PREF

Y7:0

Y0 Y1 Y2 Y3 Y4 Y5 Y716 Y717Y717 Y718 Y719

UV5:4

Numbering Shown is for 13.5 MHz Sampling.

UV7:6

U0

(7:6)U0(5:4)U0(3:2)U0(1:0)U1(7:6)U1(5:4)

U179

(7:6)

U179

(5:4)

U179

(3:2)

U179

(1:0)

V0

(7:6)V0(5:4)V0(3:2)V0(1:0)V1(7:6)V1(5:4)

V179

(7:6)

V179

(5:4)

V179

(3:2)

V179

(1:0)

UV3:0 Logic 0

Figure 2–15. 12-bit 4:1:1 Output Format

2.3.4 Video Port 8-Bit 4:2:2 and ITU–R BT.656 Output Format Timing

Y718

SCLK

Y7:0

U0 Y0 V0 Y1 U1 Y2 U359 V359 Y719

Numbering Shown is for 13.5 MHz Sampling.

UV7:0 High Impedance

Figure 2–16. 8-Bit 4:2:2 and ITU-R BT.656 Output Formats

2.4 Synchronization Signals

The TVP5020 generates synchronization signals to accompany the output video data stream. The following
figures show the default timing for the horizontal and vertical sync and associated signals.

2–10

Composite

Video–

Odd Field

VSYN

5251 234567891011 212223

FID

GPCL/VBLK

Composite

Video–

Odd Field

VSYN

262 263 264 265 266 267 268 269 270 271 272 273 283 284 285

FID

GPCL/VBLK

Composite

Video–

Odd Field

VSYN

310 311 312 313 314 315 316 317 318 319 320 334 335 336 337

FID

GPCL/VBLK

Composite

Video–

Odd Field

VSYN

622 623 624 625 1 2 3 4 5 6 7 21 22 23 24

FID

GPCL/VBLK

525–Line

625–Line

Note: Line Numbering Conforms to ITU–R BT .470

FID

HSYN

Horizontal Detail (Default HSYN Timing)

Figure 2–17. Vertical Synchronization Signals

2–11

8–Bit 4:2:2 Timing With 2x Pixel Clock (SCLK) Reference

16–Bit 4:2:2 Timing With 1x Pixel Clock (PCLK) Reference

AVID

HSYN

AVID

HSYN

1436

NTSC 601

Datastream

Datastream

Datastream

PAL 601
ITU 656

NTSC sqp
ITU 656

PAL sqp
ITU 656

NTSC 601
PAL 601
NTSC sqp
PAL sqp

1437 1438 1439 1440 1441 ... 1471 1472 ... 1599 1560 ... 1711 1712 1713 1714 1715 0 1 2 3

1436 1437 1438 1439 1440 1441 ... 1463 1464 ... 1591 1592 ... 1723 1724 1725 1726 1727 0 1 2 3

Cb

359Y718Cr359Y719

FF 00

...

10 80

...

10 80

...

10 FF 00 00 XX Cb0Y0Cr0Y

1

1276 1277 1278 1279 1280 1281 ... 1323 1324 ... 1451 1452 ... 1555 1556 1557 1558 1559 0 1 2 3

Cb

319Y638Cr319Y639

FF 00

...

10 80

...

10 80

...

10 FF 00 00 XX Cb0Y0Cr0Y

1

1532 1533 1534 1535 1536 1537 ... 1587 1588 ... 1715 1716 ... 1883 1884 1885 1886 1887 0 1123

Cb

383Y766Cr383Y767

FF 00

...

10 80 10 80

... ...

10 FF 00 00 XX Cb0Y0Cr0Y

1

718 719 720 ... 735 736 ... 799 800 ... 855 856 857 0 1
718 719 720 ... 731 732 ... 795 796 ... 861 862 863 0 1
638 639 640 ... 661 662 ... 725 726 ... 777 778 779 0 1
766 767 768 ... 793 794 ... 857 858 ... 941 942 943 0 1

Figure 2–18. Horizontal Synchronization Signals

2–12

2.5 I2C/VIP/VMI Host Interface

Communication with the TVP5020 is via an interface that is configurable at power up to support an I2C, VIP ,
or VMI bus host. The host interface accesses status and control registers and retrieves sliced VBI data. The
host interface also initializes the TVP5020’s internal microprocessor.

I2C

Interface

Module

VIP

Interface

Module

VMI

Interface

Module

I/O

MUX

I/O

DMA

BIU

Interface

Module

GLCO, PALI, FID

TVP, CPU
Interface

VDP
Modules

VC0
VC1
VC3

VC0
VC1
VC2
VC3

INTREQ

A0–A1
D0–D7

VC0
VC1
VC2
VC3

INTREQ

Figure 2–19. Host Interface

The host port mode is selected by attaching external pullup and pulldown resistors to the GLCO, PALI, and
FID terminals. The TVP5020 samples the state of the terminals at trailing edge of RSTINB

and configures
the host port accordingly. Table 2–2 shows the pullup/pulldown combinations required to select each of the
host port modes. Figure 2–19 is a block diagram of the host interface showing the mode selection and host
interface terminals, as well as interfaces to the internal microprocessor and VBI data processor.

Table 2–2. Host Port Select

GLCO PALI FID

TERMINALS

2 1 0

I2C Host Port 0 0 1
VIP Host Port 0 1 0
VMI Host Port Mode A 1 0 1
VMI Host Port Mode B 1 1 0
VMI Host Port Mode C 1 1 1

2.6 I2C Interface

The TVP5020 host port interface is configured for I2C operation by attaching external pull-up and pull-down
resisters to the GLCO, PALI, and FID terminals. The following is the combination of resisters required to
select the I

2

C host mode. (1 is pullup and 0 is pulldown)

GLCO PALI FID

TERMINALS

2 1 0

I2C Host Port Enabled 0 0 1

2–13

2.6.1 I2C Host Port Select

The I2C standard consists of two signals, serial input/output data (VC1) line and input/output clock line
(VC0), that carry information between the devices connected to the bus. A third signal (VC3) is used for slave
address selection. Although the I

2

C system can be multimastered, the TVP5020 will function as a slave

device only.
Both SDA and SCL are bidirectional lines that connect to a positive supply voltage via a pullup resistor. When

the bus is free, both lines are high.
The slave address select terminal (VC3) enables the use of two TVP5020 devices tied to the same I

2

C bus.

Table 2–3 summarizes the terminal functions of the I

2

C mode host interface.

Table 2–3. I

2

C Host Port Terminal Description

SIGNAL TYPE DESCRIPTION

VC3 (I2CA) I Slave address selection
VC0 (SCL) I/O (OD) Input/output clock line
VC1 (SDA) I/O (OD) Input/output data line

NOTE: OD = Open drain

1–7

Address

8

RW

9

ACK

1–7

Data

8

Data

9

ACK

1–7

Data

8

Data

9

ACK

P

S

VC1

(SDA)

VC0

(SCL)

Start Condition

VC0

(SCL)

Stop

12C Data Transfer

Figure 2–20. I2C Data Transfer Example

Data transfer rate on the bus is up to 400 kbits/s. The number of interfaces connected to the bus is dependent
on the bus capacitance limit of 400 pF. The data on the SDA line must be stable during the high period of
the clock. The high or low state of the data line can only change with the clock signal on the SCL line being
low.

• When transferring multiple bytes during one read or write operation, the internal subaddress is
not automatically incremented.

• A high to low transition on the SDA line while the SCL is high indicates a start condition.

• A low to high transition on the SDA line while the SCL is high indicates a stop condition

• Acknowledge is signalled by SDA low during the ninth SCL high.

• Not-acknowledge is signalled by SDA high during the ninth SCL high.

Every byte placed on the SDA line must be 8 bits long. The number of bytes that can be transferred is
unrestricted. An acknowledge bit follows each byte. If the slave can not receive another complete byte of
data until it has performed another function, it holds the clock line (SCL) low. An SCL low forces the master