Texas Instruments TVP3030-250MEP, TVP3030-230PPA, TVP3030-220PPA, TVP3030-175PPA Datasheet

TVP3030

Data Manual

Video Interface Palette

SLAS111

October 1995

Printed on Recycled Paper

ii

IMPORTANT NOTICE

Texas Instruments (TI) reserves the right to make changes to its products or to
discontinue any semiconductor product or service without notice, and advises its
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orders, that the information being relied on is current.

TI warrants performance of its semiconductor products and related software to the
specifications applicable at the time of sale in accordance with TI’s standard warranty.
T esting and other quality control techniques are utilized to the extent TI deems necessary
to support this warranty. Specific testing of all parameters of each device is not
necessarily performed, except those mandated by government requirements.

Certain applications using semiconductor products may involve potential risks of death,
personal injury, or severe property or environmental damage (“Critical Applications”).

TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED,
AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT
APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.

Inclusion of TI products in such applications is understood to be fully at the risk of the
customer. Use of TI products in such applications requires the written approval of an
appropriate TI officer . Questions concerning potential risk applications should be directed
to TI through a local SC sales office.

In order to minimize risks associated with the customer’s applications, adequate design
and operating safeguards should be provided by the customer to minimize inherent or
procedural hazards.

TI assumes no liability for applications assistance, customer product design, software
performance, or infringement of patents or services described herein. Nor does TI
warrant or represent that any license, either express or implied, is granted under any
patent right, copyright, mask work right, or other intellectual property right of TI covering
or relating to any combination, machine, or process in which such semiconductor
products or services might be or are used.

Copyright  1995, Texas Instruments Incorporated

iii

Contents

Section Title Page

1 Introduction 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1 Features 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 Functional Block Diagram 1–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 Terminal Assignments 1–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4 Ordering Information 1–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.5 Terminal Functions 1–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Detailed Description 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 MPU Interface 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 Color Palette RAM 2–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.1 Writing to Color-Palette RAM 2–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.2 Reading From Color-Palette RAM 2–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.3 8- or 6-Bit Mode Selection 2–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.4 Pixel Read-Mask Register 2–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.5 Palette-Page Register 2–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 Cursor and Overscan Color Registers 2–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4 Clock Selection 2–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5 PLL Clock Generators 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.1 Pixel Clock PLL 2–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.2 Memory Clock PLL 2–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.3 Loop Clock PLL 2–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6 Frame-Buffer Interface 2–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6.1 Frame-Buffer Clocking 2–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6.2 Frame Buffer Timing Without Using SCLK 2–15. . . . . . . . . . . . . . . . . . . . . . .

2.6.3 Frame Buffer Timing Using SCLK 2–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6.4 Split Shift-Register-Transfer Support 2–16. . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7 Byte Router 2–17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7.1 Byte Router Control Register 2–18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.8 Multiplexing Modes of Operation 2–19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.8.1 Little-Endian and Big-Endian Data Format 2–19. . . . . . . . . . . . . . . . . . . . . . .

2.8.2 VGA Modes 2–19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.8.3 Pseudo-Color Mode 2–20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.8.4 Direct-Color Mode 2–20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.8.5 True-Color Mode 2–21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.8.6 Packed-24 Mode 2–21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.8.7 Multiplex-Control Registers 2–23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.9 On-Chip Cursor 2–35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.9.1 Cursor RAM 2–35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.9.2 Cursor Positioning 2–36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.9.3 Three-Color 64 × 64 Cursor 2–37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.9.4 Interlaced Cursor Operation 2–38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

iv

Contents (Continued)

Section Title Page

2.10 Color-Key Switching 2–38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11 Overscan Border 2–39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.12 Horizontal Zooming 2–40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.13 Test Functions 2–40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.13.1 16-Bit CRC 2–40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.13.2 Sense Comparator Output and Test Register 2–41. . . . . . . . . . . . . . . . . . . .

2.13.3 Identification Code 2–42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.13.4 Silicon Revision 2–42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.14 Reset 2–42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.15 Analog Output Specifications 2–42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.16 Register Definitions 2–45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.16.1 General-Control Register 2–45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.16.2 Miscellaneous-Control Register 2–45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.16.3 Indirect Cursor-Control Register 2–46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.16.4 Direct Cursor-Control Register 2–46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.16.5 Cursor-Position (x, y) Registers 2–47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.16.6 Latch-Control Register 2–47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.16.7 Color-Key Control Register 2–48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.16.8 Color-Key (Overlay, Red, Green, Blue) Registers 2–48. . . . . . . . . . . . . . . .

2.16.9 CRC Remainder LSB and MSB Registers 2–49. . . . . . . . . . . . . . . . . . . . . . .

2.16.10 CRC Bit Select Register 2–49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 Electrical Characteristics 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range 3–1. . .

3.2 Recommended Operating Conditions 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 Electrical Characteristics 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4 Operating Characteristics 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5 Timing Requirements 3–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6 Switching Characteristics 3–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.7 Timing Diagrams 3–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Appendix A Frequency Synthesis PLL Register Settings A–1. . . . . . . . . . . . . . . . . . . . . .

Appendix B PLL Programming Examples B–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Appendix C PC-Board Layout Considerations C–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Appendix D Mechanical Data D–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

v

List of Illustrations

Figure Title Page

1–1 Functional Block Diagram 1–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–2 Terminal Assignments 1–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–1 TVP3030 Clocking Scheme 2–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–2 Loop Clock PLL Operation 2–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–3 Typical Configuration – VRAM Clocked by Accelerator 2–14. . . . . . . . . . . . . . . . . . . .

2–4 Typical Configuration – VRAM Clocked by TVP3030 2–14. . . . . . . . . . . . . . . . . . . . .

2–5 Frame Buffer Timing Without Using SCLK 2–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–6 Frame Buffer Timing Using SCLK 2–16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–7 Frame Buffer Timing Using SCLK (With First SCLK Pulse Relocated) 2–16. . . . . . .

2–8 Cursor-RAM Organization 2–36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–9 Cursor Positioning 2–37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–10 Overscan Border 2–40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–11 CRC Algorithm 2–41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–12 Equivalent Circuit of the Current Output (IOG) 2–43. . . . . . . . . . . . . . . . . . . . . . . . . . .

2–13 Composite Video Output (With 0 IRE, 8-Bit Output) 2–44. . . . . . . . . . . . . . . . . . . . . .

2–14 Composite Video Output (With 7.5 IRE, 8-Bit Output) 2–44. . . . . . . . . . . . . . . . . . . . .

3–1 MPU Interface Timing 3–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–2 Video Input/Output Timing 3–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

vi

List of Tables

Table Title Page

2–1 Direct Register Map 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–2 Indirect Register Map (Extended Registers) 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–3 Allocation of Palette-Page Register Bits 2–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–4 Color Register Address Format 2–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–5 Clock-Selection Register Bits CSR(2–0) 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–6 PLL Top Level Registers 2–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–7 PLL Address Register 2–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–8 PLL Data Register Pointer Format 2–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–9 Pixel Clock PLL Registers 2–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–10 Pixel Clock PLL Frequency Selection 2–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–11 MCLK PLL Registers 2–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–12 MCLK/Loop Clock Control Register 2–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–13 Loop Clock PLL Registers 2–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–14 Loop Clock PLL Settings for Packed-24 Modes 2–13. . . . . . . . . . . . . . . . . . . . . . . . . .

2–15 Byte Router Control Register 2–18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–16 Multiplex Mode and Bus-Width Selection 2–24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–17 Pseudo-Color Mode Pixel-Latching Sequence 2–28. . . . . . . . . . . . . . . . . . . . . . . . . . .

2–18 Packed-24 Format (R–G–B Mode) 2–29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–19 Packed-24 Format (B–G–R Mode) 2–30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–20 Direct-Color Mode Pixel-Latching Sequence (Little-Endian) 2–31. . . . . . . . . . . . . . .

2–21 Direct-Color Mode Pixel-Latching Sequence (Big-Endian) 2–33. . . . . . . . . . . . . . . . .

2–22 General Purpose I/O Registers 2–37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–23 General-Control Register 2–45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–24 Miscellaneous-Control Register 2–45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–25 Indirect Cursor-Control Register 2–46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–26 Direct Cursor-Control Register 2–46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–27 Latch-Control Register 2–47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–28 Color-Key Control Register 2–48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–29 CRC Bit Select Register 2–49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–1

1 Introduction

The TVP3030 is an advanced video interface palette (VIP) from T exas Instruments implemented in EPIC

0.8-micron CMOS process. The TVP3030 is a 128-bit VIP that provides virtually all features of the 64-bit
TVP3026. The TVP3030 doubles the pixel bus bandwidth, enabling 24-bit/pixel displays at resolutions up
to 1600 × 1280 at a 76-Hz refresh rate. Also, 24-bit/pixel graphics at 1280 × 1024 resolution may be
implemented at higher refresh rates with or without the use of pixel packing.

With the wider pixel bus comes additional 24-bit/pixel multiplexing modes: 4:1 (128-bit bus width for overlay
and RGB) and 5:1 (120-bit bus width for RGB). The byte router function allows pseudo-color or monochrome
image data to be taken from the red, green, or blue color channels. This enables high performance
24-bit/pixel architectures organized as red, green, and blue memory banks to provide 8-bit/pixel modes as
well.

The TVP3030 extends the packed-24 modes to include 16:3 (pixels:load clocks) using a 128-bit pixel bus
width. This enables, for example, 24-bit/pixel graphics at 220 MHz pixel rate with only a 40 MHz VRAM serial
output. With the 8:3 packed-24 mode (64-bit pixel bus width), a 24-bit/pixel display with 1280 x 1024
resolution may be packed into 4 megabytes of VRAM. A PLL-generated, 50 % duty cycle reference clock
is output in the packed-24 modes, maximizing VRAM cycle time.

The TVP3030 supports all of the pixel formats of the TVP3026 VIP. Data can be split into 4 or 8 bit planes
for pseudo-color mode or split into 12-, 16- or 24-bit true-color and direct-color modes. For the 24-bit direct
color modes, an 8-bit overlay plane is available. The 16-bit direct- and true-color modes can be configured
to IBM XGA



(5, 6, 5), TARGA (5, 5, 5, 1), or (6, 6, 4) as another existing format. An additional 12-bit mode
(4, 4, 4, 4) is supported with 4 bits for each color and overlay. All color modes support selection of little or
big endian data format for the pixel bus. Additionally, the device is also software compatible with the
IMSG176/8 and Bt476/8 color palettes.

Two fully programmable PLLs for pixel clock and memory clock functions are provided for dramatic
improvements in graphics system cost and integration. A third loop clock PLL is incorporated making pixel
data latch timing much simpler than with other existing color palettes. In addition, an external digital clock
input is provided for VGA modes. The reference clock output is driven by the loop clock PLL and provides
a timing reference to the graphics accelerator. The shift clock output may be used directly as the VRAM shift
clock.

Like the TVP3026, the TVP3030 also integrates a complete, IBM XGA-compatible hardware cursor on chip,
making significant graphics performance enhancements possible. Additionally, color-keyed switching is
provided, giving the user an efficient means of combining graphic overlays and direct-color images
on-screen.

The TVP3030 has three 256-by-8 color lookup tables with triple 8-bit video digital-to-analog converters
(DACs) capable of directly driving a doubly terminated 75-Ω line. The lookup tables are designed with a
dual-ported RAM architecture that enables ultra-high speed operation.

The device features a separate VGA bus which supports the integrated VGA modes in graphics accelerator
applications, allowing efficient support for VGA graphics and text modes. The separate bus is also useful
for accepting data from the feature connector of most VGA supported personal computers, without the need
for external data multiplexing.

EPIC is a trademark of Texas Instruments Incorporated.
XGA is a registered trademark of IBM.
TARGA is a registered trademark of Truevision Incorporated.

1–2

The TVP3030 is highly system integrated. It can be connected to the serial port of VRAM devices without
external buffering and connected to many graphics engines directly . It also supports the split shift-register
transfer operation, which is common to many industry standard VRAM devices. T o aid in manufacturing test
and field diagnosis, several highly integrated test functions have been designed to enable simplified testing
of the palette and the entire graphics subsystem.

1.1 Features

• Supports System Resolutions up to 1600 × 1280 @ 86-Hz Refresh Rate

• Supports Color Depths of 4, 8, 16, 24 and 32 Bit/Pixel, All at Maximum Resolution

• 128-Bit-Wide Pixel Bus

• Versatile Direct-Color Modes:

– 24-Bit/Pixel with 8-Bit Overlay (O, R, G, B)
– 24-Bit/Pixel Packed-24 (R, G, B)
– 16-Bit/Pixel (5, 6, 5) XGA Configuration
– 16-Bit/Pixel (6, 6, 4) Configuration
– 15-Bit/Pixel With 1 Bit Overlay (1, 5, 5, 5) TARGA Configuration
– 12-Bit/Pixel With 4 Bit Overlay (4, 4, 4, 4)

• True-Color Gamma Correction

• Supports Packed Pixel Formats for 24 Bit/Pixel Using a 32, 64, or 128 Bit/Pixel Bus

• 50% Duty Cycle Reference Clock for Higher Screen Refresh Rates in Packed-24 Modes

• Programmable Frequency Synthesis PLLs for Dot Clock and Memory Clock

• Loop Clock PLL Compensates for System Delay and Guarantees Reliable Data Latching

• Versatile Pixel Bus Interface Supports Little- and Big-Endian Data Formats

• 175-, 220- and 250-MHz Versions

• On-Chip Hardware Cursor, 64 × 64 × 2 Cursor (XGA and X-Windows Functionally Compatible)

• Byte Router Allows Use of R, G, or B Direct-Color Channels Individually

• Direct Interfacing to Video RAM

• Supports Overscan for Creation of Custom Screen Borders

• Color-Keyed Switching of Direct Color and True Color or Overlay

• Triple 8-Bit D/A Converters

• Analog Output Comparators for Monitor Detection

• RS-343A Compatible Outputs

• Direct VGA Pass-Through Capability

• Palette Page Register

• Horizontal Zooming Capability

• EPIC 0.8-µm CMOS Process

1–3

1.2 Functional Block Diagram

Pixel

Bus

Latch

1:1
2:1
4:1

5:1
Pipe
MUX

128 128 32

True
Color
MUX

24

Unpack

Logic

24

24

Color

Key

Switch

32

Pseudo

Color
MUX

32

8

Read
Mask

Page

Reg

24

8

8

Byte

Router

24

8 8

VGA

Latch

MPU

Registers

and

Control

Logic

8

4

Clock Select

Loop

Clock

PLL

Pixel

Clock

PLL

Memory

Clock

PLL

2

RESET

RCLK

SCLK

CLK0

SFLAG

PCLKOUT

PLLSEL (1,0)

XTAL2

XTAL1

MCLK

P (127– 0)

LCLK

VGA (7– 0)

D (7– 0)

RS (3– 0)

RD

WR

Internal

Dot Clock

32

24

8

Figure 1–1. Functional Block Diagram

1–4

1.2. Functional Block Diagram (Continued)

8

8

8

8

8

24

3 × 256 × 8

Color

Palette

RAM

8
8

Direct

Color

Pipeline

Delay

1 × 24

Overscan

Color

3 × 24
Cursor
Colors

24

24

24

24

64 × 64 × 2

Cursor RAM

and Control

24

2

Output MUX

DAC

DAC

DAC

8

8

8

Test Function

and

Sense Comparator

V

ref

1.235 V

REF

FS ADJUST

Video Signal

Control

COMP2
COMP1

IOR

IOG

IOB

SENSE

HSYNCOUT

VSYNCOUT

2

ODD/EVEN

OVS

SYSHS

SYSVS

SYSBL

VGAHS

VGAVS

VGABL

24

Figure 1–1. Functional Block Diagram (Continued)

1–5

1.3 Terminal Assignments

SYSHS

MCLK

ODD/EVEN

LCLK
RCLK
SCLK

P103
P102
P101
P100

P99
P98
P97
P96
P95

P94
GND
GND

DVDD

PLLGND

PLLVDD

PCLKOUT

PLLVDD
PLLSEL1
PLLSEL0

P93
P92
P91
P90
P89
P88
P87
P86
P85
P84
P83
P82
P81
P80
P79
P78
P77
P76
P75
P74
P73
P72
P71
P70
P69
P68
P67

1234567891011121314151617181920212223242526272829303132333435

363738394041424344454647484950

51

P66

XTAL2

XTAL1

GND

DVDD

P104

P105

P106

P107

P108

P109

P110

P111

P112

P113

P114

P115

P116

P117

P118

P119

P120

P121

P122

P123

P124

P125

P126

P127

CLK0

SFLAG

VGABL

VGAVS

VGAHS

SYSBL

SYSVS

OVS

VGA7

VGA6

VGA5

VGA4

VGA3

VGA2

VGA1

VGA0

GND

GND

GND

GND

AVDD

AVDD

AVDD

AVDD
COMP2
REF
COMP1
FS ADJUST
GND
IOB
GND
IOG
GND
IOR
GND
VSYNCOUT
HSYNCOUT
DVDD
GND
P0
P1
SENSE
RESET

P2
P3
P4
P5
P6
RS2
RS1
RS0
D0
D1
D2
D3
D4
D5
D6
D7
GND
DVDD
RD
WR
RS3
P7
P8
P9
P10
P11
P12
P13
P14
P15
P16
P17

104
103
102
101
100

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53

52

P65

P64

P63

P62

P61

P60

P59

P58

P57

P56

P55

P54

P53

P52

P51

P50

P49

P48

P47

P46

P45

P44

P43

P42

P41

P40

GND

GND

DVDD

DVDD

P39

P38

P37

P36

P35

P34

P33

P32

P31

P30

P29

P28

P27

P26

P25

P24

P23

P22

P21

P20

P19

P18

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208

Figure 1–2. Terminal Assignments

1–6

1.4 Ordering Information

TVP3030 – XXX XXX

Pixel Clock Frequency Indicator

MUST CONTAIN THREE CHARACTERS:

–175: 175-MHz pixel clock
–220: 220-MHz pixel clock
–250: 250-MHz pixel clock

Package

MUST CONTAIN THREE LETTERS:

–175: PPA Plastic Quad Flatpack
–220: PPA Plastic Quad Flatpack
–250: MEP Metal Quad Flatpack

1.5 Terminal Functions

TERMINAL

NAME NO.

I/O

DESCRIPTION

AV

DD

104–107 Analog power. All AVDD terminals must be connected. A separate cutout in the

DVDD plane should be made for AVDD. The DVDD and AVDD planes should be
connected only at a single point through a ferrite bead close to where power enters
the board.

CLK0 128 I Dot clock 0 TTL input. CLK0 can be selected to drive the dot clock at frequencies

up to 140 MHz. When using the VGA port, the maximum frequency is 85 MHz.
CLK0 can be selected as the latch clock for VGA data and video controls.
(power-up default).

COMP1,
COMP2

101, 103 I Compensation. COMP1 and COMP2 provide compensation for the internal

reference amplifier . A 0.1-µF ceramic capacitor is required between COMP1 and
COMP2. This capacitor must be as close to the device as possible to avoid noise
pick up.

DV

DD

29, 30, 67,

90, 153,

174

Digital power. All DVDD terminals must be connected to the digital power plane
with sufficient decoupling capacitors near the TVP3030.

D7–D0 69–76 I/O MPU interface data bus. These terminals are used to transfer data in and out of

the register map, palette RAM, and cursor RAM.

FS ADJUST 100 I Full-scale adjustment. A resistor connected between this terminal and ground

controls the full-scale range of the DACs.

GND 27, 28, 68,

89, 93, 95,

97, 99,
108–111,
154, 172,

173

Ground. All GND terminals must be connected. A common ground plane should
be used.

NOTE: All unused inputs should be tied to a logic level and not be allowed to float.

1–7

1.5 Terminal Functions (Continued)

TERMINAL

NAME NO.

I/O

DESCRIPTION

HSYNCOUT,
VSYNCOUT

91, 92 O Horizontal and vertical sync outputs. These outputs are pipeline delayed

versions of the selected sync inputs. Output polarity inversion may be
independently selected using general control register bits GCR(1,0).

IOR, IOG,
IOB

94, 96, 98 O Analog current outputs. These outputs can drive a 37.5-Ω load directly (doubly

terminated 75-Ω line), thus eliminating the requirement for any external buffering.

LCLK 159 I Latch clock input. LCLK is used to latch pixel-bus-input data and system video

controls. VGA data may also be latched with LCLK if so selected. LCLK may be
a delayed version of RCLK or a divided and delayed version of RCLK provided
that linear phase changes in RCLK cause corresponding linear phase changes
in LCLK.

MCLK 157 O Memory clock output. MCLK is the output of an independently programmable

PLL frequency synthesizer. The dot clock may be output on this terminal while
the MCLK frequency is reprogrammed.

PCLKOUT 177 O Pixel clock PLL output. PCLKOUT is a buffered version of the pixel clock PLL

output and is mainly for test purposes. This output is independent of the dot clock
source selected by the clock selection register.

PLLGND 175 Ground for regulated PLL supplies. Decoupling capacitors should be connected

between PLLVDD and PLLGND. PLLGND should be connected to the system
ground plane through a ferrite bead.

PLLV

DD

176, 178 PLL power supply. PLLVDD must be a well regulated 5 V power supply voltage.

Decoupling capacitors should be connected between PLLVDD and PLLGND.
T erminal 176 supplies power to the pixel clock PLL. T erminal 178 supplies power
to the MCLK PLL and the loop clock PLL.

OVS 120 I Overscan input. OVS is used to control the display of custom screen borders. If

OVS is not used, it should be connected to GND.

ODD/EVEN 158 I Odd or even field display. ODD/EVEN indicates odd or even field during

interlaced display for cursor operation. Logic 0 indicates the even field and logic
1 indicates the odd field.

PLLSEL1,
PLLSEL0

179, 180 I Pixel clock PLL frequency selection. Selects among two fixed frequencies and

the programmed frequency of the pixel clock PLL.

P127–P0 1–26,

31–63,

80–84,

87, 88,
129–152,
162–171,

181–208

I Pixel input port. The port can be used in various multiplexing modes. Unused

terminals should not be allowed to float.

NOTE: All unused inputs should be tied to a logic level and not be allowed to float.

1–8

1.5 Terminal Functions (Continued)

TERMINAL

NAME NO.

I/O

DESCRIPTION

RCLK 160 O Reference clock output. RCLK can be programmed to output either the pixel clock

PLL (power up default) or the loop clock PLL. The pixel clock PLL is selected to
provide a reference clock to the VGA controller. In this configuration, the VGA
controller returns VGA data and video controls along with a synchronous clock
which becomes the TVP3030 dot clock source via CLK0. For all other modes, the
loop clock PLL is selected to provide the reference clock. In this configuration, the
pixel clock PLL (or external clock) becomes the TVP3030 dot clock source. The
reference clock is used to generate VRAM shift clocks (or clock a VGA controller)
and generate video controls. The pixel port (or VGA port) and video controls are
latched by LCLK. The loop clock PLL controls the phase of RCLK to phase-lock
the received LCLK with the internal dot clock.
For systems that use SCLK as the VRAM shift clock, RCLK should be connected
to LCLK. An external buffer may be used between RCLK and LCLK if SCLK is also
buffered, within the timing constraints of the TVP3030. RCLK is not gated off
during blank.

REF 102 I/O Voltage reference for DACs. An internal voltage reference of nominally 1.235 V

is provided, which requires an external 0.1-µF ceramic capacitor between REF
and analog GND. However, the internal reference voltage can be overdriven by
an externally supplied reference voltage.

RESET 85 I Master reset. All the registers assume their default state after reset. The default

state is VGA mode 2 (CLK0 latching of VGA data and video controls).

RD 66 I Read strobe input. A logic 0 on this terminal initiates a read from the register map.

Read transfer data is enabled onto the D(7–0) bus when RD

is low.

RS3–RS0 64, 77–79 I Register select inputs. These terminals specify the location in the direct register

map that is to be accessed as shown in Table 2–1.

SCLK 161 O Shift clock output. SCLK is a gated version of the loop clock PLL output and is

gated off during blank. SCLK may be used to drive the VRAM shift clock directly .
This is intended for designs in which the graphics controller does not supply the
VRAM shift clock.

SENSE 86 O Test mode DAC comparator output signal. This terminal is low if one or more of

the DAC output analog levels is above the internal comparator reference of
350 mV ±50 mV.

SFLAG 127 I Split shift register transfer flag. A high pulse on this terminal during blank is passed

directly to the SCLK terminal. This operation is available to meet the special serial
clocking requirements of some VRAM devices. If SFLAG is not used, SFLAG
should be connected to GND.

SYSBL 123 I System blank input. SYSBL is active low. This should be selected for all modes

other than VGA mode 2. This signal is pipeline delayed before being passed to
the DACs.

1–9

1.5 Terminal Functions (Continued)

TERMINAL

NAME NO.

I/O

DESCRIPTION

SYSHS,
SYSVS

121, 122 I System horizontal and vertical sync inputs. These signals should be selected for

all modes other than VGA mode 2. These signals are pipeline delayed and each
may be inverted before being passed to the HSYNCOUT and VSYNCOUT
terminals. General control register bits GCR(1,0) control the polarity inversion.
If used to generate the sync level on the green current output, SYSHS

and

SYSVS

must be active low at the input to the TVP3030.

VGABL 126 I VGA blank input. VGABL is active low. This should be selected when in VGA

mode 2 (CLK0 latching of VGA data and video controls). VGABL

is pipeline

delayed before being passed to the DACs.

VGAHS,
VGAVS

124, 125 I VGA horizontal and vertical sync inputs. These signals should be used when in

VGA mode 2 (CLK0 latching of VGA data and video controls). These signals are
pipeline delyed and each may be inverted before being passed to the
HSYNCOUT and VSYNCOUT terminals. General control regiser bits GCR(1,0)
control the polarity inversion. If used to generate the sync level on the green
current output, VGAHS and VGAVS must be active low at the input to the
TVP3030.

VGA7 –VGA0 112 –119 I VGA port. This bus can be selected as the pixel input bus for VGA modes, but

it does not allow for any multiplexing.

WR 65 I Write strobe input. A logic 0 on this terminal initiates a write to the register map.

Write transfer data is latched from the D(7–0) bus with the rising edge of WR

.

XTAL1,
XTAL2

155, 156 I/O Connection for quartz crystal resonator as a reference for the frequency

synthesis PLLs. XTAL2 may be used as a TTL reference clock input, in which
case XTAL1 is left unconnected.

NOTE: All unused inputs should be tied to a logic level and not be allowed to float.

1–10

2–1

2 Detailed Description

2.1 MPU Interface

A standard microprocessor interface is supported, giving the MPU direct access to the registers and
memories of the TVP3030. The processor interface is controlled via read and write strobes (RD

, WR), four

register select terminals (RS3–RS0), and the D7–D0 data terminals. A software selectable 8/6

function is
used to select between an 8- or 6-bit-wide data path to the color palette RAM and is provided to maintain
VGA compatibility.

Table 2–1 lists the direct register map. These registers are addressed directly by the register select lines
RS0–RS3. Table 2–2 lists the indirect register map. The index for the indirect register map is loaded into
the index register (direct register: 0000). This register is also used to store the palette RAM write address
and cursor RAM write address. The indexed data register (direct register: 1010) is then used to read or write
the register pointed to in the indirect register map. The index does not post-increment following accesses
to the indirect map.

Table 2–1. Direct Register Map

RS3 RS2 RS1 RS0 REGISTER ADDRESSED BY MPU R/W DEF AULT (HEX)

0 0 0 0

Palette/Cursor RAM Write Address/
Index

R/W XX

0 0 0 1 Palette RAM Data R/W XX
0 0 1 0 Pixel Read-Mask R/W FF
0 0 1 1 Palette/Cursor RAM Read Address R/W XX
0 1 0 0 Cursor/Overscan Color Write Address R/W XX
0 1 0 1 Cursor/Overscan Color Data R/W XX
0 1 1 0 Reserved
0 1 1 1 Cursor/Overscan Color Read Address R/W XX
1 0 0 0 Reserved
1 0 0 1 Direct Cursor Control R/W 00
1 0 1 0 Indexed Data R/W XX
1 0 1 1 Cursor RAM Data R/W XX
1 1 0 0 Cursor-Position X LSB R/W XX
1 1 0 1 Cursor-Position X MSB R/W XX
1 1 1 0 Cursor-Position Y LSB R/W XX
1 1 1 1 Cursor-Position Y MSB R/W XX

2–2

Table 2–2. Indirect Register Map (Extended Registers)

INDEX R/W DEFAULT

REGISTER ADDRESSED

BY INDEX REGISTER

0x00 Reserved
0x01 R 0x00

†

Silicon Revision

0x02–0x05 Reserved

0x06 R/W 0x00 Indirect Cursor Control
0x07 R/W 0xE4 Byte Router Control

0x08–0x0E Reserved

0x0F R/W 0x06 Latch Control

0x10–0x17 Reserved

0x18 R/W 0x80 True Color Control
0x19 R/W 0x98 Multiplex Control
0x1A R/W 0x07 Clock Selection
0x1B Reserved
0x1C R/W 0x00 Palette Page
0x1D R/W 0x00 General Control
0x1E R/W 0x00 Miscellaneous Control

0x1F–0x2B Reserved

0x2C R/W XX PLL Address
0x2D R/W XX Pixel Clock PLL Data
0x2E R/W XX Memory Clock PLL Data
0x2F R/W XX Loop Clock PLL Data
0x30 R/W XX Color-Key Overlay Low
0x31 R/W XX Color-Key Overlay High

0x32 R/W XX Color-Key Red Low
0x33 R/W XX Color-Key Red High
0x34 R/W XX Color-Key Green Low
0x35 R/W XX Color-Key Green High
0x36 R/W XX Color-Key Blue Low
0x37 R/W XX Color-Key Blue High
0x38 R/W 0x00 Color-Key Control
0x39 R/W 0x18 MCLK/Loop Clock Control
0x3A R/W 0x00 Sense Test
0x3B R XX Test Mode Data
0x3C R XX CRC Remainder LSB

†

Silicon revision register is initially 0x00.

2–3

Table 2–2. Indirect Register Map (Extended Registers) (Continued)

INDEX R/W DEFAULT

REGISTER ADDRESSED

BY INDEX REGISTER

0x3D R XX CRC Remainder MSB
0x3E W XX CRC Bit Select
0x3F R 0x30 Device ID
0xFF W XX Software Reset

2.2 Color Palette RAM

The color palette RAM is addressed by an internal 8-bit address register for reading/writing data from/to the
RAM. This register is automatically incremented following a RAM transfer, allowing the entire palette to be
read/written with only one access of the address register. When the address register increments beyond
the last location in RAM, it is reset to the first location (address 0). All read and write accesses to the RAM
are asynchronous to the internal clocks but are performed within one dot clock. Therefore, read/write
accesses do not cause any noticeable disturbance on the display.

The color palette RAM is 24 bits wide for each location and 8 bits wide for each color. Since a MPU access
is eight bits wide, the color data stored in the palette is eight bits even when the six-bit mode is chosen. If
the six-bit mode is chosen, the two MSBs of color data in the palette have the values previously written.
However, if they are read back in the six-bit mode, the two MSBs are 0s to be compatible with the INMOS
IMSG176 and Brooktree Bt176. The output multiplexer shifts the six LSB bits to the six MSB positions and
fills the two LSBs with 0s after the color palette. The multiplexer then feeds the data to the DAC. The test
mode data register and the CRC calculation both take data after the output multiplexer, enabling total system
verification. The color palette access is described in the following two sections, and it is fully compatible with
IMSG176/8 and Bt476/8.

2.2.1 Writing to Color-Palette RAM

T o load the color palette, the MPU must first write to the palette RAM write address register (direct register:

0000) with the address where the modification is to start. The selected palette RAM location is loaded a byte
at a time by writing a sequence of three bytes (red, green, and blue) to the palette RAM data register (direct
register: 0001). After the blue write cycle, the palette RAM address register increments to the next location,
which the MPU may modify by simply writing another sequence of red, green, and blue data.

2.2.2 Reading From Color-Palette RAM

Reading from the palette is performed by writing to the palette read address register (direct register: 001 1)
with the location to be read. Three successive MPU reads from the palette RAM data register produce red,
green, and blue color data (6 or 8 bits depending on the 8/6

mode) for the specified location. Following the
blue read cycle, the address register is incremented. Since the color-palette RAM is dual ported, the RAM
may be read during active display without disturbing the video.

2.2.3 8- or 6-Bit Mode Selection

The 8-bit or 6-bit DAC resolution is software selectable. The default is 6-bit resolution. Bit MSC3 in the
miscellaneous control register selects 8-bit operation (logic 1) or 6-bit operation (logic 0).

2.2.4 Pixel Read-Mask Register

The pixel read-mask register (direct register: 0010) is an 8-bit register used to enable or disable a bit plane
from addressing the color-palette RAM in the pseudo-color and VGA modes. Each palette address bit is
logically ANDed with the corresponding bit from the read-mask register before going to the palette-page
register and addressing the palette RAM.

2.2.5 Palette-Page Register

The palette-page register (index: 0x1C) allows selection of multiple color look-up tables stored in the palette
RAM when using a mode that addresses the palette RAM with less than 8 bits. When using 1, 2, or 4 bit

2–4

planes in the pseudo color or direct color + overlay modes, the additional planes are provided from the
palette-page register before the data addresses the color palette. This is illustrated in Table 2–3.

NOTE:

The additional bits from the page register are inserted after the read mask.
The palette-page register specifies the additional bit planes for the overlay field in

direct-color modes with less than 8 bits per pixel overlay.

Table 2–3. Allocation of Palette-Page Register Bits

NUMBER OF BIT PLANES MSB PALETTE ADDRESS BITS LSB

8 M M M M M M M M
4 P7 P6 P5 P4 M M M M
2 P7 P6 M M M M M M
1 P7 M M M M M M M

Pn = n bit from page register
M = bit from pixel port

2.3 Cursor and Overscan Color Registers

The registers for the three cursor colors and the overscan border color are accessed through the direct
register map. See Section 2.9 for the overscan border and Section 2.7.3 for use of the cursor colors.

The color write address register (direct register: 0100) must be initialized before writing to the color registers.
The lower two bits of this register select one of the four color registers according to T able 2–4. The selected
24-bit color register is loaded a byte at a time by writing a sequence of three bytes (red, green, and blue)
to the color data register (direct register: 0101). After the blue byte is written, the color address register
increments to the next color. All four colors may be loaded with a single write to the color write address
register followed by 12 consecutive writes to the color data register.

The color read address register (direct register: 0111) must be initialized before reading from the color
registers. The lower two bits of this register select one of the four color registers according to T able 2–4. Next,
the color data register (direct register: 0101) is read three times, producing red, green, and blue bytes from
the selected register. After the blue byte is read, the color address register is incremented to the next color .
All four colors may be read with a single write to the color read address register followed by 12 consecutive
reads of the color data register.

The sequence followed by the color address register is overscan color, cursor color 0, cursor color 1, cursor
color 2, . . ., etc. The starting point depends on what was written to the color write address or color read
address register.

Table 2–4. Color Register Address Format

BIT 1 BIT 0 REGISTER

0 0 Overscan color
0 1 Cursor color 0
1 0 Cursor color 1
1 1 Cursor color 2

2.4 Clock Selection

The TVP3030 VIP provides a single TTL clock input (CLK0) which can be used for pixel rates up to 140 MHz.
At reset, CLK0 is selected as the clock source for VGA mode 2. This power-up state supports VGA pass
through operation without requiring software intervention. See Table 2–5 for the clock selection register
definition.

There are two ways of using CLK0 as a clock source. If CSR(2–0) = 111, CLK0 is selected as the clock
source to generate the internal dot clock. In this mode, multiplex control register bit MCR6 must be logic 0

2–5

if the VGA port is used. This selects latching of VGA(7–0) and VGABL with CLK0. If CSR(2–0) = 000, CLK0
is also selected as the clock source to generate the internal dot clock. However, in this mode, MCR6 must
be logic 1 if the VGA port is used. This selects latching of VGA(7–0) and SYSBL

with LCLK.

Additionally , two crystal oscillator terminals (XT AL1, XTAL2) are provided for the integrated pixel clock and
memory clock frequency synthesis PLLs. These terminals are intended for use with a quartz crystal
resonator, but a discrete oscillator can also be utilized and input on the XTAL2 terminal (XTAL1 terminal
should be left floating in this case).

Selection of the pixel clock PLL as the pixel clock source is performed by programming the clock selection
register.

Table 2–5. Clock-Selection Register Bits CSR(3–0) (Index: 0x1A, Access: R/W, Default: 0x07)

CLOCK SELECT
REGISTER BITS

FUNCTION

3 2 1 0

FUNCTION

0 0 0 0 Select CLK0 as clock source (for use with LCLK latching of VGA port). See

Section 2.8.2.
0 0 0 1 Reserved
0 0 1 0 Reserved
0 0 1 1 Reserved
0 1 0 0 Reserved

0 1 0 1 Select pixel clock PLL as clock source
0 1 1 0 Disable internal dot clock for reduced power consumption
0 1 1 1 Select CLK0 as clock source (for use with CLK0 latching of VGA port). See

Section 2.8.2.
1 X X X Reserved

2.5 PLL Clock Generators

In addition to externally supplied clock sources, the TVP3030 has three on-chip, fully programmable,
frequency-synthesis phase-locked loops (PLLs). The first (pixel clock) PLL is intended for pixel clock
generation for frequencies up to the device limit. The second (MCLK) PLL is provided for general clocking
such as the system clock or memory clock, and the third PLL (called the loop clock PLL) is provided for
synchronizing pixel data and latch timing by compensating for system loop delay.

2–6

The clock generators use a modified M over (N × 2P) scheme to enable a wide range of precise frequencies.
(Appendix A provides a listing of all frequencies that can be synthesized and the register values for each.)
The advanced PLLs utilize an internal loop filter to provide maximum noise immunity and minimum jitter.
Except for the reference crystal or oscillator, no external components or adjustments are necessary. Each
PLL can be independently enabled or disabled for maximum system flexibility. Figure 2–1 illustrates the
TVP3030 clocking scheme. The PLLs are programmed through a group of four registers in the TVP3030
indirect register map. The registers are listed in the following table.

Table 2–6. PLL Top Level Registers

INDEX REGISTER

0x2C PLL address register (PAR)
0x2D Pixel clock PLL data register (PPD)
0x2E MCLK PLL data register (MPD)
0x2F Loop clock PLL data register (LPD)

The PLL address register (PAR) is used to point to the M, N, P, and status registers of each PLL. This register
allows read and write access and contains three 2-bit pointers, one for each PLL, according to the T able 2–7.
Each pointer may be programmed independently.

Table 2–7. PLL Address Register

(Index: 0x2C, Access: R/W, Default: Uninitialized)

PAR BITS POINTER

1–0 Pixel clock PLL data register pointer
3–2 MCLK PLL data register pointer
5–4 Loop clock PLL data register pointer

Each PLL data register pointer points its associated PLL to one of its four PLL registers according to
Table 2–8.

Table 2–8. PLL Data Register Pointer Format

BIT 1 BIT 0 REGISTER

0 0 N value register
0 1 M value register
1 0 P value register
1 1 Status register (read-only)

Once the PLL data register pointers are set, the selected registers are accessed through the pixel clock PLL
data register (index: 0x2D), MCLK PLL data register (index: 0x2E) or the loop clock PLL data register (index:
0x2F). The PLL data register pointer bits are independently auto-incremented following a write cycle to the
corresponding PLL data register. The current state of each pointer can be identified by reading the PLL
address register (index: 0x2C). The PLL data register pointer bits do not auto increment following a read
cycle of the PLL data registers.

The most efficient way to program the pixel clock PLL is to first write zeros to PLL address register bits
PAR(1,0) followed by three consecutive writes to the pixel clock PLL data register to program the N, M, and
P-value registers. Following the third write, the pixel clock PLL pointer will point to the read-only status
register. The status register can then be polled until the LOCK bit is set (the pointer does not auto-increment
on reads). For test purposes, the pixel clock PLL can be output on the PCLKOUT terminal by programming
the pixel clock PLL P value register bit 6 to a logic 1.

2–7

Loop

Clock PLL

Pixel Clock

PLL

MCLK

PLL

Crystal
Amplifier

RCLK

MCLK

Internal
Dot Clock

CLK0

XTAL2

XTAL1

PCLKOUT

LCLK

Figure 2–1. TVP3030 Clocking Scheme

2.5.1 Pixel Clock PLL

The pixel clock PLL may be used at frequencies up to the device limit. Appendix A provides optimal register
values for all frequencies that can be synthesized using the common 14.31818 MHz reference. The
following equations describe the voltage controlled oscillator frequency and the PLL output frequency for
the pixel clock PLL as a function of the N, M, and P values and the reference frequency F

REF

.

The frequency of the voltage controlled oscillator (VCO) is given by:

Provided:

F

VCO

+8

F

REF

65*M
65*N

Minimum VCO FrequencyvF

VCO

v

Maximum VCO Frequency

Then the PLL output frequency is :

F

PLL

+

F

VCO

2

P

The N-, M-, and P-value registers may be programmed to any value within the following limits:

40vN(5–0)v62
1vM(5–0)v62
0vP(1,0)v3

If several N, M, and P selections meet the above criteria, choose the selection with the largest N(5–0). The
bit assignments of the N-, M-, and P-value and the status register for the pixel clock PLL are given in T able
2–9. The bits shown as logic 0 or logic 1 must be written with these fixed values. PCLKEN enables the pixel
clock PLL output onto the PCLKOUT output terminal when logic 1. When PCLKEN is logic 0, the PCLKOUT
terminal is held at logic 0. PLLEN resets the PLL when logic 0 and enables the PLL to oscillate when logic

1. The LOCK status bit indicates that the PLL has locked to the selected frequency when logic 1. The
remaining status register bits are for test purposes.

Table 2–9. Pixel Clock PLL Registers

REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

N value 1 1 N5 N4 N3 N2 N1 N0
M value 0 0 M5 M4 M3 M2 M1 M0
P value PLLEN PCLKEN 1 1 0 0 P1 P0
Status X LOCK X X X X X X

2–8

2.5.1.1 Pixel Clock PLL Frequency Selection

The pixel clock PLL frequency may be selected using the PLL select inputs PLLSEL(1,0) as shown in
Table 2–10. The first two selections are fixed frequency settings for standard VGA operation. Use of a
standard 14.31818 MHz crystal is assumed. When PLLSEL1 is logic 1, the frequency specified by the pixel
clock PLL N-, M-, and P-value registers is selected.

The frequency select inputs also apply to the loop clock PLL. When a fixed frequency is selected
(PLLSEL(1,0) = 0x), the loop clock PLL output frequency is the same as the internal dot clock frequency.

For VGA Mode 1, the pixel clock PLL should be selected as the dot clock source (CSR = 0x05) and the RCLK
terminal should pass the loop clock PLL output (MCK5 = 1). Then, when PLLSEL(1,0) changes between
a programmed frequency and a fixed frequency, the loop clock PLL does not require reprogramming.

For VGA Mode 2, CLK0 should be selected as the dot clock source (CSR = 0x07) and the RCLK terminal
should pass the pixel clock PLL output (MCK5 = 0). In this case, the loop clock PLL should be disabled (bit
P7 = 0) since its output is not used. When PLLSEL1 is logic 1, the frequency specified by the loop clock PLL
N-, M-, and P-value registers is selected.

Table 2–10. Pixel Clock PLL Frequency Selection

PLLSEL1 PLLSEL0 PIXEL CLOCK PLL FREQUENCY LOOP CLOCK PLL FREQUENCY

0 0 25.057 MHz 25.057 MHz
0 1 28.636 MHz 28.636 MHz
1 X Programmed by pixel clock PLL registers Programmed by loop clock PLL registers

2.5.2 Memory Clock PLL

The memory clock (MCLK) PLL may be used at frequencies up to 100 MHz. Appendix A provides optimal
register values for all frequencies that can be synthesized using the common 14.31818 MHz reference. The
MCLK PLL maximum output frequency of 100 MHz may not be exceeded. The equations for the VCO
frequency and for the PLL output frequency are the same as for the pixel clock PLL.

Provided:

F

VCO

+8

F

REF

65*M
65*N

Minimum VCO FrequencyvF

VCO

v

Maximum VCO Frequency

Then the PLL output frequency is :

F

PLL

+

F

VCO

2

P

The N-, M-, and P-value registers may be programmed to any value within the following limits:

40vN(5–0)v62
1vM(5–0)v62
0vP(1,0)v3

If several N, M, and P selections meet the above criteria, choose the selection with the largest N(5–0).
The bit assignments of the N-, M-, and P-value and the status register for the MCLK PLL are given in

Table 2–11. The bits shown as logic 0 or logic 1 must be written with these fixed values. PLLEN resets the
PLL when logic 0 and enables the PLL to oscillate when logic 1. The LOCK status bit indicates that the PLL
has locked to the selected frequency when logic 1. The remaining status register bits are for test purposes.
The MCLK PLL and loop clock PLL are further controlled by the MCLK/loop clock control register shown
in Table 2–12.

2–9

Table 2–11. MCLK PLL Registers

REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

N value 1 1 N5 N4 N3 N2 N1 N0
M value 0 0 M5 M4 M3 M2 M1 M0
P value PLLEN 0 1 1 0 0 P1 P0
Status X LOCK X X X X X X

Table 2–12. MCLK/Loop Clock Control Register (Index: 0x39, Access: R/W, Default: 0x18)

BIT NAME VALUES DESCRIPTION

MKC7, MKC6, 00 Reserved

MKC5 0: Pixel clock PLL

(default)
1:Loop clock PLL

Selects signal to output on RCLK terminal. Pixel clock PLL is selected as
default to support VGA mode 2. In VGA mode 2, the graphics accelerator
receives RCLK and returns its VGA output clock to the CLK0 terminal
along with synchronous VGA data. Select loop clock PLL for all modes
using LCLK data latching. These include all modes using the pixel port
P127–P0 and VGA mode 1 which uses LCLK latching of VGA7–VGA0.

MKC4 0: Dot clock

1: MCLK PLL (default)

Selects signal to output on MCLK terminal. MCLK PLL is selected as
default. Select dot clock to ensure a stable output on MCLK while MCLK
PLL frequency is reprogrammed. See Section 2.5.2.1. A change of this
bit does not take effect until a logic 0 to logic 1 transition of bit MKC3
occurs, during which bit MKC4 should not be changed.

MKC3 0:

1: (default)

Strobe for MCLK terminal output multiplexer control (MKC4). A logic 0 to
logic 1 transition of this bit strobes in bit MKC4, causing bit MKC4 to take
effect. While the logic 0 to logic 1 transition occurs on MKC3, MKC4
should not be changed.

MKC2, MKC1,

MKC0

000: Divide by 2 (default)
001: Divide by 4
010: Divide by 6
011: Divide by 8
100: Divide by 10
101: Divide by 12
110: Divide by 14
111: Divide by 16

Loop clock PLL post scalar Q divider. This additional frequency division
is applied after the 2P division of the loop clock PLL P-value register. For
a binary value of Q in MKC2–MKC0, the resulting frequency division is
2*(Q+1).

After device reset, the MCLK PLL outputs a 50.11 MHz clock frequency and the pixel clock PLL output
depends on the PLLSEL1 and PLLSEL0 inputs according to Table 2–10. These frequencies assume a
standard 14.31818 MHz crystal reference.

2–10

2.5.2.1 Changing the MCLK Frequency

The MCLK is normally used as the graphics controller system clock and memory clock. During
reprogramming of the PLLs, a wide range of unpredictable frequencies are generated as the PLL transitions
to the new programmed frequency . These transition effects can produce unwanted results in some systems.
The TVP3030 provides a mechanism for smooth transitioning of the MCLK PLL. The following programming
steps are recommended.

1. Program the pixel clock PLL to the same frequency to which MCLK will be changed, and poll the
pixel clock PLL status until the LOCK bit is logic 1.

2. Select the pixel clock PLL as the dot clock source if it is not already selected.

3. Switch to output dot clock on the MCLK terminal by writing bits MKC4, MKC3 to 0,0 followed by
0,1 in MCLK/loop clock control register.

4. Program the MCLK PLL for the new frequency and poll the MCLK PLL status until the LOCK bit
is logic 1.

5. Switch to output MCLK on the MCLK terminal by writing bits MKC4, MKC3 to 1,0 followed by 1,1
in MCLK control register.

6. Reprogram the pixel clock PLL to its operating frequency.

2.5.3 Loop Clock PLL

Many of the current high performance graphics accelerators with built in VGA support generate their own
VRAM shift clock and pixel data latching clock (LCLK) as discussed in Section 2.6.2. As stated before, the
TVP3030 provides an RCLK timing reference output to be used by the graphics controller to generate these
signals. A common industry problem exists, however, in that the delay through the loop (i.e., from RCLK
through the controller to produce LCLK and pixel data) may be greater than the RCLK cycle time minus setup
time. It then becomes very difficult to resynchronize the rising edges of the LCLK signal to the internal dot
clock within the specified timing requirements. Variations in graphics accelerator propagation delays from
device to device can cause severe production problems at the board level. The TVP3030 incorporates a
unique loop clock PLL circuit to maintain a valid LCLK/dot clock phase relationship and ensure that proper
LCLK and pixel data setup timing is met, regardless of the amount of system loop delay.

After device reset, the loop clock PLL provides the dot clock frequency to the RCLK output multiplexer.
However, the RCLK output multiplexer will ignore the loop clock PLL output and instead pass the pixel clock
PLL output to the RCLK terminal, which provides a reference clock to the VGA controller. In this configuration
(VGA mode 2), the VGA controller returns VGA data and video controls along with a synchronous clock that
becomes the TVP3030 dot clock source via CLK0. The PLLSEL(1,0) lines select either the 25.057 MHz or

28.636 MHz VGA frequencies.
Figure 2–2 illustrates the pixel data latching structure and the operation of the loop clock PLL. The selected

clock source is used to generate the dot clock which drives most of the digital logic of the TVP3030. The
dot clock is used as a reference frequency by the loop clock PLL and is subdivided as specified by the
N value register. The incoming LCLK is used as the other input of the PLL and is subdivided as specified
by the M value register. The PLL generates RCLK with the proper frequency and phase shift to phase align
the divided dot clock and divided LCLK. The pixel bus is latched on the rising edge of LCLK and then aligned
with the internal dot clock to synchronize with internal logic.

2–11

Loop Clock

PLL

DQ DQ

LCLK

Dot

Clock

Input Data Latch Structure

TVP3030

RCLK

CLK0

LCLK

P(127–0)

Graphics

Accelerator

VRAM

From Pixel Clock PLL

Figure 2–2. Loop Clock PLL Operation

The bit assignments of the N-, M-, and P-value and the status register for the loop clock PLL are shown in
Table 2–13. The bits shown as logic 0 or logic 1 must be written with these fixed values. PLLEN resets the
PLL when logic 0 and enables the PLL to oscillate when logic 1. The LOCK status bit indicates that the PLL
has locked to the selected frequency when logic 1. The remaining status register bits are for test purposes.

The N-, M-, and P-value registers may be programmed to any value within the following limits.

1vN(5–0)v62
1vM(5–0)v62
0vP(1,0)v3

LESEN enables the LCLK edge synchronizer function and should be logic 1 whenever a packed-24 mode
is used. In the packed-24 modes, only one LCLK rising edge per pixel group is aligned with the internal dot
clock. For example, in 8:3 packed-24 mode, only one of the three LCLKs is aligned to the internal dot clock.
The LCLK edge synchronizer function allows selection of which LCLK edge in the sequence of pixel bus
words is aligned with the internal dot clock. For each packed-24 mode there is an optimum setting for the
LCLK edge synchonizer delay LES1 and LES0. See Table 2–14 and Section 2.8.6 for more details.

Table 2–13. Loop Clock PLL Registers

REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

N value 1 1 N5 N4 N3 N2 N1 N0
M value LES1 LES0 M5 M4 M3 M2 M1 M0
P value PLLEN 1 1 1 LESEN 0 P1 P0
Status X LOCK X X X X X X

2.5.3.1 Programming for All Modes Except Packed-24

For all modes except packed-24, programming of the loop clock PLL registers depends on the system
configuration, pixel rate, color depth and pixel bus width. In addition, the internal VCO must be within its
operating range of 1 10 – 220 MHz for the required RCLK output frequency. To determine the proper M, N,
P, and Q register values one should know the following.

• Dot clock frequency (MHz) (F

D

) – pixel rate

• Bits/pixel (B) – bits/pixel including overlay fields

• Pixel bus width (W) – total pixel bus width used for this mode

• External division factor (K) – external frequency division between RCLK output and LCLK input

2–12

The dot clock frequency can either be generated by the on-chip pixel clock PLL or by an external clock
source. The following two parameters can be easily calculated from the above parameters.

• LCLK frequency (MHz) (F

L

) – frequency at which pixel bus is loaded by TVP3030

• RCLK frequency (MHz) (F

R

) – frequency at RCLK output terminal of TVP3030

The LCLK frequency is given by

FL+

FD

B

W

The RCLK frequency is FL times the external divide factor. If no external divide factor, K = 1.

FR+K

FL+K

FD

B

W

The N and M values are set as follows:

N+65*4

W

B

M+61

The P and Q frequency dividers must be programmed so that the VCO is within its operating range. The
VCO frequency is post-scaled by the P-divider followed by the Q-divider. The P-divider register (P) can take
on values of 0, 1, 2, or 3 which correspond to division factors of 1, 2, 4, or 8. The Q-divider register (Q) is
stored in bits 2 – 0 of the MCLK/loop clock control register (index: 0x39) and can take on values of 0, 1, 2,
. . ., 7 which correspond to division factors of 2, 4, 6, . . ., 16. The total post scalar frequency division factor
is:

Z+2

P)1

(Q)1)+

F

VCO

(65*N

)

4 F

D

K

Next, set F

VCO

to the lower limit of 110 MHz and solve for Z:

Z

+

27.5

(65*N

)

FD

K

Finally , determine the P and Q values:

IF Zv16 then P+largest integer less than log2(Z), Q+0

IF Zu16 then P+3, Q

+

smallest integer greater than

Z*16

16

Set bits 7,6 of the N-value register to 1,1 (default). Set LES1 and LES0 in the M-value register (bits 7,6) to
0,0 (default). Set bits 7–2 of the P-value register to 11 1 1 00. This enables the PLL to oscillate and disables
the LCLK edge synchronizer function, which is only used for packed-24 modes. To reset the PLL, set bit 7
of the P-value register to logic 0.

2.5.3.2 Programming for Packed-24 Modes

For packed-24 modes, the loop clock PLL is programmed according to Table 2–14. The LCLK edge
synchronizer delay (M-value register bits 7,6) depends on whether the graphics accelerator is driving the
VRAM shift clock (true color control register bit TCR5 is logic 0) or the TVP3030 is driving the VRAM shift
clock (TCR5 = logic 1). See Section 2.8.6 for a typical setup procedure for packed-24 modes.

2–13

Table 2–14. Loop Clock PLL Settings for Packed-24 Modes

PACKED-24 MODE BIT TCR5 (Index 0x18) N-VALUE REGISTER M-VALUE REGISTER

4:3 0 0xFD 0xBE
8:3 0 0xF9 0xBE

16:3 0 0xF1 0xBE

5:4 0 0xFC 0xBD
5:2 0 0xFC 0xBF
5:1 0 0xF7 0xBF
4:3 1 0xFD 0xBE
8:3 1 0xF9 0xBE

16:3 1 0xF1 0xBE

5:4 1 0xFC 0xBD
5:2 1 0xFC 0xBF

5:1 1 0xF7 0xBF

The P and Q frequency dividers must be programmed so that the VCO is within its operating range. The
VCO frequency is post scaled by the P-divider followed by the Q-divider. The P-divider register (P) can take
on values of 0, 1, 2, or 3 which correspond to division factors of 1, 2, 4, or 8. The Q-divider register (Q) is
stored in bits 2 – 0 of the MCLK/loop clock control register (index: 0x39) and can take on values of 0, 1, 2,
. . ., 7 which correspond to division factors of 2, 4, 6, . . ., 16. The total post-scalar frequency division factor
is:

Z+2

P)1

(Q)1)+

F

VCO

FD

K

65*N

65*M

Next, set F

VCO

to the lower limit of 110 MHz and solve for Z:

Z

+

110

FD

K

65*N
65*M

Finally , determine the P and Q values:

IF Zv16 then P+largest integer less than log2(Z), Q+0

IF Zu16 then P+3, Q

+

smallest integer greater than

Z*16

16

Set bits 7–2 of the P-value register to 11 11 10. This enables the PLL to oscillate and enables the LCLK edge
synchronizer function. To reset the PLL, set bit 7 of the P-value register to logic 0.

2.5.3.3 Typical Device Connection

After reset, the TVP3030 defaults to VGA mode 2 (VGA pass through mode, see Section 2.8.2). The RCLK
terminal outputs the pixel clock PLL frequency which is selected by PLLSEL1 and PLLSEL0. CLK0 is
selected as the clock source and the VGA port is selected as well as VGABL

, VGAHS, and VGAVS and

these are latched with CLK0. The MCLK PLL outputs the default 50.11MHz clock frequency.
Figure 2–3 shows the typical device connection for a system with VRAM clocked by the graphics

accelerator. After power up, the pixel clock PLL is output on RCLK and this clock drives the graphics
accelerator’s VGA controller and video timing logic. The accelerator’s output clock is output synchronous
to the VGA data and is input to the TVP3030 CLK0 input as the dot clock source.

Figure 2–4 shows the typical device connection for a system with VRAM clocked by the TVP3030. In this
case, the RCLK is tied back to the LCLK and this same clock drives the graphics accelerator’s VGA
controller and video timing logic. If necessary, the RCLK and SCLK signals may be externally buf fered within
the timing constraints (RCLK to LCLK delay) of the TVP3030. The pixel clock PLL is output on RCLK after
power up.

2–14

For high resolution modes, in both configurations, the pixel data is received from VRAM and the loop clock
PLL is used to adjust RCLK so that the received LCLK is aligned with the internal dot clock. The loop clock
PLL must be selected for output on the RCLK terminal. The pixel clock PLL (or an external clock source)
should be selected as the dot clock source.

Graphics

Accelerator

VRAM

VGA(7–0)

LCLK

CLK0

P(127–0)

MCLK

RCLK

TVP3030

Figure 2–3. Typical Configuration – VRAM Clocked by Accelerator

Graphics

Accelerator

VRAM

VGA(7–0)

LCLK

CLK0

P(127–0)

MCLK

RCLK

TVP3030

SCLK

Figure 2–4. Typical Configuration – VRAM Clocked by TVP3030

2.6 Frame-Buffer Interface

The TVP3030 provides two output clock signals and one input clock signal for controlling the frame-buffer
interface: SCLK, RCLK, and LCLK. Clocking of the frame buffer interface is discussed in Section 2.6.1. The
128-bit pixel bus allows many operational display modes as defined in Section 2.8 and T able 2–16. The pixel
latching sequence is initiated by a rising edge on LCLK. For those multiplexed modes in which multiple pixels
are latched on one LCLK rising edge, the pixel clock shifts the pixels out starting with the pixels that reside
on the low numbered pixel port terminals. For example, in an 8-bit-per-pixel pseudo-color mode with an 8:1
multiplex ratio, the pixel display sequence is P(7–0), P(15–8), P(23–16), P(31–24), P(39–32), P(47–40),
P(55–48), and P(63–56).

The TVP3030 frame-buffer interface also supports little- and big-endian data formats on the pixel bus. This
can be controlled by general-control register (GCR) bit 3. See Section 2.8.1 for details of operation.

2.6.1 Frame-Buffer Clocking

The TVP3030 provides SCLK and RCLK, allowing for flexibility in the frame buffer interface timing. For the
pixel port (P127–P0), data is always latched on the rising edge of LCLK. If bit TCR5 in the true-color control
register is logic 1, use of SCLK is assumed and internal pipeline delay is added to sync and blank to account
for the delay in the generation of SCLK. If TCR5 is logic 0 (default), then this pipeline delay is not added,
and SCLK should not be used.