TEXAS INSTRUMENTS TUSB3410, TUSB34101 Technical data

 

    

Data Manua

July 2007 Computer Interface Solutions

SLLS519F

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty . Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

Following are URLs where you can obtain information on other Texas Instruments products and application solutions:

Products Applications

Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security

Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless

Mailing Address: Texas Instruments

Post Office Box 655303 Dallas, Texas 75265

Contents

Section Page

1 Introduction 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1 Controller Description 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 Ordering Information 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 Revision History 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Main Features 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 USB Features 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 General Features 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 Enhanced UART Features 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4 Terminal Assignment 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 Detailed Controller Description 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1 Operating Modes 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 USB Interface Configuration 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.1 External Memory Case 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.2 Host Download Case 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 USB Data Movement 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4 Serial Port Setup 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5 Serial Port Data Modes 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5.1 RS-232 Data Mode 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5.2 RS-485 Data Mode 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5.3 IrDA Data Mode 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 MCU Memory Map 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1 Miscellaneous Registers 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1.1 ROMS: ROM Shadow Configuration Register (Addr:FF90h) 14 . . . . . . . . . . . . . . . . . . .

4.1.2 Boot Operation (MCU Firmware Loading) 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1.3 WDCSR: Watchdog Timer, Control, and Status Register (Addr:FF93h) 15 . . . . . . . . .

4.2 Buffers + I/O RAM Map 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3 Endpoint Descriptor Block (EDB−1 to EDB−3) 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3.1 OEPCNF_n: Output Endpoint Configuration (n = 1 to 3)

4.3.2 OEPBBAX_n: Output Endpoint X-Buffer Base Address (n = 1 to 3) (Offset 1) 19 . . . .

4.3.3 OEPBCTX_n: Output Endpoint X Byte Count (n = 1 to 3) (Offset 2) 20 . . . . . . . . . . . .

4.3.4 OEPBBAY_n: Output Endpoint Y-Buffer Base Address (n = 1 to 3) (Offset 5) 20 . . . .

4.3.5 OEPBCTY_n: Output Endpoint Y-Byte Count (n = 1 to 3) (Offset 6) 20 . . . . . . . . . . . .

4.3.6 OEPSIZXY_n: Output Endpoint X-/Y-Buffer Size (n = 1 to 3) (Offset 7) 21 . . . . . . . . .

4.3.7 IEPCNF_n: Input Endpoint Configuration (n = 1 to 3)

4.3.8 IEPBBAX_n: Input Endpoint X-Buffer Base Address (n = 1 to 3) (Offset 1) 21 . . . . . .

4.3.9 IEPBCTX_n: Input Endpoint X-Byte Count (n = 1 to 3) (Offset 2) 22 . . . . . . . . . . . . . .

4.3.10 IEPBBAY_n: Input Endpoint Y-Buffer Base Address (n = 1 to 3) (Offset 5) 22 . . . . . .

4.3.11 IEPBCTY_n: Input Endpoint Y-Byte Count (n = 1 to 3) (Offset 6) 22 . . . . . . . . . . . . . . .

4.3.12 IEPSIZXY_n: Input Endpoint X-/Y-Buffer Size (n = 1 to 3) (Offset 7) 23 . . . . . . . . . . . .

4.4 Endpoint-0 Descriptor Registers 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.4.1 IEPCNFG_0: Input Endpoint-0 Configuration Register (Addr:FF80h) 23 . . . . . . . . . . .

4.4.2 IEPBCNT_0: Input Endpoint-0 Byte Count Register (Addr:FF81h) 24 . . . . . . . . . . . . .

4.4.3 OEPCNFG_0: Output Endpoint-0 Configuration Register (Addr:FF82h) 24 . . . . . . . . .

4.4.4 OEPBCNT_0: Output Endpoint-0 Byte Count Register (Addr:FF83h) 24 . . . . . . . . . . .

(Base Addr: FF08h, FF10h, FF18h) 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(Base Addr: FF48h, FF50h, FF58h) 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

July 2007 SLLS519F

iii

Contents

Section Page

5 USB Registers 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1 FUNADR: Function Address Register (Addr:FFFFh) 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2 USBSTA: USB Status Register (Addr:FFFEh) 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3 USBMSK: USB Interrupt Mask Register (Addr:FFFDh) 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.4 USBCTL: USB Control Register (Addr:FFFCh) 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.5 MODECNFG: Mode Configuration Register (Addr:FFFBh) 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.6 Vendor ID/Product ID 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.7 SERNUM7: Device Serial Number Register (Byte 7) (Addr:FFEFh) 28 . . . . . . . . . . . . . . . . . . . . . .

5.8 SERNUM6: Device Serial Number Register (Byte 6) (Addr:FFEEh) 29 . . . . . . . . . . . . . . . . . . . . . .

5.9 SERNUM5: Device Serial Number Register (Byte 5) (Addr:FFEDh) 29 . . . . . . . . . . . . . . . . . . . . . .

5.10 SERNUM4: Device Serial Number Register (Byte 4) (Addr:FFECh) 29 . . . . . . . . . . . . . . . . . . . . . .

5.11 SERNUM3: Device Serial Number Register (Byte 3) (Addr:FFEBh) 29 . . . . . . . . . . . . . . . . . . . . . .

5.12 SERNUM2: Device Serial Number Register (Byte 2) (Addr:FFEAh) 30 . . . . . . . . . . . . . . . . . . . . . .

5.13 SERNUM1: Device Serial Number Register (Byte 1) (Addr:FFE9h) 30 . . . . . . . . . . . . . . . . . . . . . .

5.14 SERNUM0: Device Serial Number Register (Byte 0) (Addr:FFE8h) 30 . . . . . . . . . . . . . . . . . . . . . .

5.15 Function Reset And Power-Up Reset Interconnect 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.16 Pullup Resistor Connect/Disconnect 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6 DMA Controller 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.1 DMA Controller Registers 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.1.1 DMACDR1: DMA Channel Definition Register (UART Transmit Channel)

(Addr:FFE0h) 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.1.2 DMACSR1: DMA Control And Status Register (UART Transmit Channel)

(Addr:FFE1h) 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.1.3 DMACDR3: DMA Channel Definition Register (UART Receive Channel)

(Addr:FFE4h) 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.1.4 DMACSR3: DMA Control And Status Register (UART Receive Channel)

(Addr:FFE5h) 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2 Bulk Data I/O Using the EDB 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2.1 IN Transaction (TUSB3410 to Host) 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2.2 OUT Transaction (Host to TUSB3410) 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7 UART 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.1 UART Registers 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.1.1 RDR: Receiver Data Register (Addr:FFA0h) 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.1.2 TDR: Transmitter Data Register (Addr:FFA1h) 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.1.3 LCR: Line Control Register (Addr:FFA2h) 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.1.4 FCRL: UART Flow Control Register (Addr:FFA3h) 41 . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.1.5 Transmitter Flow Control 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.1.6 MCR: Modem-Control Register (Addr:FFA4h) 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.1.7 LSR: Line-Status Register (Addr:FFA5h) 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.1.8 MSR: Modem-Status Register (Addr:FFA6h) 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.1.9 DLL: Divisor Register Low Byte (Addr:FFA7h) 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.1.10 DLH: Divisor Register High Byte (Addr:FFA8h) 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.1.11 Baud-Rate Calculation 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.1.12 XON: Xon Register (Addr:FFA9h) 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.1.13 XOFF: Xoff Register (Addr:FFAAh) 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.1.14 MASK: UART Interrupt-Mask Register (Addr:FFABh) 48 . . . . . . . . . . . . . . . . . . . . . . . .

July 2007SLLS519F

Contents

Section Page

7.2 UART Data Transfer 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2.1 Receiver Data Flow 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2.2 Hardware Flow Control 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2.3 Auto RTS (Receiver Control) 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2.4 Auto CTS (Transmitter Control) 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2.5 Xon/Xoff Receiver Flow Control 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2.6 Xon/Xoff Transmit Flow Control 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8 Expanded GPIO Port 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.1 Input/Output and Control Registers 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.1.1 PUR_3: GPIO Pullup Register For Port 3 (Addr:FF9Eh) 51 . . . . . . . . . . . . . . . . . . . . . .

9 Interrupts 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.1 8052 Interrupt and Status Registers 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.1.1 8052 Standard Interrupt Enable (SIE) Register 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.1.2 Additional Interrupt Sources 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.1.3 VECINT: Vector Interrupt Register (Addr:FF92h) 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.1.4 Logical Interrupt Connection Diagram (Internal/External) 55 . . . . . . . . . . . . . . . . . . . . . .

10 I2C Port 57 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.1 I

C Registers 57 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.1.1 I2CSTA: I2C Status and Control Register (Addr:FFF0h) 57 . . . . . . . . . . . . . . . . . . . . . .

10.1.2 I2CADR: I2C Address Register (Addr:FFF3h) 58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.1.3 I2CDAI: I2C Data-Input Register (Addr:FFF2h) 58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.1.4 I2CDAO: I2C Data-Output Register (Addr:FFF1h) 58 . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.2 Random-Read Operation 58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.3 Current-Address Read Operation 59 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.4 Sequential-Read Operation 59 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.5 Byte-Write Operation 60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.6 Page-Write Operation 61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11 TUSB3410 Bootcode Flow 63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.1 Introduction 63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.2 Bootcode Programming Flow 63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.3 Default Bootcode Settings 64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.3.1 Device Descriptor 64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.3.2 Configuration Descriptor 65 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.3.3 Interface Descriptor 66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.3.4 Endpoint Descriptor 66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.3.5 String Descriptor 66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.4 External I2C Device Header Format 68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.4.1 Product Signature 68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.4.2 Descriptor Block 69 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.5 Checksum in Descriptor Block 69 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.6 Header Examples 69 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.6.1 TUSB3410 Bootcode Supported Descriptor Block 69 . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.6.2 USB Descriptor Header 69 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.6.3 Autoexec Binary Firmware 71 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.7 USB Host Driver Downloading Header Format 72 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

July 2007 SLLS519F

Contents

Section Page

11.8 Built-In Vendor Specific USB Requests 72 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.8.1 Reboot 72 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.8.2 Force Execute Firmware 72 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.8.3 External Memory Read 73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.8.4 External Memory Write 73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.8.5 I

C Memory Read 73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.8.6 I2C Memory Write 73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.8.7 Internal ROM Memory Read 74 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.9 Bootcode Programming Consideration 74 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.9.1 USB Requests 74 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.9.2 Hardware Reset Introduced by the Firmware 77 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.10 File Listings 78 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12 Electrical Specifications 79 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.1 Absolute Maximum Ratings 79 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.2 Commercial Operating Condition (3.3 V) 79 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.3 Electrical Characteristics 79 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13 Application Notes 81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.1 Crystal Selection 81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.2 External Circuit Required for Reliable Bus Powered Suspend Operation 81 . . . . . . . . . . . . . . . . . .

13.3 Wakeup Timing (WAKEUP or RI/CP Transitions) 82 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.4 Reset Timing 82 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

July 2007SLLS519F

List of Illustrations

Figure Title Page

1−1 Data Flow 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1−2 USB-to-Serial (Single Channel) Controller Block Diagram 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−1 RS-232 and IR Mode Select 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−2 USB-to-Serial Implementation (RS-232) 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−3 RS-485 Bus Implementation 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−1 MCU Memory Map 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−1 Reset Diagram 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−2 Pullup Resistor Connect/Disconnect Circuit 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7−1 MSR and MCR Registers in Loop-Back Mode 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7−2 Receiver/Transmitter Data Flow 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7−3 Auto Flow Control Interconnect 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9−1 Internal Vector Interrupt 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11−1 Control Read Transfer 75 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11−2 Control Write Transfer Without Data Stage 76 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13−1 Crystal Selection 81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13−2 External Circuit 81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13−3 Reset Timing 82 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

July 2007 SLLS519F

vii

List of Tables

Table Title Page

2−1 Terminal Functions 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−1 ROM/RAM Size Definition Table 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−2 XDATA Space 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−3 Memory-Mapped Registers Summary (XDATA Range = FF80h ” FFFFh) 16 . . . . . . . . . . . . . . . . . . . .

4−4 EDB Memory Locations 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−5 Endpoint Registers and Offsets in RAM (n = 1 to 3) 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−6 Endpoint Registers Base Addresses 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−7 Input/Output EDB-0 Registers 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6−1 DMA Controller Registers 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6−2 DMA IN-Termination Condition 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7−1 UART Registers Summary 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7−2 Transmitter Flow-Control Modes 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7−3 Receiver Flow-Control Possibilities 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7−4 DLL/DLH Values and Resulted Baud Rates 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9−1 8052 Interrupt Location Map 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9−2 Vector Interrupt Values 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11−1 Device Descriptor 65 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11−2 Configuration Descriptor 65 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11−3 Interface Descriptor 66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11−4 Output Endpoint1 Descriptor 66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11−5 String Descriptor 67 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11−6 USB Descriptors Header 70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11−7 Autoexec Binary Firmware 72 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11−8 Host Driver Downloading Format 72 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11−9 Bootcode Response to Control Read Transfer 75 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11−10 Bootcode Response to Control Write Without Data Stage 76 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11−11 Vector Interrupt Values and Sources 77 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

viii

July 2007SLLS519F

1 Introduction

1.1 Controller Description

The TUSB3410 provides bridging between a USB port and an enhanced UART serial port. The TUSB3410 contains all the necessary logic to communicate with the host computer using the USB bus. It contains an 8052 microcontroller unit (MCU) with 16K bytes of RAM that can be loaded from the host or from the external on-board memory via an I port at boot time. The ROM code also contains an I command decoding, UART setup, and error reporting, are managed by the internal MCU firmware under the auspices of the PC host.

The TUSB3410 can be used to build an interface between a legacy serial peripheral device and a PC with USB ports, such as a legacy-free PC. Once configured, data flows from the host to the TUSB3410 via USB OUT commands and then out from the TUSB3410 on the SOUT line. Conversely, data flows into the TUSB3410 on the SIN line and then into the host via USB IN commands.

C bus. It also contains 10K bytes of ROM that allow the MCU to configure the USB

Introduction

C boot loader. All device functions, such as the USB

Host (PC or On-The-Go Dual-Role Device)

Out

USB

TUSB3410

Figure 1−1. Data Flow

SOUT

SIN

Legacy

Serial

Peripheral

SLLS519F—July 2007 TUSB3410

Introduction

12 MHz

Clock

Oscillator

8052

PLL

and

Dividers

P, DM

USB

TxR

USB

Serial

Interface

Engine

24 MHz

10K × 8

ROM

16K × 8

RAM

2K × 8 SRAM

CPU-I/F

Suspend/

Resume

UBM

USB Buffer

Manager

Core

8 8

2 × 16-Bit

Timers

8 4

Port 3

SIN

I2C

Controller

DMA-1 DMA-3

UART−1

SOUT

P3.4 P3.3 P3.1 P3.0

I2C Bus

RTS CTS DTR DSR

TDM

Control

Logic

M U X

Encoder

Decoder

M U X

Figure 1−2. USB-to-Serial (Single Channel) Controller Block Diagram

SOUT/IR_SOU

SIN/IR_SIN

SLLS519F—July 2007TUSB3410

1.2 Ordering Information

COMMENT

−40°C to 85°C

0°C to 70°C

32-TERMINAL LQFP PACKAGE 32-TERMINAL QFN PACKAGE

TUSB3410 I VF TUSB3410 I RHB

TUSB3410 VF TUSB3410 RHB Shipped in trays

PACKAGED DEVICES

TUSB3410 I RHBR

Industrial temperature range Shipped in trays

Industrial temperature range Tape and Reel Option

TUSB3410 RHBR Tape and Reel Option

1.3 Revision History

Version Date Changes

Mar−2002 Initial Release

A Apr−2002 1. General grammatical corrections

B Jun−2002 1. Removed Design−in warning from cover sheet

C Nov−2003 1. Added Industrial Temperature Option and Information

D July 2005 1. General grammatical corrections

F July 2007 1. Added ordering information for TUSB3410IRHBR and TUSB3410RHBR

2. Added Design−in warning on cover sheet

3. Removed references to Optional preprogrammed VID/PID Registers from Section 5.1.6 through 5.1.11. Renumber the remainder of Section 5.1 accordingly – option no longer supported.

4. Clarified GPIO pin availability

2. Added Note 8 to Terminal Functions Table for GPIO Pins.

3. Removed Section 3.2.3 – Production Programming Mode – Mode no longer supported.

4. Added Clock Output Control description to section 5.1.5.

5. Removed Section 11.6.4 USB Descriptor with Binary Firmware

6. Added Icc Spec to Table 12.3

2. Added USB Logo to Cover

2. Numerous technical corrections

Introduction

SLLS519F—July 2007 TUSB3410

Introduction

SLLS519F—July 2007TUSB3410

2 Main Features

2.1 USB Features

• Fully compliant with USB 2.0 full speed specifications: TID #40340262

• Supports 12-Mbps USB data rate (full speed)

• Supports USB suspend, resume, and remote wakeup operations

• Supports two power source modes:

− Bus-powered mode

− Self-powered mode

• Can support a total of three input and three output (interrupt, bulk) endpoints

2.2 General Features

• Integrated 8052 microcontroller with

− 256 × 8 RAM for internal data

− 10K × 8 ROM (with USB and I

− 16K × 8 RAM for code space loadable from host or I2C port

− 2K × 8 shared RAM used for data buffers and endpoint descriptor blocks (EDB)

C boot loader)

Main Features

− Four GPIO terminals from 8052 port 3

− Master I

− MCU operates at 24 MHz providing 2 MIPS operation

− 128-ms watchdog timer

• Built-in two-channel DMA controller for USB/UART bulk I/O

• Operates from a 12-MHz crystal

• Supports USB suspend and resume

• Supports remote wake-up

• Available in 32-terminal LQFP

• 3.3-V operation with 1.8-V core operating voltage provided by on-chip 1.8-V voltage regulator

C controller for EEPROM device access

2.3 Enhanced UART Features

• Software/hardware flow control:

− Programmable Xon/Xoff characters

− Programmable Auto-RTS

• Automatic RS-485 bus transceiver control, with and without echo

• Selectable IrDA mode for up to 115.2 kbps transfer

/DTR and Auto-CTS/DSR

• Software selectable baud rate from 50 to 921.6 k baud

• Programmable serial-interface characteristics

− 5-, 6-, 7-, or 8-bit characters

− Even, odd, or no parity-bit generation and detection

− 1-, 1.5-, or 2-stop bit generation

SLLS519F—July 2007 TUSB3410

Main Features

• Line break generation and detection

• Internal test and loop-back capabilities

• Modem-control functions (CTS

• Internal diagnostics capability

− Loopback control for communications link-fault isolation

− Break, parity, overrun, framing-error simulation

2.4 Terminal Assignment

, RTS, DSR, DTR, RI, and DCD)

VF PACKAGE

(TOP VIEW)

TEST1

TEST0

CLKOUT

DTR

RTS

SOUT/IR_SOUT

23 22 21 20 19

24 18

25 26 27 28 29 30 31 32

3 4 5 6 7 8

VCC

X1/CLKI

GND

P3.4 P3.3 P3.1 P3.0

GND

SIN/IR_SIN

16 15 14 13 12

RI/CP DCD DSR CTS WAKEUP SCL SDA RESET

VCC

VREGEN

SUSPEND

PUR

VDD18

GND

SLLS519F—July 2007TUSB3410

Main Features

I/O

DESCRIPTION

Table 2−1. Terminal Functions

TERMINAL

NAME NO.

CLKOUT 22 O Clock output (controlled by bits 2 (CLKOUTEN) and 3(CLKSLCT) in the MODECNFG register (see

CTS 13 I UART: Clear to send (see Note 4) DCD 15 I UART: Data carrier detect (see Note 4) DM 7 I/O Upstream USB port differential data minus DP 6 I/O Upstream USB port differential data plus DSR 14 I UART: Data set ready (see Note 4) DTR 21 O UART: Data terminal ready (see Note 1) GND 8, 18, 28 GND Digital ground P3.0 32 I/O General-purpose I/O 0 (port 3, terminal 0) (see Notes 3, 5, and 8) P3.1 31 I/O General-purpose I/O 1 (port 3, terminal 1) (see Notes 3, 5, and 8) P3.3 30 I/O General-purpose I/O 3 (port 3, terminal 3) (see Notes 3, 5, and 8) P3.4 29 I/O General-purpose I/O 4 (port 3, terminal 4) (see Notes 3, 5, and 8) PUR 5 O Pull-up resistor connection (see Note 2) RESET 9 I Device master reset input (see Note 4) RI/CP 16 I UART: Ring indicator (see Note 4) RTS 20 O UART: Request to send (see Note 1) SCL 11 O Master I2C controller: clock signal (see Note 1) SDA 10 I/O Master I2C controller: data signal (see Notes 1 and 5) SIN/IR_SIN 17 I UART: Serial input data / IR Serial data input (see Note 6) SOUT/IR_SOUT 19 O UART: Serial output data / IR Serial data output (see Note 7) SUSPEND 2 O Suspend indicator terminal (see Note 3). When this terminal is asserted high, the device is in

TEST0 23 I Test input (for factory test only) (see Note 5). This terminal must be tied to VCC through a 10-kΩ

TEST1 24 I Test input (for factory test only) (see Note 5). This terminal must be tied to VCC through a 10-kΩ

VCC 3, 25 PWR 3.3 V VDD18 4 PWR 1.8-V supply. An internal voltage regulator generates this supply voltage when terminal VREGEN is

VREGEN 1 I This active-low terminal is used to enable the 3.3-V to 1.8-V voltage regulator. WAKEUP 12 I Remote wake-up request terminal. When low, wakes up system (see Note 5) X1/CLKI 27 I 12-MHz crystal input or clock input X2 26 O 12-MHz crystal output

NOTES: 1. 3-state CMOS output (±4-mA drive/sink)

2. 3-state CMOS output (±8-mA drive/sink)

3. 3-state CMOS output (±12-mA drive/sink)

4. TTL-compatible, hysteresis input

5. TTL-compatible, hysteresis input, with internal 100-µA active pullup resistor

6. TTL-compatible input without hysteresis, with internal 100-µA active pullup resistor

7. Normal or IR mode: 3-state CMOS output (±4-mA drive/sink)

8. The MCU treats the outputs as open drain types in that the output can be driven low continuously, but a high output is driven for two clock cycles and then the output is high impedance.

Section 5.5 and Note 1)

suspend mode.

resistor.

low. When VREGEN

is high, 1.8 V must be supplied externally.

SLLS519F—July 2007 TUSB3410

Main Features

SLLS519F—July 2007TUSB3410

3 Detailed Controller Description

3.1 Operating Modes

The TUSB3410 controls its USB interface in response to USB commands, and this action is independent of the serial port mode selected. On the other hand, the serial port can be configured in three different modes.

As with any interface device, data movement is the main function of the TUSB3410, but typically the initial configuration and error handling consume most of the support code. The following sections describe the various modes the device can be used in and the means of configuring the device.

3.2 USB Interface Configuration

The TUSB3410 contains onboard ROM microcode, which enables the MCU to enumerate the device as a USB peripheral. The ROM microcode can also load application code into internal RAM from either external memory via the I

3.2.1 External Memory Case

After reset, the TUSB3410 is disconnected from the USB. Bit 7 (CONT) in the USBCTL register (see Section 5.4) is cleared. The TUSB3410 checks the I then it uploads the code from the external memory device into the RAM program space. Once loaded, the TUSB3410 connects to the USB by setting the CONT bit and enumeration and configuration are performed. This is the most likely use of the device.

3.2.2 Host Download Case

If the valid code is not found at the I2C port, then the TUSB3410 connects to the USB by setting bit 7 (CONT) in the USBCTL register (see Section 5.4), and then an enumeration and default configuration are performed. The host can download additional microcode into RAM to tailor the application. Then, the MCU causes a disconnect and reconnect by clearing and setting the CONT bit, which causes the TUSB3410 to be re-enumerated with a new configuration.

C bus or from the host via the USB.

Detailed Controller Description

C port for the existence of valid code; if it finds valid code,

3.3 USB Data Movement

From the USB perspective, the TUSB3410 looks like a USB peripheral device. It uses endpoint 0 as its control endpoint, as do all USB peripherals. It also configures up to three input and three output endpoints, although most applications use one bulk input endpoint for data in, one bulk output endpoint for data out, and one interrupt endpoint for status updates. The USB configuration likely remains the same regardless of the serial port configuration.

Most data is moved from the USB side to the UART side and from the UART side to the USB side using on-chip DMA transfers. Some special cases may use programmed I/O under control of the MCU.

3.4 Serial Port Setup

The serial port requires a few control registers to be written to configure its operation. This configuration likely remains the same regardless of the data mode used. These registers include the line control register that controls the serial word format and the divisor registers that control the baud rate.

These registers are usually controlled by the host application.

3.5 Serial Port Data Modes

The serial port can be configured in three different, although similar, data modes: the RS-232 data mode, the RS-485 data mode, and the IrDA data mode. Similar to the USB mode, once configured for a specific application, it is unlikely that the mode would be changed. The different modes affect the timing of the serial input and output or the use of the control signals. However, the basic serial-to-parallel conversion of the receiver and parallel-to-serial conversion of the transmitter remain the same in all modes. Some features are available in all modes, but are only applicable in certain modes. For instance, software flow control via Xoff/Xon characters can be used in all modes, but would usually only be used in RS-232 or IrDA mode because the RS-485 mode is half-duplex communication. Similarly, hardware flow control via RTS handshaking is available in RS-232 or IrDA mode. However, this would probably be used only in RS-232 mode, since in IrDA mode only the SIN and SOUT paths are optically coupled.

/CTS (or DTR/DSR)

SLLS519F—July 2007 TUSB3410

Detailed Controller Description

3.5.1 RS-232 Data Mode

The default mode is called the RS-232 mode and is typically used for full duplex communication on SOUT and SIN. In this mode, the modem control outputs (RTS outputs. The modem control inputs (CTS inputs. Alternatively , R TS receive FIFO overruns. Finally, software flow control via Xoff/Xon characters can be used for the same purpose.

This mode represents the most general-purpose applications, and the other modes are subsets of this mode.

3.5.2 RS-485 Data Mode

The RS-485 mode is very similar to the RS-232 mode in that the SOUT and SIN formats remain the same. Since RS-485 is a bus architecture, it is inherently a single duplex communication system. The TUSB3410 in RS-485 mode controls the RTS receiver. When in RS-485 mode, the enable signals for transmitting are automatically asserted whenever the DMA is set up for outbound data. The receiver can be left enabled while the driver is enabled to allow an echo if desired, but when receive data is expected, the driver must be disabled. Note that this precludes use of hardware flow control, since this is a half-duplex operation, it would not be effective. Software flow control is supported, but may be of limited value.

The RS-485 mode is enabled by setting bit 7 (485E) in the FCRL register (see Section 7.1.4), and bit 1 (RCVE) in the MCR register (see Section 7.1.6) allows the receiver to eavesdrop while in the RS-485 mode.

and DTR) communicate to a modem or are general

, DSR, DCD, and RI/CP) communicate to a modem or are general

and CTS (or DTR and DSR) can throttle the data flow on SOUT and SIN to prevent

and DTR signals such that either can enable an RS-485 driver or RS-485

3.5.3 IrDA Data Mode

The IrDA mode encodes SOUT and decodes SIN in the manner prescribed by the IrDA standard, up to

115.2 kbps. Connection to an external IrDA transceiver is required. Communications is usually full duplex. Generally , i n a n IrDA system, only the SOUT and SIN paths are connected so hardware flow control is usually not an option. Software flow control is supported.

The IrDA mode is enabled by setting bit 6 (IREN) in the USBCTL register (see Section 5.4). The IR encoder and decoder circuitry work with the UART to change the serial bit stream into a series of pulses

and back again. For every zero bit in the outbound serial stream, the encoder sends a low-to-high-to-low pulse with the duration of 3/16 of a bit frame at the middle of the bit time. For every one bit in the serial stream, the output remains low for the entire bit time.

The decoding process consists of receiving the signal from the IrDA receiver and converting it into a series of zeroes and ones. As the converse to the encoder, the decoder converts a pulse to a zero bit and the lack of a pulse to a one bit.

SLLS519F—July 2007TUSB3410

Detailed Controller Description

From

UART

IREN (in

USBCTL

UART

BaudOut

Clock

TXCNTL (in

MODECNFG

3.556 MHz

CLKSLCT (in

MODECNFG

UART

Receiver

SOUT

SIN

SOUT

Encoder

SOFTSW (in MODECNFG

M U X

CLKOUTEN

MODECNFG

U X

IR_RX

Decoder

IR_TX

(in

M U X

3.3 V

SOUT/IR_SOU Terminal

CLKOUT Terminal

SIN/IR_SIN Terminal

Figure 3−1. RS-232 and IR Mode Select

SLLS519F—July 2007 TUSB3410

Detailed Controller Description

12 MHz

X1/CLKI

DTR

DB9

Connector

Transceivers

RTS

RI/CP

DCD DSR

CTS

SOUT

SIN

P3.0 P3.1 P3.3 P3.4

USB-0

DP DM

TUSB3410

Figure 3−2. USB-to-Serial Implementation (RS-232)

12 MHz

X1/CLKI

RTS

Serial Port

6 8

GPIO Terminals for Other Onboard Control Function

RS-485 Bus

SOUT

DTR

RTS

USB-0

DP DM

TUSB3410

2-Bit Time 1-Bit Max

Receiver is Disabled if RCVE = 0

SOUT

DTR

SIN

RS-485

Transceiver

Figure 3−3. RS-485 Bus Implementation

SLLS519F—July 2007TUSB3410

4 MCU Memory Map

Figure 4−1 illustrates the MCU memory map under boot and normal operation.

The internal 256 bytes of RAM are not shown, since they are assumed to be in the standard 8052 location (0000h to 00FFh). The shaded areas represent the internal ROM/RAM.

• When bit 0 (SDW) of the ROMS register is 0 (boot mode)

The 10K ROM is mapped to address (0x0000−0x27FF) and is duplicated in location (0x8000−0xA7FF) in code space. The internal 16K RAM is mapped to address range (0x0000−0x3FFF) in data space. Buffers, MMR, and I/O are mapped to address range (0xF800−0xFFFF) in data space.

• When bit 0 (SDW) is 1 (normal mode)

The 10K ROM is mapped to (0x8000−0xA7FF) in code space. The internal 16K RAM is mapped to address range (0x0000−0x3FFF) in code space. Buffers, MMR, and I/O are mapped to address range (0xF800−0xFFFF) in data space.

MCU Memory Map

NOTE:

0000h

27FFh

3FFFh

8000h

A7FFh

Boot Mode (SDW = 0)

CODE XDATA

10K Boot ROM

(16K)

Read/Write

Normal Mode (SDW = 1)

CODE XDATA

16K Code RAM Read Only

10K Boot ROM

F800h

2K Data

MMR

FF7Fh FF80h

FFFFh

2K Data

MMR

Figure 4−1. MCU Memory Map

SLLS519F—July 2007 TUSB3410

MCU Memory Map

SDW

BOOT ROM

RAM CODE

ROM CODE

4.1 Miscellaneous Registers

4.1.1 ROMS: ROM Shadow Configuration Register (Addr:FF90h)

This register is used by the MCU to switch from boot mode to normal operation mode (boot mode is set on power-on reset only). In addition, this register provides the device revision number and the ROM/RAM configuration.

765 4 32 1 0

ROA S1 S0 RSVD RSVD RSVD RSVD SDW

R/O R/O R/O R/O R/O R/O R/O R/W

BIT

4−1 RSVD No effect These bits are always read as 0000b. 6−5 S[1:0] No effect Code space size. These bits define the ROM or RAM code-space size (bit 7 (ROA) defines ROM or

NAME RESET FUNCTION

0 SDW 0

7 ROA No effect ROM or RAM version. This bit indicates whether the code space is RAM or ROM based. This bit is

This bit enables/disables boot ROM. (Shadow the ROM). SDW = 0 When clear, the MCU executes from the 10K boot ROM space. The boot ROM appears in two

locations: 0000 h and 8000h. The 16K RAM is mapped to XDATA space; therefore, a read/write operation is possible. This bit is set by the MCU after the RAM load is completed. The MCU cannot clear this bit; it is cleared on power-up reset or watchdog time-out reset.

SDW = 1 When set by the MCU, the 10K boot ROM maps to location 8000h, and the 16K RAM is mapped

to code space, starting at location 0000h. At this point, the MCU executes from RAM, and the write operation is disabled (no write operation is possible in code space).

RAM). These bits are permanently set to 10b, indicating 16K bytes of code space, and are not affected by reset (see Table 4−1).

00 = 4K bytes code space size 01 = 8K bytes code space size 10 = 16K bytes code space size 11 = 32K bytes code space size

permanently set to 1, indicating the code space is RAM, and is not affected by reset (see Table 4−1). ROA = 0 Code space is ROM ROA = 1 Code space is RAM

Table 4−1. ROM/RAM Size Definition Table

ROMS REGISTER

ROA S1 S0

0 0 0 None None 4K 0 0 1 None None 8K 0 1 0 None None 16K (reserved) 1 1 1 None None 32K (reserved) 1 0 0 10K 4K None 1 0 1 10K 8K None

†

1 1 1 10K 32K (reserved) None

†

This is the hardwired setting.

†

10K

†

16K

†

None

†

4.1.2 Boot Operation (MCU Firmware Loading)

Since the code space is in RAM (with the exception of the boot ROM), the TUSB3410 firmware must be loaded from an external source. Two sources are available for booting: one from an external serial EEPROM connected to the I register (see Section 4.1.1) and bit 7 (CONT) in the USBCTL register (see Section 5.4) are cleared. This configures the memory space to boot mode (see Table 4−3) and keeps the device disconnected from the host. The first instruction is fetched from location 0000h (which is in the 10K ROM). The 16K RAM is mapped to XDATA space (location 0000h). The MCU executes a read from an external EEPROM and tests whether it contains the code (by testing for boot signature). If it contains the code, then the MCU reads from EEPROM

C bus and the other from the host via the USB. On device reset, bit 0 (SDW) in the ROMS

SLLS519F—July 2007TUSB3410

MCU Memory Map

and writes to the 16K RAM in XDATA space. If it does not contain the code, then the MCU proceeds to boot from the USB.

Once the code is loaded, the MCU sets the SDW bit to 1 in the ROMS register . This switches the memory map to normal mode; that is, the 16K RAM is mapped to code space, and the MCU starts executing from location 0000h. Once the switch is done, the MCU sets the CONT bit to 1 in the USBCTL register. This connects the device to the USB and results in normal USB device enumeration.

4.1.3 WDCSR: Watchdog Timer, Control, and Status Register (Addr:FF93h)

A watchdog timer (WDT) with 1-ms clock is provided. If this register is not accessed for a period of 128 ms, then the WDT counter resets the MCU (see Figure 5−1). The watchdog timer is enabled by default and can be disabled by writing a pattern of 101010b into the WDD[5:0] bits. The 1-ms clock for the watchdog timer is generated from the SOF pulses. Therefore, in order for the watchdog timer to count, bit 7 (CONT) in the USBCTL register (see Section 5.4) must be set.

765 4 32 1 0

WDD0 WDR WDD5 WDD4 WDD3 WDD2 WDD1 WDT

R/W R/C R/W R/W R/W R/W R/W W/O

BIT

5−1 WDD[5:1] 00000 These bits disable the watchdog timer. For the timer to be disabled these bits must be set to 10101b and

NAME RESET FUNCTION

0 WDT 0 MCU must write a 1 to this bit to prevent the watchdog timer from resetting the MCU. If the MCU does not

6 WDR 0

7 WDD0 1 This bit is one of the six disable bits for the watchdog timer. This bit must be cleared in order for the

write a 1 in a period of 128 ms, the watchdog timer resets the device. Writing a 0 has no effect on the watchdog timer. (The watchdog timer is a 7-bit counter using a 1-ms CLK.) This bit is read as 0.

bit 7 (WDD0) must also be set to 0. If any other pattern is present, then the watchdog timer is in operation. Watchdog reset indication bit. This bit indicates if the reset occurred due to power-on reset or watchdog

timer reset. WDR = 0 A power-up reset occurred WDR = 1 A watchdog time-out reset occurred. To clear this bit, the MCU must write a1. Writing a 0 has no

effect.

watchdog timer to be disabled.

4.2 Buffers + I/O RAM Map

The address range from F800h to FFFFh (2K bytes) is reserved for data buffers, setup packet, endpoint descriptors block (EDB), and all I/O. There are 128 locations reserved for memory-mapped registers (MMR). Table 4−2 represents the XDATA space allocation and access restriction for the DMA, USB buffer manager (UBM), and MCU.

Table 4−2. XDATA Space

DESCRIPTION ADDRESS RANGE UBM ACCESS DMA ACCESS MCU ACCESS

Internal MMRs

(Memory-Mapped Registers)

EDB

(Endpoint Descriptors Block)

Setup Packet FF07h−FF00h Yes No Yes

Input Endpoint-0 Buffer FEFFh−FEF8h Yes Yes Yes

Output Endpoint-0 Buffer FEF7h−FEF0h Yes Yes Yes

Data Buffers FEEFh−F800h Yes Yes Yes

FFFFh−FF80h

FF7Fh−FF08h Only for EDB update Only for EDB update Yes

(Only EDB-0)

(only data register and EDB-0)

Yes

SLLS519F—July 2007 TUSB3410

MCU Memory Map

Table 4−3. Memory-Mapped Registers Summary (XDATA Range = FF80h → FFFFh)

ADDRESS REGISTER DESCRIPTION

FFFFh FUNADR Function address register

FFFEh USBSTA USB status register FFFDh USBMSK USB interrupt mask register FFFCh USBCTL USB control register

FFFBh MODECNFG Mode configuration register

FFFAh−FFF4h Reserved

FFF3h I2CADR I2C-port address register

FFF2h I2CDATI I2C-port data input register

FFF1h I2CDATO I2C-port data output register

FFF0h I2CSTA I2C-port status register

FFEFh SERNUM7 Serial number byte 7 register FFEEh SERNUM6 Serial number byte 6 register FFEDh SERNUM5 Serial number byte 5 register FFECh SERNUM4 Serial number byte 4 register FFEBh SERNUM3 Serial number byte 3 register FFEAh SERNUM2 Serial number byte 2 register

FFE9h SERNUM1 Serial number byte 1 register

FFE8h SERNUM0 Serial number byte 0 register

FFE7h−FFE6h Reserved

FFE5h DMACSR3 DMA-3: Control and status register

FFE4h DMACDR3 DMA-3: Channel definition register

FFE3h−FFE2h Reserved

FFE1h DMACSR1 DMA-1: Control and status register

FFE0h DMACDR1 DMA-1: Channel definition register

FFDFh−FFACh Reserved

FFABh MASK UART: Interrupt mask register

FFAAh XOFF UART: Xoff register

FFA9h XON UART: Xon register

FFA8h DLH UART: Divisor high-byte register

FFA7h DLL UART: Divisor low-byte register

FFA6h MSR UART: Modem status register

FFA5h LSR UART: Line status register

FFA4h MCR UART: Modem control register

FFA3h FCRL UART: Flow control register

FFA2h LCR UART: Line control registers

FFA1h TDR UART: Transmitter data registers

FFA0h RDR UART: Receiver data registers

FF9Eh PUR_3 GPIO: Pullup register for port 3

SLLS519F—July 2007TUSB3410

MCU Memory Map

Table 4−3. Memory-Mapped Registers Summary (XDATA Range = FF80h → FFFFh) (Continued)

ADDRESS REGISTER DESCRIPTION

FF9Dh−FF94h

FF93h FF92h VECINT Vector interrupt register FF91h Reserved FF90h ROMS ROM shadow configuration register

FF8Fh−FF84h Reserved

FF83h OEPBCNT_0 Output endpoint_0: Byte count register FF82h OEPCNFG_0 Output endpoint_0: Configuration register FF81h IEPBCNT_0 Input endpoint_0: Byte count register FF80h IEPCNFG_0 Input endpoint_0: Configuration register

Reserved WDCSR

Watchdog timer control and status register

Table 4−4. EDB Memory Locations

ADDRESS REGISTER DESCRIPTION

FF7Fh−FF60h Reserved

FF5Fh IEPSIZXY_3 Input endpoint_3: X-Y buffer size FF5Eh IEPBCTY_3 Input endpoint_3: Y-byte count FF5Dh IEPBBAY_3 Input endpoint_3: Y-buffer base address FF5Ch − Reserved FF5Bh − Reserved FF5Ah IEPBCTX_3 Input endpoint_3: X-byte count FF59h IEPBBAX Input endpoint_3: X-buffer base address FF58h IEPCNF_3 Input endpoint_3: Configuration FF57h IEPSIZXY_2 Input endpoint_2: X-Y buffer size FF56h IEPBCTY_2 Input endpoint_2: Y-byte count FF55h IEPBBAY_2 Input endpoint_2: Y-buffer base address FF54h − Reserved FF53h − Reserved FF52h IEPBCTX_2 Input endpoint_2: X-byte count FF51h IEPBBAX_2 Input endpoint_2: X-buffer base address FF50h IEPCNF_2 Input endpoint_2: Configuration FF4Fh IEPSIZXY_1 Input endpoint_1: X-Y buffer size FF4Eh IEPBCTY_1 Input endpoint_1: Y-byte count FF4Dh IEPBBAY_1 Input endpoint_1: Y-buffer base address FF4Ch − Reserved FF4Bh − Reserved FF4Ah IEPBCTX_1 Input endpoint_1: X-byte count FF49h IEPBBAX_1 Input endpoint_1: X-buffer base address FF48h IEPCNF_1 Input endpoint_1: Configuration FF47h

↑ Reserved FF20h FF1Fh OEPSIZXY_3 Output endpoint_3: X-Y buffer size FF1Eh OEPBCTY_3 Output endpoint_3: Y-byte count FF1Dh OEPBBAY_3 Output endpoint_3: Y-buffer base address

FF1Bh−FF1Ch − Reserved

SLLS519F—July 2007 TUSB3410

MCU Memory Map

↑

Table 4−4. EDB Memory Locations (Continued)

ADDRESS REGISTER DESCRIPTION

FF1Ah OEPBCTX_3 Output endpoint_3: X-byte count

FF19h OEPBBAX_3 Output endpoint_3: X-buffer base address FF18h OEPCNF_3 Output endpoint_3: Configuration FF17h OEPSIZXY_2 Output endpoint_2: X-Y buffer size FF16h OEPBCTY_2 Output endpoint_2: Y-byte count FF15h OEPBBAY_2 Output endpoint_2: Y-buffer base address

FF14h−FF13h − Reserved

FF12h OEPBCTX_2 Output endpoint_2: X-byte count FF11h OEPBBAX_2 Output endpoint_2: X-buffer base address

FF10h OEPCNF_2 Output endpoint_2: Configuration FF0Fh OEPSIZXY_1 Output endpoint_1: X-Y buffer size FF0Eh OEPBCTY_1 Output endpoint_1: Y-byte count FF0Dh OEPBBAY_1 Output endpoint_1: Y -buffer base address

FF0Ch−FF0Bh − Reserved

FF0Ah OEPBCTX_1 Output endpoint_1: X-byte count

FF09h OEPBBAX_1 Output endpoint_1: X-buffer base address

FF08h OEPCNF_1 Output endpoint_1: Configuration

FF07h

↑ (8 bytes) Setup packet block

FF00h FEFFh

↑ (8 bytes) Input endpoint_0 buffer FEF8h FEF7h

↑ (8 bytes) Output endpoint_0 buffer FEF0h

FEEFh TOPBUFF Top of buffer space

↑

F800h STABUFF Start of buffer space

Buffer space

4.3 Endpoint Descriptor Block (EDB−1 to EDB−3)

Data transfers between the USB, the MCU, and external devices that are defined by an endpoint descriptor block (EDB). Three input and three output EDBs are provided. With the exception of EDB-0 (I/O endpoint-0), all EDBs are located in SRAM as per Table 4−3. Each EDB contains information describing the X- and Y-buffers. In addition, each EDB provides general status information.

Table 4−5 describes the EDB entries for EDB−1 to EDB−3. EDB−0 registers are described in Table 4−6.

SLLS519F—July 2007TUSB3410

MCU Memory Map

STALL

Table 4−5. Endpoint Registers and Offsets in RAM (n = 1 to 3)

OFFSET ENTRY NAME DESCRIPTION

07 EPSIZXY_n I/O endpoint_n: X/Y-buffer size 06 EPBCTY_n I/O endpoint_n: Y-byte count 05 EPBBAY_n I/O endpoint_n: Y-buffer base address 04 SPARE Not used 03 SPARE Not used 02 EPBCTX_n I/O endpoint_n: X-byte count 01 EPBBAX_n I/O endpoint_n: X-buffer base address 00 EPCNF_n I/O endpoint_n: Configuration

Table 4−6. Endpoint Registers Base Addresses

BASE ADDRESS DESCRIPTION

FF08h Output endpoint 1 FF10h Output endpoint 2 FF18h Output endpoint 3 FF48h Input endpoint 1 FF50h Input endpoint 2 FF58h Input endpoint 3

4.3.1 OEPCNF_n: Output Endpoint Configuration (n = 1 to 3) (Base Addr: FF08h, FF10h, FF18h)

765 4 32 1 0

UBME ISO=0 TOGLE DBUF STALL USBIE RSV RSV

R/W R/W R/W R/W R/W R/W R/W R/W

BIT NAME RESET FUNCTION

1−0 RSV x Reserved = 0

2 USBIE x USB interrupt enable on transaction completion. Set/cleared by the MCU.

3 STALL 0

4 DBUF x Double-buffer enable. Set/cleared by the MCU.

5 TOGLE x USB toggle bit. This bit reflects the toggle sequence bit of DATA0, DATA1. 6 ISO x ISO = 0 Nonisochronous transfer. This bit must be cleared by the MCU since only nonisochronous transfer

7 UBME x USB buffer manager (UBM) enable/disable bit. Set/cleared by the MCU.

USBIE = 0 No interrupt on transaction completion USBIE = 1 Interrupt on transaction completion

USB stall condition indication. Set/cleared by the MCU. STALL = 0

STALL = 1

DBUF = 0 Primary buffer only (X-buffer only) DBUF = 1 Toggle bit selects buffer

is supported.

UBME = 0 UBM cannot use this endpoint UBME = 1 UBM can use this endpoint

No stall USB stall condition. If set by the MCU, then a STALL handshake is initiated and the bit is cleared by the MCU.

4.3.2 OEPBBAX_n: Output Endpoint X-Buffer Base Address (n = 1 to 3) (Offset 1)

765 4 32 1 0

A10 A9 A8 A7 A6 A5 A4 A3

R/W R/W R/W R/W R/W R/W R/W R/W

BIT

7−0 A[10:3] x A[10:3] of X-buffer base address (padded with 3 LSBs of zeros for a total of 11 bits). This value is set by

SLLS519F—July 2007 TUSB3410

NAME RESET FUNCTION

the MCU. The UBM or DMA uses this value as the start-address of a given transaction. Note that the UBM or DMA does not change this value at the end of a transaction.

MCU Memory Map

4.3.3 OEPBCTX_n: Output Endpoint X Byte Count (n = 1 to 3) (Offset 2)

765 4 32 1 0

NAK C6 C5 C4 C3 C2 C1 C0

R/W R/W R/W R/W R/W R/W R/W R/W

BIT NAME RESET FUNCTION

6−0 C[6:0] x X-buffer byte count:

7 NAK x NAK = 0

X000.0000b Count = 0 X000.0001b Count = 1 byte : : X011.1111b Count = 63 bytes X100.0000b Count = 64 bytes Any value ≥ 100.0001b may result in unpredictable results.

NAK = 1

No valid data in buffer. Ready for host OUT Buffer contains a valid packet from host (gives NAK response to Host OUT request)

4.3.4 OEPBBAY_n: Output Endpoint Y-Buffer Base Address (n = 1 to 3) (Offset 5)

765 4 32 1 0

A10

R/W R/W R/W R/W R/W R/W R/W R/W

A9 A8 A7 A6 A5 A4 A3

BIT

7−0 A[10:3] x A[10:3] of Y-buffer base address (padded with 3 LSBs of zeros for a total of 11 bits). This value is set by

NAME RESET FUNCTION

the MCU. The UBM or DMA uses this value as the start-address of a given transaction. Furthermore, UBM or DMA does not change this value at the end of a transaction.

4.3.5 OEPBCTY_n: Output Endpoint Y-Byte Count (n = 1 to 3) (Offset 6)

765 4 32 1 0

NAK

R/W R/W R/W R/W R/W R/W R/W R/W

BIT

6−0 C[6:0] x Y-byte count:

7 NAK x NAK = 0

NAME RESET FUNCTION

C6 C5 C4 C3 C2 C1 C0

X000.0000b Count = 0 X000.0001b Count = 1 byte : : X011.1111b Count = 63 bytes X100.0000b Count = 64 bytes Any value ≥ 100.0001b may result in unpredictable results.

NAK = 1

No valid data in buffer. Ready for host OUT Buffer contains a valid packet from host (gives NAK response to Host OUT request)

SLLS519F—July 2007TUSB3410

MCU Memory Map

4.3.6 OEPSIZXY_n: Output Endpoint X-/Y-Buffer Size (n = 1 to 3) (Offset 7)

765 4 32 1 0

RSV

R/W R/W R/W R/W R/W R/W R/W R/W

S6 S5 S4 S3 S2 S1 S0

BIT

6−0 S[6:0] x X- and Y-buffer size:

7 RSV x Reserved = 0

NAME RESET FUNCTION

0000.0000b Size = 0

0000.0001b Size = 1 byte : :

0011.1111b Size = 63 bytes

0100.0000b Size = 64 bytes Any value ≥ 100.0001b may result in unpredictable results.

4.3.7 IEPCNF_n: Input Endpoint Configuration (n = 1 to 3) (Base Addr: FF48h, FF50h, FF58h)

765 4 32 1 0

UBME ISO=0 TOGLE DBUF STALL USBIE RSV RSV

R/W R/W R/W R/W R/W R/W R/W R/W

BIT

1−0 RSV x Reserved = 0

2 USBIE x USB interrupt enable on transaction completion

3 STALL 0 USB stall condition indication. Set by the UBM but can be set/cleared by the MCU

4 DBUF x Double buffer enable

5 TOGLE x USB toggle bit. This bit reflects the toggle sequence bit of DATA0, DATA1 6 ISO x ISO = 0 Nonisochronous transfer. This bit must be cleared by the MCU since only nonisochronous

7 UBME x UBM enable/disable bit. Set/cleared by the MCU

NAME RESET FUNCTION

USBIE = 0 No interrupt on transaction completion USBIE = 1 Interrupt on transaction completion

STALL = 0 No stall STALL = 1 USB stall condition. If set by the MCU, then a STALL handshake is initiated and the bit is cleared automatically.

DBUF = 0 Primary buffer only (X-buffer only) DBUF = 1 Toggle bit selects buffer

transfer is supported

UBME = 0 UBM cannot use this endpoint UBME = 1 UBM can use this endpoint

4.3.8 IEPBBAX_n: Input Endpoint X-Buffer Base Address (n = 1 to 3) (Offset 1)

765 4 32 1 0

A10

R/W R/W R/W R/W R/W R/W R/W R/W

BIT

7−0 A[10:3] x A[10:3] of X-buffer base address (padded with 3 LSBs of zeros for a total of 11 bits). This value is set by

SLLS519F—July 2007 TUSB3410

NAME RESET FUNCTION

A9 A8 A7 A6 A5 A4 A3

the MCU. The UBM or DMA uses this value as the start-address of a given transaction, but note that the UBM or DMA does not change this value at the end of a transaction.

+ 67 hidden pages