TEXAS INSTRUMENTS TUSB3210 Technical data

TUSB3210

Universal Serial Bus General-Purpose Device Controller

Data Manual

August 2007 DIBU

SLLS466F

TUSB3210 Universal Serial Bus General-Purpose Device Controller

SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007

Contents

1 Introduction ......................................................................................................................... 7

1.1 Features ....................................................................................................................... 7

1.2 Description .................................................................................................................... 7

1.3 Ordering Information ........................................................................................................ 7

1.4 Device Information ........................................................................................................... 8

1.5 Revision History ............................................................................................................ 11

2 Functional Description ........................................................................................................ 12

2.1 MCU Memory Map ......................................................................................................... 12

2.2 Miscellaneous Registers .................................................................................................. 13

2.2.1 TUSB3210 Boot Operation ..................................................................................... 13

2.2.2 MCNFG: MCU Configuration Register ........................................................................ 13

2.2.3 PUR_n: GPIO Pullup Register for Port n (n = 0 to 3) ....................................................... 14

2.2.4 INTCFG: Interrupt Configuration .............................................................................. 14

2.2.5 WDCSR: Watchdog Timer, Control, and Status Register .................................................. 14

2.2.6 PCON: Power Control Register (at SFR 87h) ............................................................... 15

2.3 Buffers + I/O RAM Map .................................................................................................... 16

2.4 Endpoint Descriptor Block (EDB-1 to EDB-3) .......................................................................... 18

2.4.1 OEPCNF_n: Output Endpoint Configuration (n = 1 to 3) ................................................... 19

2.4.2 OEPBBAX_n: Output Endpoint X-Buffer Base Address (n = 1 to 3) ..................................... 20

2.4.3 OEPBCTX_n: Output Endpoint X-Byte Count (n = 1 to 3) ................................................. 20

2.4.4 OEPBBAY_n: Output Endpoint Y-Buffer Base Address (n = 1 to 3) ..................................... 20

2.4.5 OEPBCTY_n: Output Endpoint Y-Byte Count (n = 1 to 3) ................................................. 21

2.4.6 OEPSIZXY_n: Output Endpoint X-/Y-Buffer Size (n = 1 to 3) ............................................. 21

2.4.7 IEPCNF_n: Input Endpoint Configuration (n = 1 to 3) ...................................................... 21

2.4.8 IEPBBAX_n: Input Endpoint X-Buffer Base Address (n = 1 to 3) ......................................... 22

2.4.9 IEPBCTX_n: Input Endpoint X-Byte Base Address (n = 1 to 3) ........................................... 22

2.4.10 IEPBBAY_n: Input Endpoint Y-Buffer Base Address (n = 1 to 3) ......................................... 23

2.4.11 IEPBCTY_n: Input Endpoint Y-Byte Count (n = 1 to 3) .................................................... 23

2.4.12 IEPSIZXY_n: Input Endpoint X-/Y-Buffer Size (n = 1 to 3) ................................................ 23

2.5 Endpoint-0 Descriptor Registers ......................................................................................... 24

2.5.1 IEPCNFG_0: Input Endpoint-0 Configuration Register ..................................................... 24

2.5.2 IEPBCNT_0: Input Endpoint-0 Byte-Count Register ........................................................ 25

2.5.3 OEPCNFG_0: Output Endpoint-0 Configuration Register ................................................. 25

2.5.4 OEPBCNT_0: Output Endpoint-0 Byte-Count Register .................................................... 26

2.6 USB Registers .............................................................................................................. 26

2.6.1 FUNADR: Function Address Register ........................................................................ 26

2.6.2 USBSTA: USB Status Register ................................................................................ 27

2.6.3 USBMSK: USB Interrupt Mask Register ...................................................................... 28

2.6.4 USBCTL: USB Control Register ............................................................................... 28

2.6.5 VIDSTA: VID/PID Status Register ............................................................................. 29

2.7 Function Reset and Power-Up Reset Interconnect .................................................................... 29

2.8 Pullup Resistor Connect/Disconnect ..................................................................................... 30

2.9 8052 Interrupt and Status Registers ..................................................................................... 30

2.9.1 8052 Standard Interrupt Enable Register .................................................................... 31

2.9.2 Additional Interrupt Sources .................................................................................... 31

2.9.3 VECINT: Vector Interrupt Register ............................................................................ 32

2.9.4 Logical Interrupt Connection Diagram ( INT0) ................................................................ 33

2.9.5 P2[7:0], P3.3 Interrupt ( INT1) .................................................................................. 33

2.10 I

C Registers ................................................................................................................ 34

2.10.1 I2CSTA: I

2.10.2 I2CADR: I

C Status and Control Register .................................................................... 34

C Address Register ................................................................................ 35

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Universal Serial Bus

General-Purpose Device Controller

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2.10.3 I2CDAI: I

2.10.4 I2CDAO: I

2.11 Read/Write Operations .................................................................................................... 35

2.11.1 Read Operation (Serial EEPROM) ............................................................................ 35

2.11.2 Current Address Read Operation ............................................................................. 36

2.11.3 Sequential Read Operation .................................................................................... 36

2.11.4 Write Operation (Serial EEPROM) ............................................................................ 37

2.11.5 Page Write Operation ........................................................................................... 37

3 Specifications .................................................................................................................... 39

3.1 Absolute Maximum Ratings ............................................................................................... 39

3.2 Commercial Operating Conditions ....................................................................................... 39

3.3 Electrical Characteristics .................................................................................................. 39

4 Application ........................................................................................................................ 40

4.1 Examples .................................................................................................................... 40

4.2 Reset Timing ................................................................................................................ 41

C Data-Input Register .............................................................................. 35

C Data-Output Register ........................................................................... 35

Contents 3

TUSB3210 Universal Serial Bus General-Purpose Device Controller

SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007

List of Figures

1-1 TUSB3210 Block Diagram ........................................................................................................ 8

1-2 Terminal Assignments ............................................................................................................. 9

2-1 MCU Memory Map (TUSB3210) ................................................................................................ 12

2-2 Reset Diagram ..................................................................................................................... 30

2-3 Pullup Resistor Connect/Disconnect Circuit ................................................................................... 30

2-4 Internal Vector Interrupt ( INT0) .................................................................................................. 33

2-5 P2[7:0], P3.3 Input Port Interrupt Generation ................................................................................. 33

4-1 Example LED Connection ........................................................................................................ 40

4-2 Partial Connection Bus Power Mode ........................................................................................... 40

4-3 Upstream Connection (a) Non-Switching Power Mode (b) Switching Power Mode ...................................... 41

4-4 Reset Timing ....................................................................................................................... 42

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Universal Serial Bus

General-Purpose Device Controller

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List of Tables

1-1 Terminal Functions ................................................................................................................. 9

1-2 Test0/Test1 Functions ............................................................................................................ 10

2-1 XDATA Space ..................................................................................................................... 16

2-2 Memory-Mapped Register Summary (XDATA Range = FF80 → FFFF) .................................................. 17

2-3 EDB and Buffer Allocations in XDATA ......................................................................................... 18

2-4 EDB Entries in RAM (n = 1 to 3) ................................................................................................ 19

2-5 Input/Output EDB-0 Registers ................................................................................................... 24

2-6 External Pin Mapping to S[3:0] in VIDSTA Register .......................................................................... 29

2-7 8052 Interrupt Location Map ..................................................................................................... 30

2-8 Vector Interrupt Values ........................................................................................................... 32

List of Tables 5

TUSB3210 Universal Serial Bus General-Purpose Device Controller

SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007

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General-Purpose Device Controller

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1 Introduction

1.1 Features

• Multiproduct Support With One Code and One

Chip (up to 16 Products With One Chip)

• Fully Compliant With USB 2.0 Full-Speed

Specifications: TID #40270269

• Supports 12 Mbits/s USB Data Rate (Full

Speed)

• Supports USB Suspend/Resume and

Remote Wake-up Operation

• Integrated 8052 Microcontroller With: – 256 × 8 RAM for Internal Data – 8K × 8 RAM Code Space Available for

Downloadable Firmware From Host or I2C

(1)

Port.

(1) The TUSB3210 has 8K × 8 RAM for development. (2) This is the buffer space for USB packet transactions.

– 512 × 8 Shared RAM Used for Data Buffers and

Endpoint Descriptor Blocks (EDB)

– Four 8052 GPIO Ports, Ports 0,1, 2, and 3

– Master I2C Controller for External Slave

Device Access

– Watchdog Timer

• Operates From a 12-MHz Crystal

• On-Chip PLL Generates 48 MHz

• Supports a Total of 3 Input and 3 Output

(Interrupt, Bulk) Endpoints

• Powerdown Mode

• 64-Pin TQFP Package

• Applications Include Keyboard, Bar Code

Reader, Flash Memory Reader, GeneralPurpose Controller

TUSB3210

Universal Serial Bus

(2)

1.2 Description

The TUSB3210 is a USB-based controller targeted as a general-purpose MCU with GPIO. The TUSB3210 has 8K × 8 RAM space for application development. In addition, the programmability of the TUSB3210 makes it flexible enough to use for various other general USB I/O applications. Unique vendor identification and product identification (VID/PID) can be selected without the use of an external EEPROM. Using a 12-MHz crystal, the onboard oscillator generates the internal system clocks. The device can be programmed via an inter-IC (I2C) serial interface at power on from an EEPROM, or optionally, the application firmware can be downloaded from a host PC via USB. The popular 8052-based microprocessor allows several third-party standard tools to be used for application development. In addition, the vast amounts of application code available in the general market also can be used (this may or may not require some code modification due to hardware variations).

1.3 Ordering Information

PRODUCT PACKAGE

TUSB3210PM PM 0 ° C to 70 ° C TUSB3210PM TUSB3210PM 160-piece tray

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package .

(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com .

Plastic quad

flatpack 64

(1) (2)

PACKAGE PACKAGE ORDERING TRANSPORT

CODE MARKING NUMBER MEDIA

OPERATING

TEMPERATURE

RANGE

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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RSTI

8052 Core

6K × 8

ROM

8K × 8

RAM

512 × 8

SRAM

CPU − I/F Suspend/

Resume

UBM

USB Buffer

Manager

TDM

Control

Logic

USB

SIE

USB TxR

USB-0

PLL

and

Dividers

Clock

Oscillator

12 MHz

2 × 16-Bit

Timers

I2C

Controller

Reset,

Interrupt

and WDT

8 P0.[7:0]

8 P1.[7:0]

8 P2.[7:0]

8 P3.[7:0]

I2C Bus

Port 0

Port 1

Port 2

Port 3

Logic

TUSB3210 Universal Serial Bus General-Purpose Device Controller

SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007

1.4 Device Information

Functional Block Diagram

Figure 1-1. TUSB3210 Block Diagram

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1 2 3

P1.1 P1.0 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 GND P2.1 P2.0 GND TEST2 DM DP PUR

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

P0.6 P0.7 P3.7 P3.6 P3.5 P3.4 P3.3 P3.2

P3.1/S1/TXD

P3.0/S0/RXD

GND

X2 X1

VCC

NC NC

5 6 7 8

P1.3

VREN

47 46 45 44 4348 42

P0.3

P0.2

P0.1

P0.0

GND

P1.7

P1.6

VCC

SDA

SCL

RST

GND

RSV

40 39 3841

9 10 11 12 13

37 36

RSV

1.8VDD

P1.5

35 34 33

14 15 16

TEST0

TEST1

SUSP

P1.4

VCC

P1.2

P0.5

P0.4

PM PACKAGE

(TOP VIEW)

TUSB3210

Universal Serial Bus

General-Purpose Device Controller

SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007

Figure 1-2. Terminal Assignments

Table 1-1. Terminal Functions

TERMINAL

NAME NO.

(1)

1.8VDD

DM 19 I/O Differential data-minus USB DP 18 I/O Differential data-plus USB GND 5, 21 24, — Power supply ground

NC 2, 3, 6, 7, No connection

P0.[0:7] 43, 44, I/O General-purpose I/O port 0 bits 0–7, Schmitt-trigger input, 100- μ A active pullup, open-drain output

P1.[0:7] 31, 32, I/O General-purpose I/O port 1 bits 0–7, Schmitt-trigger input, 100- μ A active pullup, open-drain output

(1) During normal operation, the internal 3.3- to 1.8-V voltage regulator of the TUSB3210 is enabled and provides power to the core. To

save power during the suspend mode, the internal regulator is disabled. In this case, the pin becomes an input, and a simple external power source is required to provide power to the core. This source needs to supply a limited amount of power (10 μ A maximum) within the voltage range of 1 to 1.95 V.

(2) All open-drain output pins can sink up to 8 mA.

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37 I/O 1.8 V. When VREN is high, 1.8 V must be applied externally to provide current for the core during

42, 59

63, 64

45, 46, 47, 48,

49, 50

33, 34, 35, 36,

40, 41

I/O DESCRIPTION

suspend.

(2)

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TUSB3210 Universal Serial Bus General-Purpose Device Controller

SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007

Table 1-1. Terminal Functions (continued)

TERMINAL

NAME NO.

P2.[0:7] 22, 23, I/O General-purpose I/O port 2 bits 0–7, Schmitt-trigger input, 100- μ A active pullup, open-drain output

P3.0/S0/RXD 58 I/O P3.0: General-purpose I/O port 3 bit 0, Schmitt-trigger input, 100- μ A active pullup, open-drain output

P3.1/S1/TXD 57 I/O P3.1: General-purpose I/O port 3 bit 1, Schmitt-trigger input, 100- μ A active pullup, open-drain output

P3.2 56 I/O General-purpose I/O port 3 bit 2, Schmitt-trigger input, 100- μ A active pullup, open-drain output

P3.3 55 I/O General-purpose I/O port 3 bit 3, Schmitt-trigger input, 100- μ A active pullup, open-drain output

P3.[4:7] 54, 53, I/O General-purpose I/O port 3 bits 4–7, Schmitt-trigger input, 100- μ A active pullup, open-drain output

PUR 17 O Pullup resistor connection pin (3-state) push-pull CMOS output ( ± 4 mA) RST 13 I Controller master reset signal, Schmitt-trigger input, 100- μ A active pullup RSV 1, 4 Reserved (Do not connect these pins.) S2 8 I General-purpose input, can be used for VID/PID selection under firmware control. This input has no

S3 9 I General-purpose input. This input has no internal pullup; therefore, it must be driven/pulled either low or

SCL 12 O Serial clock I2C; push-pull output SDA 11 I/O Serial data I2C; open-drain output SUSP 16 O Suspend status signal: suspended (HIGH); unsuspended (LOW)

(3)

TEST0

(3)

TEST1 TEST2 20 I Test input2, Schmitt-trigger input, 100- μ A active pullup. This pin is reserved for testing purposes and

VCC 10, 39, — Power supply input, 3.3 V typical

VREN 38 I Voltage regulator enable: enable active-LOW; disable active-HIGH X1 61 I 12-MHz crystal input X2 60 O 12-MHz crystal output

(3) The functions controlled by TEST0 and TEST1 are shown in Table 1-2 . Because these pins have internal pullups, they can be left

unconnected for the default mode.

TEST0 TEST1 Function

0 0 Selects 48-MHz clock input (from an oscillator or other onboard clock source) 0 1 Reserved for testing purposes 1 0 Reserved for testing purposes 1 1 Selects 12-MHz crystal as clock source (default)

25, 26, 27, 28,

29, 30

52, 51

14 I Test input0, Schmitt-trigger input, 100- μ A active pullup 15 I Test input1, Schmitt-trigger input, 100- μ A active pullup

I/O DESCRIPTION

S0: See Section 2.6.5 . RXD: Can be used as a UART interface

S1: See Section 2.6.5 . TXD: Can be used as a UART interface

(2)

only used internally (see Section 2.9.4 )

(2)

support INT1 input, depending on configuration (see Figure 2-5 )

internal pullup; therefore, it must be driven/pulled either low or high and cannot be left unconnected.

high and cannot be left unconnected.

(2)

should be left unconnected.

Table 1-2. Test0/Test1 Functions

(2)

; INT0

; may

(2)

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Universal Serial Bus

General-Purpose Device Controller

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1.5 Revision History

Revision Date Changes

February 2001 Initial release

A February 2003 1. Removed most references to ROM version, including the MCU

Memory Map (ROM Version) figure.

2. Clarified pin names and descriptions for pins 8 (S2), 9 (S3), 21 (GND), 37 (VDD18), 57 (P3.1/S1/TXD), and 58 (P3.0/S0/RXD).

3. Removed NOTE from cover page.

4. Expanded Ordering Information table.

5. Clarified pin functions for pins 14 (TEST0) and 15 (TEST1) (14 & 15) in Terminal Functions table. Simplified Terminal Function table for GPIO ports.

7. Added note on open-drain output pins for Terminal Functions table.

8. Added ET2 information to the 8052 Interrupt Location Map table and further clarified the entire 8052 Interrupt and Status Registers section.

9. Corrected quiescent and suspend current values in Electrical Characteristics table.

B April 2003 1. Grammatical clean-up

2. Clarification on pin 55 (P3.3) and its functionality as INT1.

3. Additional corrections in the 8052 Interrupt and Status Registers section.

C Nov-2003 1. Added USB logo to cover page.

2. Corrected pin 37 (1.8VDD) polarity in Terminal Functions table.

3. Removed note for pin 20 (TEST2) from Terminal Functions table.

4. Removed application diagram Figure 4-4 .

5. Clarified Section 4-2, Reset Timing

D June 2004 1. Corrected description for pin 20 (TEST2).

2. Added description of programmable delay to the P2[7:0], P3.3 Interrupt ( INT1) section.

3. Added delay values for I[3:0] to the INTCFG register description.

E August 2007 1. Deleted reference to 8K × 8 ROM

2. Clarified Section 2.2.2, bit 0.

3. Clarified Section 2.6.5 (VID/PID support)

TUSB3210

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0000

Boot Mode (SDW = 0)

CODE

6K Boot ROM

17FF

1FFF

6K Boot ROM

97FF

8000

FD80

FFFF

FF80

RAM

Read/Write

XDATA

MMR

512 Bytes

RAM

8K Code RAM Read Only

CODE

Normal Mode (SDW = 1)

6K Boot ROM

XDATA

MMR

512 Bytes

RAM

TUSB3210 Universal Serial Bus General-Purpose Device Controller

SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007

2 Functional Description

2.1 MCU Memory Map

Figure 2-1 illustrates the MCU memory map under boot and normal operation. It must be noted that the

internal 256 bytes of IDATA are not shown because it is assumed to be in the standard 8052 location (0000 to 00FF). The shaded areas represent the internal ROM/RAM.

When the SDW bit = 0 (boot mode): The 6K ROM is mapped to address 0000–17FF and is duplicated in location 8000–97FF in code space. The internal 8K RAM is mapped to address range 0000–1FFF in data space. Buffers, MMR and I/O are mapped to address range (FD80–FFFF) in data space.

When the SDW bit = 1 (normal mode): The 6K ROM is mapped to 8000–97FF in code space. The internal 8K RAM is mapped to address range 0000–1FFF in code space. Buffers, MMR, and I/O are mapped to address range FD80–FFFF in data space.

Figure 2-1. MCU Memory Map (TUSB3210)

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2.2 Miscellaneous Registers

2.2.1 TUSB3210 Boot Operation

Because the code space is in RAM (with the exception of the boot ROM), the TUSB3210 firmware must be loaded from an external source. Two options for booting are available: an external serial EEPROM source can be connected to the I2C bus, or the host can be used via the USB. On device reset, the SDW bit (in the ROM register) and the CONT bit in the USB control register (USBCTL) are cleared. This configures the memory space to boot mode (see memory map, Table 2-2 ) and keeps the device disconnected from the host.

The first instruction is fetched from location 0000 (which is in the 6K ROM). The 8K RAM is mapped to XDATA space (location 0000h). The MCU executes a read from an external EEPROM and tests to determine if it contains the code (test for boot signature). If it contains the code, the MCU reads from EEPROM and writes to the 8K RAM in XDATA space. If not, the MCU proceeds to boot from the USB.

Once the code is loaded, the MCU sets SDW to 1. This switches the memory map to normal mode; i.e., the 8K RAM is mapped to code space, and the MCU starts executing from location 0000h. Once the switch is done, the MCU sets CONT to 1 (in USBCTL register) This connects the device to the USB bus, resulting in the normal USB device enumeration.

2.2.2 MCNFG: MCU Configuration Register

TUSB3210

Universal Serial Bus

General-Purpose Device Controller

SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007

This register is used to control the MCU clock rate. (R/O notation indicates read only by the MCU.)

7 6 5 4 3 2 1 0

RSV XINT RSV R3 R2 R1 R0 SDW

R/W R/W R/O R/O R/O R/O R/O R/W

BIT NAME RESET FUNCTION

0 SDW 0 This bit enables/disables boot ROM.

SDW = 0 When clear, the MCU executes from the 6K boot ROM space. The boot ROM appears in

SDW = 1 When set by the MCU, the 6K boot ROM maps to location 8000h, and the 8K RAM is

4–1 R[3:0] No effect These bits reflect the device revision number.

5 RSV 0 Reserved 6 XINT 0 INT1 source control bit

XINT = 0 INT1 is connected to the P3.3 pin and operates as a standard INT1 interrupt. XINT = 1 INT1 is connected to the OR of the port-2 inputs.

7 RSV 0 Reserved

two locations: 0000 and 8000h. The 8K RAM is mapped to XDATA space; therefore, read/write operation is possible. This bit is set by the MCU after the RAM load is completed. The MCU cannot clear this bit. It is cleared on power-up reset or function reset.

mapped to code space, starting at location 0000h. At this point, the MCU executes from RAM, and write operation is disabled (no write operation is possible in code space).

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2.2.3 PUR_n: GPIO Pullup Register for Port n (n = 0 to 3)

PUR_0: GPIO pullup register for port 0 PUR_1: GPIO pullup register for port 1 PUR_2: GPIO pullup register for port 2 PUR_3: GPIO pullup register for port 3

7 6 5 4 3 2 1 0

PORT_n.7 PORT_n.6 PORT_n.5 PORT_n.4 PORT_n.3 PORT_n.2 PORT_n.1 PORT_n.0

R/W R/W R/W R/W R/W R/W R/W R/W

BIT NAME RESET FUNCTION

0–7 PORT_n.N 0 The MCU can write to this register. If the MCU sets this bit to 1, the internal pullup resistor is

2.2.4 INTCFG: Interrupt Configuration

(N = 0 to 7) disconnected from the pin. If the MCU clears this bit to 0, the pullup resistor is connected to the pin.

7 6 5 4 3 2 1 0

RSV RSV RSV RSV I3 I2 I1 I0

R/O R/O R/O R/O R/W R/W R/W R/W

The pullup resistor is connected to the V

power supply.

BIT NAME RESET FUNCTION

0–3 I[3:0] 0010 The MCU can write to this register to set the interrupt delay time for port 2 on the MCU. The value of

4–7 RSV 0 Reserved

the lower nibble represents the delay in ms. Default after reset is 2 ms.

I[3:0] Delay

0000 5 ms 0001 5 ms 0010 2 ms (default) 0011 3 ms 0100 4 ms 0101 5 ms 0110 6 ms 0111 7 ms 1000 8 ms 1001 9 ms 1010 10 ms 1011 5 ms 1100 5 ms 1101 5 ms 1110 5 ms 1111 5 ms

2.2.5 WDCSR: Watchdog Timer, Control, and Status Register

A watchdog timer (WDT) with 1-ms clock is provided. The watchdog timer works only when a USB start-of-frame has been detected by the TUSB3210. If this register is not accessed for a period of 32 ms, the WDT counter resets the MCU (see Figure 2-2 , Reset Diagram). When the IDL bit in PCON is set, the WDT is suspended until an interrupt is detected. At this point, the IDL bit is cleared and the WDT resumes operation. The WDE bit of this register is cleared only on power up or USB reset (if enabled). When the MCU writes a 1 to the WDE bit of this register, the WDT starts running. (W/O notation indicates write only by the MCU.)

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