TEXAS INSTRUMENTS TUSB3210 Technical data

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TUSB3210

Universal Serial Bus General-Purpose Device Controller

Data Manual

August 2007 DIBU

SLLS466F

TUSB3210 Universal Serial Bus General-Purpose Device Controller

SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007

Contents

1 Introduction ......................................................................................................................... 7

1.1 Features ....................................................................................................................... 7

1.2 Description .................................................................................................................... 7

1.3 Ordering Information ........................................................................................................ 7

1.4 Device Information ........................................................................................................... 8

1.5 Revision History ............................................................................................................ 11

2 Functional Description ........................................................................................................ 12

2.1 MCU Memory Map ......................................................................................................... 12

2.2 Miscellaneous Registers .................................................................................................. 13

2.2.1 TUSB3210 Boot Operation ..................................................................................... 13

2.2.2 MCNFG: MCU Configuration Register ........................................................................ 13

2.2.3 PUR_n: GPIO Pullup Register for Port n (n = 0 to 3) ....................................................... 14

2.2.4 INTCFG: Interrupt Configuration .............................................................................. 14

2.2.5 WDCSR: Watchdog Timer, Control, and Status Register .................................................. 14

2.2.6 PCON: Power Control Register (at SFR 87h) ............................................................... 15

2.3 Buffers + I/O RAM Map .................................................................................................... 16

2.4 Endpoint Descriptor Block (EDB-1 to EDB-3) .......................................................................... 18

2.4.1 OEPCNF_n: Output Endpoint Configuration (n = 1 to 3) ................................................... 19

2.4.2 OEPBBAX_n: Output Endpoint X-Buffer Base Address (n = 1 to 3) ..................................... 20

2.4.3 OEPBCTX_n: Output Endpoint X-Byte Count (n = 1 to 3) ................................................. 20

2.4.4 OEPBBAY_n: Output Endpoint Y-Buffer Base Address (n = 1 to 3) ..................................... 20

2.4.5 OEPBCTY_n: Output Endpoint Y-Byte Count (n = 1 to 3) ................................................. 21

2.4.6 OEPSIZXY_n: Output Endpoint X-/Y-Buffer Size (n = 1 to 3) ............................................. 21

2.4.7 IEPCNF_n: Input Endpoint Configuration (n = 1 to 3) ...................................................... 21

2.4.8 IEPBBAX_n: Input Endpoint X-Buffer Base Address (n = 1 to 3) ......................................... 22

2.4.9 IEPBCTX_n: Input Endpoint X-Byte Base Address (n = 1 to 3) ........................................... 22

2.4.10 IEPBBAY_n: Input Endpoint Y-Buffer Base Address (n = 1 to 3) ......................................... 23

2.4.11 IEPBCTY_n: Input Endpoint Y-Byte Count (n = 1 to 3) .................................................... 23

2.4.12 IEPSIZXY_n: Input Endpoint X-/Y-Buffer Size (n = 1 to 3) ................................................ 23

2.5 Endpoint-0 Descriptor Registers ......................................................................................... 24

2.5.1 IEPCNFG_0: Input Endpoint-0 Configuration Register ..................................................... 24

2.5.2 IEPBCNT_0: Input Endpoint-0 Byte-Count Register ........................................................ 25

2.5.3 OEPCNFG_0: Output Endpoint-0 Configuration Register ................................................. 25

2.5.4 OEPBCNT_0: Output Endpoint-0 Byte-Count Register .................................................... 26

2.6 USB Registers .............................................................................................................. 26

2.6.1 FUNADR: Function Address Register ........................................................................ 26

2.6.2 USBSTA: USB Status Register ................................................................................ 27

2.6.3 USBMSK: USB Interrupt Mask Register ...................................................................... 28

2.6.4 USBCTL: USB Control Register ............................................................................... 28

2.6.5 VIDSTA: VID/PID Status Register ............................................................................. 29

2.7 Function Reset and Power-Up Reset Interconnect .................................................................... 29

2.8 Pullup Resistor Connect/Disconnect ..................................................................................... 30

2.9 8052 Interrupt and Status Registers ..................................................................................... 30

2.9.1 8052 Standard Interrupt Enable Register .................................................................... 31

2.9.2 Additional Interrupt Sources .................................................................................... 31

2.9.3 VECINT: Vector Interrupt Register ............................................................................ 32

2.9.4 Logical Interrupt Connection Diagram ( INT0) ................................................................ 33

2.9.5 P2[7:0], P3.3 Interrupt ( INT1) .................................................................................. 33

2.10 I

C Registers ................................................................................................................ 34

2.10.1 I2CSTA: I

2.10.2 I2CADR: I

C Status and Control Register .................................................................... 34

C Address Register ................................................................................ 35

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Universal Serial Bus

General-Purpose Device Controller

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2.10.3 I2CDAI: I

2.10.4 I2CDAO: I

2.11 Read/Write Operations .................................................................................................... 35

2.11.1 Read Operation (Serial EEPROM) ............................................................................ 35

2.11.2 Current Address Read Operation ............................................................................. 36

2.11.3 Sequential Read Operation .................................................................................... 36

2.11.4 Write Operation (Serial EEPROM) ............................................................................ 37

2.11.5 Page Write Operation ........................................................................................... 37

3 Specifications .................................................................................................................... 39

3.1 Absolute Maximum Ratings ............................................................................................... 39

3.2 Commercial Operating Conditions ....................................................................................... 39

3.3 Electrical Characteristics .................................................................................................. 39

4 Application ........................................................................................................................ 40

4.1 Examples .................................................................................................................... 40

4.2 Reset Timing ................................................................................................................ 41

C Data-Input Register .............................................................................. 35

C Data-Output Register ........................................................................... 35

Contents 3

TUSB3210 Universal Serial Bus General-Purpose Device Controller

SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007

List of Figures

1-1 TUSB3210 Block Diagram ........................................................................................................ 8

1-2 Terminal Assignments ............................................................................................................. 9

2-1 MCU Memory Map (TUSB3210) ................................................................................................ 12

2-2 Reset Diagram ..................................................................................................................... 30

2-3 Pullup Resistor Connect/Disconnect Circuit ................................................................................... 30

2-4 Internal Vector Interrupt ( INT0) .................................................................................................. 33

2-5 P2[7:0], P3.3 Input Port Interrupt Generation ................................................................................. 33

4-1 Example LED Connection ........................................................................................................ 40

4-2 Partial Connection Bus Power Mode ........................................................................................... 40

4-3 Upstream Connection (a) Non-Switching Power Mode (b) Switching Power Mode ...................................... 41

4-4 Reset Timing ....................................................................................................................... 42

List of Figures4 Submit Documentation Feedback

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Universal Serial Bus

General-Purpose Device Controller

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List of Tables

1-1 Terminal Functions ................................................................................................................. 9

1-2 Test0/Test1 Functions ............................................................................................................ 10

2-1 XDATA Space ..................................................................................................................... 16

2-2 Memory-Mapped Register Summary (XDATA Range = FF80 → FFFF) .................................................. 17

2-3 EDB and Buffer Allocations in XDATA ......................................................................................... 18

2-4 EDB Entries in RAM (n = 1 to 3) ................................................................................................ 19

2-5 Input/Output EDB-0 Registers ................................................................................................... 24

2-6 External Pin Mapping to S[3:0] in VIDSTA Register .......................................................................... 29

2-7 8052 Interrupt Location Map ..................................................................................................... 30

2-8 Vector Interrupt Values ........................................................................................................... 32

List of Tables 5

TUSB3210 Universal Serial Bus General-Purpose Device Controller

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List of Tables6 Submit Documentation Feedback

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General-Purpose Device Controller

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1 Introduction

1.1 Features

• Multiproduct Support With One Code and One

Chip (up to 16 Products With One Chip)

• Fully Compliant With USB 2.0 Full-Speed

Specifications: TID #40270269

• Supports 12 Mbits/s USB Data Rate (Full

Speed)

• Supports USB Suspend/Resume and

Remote Wake-up Operation

• Integrated 8052 Microcontroller With: – 256 × 8 RAM for Internal Data – 8K × 8 RAM Code Space Available for

Downloadable Firmware From Host or I2C

(1)

Port.

(1) The TUSB3210 has 8K × 8 RAM for development. (2) This is the buffer space for USB packet transactions.

– 512 × 8 Shared RAM Used for Data Buffers and

Endpoint Descriptor Blocks (EDB)

– Four 8052 GPIO Ports, Ports 0,1, 2, and 3

– Master I2C Controller for External Slave

Device Access

– Watchdog Timer

• Operates From a 12-MHz Crystal

• On-Chip PLL Generates 48 MHz

• Supports a Total of 3 Input and 3 Output

(Interrupt, Bulk) Endpoints

• Powerdown Mode

• 64-Pin TQFP Package

• Applications Include Keyboard, Bar Code

Reader, Flash Memory Reader, GeneralPurpose Controller

TUSB3210

Universal Serial Bus

(2)

1.2 Description

The TUSB3210 is a USB-based controller targeted as a general-purpose MCU with GPIO. The TUSB3210 has 8K × 8 RAM space for application development. In addition, the programmability of the TUSB3210 makes it flexible enough to use for various other general USB I/O applications. Unique vendor identification and product identification (VID/PID) can be selected without the use of an external EEPROM. Using a 12-MHz crystal, the onboard oscillator generates the internal system clocks. The device can be programmed via an inter-IC (I2C) serial interface at power on from an EEPROM, or optionally, the application firmware can be downloaded from a host PC via USB. The popular 8052-based microprocessor allows several third-party standard tools to be used for application development. In addition, the vast amounts of application code available in the general market also can be used (this may or may not require some code modification due to hardware variations).

1.3 Ordering Information

PRODUCT PACKAGE

TUSB3210PM PM 0 ° C to 70 ° C TUSB3210PM TUSB3210PM 160-piece tray

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package .

(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com .

Plastic quad

flatpack 64

(1) (2)

PACKAGE PACKAGE ORDERING TRANSPORT

CODE MARKING NUMBER MEDIA

OPERATING

TEMPERATURE

RANGE

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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RSTI

8052 Core

6K × 8

ROM

8K × 8

RAM

512 × 8

SRAM

CPU − I/F Suspend/

Resume

UBM

USB Buffer

Manager

TDM

Control

Logic

USB

SIE

USB TxR

USB-0

PLL

and

Dividers

Clock

Oscillator

12 MHz

2 × 16-Bit

Timers

I2C

Controller

Reset,

Interrupt

and WDT

8 P0.[7:0]

8 P1.[7:0]

8 P2.[7:0]

8 P3.[7:0]

I2C Bus

Port 0

Port 1

Port 2

Port 3

Logic

TUSB3210 Universal Serial Bus General-Purpose Device Controller

SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007

1.4 Device Information

Functional Block Diagram

Figure 1-1. TUSB3210 Block Diagram

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1 2 3

P1.1 P1.0 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 GND P2.1 P2.0 GND TEST2 DM DP PUR

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

P0.6 P0.7 P3.7 P3.6 P3.5 P3.4 P3.3 P3.2

P3.1/S1/TXD

P3.0/S0/RXD

GND

X2 X1

VCC

NC NC

5 6 7 8

P1.3

VREN

47 46 45 44 4348 42

P0.3

P0.2

P0.1

P0.0

GND

P1.7

P1.6

VCC

SDA

SCL

RST

GND

RSV

40 39 3841

9 10 11 12 13

37 36

RSV

1.8VDD

P1.5

35 34 33

14 15 16

TEST0

TEST1

SUSP

P1.4

VCC

P1.2

P0.5

P0.4

PM PACKAGE

(TOP VIEW)

TUSB3210

Universal Serial Bus

General-Purpose Device Controller

SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007

Figure 1-2. Terminal Assignments

Table 1-1. Terminal Functions

TERMINAL

NAME NO.

(1)

1.8VDD

DM 19 I/O Differential data-minus USB DP 18 I/O Differential data-plus USB GND 5, 21 24, — Power supply ground

NC 2, 3, 6, 7, No connection

P0.[0:7] 43, 44, I/O General-purpose I/O port 0 bits 0–7, Schmitt-trigger input, 100- μ A active pullup, open-drain output

P1.[0:7] 31, 32, I/O General-purpose I/O port 1 bits 0–7, Schmitt-trigger input, 100- μ A active pullup, open-drain output

(1) During normal operation, the internal 3.3- to 1.8-V voltage regulator of the TUSB3210 is enabled and provides power to the core. To

save power during the suspend mode, the internal regulator is disabled. In this case, the pin becomes an input, and a simple external power source is required to provide power to the core. This source needs to supply a limited amount of power (10 μ A maximum) within the voltage range of 1 to 1.95 V.

(2) All open-drain output pins can sink up to 8 mA.

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37 I/O 1.8 V. When VREN is high, 1.8 V must be applied externally to provide current for the core during

42, 59

63, 64

45, 46, 47, 48,

49, 50

33, 34, 35, 36,

40, 41

I/O DESCRIPTION

suspend.

(2)

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TUSB3210 Universal Serial Bus General-Purpose Device Controller

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Table 1-1. Terminal Functions (continued)

TERMINAL

NAME NO.

P2.[0:7] 22, 23, I/O General-purpose I/O port 2 bits 0–7, Schmitt-trigger input, 100- μ A active pullup, open-drain output

P3.0/S0/RXD 58 I/O P3.0: General-purpose I/O port 3 bit 0, Schmitt-trigger input, 100- μ A active pullup, open-drain output

P3.1/S1/TXD 57 I/O P3.1: General-purpose I/O port 3 bit 1, Schmitt-trigger input, 100- μ A active pullup, open-drain output

P3.2 56 I/O General-purpose I/O port 3 bit 2, Schmitt-trigger input, 100- μ A active pullup, open-drain output

P3.3 55 I/O General-purpose I/O port 3 bit 3, Schmitt-trigger input, 100- μ A active pullup, open-drain output

P3.[4:7] 54, 53, I/O General-purpose I/O port 3 bits 4–7, Schmitt-trigger input, 100- μ A active pullup, open-drain output

PUR 17 O Pullup resistor connection pin (3-state) push-pull CMOS output ( ± 4 mA) RST 13 I Controller master reset signal, Schmitt-trigger input, 100- μ A active pullup RSV 1, 4 Reserved (Do not connect these pins.) S2 8 I General-purpose input, can be used for VID/PID selection under firmware control. This input has no

S3 9 I General-purpose input. This input has no internal pullup; therefore, it must be driven/pulled either low or

SCL 12 O Serial clock I2C; push-pull output SDA 11 I/O Serial data I2C; open-drain output SUSP 16 O Suspend status signal: suspended (HIGH); unsuspended (LOW)

(3)

TEST0

(3)

TEST1 TEST2 20 I Test input2, Schmitt-trigger input, 100- μ A active pullup. This pin is reserved for testing purposes and

VCC 10, 39, — Power supply input, 3.3 V typical

VREN 38 I Voltage regulator enable: enable active-LOW; disable active-HIGH X1 61 I 12-MHz crystal input X2 60 O 12-MHz crystal output

(3) The functions controlled by TEST0 and TEST1 are shown in Table 1-2 . Because these pins have internal pullups, they can be left

unconnected for the default mode.

TEST0 TEST1 Function

0 0 Selects 48-MHz clock input (from an oscillator or other onboard clock source) 0 1 Reserved for testing purposes 1 0 Reserved for testing purposes 1 1 Selects 12-MHz crystal as clock source (default)

25, 26, 27, 28,

29, 30

52, 51

14 I Test input0, Schmitt-trigger input, 100- μ A active pullup 15 I Test input1, Schmitt-trigger input, 100- μ A active pullup

I/O DESCRIPTION

S0: See Section 2.6.5 . RXD: Can be used as a UART interface

S1: See Section 2.6.5 . TXD: Can be used as a UART interface

(2)

only used internally (see Section 2.9.4 )

(2)

support INT1 input, depending on configuration (see Figure 2-5 )

internal pullup; therefore, it must be driven/pulled either low or high and cannot be left unconnected.

high and cannot be left unconnected.

(2)

should be left unconnected.

Table 1-2. Test0/Test1 Functions

(2)

; INT0

; may

(2)

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General-Purpose Device Controller

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1.5 Revision History

Revision Date Changes

February 2001 Initial release

A February 2003 1. Removed most references to ROM version, including the MCU

Memory Map (ROM Version) figure.

2. Clarified pin names and descriptions for pins 8 (S2), 9 (S3), 21 (GND), 37 (VDD18), 57 (P3.1/S1/TXD), and 58 (P3.0/S0/RXD).

3. Removed NOTE from cover page.

4. Expanded Ordering Information table.

5. Clarified pin functions for pins 14 (TEST0) and 15 (TEST1) (14 & 15) in Terminal Functions table. Simplified Terminal Function table for GPIO ports.

7. Added note on open-drain output pins for Terminal Functions table.

8. Added ET2 information to the 8052 Interrupt Location Map table and further clarified the entire 8052 Interrupt and Status Registers section.

9. Corrected quiescent and suspend current values in Electrical Characteristics table.

B April 2003 1. Grammatical clean-up

2. Clarification on pin 55 (P3.3) and its functionality as INT1.

3. Additional corrections in the 8052 Interrupt and Status Registers section.

C Nov-2003 1. Added USB logo to cover page.

2. Corrected pin 37 (1.8VDD) polarity in Terminal Functions table.

3. Removed note for pin 20 (TEST2) from Terminal Functions table.

4. Removed application diagram Figure 4-4 .

5. Clarified Section 4-2, Reset Timing

D June 2004 1. Corrected description for pin 20 (TEST2).

2. Added description of programmable delay to the P2[7:0], P3.3 Interrupt ( INT1) section.

3. Added delay values for I[3:0] to the INTCFG register description.

E August 2007 1. Deleted reference to 8K × 8 ROM

2. Clarified Section 2.2.2, bit 0.

3. Clarified Section 2.6.5 (VID/PID support)

TUSB3210

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0000

Boot Mode (SDW = 0)

CODE

6K Boot ROM

17FF

1FFF

6K Boot ROM

97FF

8000

FD80

FFFF

FF80

RAM

Read/Write

XDATA

MMR

512 Bytes

RAM

8K Code RAM Read Only

CODE

Normal Mode (SDW = 1)

6K Boot ROM

XDATA

MMR

512 Bytes

RAM

TUSB3210 Universal Serial Bus General-Purpose Device Controller

SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007

2 Functional Description

2.1 MCU Memory Map

Figure 2-1 illustrates the MCU memory map under boot and normal operation. It must be noted that the

internal 256 bytes of IDATA are not shown because it is assumed to be in the standard 8052 location (0000 to 00FF). The shaded areas represent the internal ROM/RAM.

When the SDW bit = 0 (boot mode): The 6K ROM is mapped to address 0000–17FF and is duplicated in location 8000–97FF in code space. The internal 8K RAM is mapped to address range 0000–1FFF in data space. Buffers, MMR and I/O are mapped to address range (FD80–FFFF) in data space.

When the SDW bit = 1 (normal mode): The 6K ROM is mapped to 8000–97FF in code space. The internal 8K RAM is mapped to address range 0000–1FFF in code space. Buffers, MMR, and I/O are mapped to address range FD80–FFFF in data space.

Figure 2-1. MCU Memory Map (TUSB3210)

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2.2 Miscellaneous Registers

2.2.1 TUSB3210 Boot Operation

Because the code space is in RAM (with the exception of the boot ROM), the TUSB3210 firmware must be loaded from an external source. Two options for booting are available: an external serial EEPROM source can be connected to the I2C bus, or the host can be used via the USB. On device reset, the SDW bit (in the ROM register) and the CONT bit in the USB control register (USBCTL) are cleared. This configures the memory space to boot mode (see memory map, Table 2-2 ) and keeps the device disconnected from the host.

The first instruction is fetched from location 0000 (which is in the 6K ROM). The 8K RAM is mapped to XDATA space (location 0000h). The MCU executes a read from an external EEPROM and tests to determine if it contains the code (test for boot signature). If it contains the code, the MCU reads from EEPROM and writes to the 8K RAM in XDATA space. If not, the MCU proceeds to boot from the USB.

Once the code is loaded, the MCU sets SDW to 1. This switches the memory map to normal mode; i.e., the 8K RAM is mapped to code space, and the MCU starts executing from location 0000h. Once the switch is done, the MCU sets CONT to 1 (in USBCTL register) This connects the device to the USB bus, resulting in the normal USB device enumeration.

2.2.2 MCNFG: MCU Configuration Register

TUSB3210

Universal Serial Bus

General-Purpose Device Controller

SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007

This register is used to control the MCU clock rate. (R/O notation indicates read only by the MCU.)

7 6 5 4 3 2 1 0

RSV XINT RSV R3 R2 R1 R0 SDW

R/W R/W R/O R/O R/O R/O R/O R/W

BIT NAME RESET FUNCTION

0 SDW 0 This bit enables/disables boot ROM.

SDW = 0 When clear, the MCU executes from the 6K boot ROM space. The boot ROM appears in

SDW = 1 When set by the MCU, the 6K boot ROM maps to location 8000h, and the 8K RAM is

4–1 R[3:0] No effect These bits reflect the device revision number.

5 RSV 0 Reserved 6 XINT 0 INT1 source control bit

XINT = 0 INT1 is connected to the P3.3 pin and operates as a standard INT1 interrupt. XINT = 1 INT1 is connected to the OR of the port-2 inputs.

7 RSV 0 Reserved

two locations: 0000 and 8000h. The 8K RAM is mapped to XDATA space; therefore, read/write operation is possible. This bit is set by the MCU after the RAM load is completed. The MCU cannot clear this bit. It is cleared on power-up reset or function reset.

mapped to code space, starting at location 0000h. At this point, the MCU executes from RAM, and write operation is disabled (no write operation is possible in code space).

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2.2.3 PUR_n: GPIO Pullup Register for Port n (n = 0 to 3)

PUR_0: GPIO pullup register for port 0 PUR_1: GPIO pullup register for port 1 PUR_2: GPIO pullup register for port 2 PUR_3: GPIO pullup register for port 3

7 6 5 4 3 2 1 0

PORT_n.7 PORT_n.6 PORT_n.5 PORT_n.4 PORT_n.3 PORT_n.2 PORT_n.1 PORT_n.0

R/W R/W R/W R/W R/W R/W R/W R/W

BIT NAME RESET FUNCTION

0–7 PORT_n.N 0 The MCU can write to this register. If the MCU sets this bit to 1, the internal pullup resistor is

2.2.4 INTCFG: Interrupt Configuration

(N = 0 to 7) disconnected from the pin. If the MCU clears this bit to 0, the pullup resistor is connected to the pin.

7 6 5 4 3 2 1 0

RSV RSV RSV RSV I3 I2 I1 I0

R/O R/O R/O R/O R/W R/W R/W R/W

The pullup resistor is connected to the V

power supply.

BIT NAME RESET FUNCTION

0–3 I[3:0] 0010 The MCU can write to this register to set the interrupt delay time for port 2 on the MCU. The value of

4–7 RSV 0 Reserved

the lower nibble represents the delay in ms. Default after reset is 2 ms.

I[3:0] Delay

0000 5 ms 0001 5 ms 0010 2 ms (default) 0011 3 ms 0100 4 ms 0101 5 ms 0110 6 ms 0111 7 ms 1000 8 ms 1001 9 ms 1010 10 ms 1011 5 ms 1100 5 ms 1101 5 ms 1110 5 ms 1111 5 ms

2.2.5 WDCSR: Watchdog Timer, Control, and Status Register

A watchdog timer (WDT) with 1-ms clock is provided. The watchdog timer works only when a USB start-of-frame has been detected by the TUSB3210. If this register is not accessed for a period of 32 ms, the WDT counter resets the MCU (see Figure 2-2 , Reset Diagram). When the IDL bit in PCON is set, the WDT is suspended until an interrupt is detected. At this point, the IDL bit is cleared and the WDT resumes operation. The WDE bit of this register is cleared only on power up or USB reset (if enabled). When the MCU writes a 1 to the WDE bit of this register, the WDT starts running. (W/O notation indicates write only by the MCU.)

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7 6 5 4 3 2 1 0

WDE WDR RSV RSV RSV RSV RSV WDT

R/W R/W R/O R/O R/O R/O R/O W/O

BIT NAME RESET FUNCTION

0 WDT 0 The MCU must write a 1 to this bit to prevent the WDT from resetting the MCU. If the MCU does not write a 1

in a period of 31 ms, the WDT resets the device. Writing a 0 has no effect on the WDT. (WDT is a 5-bit counter using a 1-ms CLK.) This bit is read as 0.

5–1 RSV 0 Reserved = 0

6 WDR 0 Watchdog reset indication bit. This bit indicates if the reset occurred due to power-on reset or watchdog timer

reset. WDR = 0 A power-up or USB reset occurred. WDR = 1 A watchdog time-out reset occurred. To clear this bit, the MCU must write a 1. Writing a 0 has no

effect.

7 WDE 0 Watchdog timer enable.

WDE = 0 Disabled WDE = 1 Enabled

2.2.6 PCON: Power Control Register (at SFR 87h)

TUSB3210

7 6 5 4 3 2 1 0

SMOD RSV RSV RSV GF1 GF0 RSV IDL

R/W R/O R/O R/O R/W R/W R/O R/W

BIT NAME RESET FUNCTION

0 IDL 0 MCU idle mode bit. This bit can be set by the MCU and is cleared only by the INT1 interrupt.

IDL = 0 The MCU is not in idle mode. This bit is cleared by the INT1 interrupt logic when INT1 is

IDL = 1 The MCU is in idle mode and RAM is in low-power mode. The oscillator/APLL is off and the

1 RSV 0 Reserved 3–2 GF[1:0] 00 General-purpose bits. The MCU can write and read them. 6–4 RSV 0 Reserved

7 SMOD 0 Double baud-rate control bit. For more information, see the UART serial interface in the M8052 core

specification.

asserted for at least 400 μ s.

WDT is suspended. When in suspend mode, only INT1 can be used to exit from idle state and generate an interrupt. INT1 must be asserted for at least 400 μ s for the interrupt to be recognized.

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2.3 Buffers + I/O RAM Map

The address range from FD80 to FFFF is reserved for data buffers, setup packet, endpoint descriptor blocks (EDB), and all I/O. RAM space of 512 bytes [FD80–FF7F] is used for EDB and buffers. The FF80–FFFF range is used for memory-mapped registers (MMR). Table 2-1 represents the internal XDATA space allocation.

Table 2-1. XDATA Space

DESCRIPTION ADDRESS RANGE

FFFF

memory-mapped registers ↑

Internal

(MMR)

Endpoint descriptor blocks

(EDB)

Setup packet buffer ↑

Input endpoint-0 buffer ↑

Output endpoint-0 buffer ↑

Data buffers

(368 bytes)

FF80 FF7F

↑

FF08 FF07

FF00 FEFF

512-Byte

RAM

FEF8 FEF7

FEF0 FEEF

↑

FD80

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Table 2-2. Memory-Mapped Register Summary (XDATA Range = FF80 → FFFF)

ADDRESS REGISTER DESCRIPTION

FFFF FUNADR FUNADR: Function address register

FFFE USBSTA USBSTA: USB status register FFFD USBMSK USBMSK: USB interrupt mask register FFFC USBCTL USBCTL: USB control register

↑ RESERVED

FFF6 VIDSTA VIDSTA: VID/PID status register

↑ RESERVED FFF3 I2CADR I2CADR: I2C address register FFF2 I2CDAI I2CDAI: I2C data-input register FFF1 I2CDAO I2CDAO: I2C data-output register FFF0 I2CSTA I2CSTA: I2C status and control register

↑ RESERVED

FF97 PUR3 Port 3 pullup resistor register FF96 PUR2 Port 2 pullup resistor register FF95 PUR1 Port 1 pullup resistor register FF94 PUR0 Port 0 pullup resistor register FF93 WDCSR WDCSR: Watchdog timer, control and status register FF92 VECINT VECINT: Vector interrupt register FF91 RESERVED FF90 MCNFG MCNFG: MCU configuration register

↑ RESERVED

FF84 INTCFG INTCFG: Interrupt delay configuration register FF83 OEPBCNT_0 OEPBCNT_0: Output endpoint-0 byte count register FF82 OEPCNFG_0 OEPCNFG_0: Output endpoint-0 configuration register FF81 IEPBCNT_0 IEPBCNT_0: Input endpoint-0 byte count register FF80 IEPCNFG_0 IEPCNFG_0: Input endpoint-0 configuration register

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2.4 Endpoint Descriptor Block (EDB-1 to EDB-3)

Data transfers between USB, MCU and external devices are defined by an endpoint descriptor block (EDB). Four input and four output EDBs are provided. With the exception of EDB-0 (I/O endpoint 0), all EDBs are located in SRAM as shown in Table 2-3 . Each EDB contains information describing the X and Y buffers. In addition, it provides general status information.

Table 2-3. EDB and Buffer Allocations in XDATA

ADDRESS SIZE DESCRIPTION

FF7F

↑ 32 bytes RESERVED

FF60 FF5F

↑ 8 bytes Input endpoint 3: configuration FF58 FF57

↑ 8 bytes Input endpoint 2: configuration FF50 FF4F

↑ 8 bytes Input endpoint 1: configuration FF48 FF47

↑ 40 bytes RESERVED FF20

FF1F

↑ 8 bytes Output endpoint 3: configuration FF18 FF17

↑ 8 bytes Output endpoint 2: configuration FF10 FF0F

↑ 8 bytes Output endpoint 1: configuration FF08 FF07

↑ 8 bytes Setup packet block FF00 FEFF

↑ 8 bytes Input endpoint 0: buffer FEF8 FEF7

↑ 8 bytes Output endpoint 0: buffer FEF0

FEEF Top of buffer space

↑ 368 bytes Buffer space

FD80 Start of buffer space

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Table 2-4 lists the EDB entries for EDB-1 to EDB-3. EDB-0 registers are described separately.

Table 2-4. EDB Entries in RAM (n = 1 to 3)

Offset ENTRY NAME DESCRIPTION

07 EPSIZXY_n I/O endpoint_n: X/Y buffer size 06 EPBCTY_n I/O endpoint_n: Y byte count 05 EPBBAY_n I/O endpoint_n: Y buffer base address 04 SPARE Not used 03 SPARE Not used 02 EPBCTX_n I/O endpoint_n: X byte count 01 EPBBAX_n I/O endpoint_n: X buffer base address 00 EPCNF_n I/O endpoint_n: configuration

2.4.1 OEPCNF_n: Output Endpoint Configuration (n = 1 to 3)

7 6 5 4 3 2 1 0

UBME ISO TOGLE DBUF STALL USBIE RSV RSV

R/W R/W R/W R/W R/W R/W R/O R/O

TUSB3210

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BIT NAME RESET FUNCTION

1–0 RSV 0 Reserved

2 USBIE x USB interrupt enable on transaction completion. Set/cleared by MCU.

USBIE = 0 No interrupt USBIE = 1 Interrupt on transaction completion

3 STALL 0 USB stall condition indication. Set/cleared by MCU.

STALL = 0 No stall STALL = 1 USB stall condition. If set by MCU, a STALL handshake is initiated and the bit is cleared by

4 DBUF x Double buffer enable. Set/cleared by MCU.

DBUF = 0 Primary buffer only (X-buffer only)

DBUF = 1 Toggle bit selects buffer 5 TOGLE x USB toggle bit. This bit reflects the toggle sequence bit of DATA0, DATA1. 6 ISO x ISO = 0 Non-isochronous transfer. This bit must be cleared by the MCU because only non-isochronous

7 UBME x UBM enable/disable bit. Set/cleared by the MCU.

UBME = 0 UBM cannot use this endpoint.

UBME = 1 UBM can use this endpoint.

the MCU.

transfer is supported.

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2.4.2 OEPBBAX_n: Output Endpoint X-Buffer Base Address (n = 1 to 3)

7 6 5 4 3 2 1 0 A10 A9 A8 A7 A6 A5 A4 A3 R/W R/W R/W R/W R/W R/W R/W R/W

BIT NAME RESET FUNCTION

7–0 A[10:3] x A[10:3] of X-buffer base address (padded with 3 LSB of zeros for a total of 11 bits). This value is set by

2.4.3 OEPBCTX_n: Output Endpoint X-Byte Count (n = 1 to 3)

7 6 5 4 3 2 1 0

NAK C6 C5 C4 C3 C2 C1 C0

R/W R/W R/W R/W R/W R/W R/W R/W

BIT NAME RESET FUNCTION

6–0 C[6:0] x X-Buffer Byte count:

7 NAK x NAK = 0 No valid data in buffer. Ready for host-out

the MCU. UBM or DMA uses this value as the start address of a given transaction. Furthermore, UBM or DMA does not change this value at the end of a transaction.

000 0000b → Count = 0 000 0001b → Count = 1 byte . . . 011 1111b → Count = 63 bytes 100 0000b → Count = 64 bytes Any value ≥ 100 0001b produces unpredictable results.

NAK = 1 Buffer contains a valid packet from host (host-out request is NAK)

2.4.4 OEPBBAY_n: Output Endpoint Y-Buffer Base Address (n = 1 to 3)

7 6 5 4 3 2 1 0 A10 A9 A8 A7 A6 A5 A4 A3 R/W R/W R/W R/W R/W R/W R/W R/W

BIT NAME RESET FUNCTION

7–0 A[10:3] x A[10:3] of Y-buffer base address (padded with 3 LSB of zeros for a total of 11 bits). This value is set by

the MCU. UBM or DMA uses this value as the start address of a given transaction. Furthermore, UBM or DMA does not change this value at the end of a transaction.

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2.4.5 OEPBCTY_n: Output Endpoint Y-Byte Count (n = 1 to 3)

7 6 5 4 3 2 1 0

NAK C6 C5 C4 C3 C2 C1 C0

R/W R/W R/W R/W R/W R/W R/W R/W

BIT NAME RESET FUNCTION

6–0 C[6:0] x Y-Buffer Byte count:

000 0000b → Count = 0 000 0001b → Count = 1 byte . . . 011 1111b → Count = 63 bytes 100 0000b → Count = 64 bytes Any value ≥ 100 0001b produces unpredictable results.

7 NAK x NAK = 0 No valid data in buffer. Ready for host-out

NAK = 1 Buffer contains a valid packet from host (host-out request is NAK).

2.4.6 OEPSIZXY_n: Output Endpoint X-/Y-Buffer Size (n = 1 to 3)

7 6 5 4 3 2 1 0

RSV S6 S5 S4 S3 S2 S1 S0

R/O R/W R/W R/W R/W R/W R/W R/W

TUSB3210

BIT NAME RESET FUNCTION

6–0 S[6:0] x X- and Y-Buffer size:

7 RSV 0 Reserved

000 0000b → Count = 0 000 0001b → Count = 1 byte . . . 011 1111b → Count = 63 bytes 100 0000b → Count = 64 bytes Any value ≥ 100 0001b produces unpredictable results.

2.4.7 IEPCNF_n: Input Endpoint Configuration (n = 1 to 3)

7 6 5 4 3 2 1 0

UBME ISO TOGLE DBUF STALL USBIE RSV RSV

R/W R/W R/W R/W R/W R/W R/O R/O

BIT NAME RESET FUNCTION

1–0 RSV x Reserved = 0

2 USBIE x USB interrupt enable on transaction completion

USBIE = 0 No interrupt USBIE = 1 Interrupt on transaction completion

3 STALL 0 USB stall condition indication. Set by UBM, but can be set/cleared by the MCU.

STALL = 0 No stall STALL = 1 USB stall condition. If set by the MCU, a STALL handshake is initiated and the bit is cleared

4 DBUF x Double buffer enable

DBUF = 0 Primary buffer only (X-buffer only) DBUF = 1 Toggle bit selects buffer

5 TOGLE x USB toggle bit. This bit reflects the toggle sequence bit of DATA0, DATA1.

automatically.

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BIT NAME RESET FUNCTION

6 ISO x ISO = 0 Non-isochronous transfer. This bit must be cleared by the MCU because only

7 UBME x UBM enable/disable bit. Set/cleared by the MCU.

UBME = 0 UBM cannot use this endpoint. UBME = 1 UBM can use this endpoint.

2.4.8 IEPBBAX_n: Input Endpoint X-Buffer Base Address (n = 1 to 3)

7 6 5 4 3 2 1 0 A10 A9 A8 A7 A6 A5 A4 A3 R/W R/W R/W R/W R/W R/W R/W R/W

BIT NAME RESET FUNCTION

7–0 A[10:3] x A[10:3] of X-buffer base address (padded with 3 LSB of zeros for a total of 11 bits). This value is set by

the MCU. UBM or DMA uses this value as the start address of a given transaction. Furthermore, UBM or DMA does not change this value at the end of a transaction.

2.4.9 IEPBCTX_n: Input Endpoint X-Byte Base Address (n = 1 to 3)

7 6 5 4 3 2 1 0

NAK C6 C5 C4 C3 C2 C1 C0

R/W R/W R/W R/W R/W R/W R/W R/W

non-isochronous transfer is supported.

BIT NAME RESET FUNCTION

6–0 C[6:0] x X-Buffer Byte count:

7 NAK x NAK = 0 Buffer contains a valid packet for host-in transaction

000 0000b → Count = 0 000 0001b → Count = 1 byte . . . 011 1111b → Count = 63 bytes 100 0000b → Count = 64 bytes Any value ≥ 100 0001b produces unpredictable results.

NAK = 1 Buffer is empty (host-in request is NAK)

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2.4.10 IEPBBAY_n: Input Endpoint Y-Buffer Base Address (n = 1 to 3)

7 6 5 4 3 2 1 0 A10 A9 A8 A7 A6 A5 A4 A3 R/W R/W R/W R/W R/W R/W R/W R/W

BIT NAME RESET FUNCTION

7–0 A[10:3] x A[10:3] of Y-buffer base address (padded with 3 LSB of zeros for a total of 11 bits). This value is set by

the MCU. UBM or DMA uses this value as the start address of a given transaction. Furthermore, UBM or DMA does not change this value at the end of a transaction.

2.4.11 IEPBCTY_n: Input Endpoint Y-Byte Count (n = 1 to 3)

7 6 5 4 3 2 1 0

NAK C6 C5 C4 C3 C2 C1 C0

R/W R/W R/W R/W R/W R/W R/W R/W

BIT NAME RESET FUNCTION

6–0 C[6:0] x X-BufferByte count:

000 0000b → Count = 0 000 0001b → Count = 1 byte . . . 011 1111b → Count = 63 bytes 100 0000b → Count = 64 bytes Any value ≥ 100 0001b produces unpredictable results.

7 NAK x NAK = 0 Buffer contains a valid packet for host-in transaction

NAK = 1 Buffer is empty (host-in request is NAK)

TUSB3210

2.4.12 IEPSIZXY_n: Input Endpoint X-/Y-Buffer Size (n = 1 to 3)

7 6 5 4 3 2 1 0

RSV S6 S5 S4 S3 S2 S1 S0

R/O R/W R/W R/W R/W R/W R/W R/W

BIT NAME RESET FUNCTION

6–0 S[6:0] x X- and Y-Buffer size:

7 RSV x Reserved

000 0000b → Count = 0 000 0001b → Count = 1 byte . . . 011 1111b → Count = 63 bytes 100 0000b → Count = 64 bytes Any value ≥ 100 0001b produces unpredictable results.

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2.5 Endpoint-0 Descriptor Registers

Unlike EDB-1 to EDB-3, which are defined as memory entries in SRAM, endpoint-0 is described by a set of four registers (two for output and two for input). Table 2-5 defines the registers and their respective addresses used for EDB-0 description. EDB-0 has no Base-Address Register, because these addresses are hardwired to FEF8 and FEF0. Note that the bit positions have been preserved to provide consistency with EDB-n (n = 1 to 3).

Table 2-5. Input/Output EDB-0 Registers

ADDRESS REGISTER NAME DESCRIPTION BASE ADDRESS

FF83 OEPBCNT_0 Output endpoint_0: byte-count register FF82 OEPCNFG_0 Output endpoint_0: configuration register FEF0 FF81 IEPBCNT_0 Input endpoint_0: byte-count register FF80 IEPCNFG_0 Input endpoint_0: configuration register FEF8

2.5.1 IEPCNFG_0: Input Endpoint-0 Configuration Register

7 6 5 4 3 2 1 0

UBME RSV TOGLE RSV STALL USBIE RSV RSV

R/W R/O R/O R/O R/W R/W R/O R/O

BIT NAME RESET FUNCTION

1–0 RSV 0 Reserved

2 USBIE 0 USB interrupt enable on transaction completion. Set/cleared by the MCU

USBIE = 0 No interrupt USBIE = 1 Interrupt on transaction completion

3 STALL 0 USB stall condition indication. Set/cleared by the MCU

STALL = 0 No stall STALL = 1 USB stall condition. If set by the MCU, a STALL handshake is initiated and the bit is cleared

4 RSV 0 Reserved 5 TOGLE 0 USB toggle bit. This bit reflects the toggle sequence bit of DATA0, DATA1. 6 RSV 0 Reserved 7 UBME 0 UBM enable/disable bit. Set/cleared by the MCU

UBME = 0 UBM cannot use this endpoint. UBME = 1 UBM can use this endpoint.

automatically by the next setup transaction.

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2.5.2 IEPBCNT_0: Input Endpoint-0 Byte-Count Register

7 6 5 4 3 2 1 0

NAK RSV RSV RSV C3 C2 C1 C0

R/W R/O R/O R/O R/W R/W R/W R/W

BIT NAME RESET FUNCTION

3–0 C[3:0] 0000 Byte count:

0000b → Count = 0 . . . 0111b → Count = 7 1000b → Count = 8 1001b to 1111b are reserved. (If used, defaults to 8)

6–4 RSV 0 Reserved

7 NAK 1 NAK = 0 Buffer contains a valid packet for host-in transaction.

NAK = 1 Buffer is empty (host-in request is NAK).

2.5.3 OEPCNFG_0: Output Endpoint-0 Configuration Register

TUSB3210

7 6 5 4 3 2 1 0

UBME RSV TOGLE RSV STALL USBIE RSV RSV

R/W R/O R/O R/O R/W R/W R/O R/O

BIT NAME RESET FUNCTION

1–0 RSV 0 Reserved

2 USBIE 0 USB interrupt enable on transaction completion. Set/cleared by the MCU

USBIE = 0 No interrupt USBIE = 1 Interrupt on transaction completion

3 STALL 0 USB stall condition indication. Set/cleared by the MCU

STALL = 0 No stall STALL = 1 USB stall condition. If set by the MCU, a STALL handshake is initiated and the bit is cleared

4 RSV 0 Reserved 5 TOGLE 0 USB toggle bit. This bit reflects the toggle sequence bit of DATA0, DATA1. 6 RSV 0 Reserved 7 UBME 0 UBM enable/disable bit. Set/cleared by the MCU

UBME = 0 UBM cannot use this endpoint. UBME = 1 UBM can use this endpoint.

automatically.

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2.5.4 OEPBCNT_0: Output Endpoint-0 Byte-Count Register

7 6 5 4 3 2 1 0

NAK RSV RSV RSV C3 C2 C1 C0

R/W R/O R/O R/O R/W R/W R/W R/W

BIT NAME RESET FUNCTION

3–0 C[3:0] 0000 Byte count:

6–4 RSV 0 Reserved = 0

7 NAK 1 NAK = 0 No valid data in buffer. Ready for host-out

2.6 USB Registers

0000b → Count = 0 . . . 0111b → Count = 7 1000b → Count = 8 1001b to 1111b are reserved (if used, defaults to 8).

NAK = 1 Buffer contains a valid packet from host (NAK the host).

2.6.1 FUNADR: Function Address Register

This register contains the device function address.

7 6 5 4 3 2 1 0

RSV FA6 FA5 FA4 FA3 FA2 FA1 FA0

R/O R/W R/W R/W R/W R/W R/W R/W

BIT NAME RESET FUNCTION

6–0 FA[6:0] 000 0000 These bits define the current device address assigned to the function. The MCU writes a value to this

7 RSV 0 Reserved

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2.6.2 USBSTA: USB Status Register

All bits in this register are set by the hardware and are cleared by the MCU when writing a 1 to the proper bit location (writing a 0 has no effect). In addition, each bit can generate an interrupt if its corresponding mask bit is set (R/C notation indicates read and clear only by the MCU).

7 6 5 4 3 2 1 0

RSTR SUSR RESR PWOFF PWON SETUP RSV STPOW

R/C R/C R/C R/C R/C R/C R/O R/C

BIT NAME RESET FUNCTION

0 STPOW 0 SETUP overwrite bit. Set by hardware when setup packet is received while there is already a packet in

the setup buffer. STPOW = 0 MCU can clear this bit by writing a 1. (Writing 0 has no effect.)

STPOW = 1 SETUP overwrite 1 RSV 0 Reserved 2 SETUP 0 SETUP transaction received bit. As long as SETUP is 1, IN and OUT on endpoint-0 are NAK regardless

of the value of their real NAK bits.

SETUP = 0 MCU can clear this bit by writing a 1. (Writing 0 has no effect.)

SETUP = 1 SETUP transaction has been received. 3 PWON 0 Power-on request for port 3.This bit indicates if power on to port 3 has been received. This bit generates

a PWON interrupt (if enabled).

PWON = 0 MCU can clear this bit by writing a 1. (Writing 0 has no effect.)

PWON = 1 Power on to port 3 has been received. 4 PWOFF 0 Power-off request for port 3. This bit indicates whether power off to port 3 has been received. This bit

generates a PWOFF interrupt (if enabled).

PWOFF = 0 MCU can clear this bit by writing a 1. (Writing 0 has no effect.)

PWOFF = 1 Power off to port 3 has been received. 5 RESR 0 Function resume request bit

RESR = 0 MCU can clear this bit by writing a 1. (Writing 0 has no effect.)

RESR = 1 Function resume is detected. 6 SUSR 0 Function suspended request bit. This bit is set in response to a global or selective suspend condition.

SUSR = 0 MCU can clear this bit by writing a 1. (Writing 0 has no effect.)

SUSR = 1 Function suspend is detected. 7 RSTR 0 Function reset request bit. This bit is set in response to host initiating a port reset. This bit is not affected

by USB function reset.

RSTR = 0 MCU can clear this bit by writing a 1. (Writing 0 has no effect.)

RSTR = 1 Function reset is detected.

TUSB3210

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2.6.3 USBMSK: USB Interrupt Mask Register

7 6 5 4 3 2 1 0

RSTR SUSR RESR PWOFF PWON SETUP RSV STPOW

R/W R/W R/W R/W R/W R/W R/O R/W

BIT NAME RESET FUNCTION

0 STPOW 0 SETUP overwrite interrupt enable bit

STPOW = 0 STPOW interrupt disabled

STPOW = 1 STPOW interrupt enabled 1 RSV 0 Reserved = 0 2 SETUP 0 SETUP interrupt enable bit

SETUP = 0 SETUP interrupt disabled

SETUP = 1 SETUP interrupt enabled 3 PWON 0 Power-on interrupt enable bit

PWON = 0 PWON interrupt disabled

PWON = 1 PWON interrupt enabled 4 PWOFF 0 Power-off interrupt enable bit

PWOFF = 0 PWOFF interrupt disabled

PWOFF = 1 PWOFF interrupt enabled 5 RESR 0 Function resume interrupt enable

RESR = 0 Function resume interrupt disabled

RESR = 1 Function resume interrupt enabled 6 SUSR 0 Function suspend interrupt enable

SUSR = 0 Function suspend interrupt disabled

SUSR = 1 Function suspend interrupt enabled 7 RSTR 0 Function reset interrupt enable

RSTR = 0 Function reset interrupt disabled

RSTR = 1 Function reset interrupt enabled

2.6.4 USBCTL: USB Control Register

Unlike the other registers, this register is cleared by the power-up-reset signal only. The USB reset cannot reset this register (see the reset diagram in Figure 2-2 ).

7 6 5 4 3 2 1 0

CONT RSV RWUP FRSTE RWE B/S SIR DIR

R/W R/O R/W R/W R/W R/O R/W R/W

BIT NAME RESET FUNCTION

0 DIR 0 As a response to a setup packet, the MCU decodes the request and sets or clears this bit to reflect the

1 SIR 0 SETUP interrupt status bit. This bit is controlled by the MCU to indicate to the hardware when the SETUP

2 B/S 0 Bus-/self-power control bit

Functional Description28 Submit Documentation Feedback

data transfer direction. DIR = 0 USB data OUT transaction (from host to TUSB3210) DIR = 1 USB data IN transaction (from TUSB3210 to host)

interrupt is being served. SIR = 0 SETUP interrupt is not served. MCU clears this bit before exiting the SETUP interrupt

routine.

SIR = 1 SETUP interrupt is in progress. MCU sets this bit when servicing the SETUP interrupt.

B/S = 0 The device is bus-powered. B/S = 1 The device is self-powered.

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BIT NAME RESET FUNCTION

3 RWE 0 Remote wake-up enable bit

RWE = 0 MCU clears this bit when host sends command to clear the feature. RWE = 1 MCU writes 1 to this bit when host sends set device feature command to enable the remote

wake-up feature

4 FRSTE 1 Function reset connection bit. This bit connects/disconnects the USB function reset from the MCU reset.

FRSTE = 0 Function reset is not connected to the MCU reset. FRSTE = 1 Function reset is connected to the MCU reset.

5 RWUP 0 Device remote wake-up request. This bit is set by the MCU and is cleared automatically.

RWUP = 0 Writing a 0 to this bit has no effect.

RWUP = 1 When the MCU writes a 1, a remote wake-up pulse is generated. 6 RSV 0 Reserved 7 CONT 0 Connect/disconnect bit

CONT = 0 Upstream port is disconnected. Pullup disabled

CONT = 1 Upstream port is connected. Pullup enabled

2.6.5 VIDSTA: VID/PID Status Register

This register is used to read the value on four external pins. The firmware can use this value to select one of the vendor identification/product identifications (VID/PID) stored in memory. The TUSB3210 supports up to 16 unique VID/PIDs with application code to support different products. This provides a unique opportunity for original equipment manufacturers (OEMs) to have one device to support up to 16 different product lines by using S0–S3 to select VID/PID and behavioral application code for the selected product.

TUSB3210

7 6 5 4 3 2 1 0

RSV RSV RSV RSV S3 S2 S1 S0

R/O R/O R/O R/O R/O R/O R/O R/O

BIT NAME RESET FUNCTION

3–0 S[3:0] x VID/PID selection bits. These bits reflect the status of the external pins as defined by Table 2-6 . Note that

7–4 RSV 0 Reserved = 0

a pin tied low is reflected as a 0 and a pin tied high is reflected as a 1.

Table 2-6. External Pin Mapping to S[3:0] in VIDSTA Register

VIDSTA REGISTER, S[3:0] COMMENTS

S0 58 P3.0 Dual function P3.0 I/O or S0 input S1 57 P3.1 Dual function P3.1 I/O or S1 input S2 8 S2 S2-pin is input S3 9 S3 S3-pin is input

NO. NAME

2.7 Function Reset and Power-Up Reset Interconnect

Figure 2-2 represents the logical connection of the USB-function-reset ( USBR) and power-up-reset ( RST)

pins. The internal RESET signal is generated from the RST pin ( PURS signal) or from the USB-reset ( USBR signal). The USBR can be enabled or disabled by the FRSTE bit in the USBCTL register (on power up FRSTE = 0). The internal RESET is used to reset all registers and logic, with the exception of the USBCTL and MISCTL registers. The USBCTL and MCU configuration registers (MCNFG) are cleared by the PURS signal only.

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WDT Reset

WDE

PURS

USBCTL Register

MCNFG Register

USB Function Reset

FRSTE

RESET

MCU

All Internal MMR

RST

USBR

D+

TUSB3210

DM0

DP0

CMOS

CONT-BitPUR

1.5 kΩ

15 kΩ15 kΩ

HUB

D-

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2.8 Pullup Resistor Connect/Disconnect

Figure 2-2. Reset Diagram

After reading firmware into RAM, the TUSB3210 can re-enumerate using the new firmware (no need to physically disconnect and re-connect the cable). Figure 2-3 shows an equivalent circuit implementation for Connect and Disconnect from a USB upstream port (also see Figure 4-3 b). When the CONT bit in the USBCTL register is 1, the CMOS driver sources V connect condition to the USB hub (high speed). When the CONT bit is 0, the PUR pin is driven low. In this state, the 1.5-k Ω resistor is connected to GND, resulting in device disconnection state. The PUR driver is a CMOS driver that can provide V

2.9 8052 Interrupt and Status Registers

to the pullup resistor (PUR pin) presenting a normal

– 0.1 V minimum at 8 mA of source current.

Figure 2-3. Pullup Resistor Connect/Disconnect Circuit

All seven 8052-standard interrupt sources are preserved. SIE is the standard interrupt enable register, which controls the seven interrupt sources. All the additional interrupt sources are connected together as an OR to generate INT0. The INT0 signal is provided to interrupt the MCU (see interrupt connection diagram, Figure 2-4 ).

Table 2-7. 8052 Interrupt Location Map

INTERRUPT DESCRIPTION START COMMENTS

SOURCE ADDRESS

ET2 Timer-2 interrupt 002Bh

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General-Purpose Device Controller

SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007

Table 2-7. 8052 Interrupt Location Map (continued)

INTERRUPT DESCRIPTION START COMMENTS

SOURCE ADDRESS

ES UART interrupt 0023h ET1 Timer-1 interrupt 001Bh EX1 Internal INT1 or INT1 0013h Used for P2[7:0] interrupt ET0 Timer-0 interrupt 000Bh

INT0 Internal INT0 0003h Used for all internal peripherals

Reset 0000h

2.9.1 8052 Standard Interrupt Enable Register

7 6 5 4 3 2 1 0

EA RSV ET2 ES ET1 EX1 ET0 INT0

R/W R/O R/O R/W R/W R/W R/W R/W

BIT NAME RESET FUNCTION

0 INT0 0 Enable or disable interrupt-0

INT0 = 0 Interrupt-0 is disabled. INT0 = 1 Interrupt-0 is enabled.

1 ET0 0 Enable or disable timer-0 interrupt

ET0 = 0 Timer-0 interrupt is disabled. ET0 = 1 Timer-0 interrupt is enabled.

2 EX1 0 Enable or disable interrupt-1

EX1 = 0 Interrupt-1 is disabled. EX1 = 1 Interrupt-1 is enabled.

3 ET1 0 Enable or disable timer-1 interrupt

ET1 = 0 Timer-1 interrupt is disabled. ET1 = 1 Timer-1 interrupt is enabled.

4 ES 0 Enable or disable serial port interrupts

ES = 0 Serial port interrupt is disabled. ES = 1 Serial port interrupt is enabled.

5 ET2 0 Enable or disable timer-2 interrupt

ET1 = 0 Timer-2 interrupt is disabled.

ET1 = 1 Timer-2 interrupt is enabled. 6 RSV 0 Reserved 7 EA 0 Enable or disable all interrupts (global disable)

EA = 0 Disable all interrupts.

EA = 1 Each interrupt source is individually controlled.

TUSB3210

Universal Serial Bus

2.9.2 Additional Interrupt Sources

All nonstandard 8052 interrupts (USB, I2C, etc.) are connected as an OR to generate an internal INT0. It must be noted that the external INT0 and INT1 are not used. Furthermore, INT0 must be programmed as an active-low level interrupt (not edge-triggered). A vector interrupt register is provided to identify all interrupt sources (see vector interrupt register definition, Section 2.9.3 ). Up to 64 interrupt vectors are provided. It is the responsibility of the MCU to read the vector and dispatch the proper interrupt routine.

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2.9.3 VECINT: Vector Interrupt Register

This register contains a vector value identifying the internal interrupt source that trapped to location 0003h. Writing any value to this register removes the vector and updates the next vector value (if another interrupt is pending). Note that the vector value is offset. Therefore, its value is in increments of two (bit 0 is set to

0). When no interrupt is pending, the vector is set to 00h. Table 2-8 is a table of the vector interrupt values. As shown, the interrupt vector is divided into two fields; I[2:0] and G[3:0]. The I-field defines the interrupt source within a group (on a first-come, first-served basis) and the G-field defines the group number. Group G0 is the lowest and G15 is the highest priority.

7 6 5 4 3 2 1 0

G3 G2 G1 G0 I2 I1 I0 RSV

R/W R/W R/W R/W R/W R/W R/W R/O

BIT NAME RESET FUNCTION

0 RSV 0 Reserved

3–1 I[2:0] 000 This field defines the interrupt source in a given group. See Table 2-8 : Vector Interrupt Values. Bit 0 is

7–4 G[3:0] 0000 This field defines the interrupt group. I[2:0] and G[3:0] combine to produce the actual interrupt vector.

always 0; therefore, vector values are offset by two.

Table 2-8. Vector Interrupt Values

G[3:0] (Hex) I[2:0] (Hex) VECTOR (Hex) INTERRUPT SOURCE

0 0 00 No interrupt 1 0 10 RESERVED 1 1 12 Output endpoint-1 1 2 14 Output endpoint-2 1 3 16 Output endpoint-3 1 4–7 18–1E RESERVED 2 0 20 RESERVED 2 1 22 Input endpoint-1 2 2 24 Input endpoint-2 2 3 26 Input endpoint-3 2 4–7 28–2E RESERVED 3 0 30 STPOW packet received 3 1 32 SETUP packet received 3 2 34 PWON interrupt 3 3 36 PWOFF interrupt 3 4 38 RESR interrupt 3 5 3A SUSR interrupt 3 6 3C RSTR interrupt 3 7 3E RESERVED 4 0 40 I2C TXE interrupt 4 1 42 I2C RXF interrupt 4 2 44 Input endpoint-0 4 3 46 Output endpoint-0 4 4–7 48–4E RESERVED

5–F X 90–FE RESERVED

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2.9.4 Logical Interrupt Connection Diagram ( INT0)

Interrupts

INT0

Priority

Encoder

Vector

Interrupt Sources

46h

12h

Suspend/

Resume

Logic

P2[7:0]

P3.3

INT1

XINT Bit

Programmable

Delay

Figure 2-4 represents the logical connection of the interrupt sources and the relation of the logical

connection with INT0. The priority encoder generates an 8-bit vector, corresponding to 64 interrupt sources (not all are used). The interrupt priorities are hard wired. Vector 46h is the highest and 12h is the lowest. Table 2-8 lists the interrupt source for each valid interrupt vector.

Figure 2-4. Internal Vector Interrupt ( INT0)

TUSB3210

Universal Serial Bus

General-Purpose Device Controller

SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007

2.9.5 P2[7:0], P3.3 Interrupt ( INT1)

Figure 2-5 illustrates the conceptual port-2 interrupt. All port-2 input signals are connected in a logical OR

to generate the INT1 interrupt. Note that the inputs are active-low and INT1 is programmed as a level-triggered interrupt. In addition, INT1 is connected to the suspend/resume logic for remote wake-up support. As illustrated, the XINT bit in the MCU configuration register (MCNFG) is used to select the EX1 interrupt source. When XINT = 0, P3.3 is the source, and when XINT = 1, P2[7:0] is the source. The programmable delay is determined by the setting of I[3:0] in the INTCFG register.

Figure 2-5. P2[7:0], P3.3 Input Port Interrupt Generation

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TUSB3210 Universal Serial Bus General-Purpose Device Controller

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2.10 I2C Registers

The TUSB3210 only supports a master-slave relationship; therefore, it does not support bus arbitration.

2.10.1 I2CSTA: I2C Status and Control Register

This register is used to control the stop condition for read and write operations. In addition, it provides transmitter and receiver handshake signals with their respective interrupt enable bits.

7 6 5 4 3 2 1 0

RXF RIE ERR 1/4 TXE TIE SRD SWR

R/C R/W R/C R/W R/C R/W R/W R/W

BIT NAME RESET FUNCTION

0 SWR 0 Stop write condition. This bit defines whether the I2C controller generates a stop condition when data from

1 SRD 0 Stop read condition. This bit defines whether the I2C controller generates a stop condition when data is

2 TIE 0 I2C transmitter empty interrupt enable

3 TXE 1 I2C transmitter empty. This bit indicates that data can be written to the transmitter. It can be used for

4 1/4 0 Bus speed selection

5 ERR 0 Bus error condition. This bit is set by the hardware when the device does not respond. It is cleared by the

6 RIE 0 I2C receiver ready interrupt enable

7 RXF 0 I2C receiver full. This bit indicates that the receiver contains new data. It can be used for polling or it can

the I2CDAO register is transmitted to an external device. SWR = 0 Stop condition is not generated when data from the I2CDAO register is shifted out to an

external device.

SWR = 1 Stop condition is generated when data from the I2CDAO register is shifted out to an external

device.

received and loaded into I2CDAI register. SRD = 0 Stop condition is not generated when data from SDA line is shifted into the I2CDAI register. SRD = 1 Stop condition is generated when data from SDA line is shifted into the I2CDAI register.

TIE = 0 Interrupt disabled TIE = 1 Interrupt enabled

polling or it can generate an interrupt. TXE = 0 Transmitter is full. This bit is cleared when the MCU writes a byte to the I2CDAO register. TXE = 1 Transmitter is empty. The I2C controller sets this bit when the content of the I2CDAO register is

copied to the SDA shift register.

1/4 = 0 100-kHz bus speed 1/4 = 1 400-kHz bus speed

MCU. ERR = 0 No bus error ERR = 1 Bus error condition has been detected. Clears when the MCU writes a 1. Writing a 0 has no

effect.

RIE = 0 Interrupt disabled RIE = 1 Interrupt enabled

generate an interrupt. RXF = 0 Receiver is empty. This bit is cleared when the MCU reads the I2CDAI register. RXF = 1 Receiver contains new data. This bit is set by the I2C controller when the received serial data

has been loaded into the I2CDAI register.

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General-Purpose Device Controller

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2.10.2 I2CADR: I2C Address Register

This register holds the device address and the read/write command bit.

7 6 5 4 3 2 1 0

A6 A5 A4 A3 A2 A1 A0 R/W

R/W R/W R/W R/W R/W R/W R/W R/W

BIT NAME RESET FUNCTION

0 R/W 0 Read/write command bit

R/W = 0 Write operation

R/W = 1 Read operation

7–1 A[6:0] 000 0000 Seven address bits for device addressing

2.10.3 I2CDAI: I2C Data-Input Register

This register holds the received data from an external device.

7 6 5 4 3 2 1 0

D7 D6 D5 D4 D3 D2 D1 D0

R/O R/O R/O R/O R/O R/O R/O R/O

TUSB3210

Universal Serial Bus

BIT NAME RESET FUNCTION

7–0 D[7:0] 0 8-bit input data from an I2C device

2.10.4 I2CDAO: I2C Data-Output Register

This register holds the data to be transmitted to an external device. Writing to this register starts the transfer on the SDA line.

7 6 5 4 3 2 1 0

D7 D6 D5 D4 D3 D2 D1 D0

R/W R/W R/W R/W R/W R/W R/W R/W

BIT NAME RESET FUNCTION

7–0 D[7:0] 0 8-bit output data to an I2C device

2.11 Read/Write Operations

2.11.1 Read Operation (Serial EEPROM)

A serial read requires a dummy byte write sequence to load in the 16-bit data word address. Once the device address word and data address word are clocked out and acknowledged by the device, the MCU starts a current address sequence. The following describes the sequence of events to accomplish this transaction:

Device Address + EEPROM [High Byte]

1. The MCU sets I2CSTA[SRD] = 0 .This prevents the I2C controller from generating a stop condition after the content of the I2CDAI register is received.

2. The MCU sets I2CSTA[SWR] = 0. This prevents the I2C controller from generating a stop condition after the content of the I2CDAO register is transmitted.

3. The MCU writes the device address (R/W bit = 0) to the I2CADR register (write operation).

4. The MCU writes the high byte of the EEPROM address into the I2CDAO register, starting the transfer on the SDA line.

5. The TXE bit in I2CSTA is cleared, indicating busy.

6. The content of the I2CADR register is transmitted to the EEPROM (preceded by start condition on

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TUSB3210 Universal Serial Bus General-Purpose Device Controller

SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007

SDA).

7. The content of the I2CDAO register is transmitted to the EEPROM (EEPROM address).

8. The TXE bit in I2CSTA is set, and interrupts the MCU, indicating that the I2CDAO register has been transmitted.

9. No stop condition is generated.

EEPROM [Low Byte]

1. The MCU writes the low byte of the EEPROM address into the I2CDAO register.

2. The TXE bit in I2CSTA is cleared, indicating busy.

3. The content of the I2CDAO register is transmitted to the device (EEPROM address).

4. The TXE bit in I2CSTA is set, and interrupts the MCU, indicating that the I2CDAO register has been transmitted.

5. This completes the dummy write operation. At this point, the EEPROM address is set and the MCU can do a single or a sequential read operation.

2.11.2 Current Address Read Operation

Once the EEPROM address is set, the MCU can read a single byte by executing the following steps:

1. The MCU sets I2CSTA[SRD] = 1, forcing the I2C controller to generate a stop condition after the I2CDAI register is received.

2. The MCU writes the device address (R/W bit = 1) to the I2CADR register (read operation).

3. The MCU writes a dummy byte to the I2CDAO register, starting the transfer on the SDA line.

4. The RXF bit in I2CSTA is cleared.

5. The content of the I2CADR register is transmitted to the device, preceded by a start condition on SDA.

6. Data from the EEPROM is latched into the I2CDAI register (stop condition is transmitted).

7. The RXF bit in I2CSTA is set, and interrupts the MCU, indicating that the data is available.

8. The MCU reads the I2CDAI register. This clears the RXF bit (I2CSTA[RXF] = 0).

2.11.3 Sequential Read Operation

Once the EEPROM address is set, the MCU can execute a sequential read operation by executing the following steps (Note: this example illustrates a 32-byte sequential read):

1. Device Address a. The MCU sets I2CSTA[SRD] = 0. This prevents the I2C controller from generating a stop condition

after the I2CDAI register is received. b. The MCU writes the device address (R/W bit = 1) to the I2CADR register (read operation). c. The MCU writes a dummy byte to the I2CDAO register, starting the transfer on the SDA line. d. The RXF bit in I2CSTA is cleared. e. The content of the I2CADR register is transmitted to the device (preceded by a start condition on

SDA).

2. N-Byte Read (31 bytes) a. Data from the device is latched into the I2CDAI register (stop condition is not transmitted).

b. The RXF bit in I2CSTA is set and interrupts the MCU, indicating that data is available. c. The MCU reads the I2CDAI register, clearing the RXF bit (I2CSTA[RXF] = 0). d. This operation repeats 31 times.

3. Last-Byte Read (byte no. 32) a. The MCU sets I2CSTA[SRD] = 1. This forces the I2C controller to generate a stop condition after

the I2CDAI register is received. b. Data from the device is latched into the I2CDAI register (stop condition is transmitted). c. The RXF bit in I2CSTA is set and interrupts the MCU, indicating that data is available.

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d. The MCU reads the I2CDAI register, clearing the RXF bit (I2CSTA[RXF] = 0).

2.11.4 Write Operation (Serial EEPROM)

The byte write operation involves three phases: 1) device address + EEPROM [high byte] phase, 2) EEPROM [low byte] phase, and 3) EEPROM [DATA]. The following describes the sequence of events to accomplish the byte write transaction:

Device Address + EEPROM [High Byte]

1. The MCU sets I2CSTA[SWR] = 0. This prevents the I2C controller from generating a stop condition after the content of the I2CDAO register is transmitted.

2. The MCU writes the device address (R/W bit = 0) to the I2CADR register (write operation).

3. The MCU writes the high byte of the EEPROM address into the I2CDAO register, starting the transfer on the SDA line.

4. The TXE bit in I2CSTA is cleared, indicating busy.

5. The content of the I2CADR register is transmitted to the device (preceded by a start condition on SDA).

6. The content of the I2CDAO register is transmitted to the device (EEPROM high-address).

7. The TXE bit in I2CSTA is set and interrupts the MCU, indicating that the I2CDAO register has been transmitted.

TUSB3210

Universal Serial Bus

General-Purpose Device Controller

SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007

EEPROM [Low Byte]

1. The MCU writes the low byte of the EEPROM address into the I2CDAO register.

2. The TXE bit in I2CSTA is cleared, indicating busy.

3. The content of the I2CDAO register is transmitted to the device (EEPROM address).

4. The TXE bit in I2CSTA is set and interrupts the MCU, indicating that the I2CDAO register has been

EEPROM [DATA]

1. The MCU sets I2CSTA[SWR] = 1. This forces the I2C controller to generate a stop condition after the

2. The MCU writes the DATA to be written to the EEPROM into the I2CDAO register.

3. The TXE bit in I2CSTA is cleared, indicating busy.

4. The content of the I2CDAO register is transmitted to the device (EEPROM data).

5. The TXE bit in I2CSTA is set and interrupts the MCU, indicating that the I2CDAO register has been

6. The I2C controller generates a stop condition after the content of the I2CDAO register is transmitted.

2.11.5 Page Write Operation

The page write operation is initiated the same way as byte write, with the exception that a stop condition is not generated after the first EEPROM [DATA] is transmitted. The following describes the sequence of writing 32 bytes in page mode:

transmitted.

content of the I2CDAO register is transmitted.

transmitted.

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Device Address + EEPROM [High Byte]

1. The MCU sets I2CSTA[SWR] = 0. This prevents the I2C controller from generating a stop condition after the content of the I2CDAO register is transmitted.

2. The MCU writes the device address (R/W bit = 0) to the I2CADR register (write operation).

3. The MCU writes the high byte of the EEPROM address into the I2CDAO register.

4. The TXE bit in I2CSTA is cleared, indicating busy.

5. The content of the I2CADR register is transmitted to the device (preceded by a start condition on SDA).

6. The content of the I2CDAO register is transmitted to the device (EEPROM address).

7. The TXE bit in I2CSTA is set and interrupts the MCU, indicating that the I2CDAO register has been sent.

EEPROM [Low Byte]

1. The MCU writes the low byte of the EEPROM address into the I2CDAO register.

2. The TXE bit in I2CSTA is cleared, indicating busy.

3. The content of the I2CDAO register is transmitted to the device (EEPROM address).

4. The TXE bit in I2CSTA is set and interrupts the MCU, indicating that the I2CDAO register has been sent.

31 Bytes EEPROM [DATA]

1. The MCU writes the DATA to be written to the EEPROM into the I2CDAO register.

2. The TXE bit in I2CSTA is cleared, indicating busy.

3. The content of the I2CDAO register is transmitted to the device (EEPROM data).

4. The TXE bit in I2CSTA is set and interrupts the MCU, indicating that the I2CDAO register has been sent.

5. This operation repeats 31 times.

Last Byte EEPROM [DATA]

1. The MCU sets I2CSTA[SWR] = 1. This forces the I2C controller to generate a stop condition after the content of the I2CDAO register is transmitted.

2. The MCU writes the last DATA byte to be written to the EEPROM into the I2CDAO register.

3. The TXE bit in I2CSTA is cleared, indicating busy.

4. The content of the I2CDAO register is transmitted to the EEPROM (EEPROM data).

5. The TXE bit in I2CSTA is set and interrupts the MCU, indicating that the I2CDAO register has been sent.

6. The I2C controller generates a stop condition after the content of the I2CDAO register is transmitted, terminating the 32-byte page write operation.

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TUSB3210

Universal Serial Bus

General-Purpose Device Controller

SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007

3 Specifications

3.1 Absolute Maximum Ratings

(1)

over operating free-air temperature range (unless otherwise noted)

MIN MAX UNIT

Supply voltage –0.5 4 V Input voltage –0.5 V Output voltage –0.5 V

+ 0.5 V

Input clamp current ± 20 mA Output clamp current ± 20 mA Storage temperature –65 150 ° C

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

3.2 Commercial Operating Conditions

PARAMETER MIN NOM MAX UNIT

Supply voltage 3 3.3 3.6 V

Input voltage 0 V

High-level input voltage 2 V

Low-level input voltage 0 0.8 V

Operating temperature 0 70 ° C

3.3 Electrical Characteristics

TA= 25 ° C, V

IT+

IT–

hys

CCx

CCx1.8

= 3.3 V ± 0.3 V, GND = 0 V

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT

High-level output voltage IOH= –4 mA V

– 0.5 V

Low-level output voltage IOL= 4 mA 0.5 V Positive input threshold voltage VI= V Negative input threshold voltage VI= V Hysteresis (V

– V

IT+

) VI= V

IT–

High-level input current VI= V Low-level input current VI= V Output leakage current (Hi-Z) VI= V

IH IL IH IH IL

or V

0.8 V 1 V

2 V

± 1 μ A ± 1 μ A

10 μ A Input capacitance 5 pF Output capacitance 7 pF Quiescent 25 45 mA Suspend 45 μ A Suspend 1.8 VDD 1 μ A

Submit Documentation Feedback Specifications 39

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TUSB3210

P3.2

P3.3

P3.4

P3.5

EPROM

1.8VDD VREN

SUSP

X1 X2

SCL

SDA

TUSB3210

TPS76333

5 V

3.3 V

TUSB3210 Universal Serial Bus General-Purpose Device Controller

SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007

4 Application

4.1 Examples

Figure 4-1 illustrates the port-3 pins that are assigned to drive the four example LEDs. For the connection

example shown, P3[5:2] can sink up to 8 mA each (open-drain outputs). Figure 4-2 illustrates the partial connection bus power mode. Figure 4-3 shows the USB upstream connection, and Figure 4-4 illustrates the downstream connection (only one port shown).

Figure 4-1. Example LED Connection

Figure 4-2. Partial Connection Bus Power Mode

Application 40 Submit Documentation Feedback

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3.3 V

1.5 kΩ

D+ D-

DP0 DM0

1.5 kΩ

D+

D-

DP0 DM0

Bus PWR

(5 V)

PUR

(a) (b)

4.2 Reset Timing

TUSB3210

Universal Serial Bus

General-Purpose Device Controller

SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007

Figure 4-3. Upstream Connection (a) Non-Switching Power Mode (b) Switching Power Mode

There are three requirements for the reset signal timing. First, the minimum reset pulse duration is 100 μ s. At power up, this time is measured from the time the power ramps up to 90% of the nominal V reset signal exceeds 1.2 V. The second requirement is that the clock must be valid during the last 60 μ s of the reset window. The third requirement is that, according to the USB specification, the device must be ready to respond to the host within 100 ms. This means that within the 100-ms window, the device must come out of reset, load any pertinent data from the I2C EEPROM device, and transfer execution to the application firmware if any is present. Because the latter two events can require significant time, the amount of which can change from system to system, TI recommends having the device come out of reset within 30 ms, leaving 70 ms for the other events to complete. This means the reset signal should rise to

1.8 V within 30 ms.

until the

These requirements are depicted in Figure 4-4 . Notice that when using a 12-MHz crystal or the 48-MHz oscillator, the clock signal may take several milliseconds to ramp up and become valid after power up. Therefore, the reset window may need to be elongated up to 10 ms or more to ensure that there is a 60- μ s overlap with a valid clock.

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CLK

RESET

90%

3.3 V

1.2 V

0 V

>60 µs

100 µs < RESET TIME

1.8 V

RESET TIME < 30 ms

TUSB3210 Universal Serial Bus General-Purpose Device Controller

SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007

Figure 4-4. Reset Timing

Application 42 Submit Documentation Feedback

PACKAGE OPTION ADDENDUM

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27-Jul-2007

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package

Drawing

Pins Package

Qty

Eco Plan

TUSB3210PM ACTIVE LQFP PM 64 160 Green (RoHS &

no Sb/Br)

TUSB3210PMG4 ACTIVE LQFP PM 64 160 Green (RoHS &

no Sb/Br)

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-3-260C-168 HR

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

MECHANICAL DATA

MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996

PM (S-PQFP-G64) PLASTIC QUAD FLATPACK

0,50

0,27 0,17

7,50 TYP

10,20

9,80

12,20

11,80

0,08

0,05 MIN

0,13 NOM

Gage Plane

0,25

0°–7°

1,45 1,35

1,60 MAX

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 D. May also be thermally enhanced plastic with leads connected to the die pads.

0,75 0,45

Seating Plane

0,08

4040152/C 11/96

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

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TEXAS INSTRUMENTS TUSB3210 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

1 Introduction

1.1 Features

1.2 Description

1.3 Ordering Information

1.4 Device Information

1.5 Revision History

2 Functional Description

2.1 MCU Memory Map

2.2 Miscellaneous Registers

2.2.1 TUSB3210 Boot Operation

2.2.2 MCNFG: MCU Configuration Register

2.2.3 PUR_n: GPIO Pullup Register for Port n (n = 0 to 3)

2.2.4 INTCFG: Interrupt Configuration

2.2.5 WDCSR: Watchdog Timer, Control, and Status Register

2.2.6 PCON: Power Control Register (at SFR 87h)

2.3 Buffers + I/O RAM Map

2.4 Endpoint Descriptor Block (EDB-1 to EDB-3)

2.4.1 OEPCNF_n: Output Endpoint Configuration (n = 1 to 3)

2.4.2 OEPBBAX_n: Output Endpoint X-Buffer Base Address (n = 1 to 3)

2.4.3 OEPBCTX_n: Output Endpoint X-Byte Count (n = 1 to 3)

2.4.4 OEPBBAY_n: Output Endpoint Y-Buffer Base Address (n = 1 to 3)

2.4.5 OEPBCTY_n: Output Endpoint Y-Byte Count (n = 1 to 3)

2.4.6 OEPSIZXY_n: Output Endpoint X-/Y-Buffer Size (n = 1 to 3)

2.4.7 IEPCNF_n: Input Endpoint Configuration (n = 1 to 3)

2.4.8 IEPBBAX_n: Input Endpoint X-Buffer Base Address (n = 1 to 3)

2.4.9 IEPBCTX_n: Input Endpoint X-Byte Base Address (n = 1 to 3)

2.4.10 IEPBBAY_n: Input Endpoint Y-Buffer Base Address (n = 1 to 3)

2.4.11 IEPBCTY_n: Input Endpoint Y-Byte Count (n = 1 to 3)

2.4.12 IEPSIZXY_n: Input Endpoint X-/Y-Buffer Size (n = 1 to 3)

2.5 Endpoint-0 Descriptor Registers

2.5.1 IEPCNFG_0: Input Endpoint-0 Configuration Register

2.5.2 IEPBCNT_0: Input Endpoint-0 Byte-Count Register

2.5.3 OEPCNFG_0: Output Endpoint-0 Configuration Register

2.5.4 OEPBCNT_0: Output Endpoint-0 Byte-Count Register

2.6 USB Registers

2.6.1 FUNADR: Function Address Register

2.6.2 USBSTA: USB Status Register

2.6.3 USBMSK: USB Interrupt Mask Register

2.6.4 USBCTL: USB Control Register

2.6.5 VIDSTA: VID/PID Status Register

2.7 Function Reset and Power-Up Reset Interconnect

2.8 Pullup Resistor Connect/Disconnect

2.9 8052 Interrupt and Status Registers

2.9.1 8052 Standard Interrupt Enable Register

2.9.2 Additional Interrupt Sources

2.9.3 VECINT: Vector Interrupt Register

2.9.4 Logical Interrupt Connection Diagram ( INT0)

2.9.5 P2[7:0], P3.3 Interrupt ( INT1)

2.10 I2C Registers

2.10.1 I2CSTA: I2C Status and Control Register

2.10.2 I2CADR: I2C Address Register

2.10.3 I2CDAI: I2C Data-Input Register

2.10.4 I2CDAO: I2C Data-Output Register

2.11 Read/Write Operations

2.11.1 Read Operation (Serial EEPROM)

2.11.2 Current Address Read Operation

2.11.3 Sequential Read Operation

2.11.4 Write Operation (Serial EEPROM)

2.11.5 Page Write Operation

3 Specifications

3.1 Absolute Maximum Ratings

3.2 Commercial Operating Conditions

3.3 Electrical Characteristics

4 Application

4.1 Examples

4.2 Reset Timing