TEXAS INSTRUMENTS TUSB3200A Technical data

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Data Manual

2001 Digital Speaker Department

SLES018

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Contents

Section Title Page

1 Introduction 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1 Features 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 Functional Block Diagram 1–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 Terminal Assignments – Normal Mode 1–4. . . . . . . . . . . . . . . . . . . . . . . . .

1.4 Terminal Assignments – External MCU Mode 1–4. . . . . . . . . . . . . . . . . . .

1.5 Ordering Information 1–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.6 Terminal Functions – Normal Mode 1–5. . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.7 Terminal Functions – External MCU Mode 1–7. . . . . . . . . . . . . . . . . . . . . .

1.8 Device Operation Modes 1–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.9 Terminal Assignments for Codec Port Interface Modes 1–9. . . . . . . . . . .

2 Description 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 Architectural Overview 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.1 Oscillator and PLL 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.2 Clock Generator and Sequencer Logic 2–1. . . . . . . . . . . . . . . .

2.1.3 Adaptive Clock Generator (ACG) 2–1. . . . . . . . . . . . . . . . . . . . .

2.1.4 USB Transceiver 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.5 USB Serial Interface Engine (SIE) 2–1. . . . . . . . . . . . . . . . . . . .

2.1.6 USB Buffer Manager (UBM) 2–2. . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.7 USB Frame Timer 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.8 USB Suspend and Resume Logic 2–2. . . . . . . . . . . . . . . . . . . . .

2.1.9 MCU Core 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.10 MCU Memory 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.11 USB Endpoint Configuration Blocks and

Endpoint Buffer Space 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.12 DMA Controller 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.13 Codec Port Interface 2–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.14 I

2.1.15 Pulse Width Modulation (PWM) Output 2–3. . . . . . . . . . . . . . . .

2.1.16 General-Purpose IO Ports (GPIO) 2–3. . . . . . . . . . . . . . . . . . . .

2.1.17 Interrupt Logic 2–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.18 Reset Logic 2–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 Device Operation 2–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.1 Clock Generation 2–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.2 Device Initialization 2–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.3 USB Enumeration 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.4 USB Reset 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.5 USB Suspend and Resume Modes 2–6. . . . . . . . . . . . . . . . . . .

C Interface 2–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

iii

2.2.6 Power Supply Sequencing 2–6. . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.7 USB Transfers 2–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.8 Adaptive Clock Generator (ACG) 2–14. . . . . . . . . . . . . . . . . . . . .

2.2.9 Microcontroller Unit 2–16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.10 External MCU Mode Operation 2–16. . . . . . . . . . . . . . . . . . . . . . .

2.2.11 Interrupt Logic 2–16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.12 DMA Controller 2–17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.13 Codec Port Interface 2–17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.14 I

C Interface 2–22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 Electrical Specifications 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1 Absolute Maximum Ratings Over Operating Temperature Ranges 3–1.

3.2 Recommended Operating Conditions 3–1. . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 Electrical Characteristics Over Recommended

Operating Conditions 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4 Timing Characteristics 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4.1 Clock and Control Signals Over Recommended Operating

Conditions 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4.2 USB Transceiver Signals Over Recommended Operating

Conditions 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4.3 Codec Port Interface Signals (AC ’97 Modes) 3–4. . . . . . . . . .

3.4.4 Codec Port Interface Signals (I

S Modes)

Over Recommended Operating Conditions 3–5. . . . . . . . . . . .

3.4.5 Codec Port Interface Signals (General-Purpose Mode)

Over Recommended Operating Conditions 3–5. . . . . . . . . . . .

3.4.6 I

C Interface Signals Over Recommended

Operating Conditions 3–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 Application Information 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Appendix

A MCU Memory and Memory Mapped Registers A–1. . . . . . . . . . . . . . . . . . . . . .

A.1 MCU Memory Space A–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A.2 Internal Data Memory A–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A.3 External MCU Mode Memory Space A–3. . . . . . . . . . . . . . . . . . . . . . . . . . .

A.4 USB Endpoint Configuration Blocks and Data Buffers Space A–4. . . . .

A.5 Memory-Mapped Registers A–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B Mechanical Data B–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

List of Illustrations

Figure Title Page

2–1 Adaptive Clock Generator 2–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–2 Connection of the TUSB3200A to an AC ’97 Codec 2–19. . . . . . . . . . . . . . . . . . .

2–3 Connection of the TUSB3200A to Multiple AC ’97 Codecs 2–20. . . . . . . . . . . . . .

2–4 Single Byte Write Transfer 2–23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–5 Multiple Byte Write Transfer 2–23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–6 Single Byte Read Transfer 2–23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–7 Multiple Byte Read Transfer 2–24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–1 External Interrupt Timing Waveform 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–2 USB Differential Driver Timing Waveform 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–3 BIT_CLK Timing Waveform 3–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–4 SYNC Timing Waveform 3–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–5 Delay Time, Setup Time, and Hold Time Timing Waveforms 3–4. . . . . . . . . . . .

3–6I

3–7 General-Purpose Mode Timing Waveforms 3–5. . . . . . . . . . . . . . . . . . . . . . . . . . .

3–8 SCL and SDA Timing Waveforms 3–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–9 Start and Stop Conditions Timing Waveforms 3–6. . . . . . . . . . . . . . . . . . . . . . . . .

3–10 Acknowledge Timing Waveform 3–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–1 Typical TUSB3200A Device Connections 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . .

A–1 Boot Loader Memory Map 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–1 Normal Operating Mode Memory Map 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–1 USB Endpoint Configuration Blocks and Buffer Space Memory Map 4–1. . . . .

S Mode Timing Waveforms 3–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

List of Tables

Table Title Page

2–1 EEPROM Header 2–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–2 USB Device Information 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–3 Terminal Assignments for Codec Port Interface AC ’97 10 Mode 2–18. . . . . . . .

2–4 Terminal Assignments for Codec Port Interface AC ’97 20 Mode 2–19. . . . . . . .

2–5 Terminal Assignments for Codec Port Interface I 2–6 SLOT Assignments for Codec Port Interface I 2–7 SLOT Assignments for Codec Port Interface I 2–8 Channel Order for 6-Channel Application in I 2–9 Terminal Assignments for Codec Port Interface General-Purpose Mode 2–22. .

S Modes 2–20. . . . . . . . . . . . .

S Mode (Output) 2–21. . . . . . . . .

S Mode (Input) 2–21. . . . . . . . . .

S Mode 4 (Output) 2–21. . . . . . . .

1 Introduction

The TUSB3200A integrated circuit (IC) is a universal serial bus (USB) peripheral interface device designed specifically for applications that require isochronous data streaming. Applications include digital speakers, which require the streaming of digital audio data between the host PC and the speaker system via the USB connection. The TUSB3200A device is fully compatible with the USB Specification V ersion 1.1 and the USB Audio Class Specification.

The TUSB3200A uses a standard 8052 microcontroller unit (MCU) core with on-chip memory. The MCU memory includes 4K bytes of program memory ROM that contains a boot loader program. At initialization, the boot loader program downloads the application program code to an 8K RAM from a nonvolatile memory on the printed-circuit board (PCB). The MCU handles all USB control, interrupt and bulk endpoint transactions. In addition, the MCU can handle USB isochronous endpoint transactions.

The USB interface includes an integrated transceiver that supports 12 Mb/s (full speed) data transfers. In addition to the USB control endpoint, support is provided for up to seven in endpoints and seven out endpoints. The USB endpoints are fully configurable by the MCU application code using a set of endpoint configuration blocks that reside in on-chip RAM. All USB data transfer types are supported.

The TUSB3200A device also includes a codec port interface (C-Port) that can be configured to support several industry standard serial interface protocols. These protocols include the audio codec (AC) ’97 Revision 1.X, the audio codec (AC) ’97 Revision 2.X and several Inter-IC sound (I

A direct memory access (DMA) controller with four channels is provided for streaming the USB isochronous data packets to/from the codec port interface. Each DMA channel can support one USB isochronous endpoint.

An on-chip phase lock loop (PLL) and adaptive clock generator (ACG) provide support for the USB synchronization modes, which include asynchronous, synchronous and adaptive.

Other on-chip MCU peripherals include an Inter-IC control (I (GPIO) ports, and a pulse width modulation (PWM) output.

S) modes.

C) serial interface, two general-purpose input/output

The TUSB3200A device is implemented in a 3.3-V 0.25 µm CMOS technology . In addition, the use of 5-V compatible input/output buffers for the codec port interface allows the TUSB3200A device to be connected to either 3.3-V or 5-V codec devices.

1.1 Features

• Universal Serial Bus (USB)

• USB Specification version 1.1 compatible

• USB Audio Class Specification 1.0 compatible

• Integrated USB transceiver

• Supports 12 Mb/s data rate (full speed)

• Supports suspend/resume and remote wake-up

• Supports control, interrupt, bulk and isochronous data transfer types

• Supports up to a total of 7 in endpoints and 7 out endpoints in addition to the control endpoint

• Data transfer type, data buffer size, single or double buffering is programmable for each endpoint

• On-chip adaptive clock generator (ACG) supports asynchronous, synchronous and adaptive

synchronization modes for isochronous endpoints

• T o support synchronization for streaming USB audio data, the ACG can be used to generate the master clock for the codec

1–1

• Micro-Controller Unit (MCU)

• Standard 8052 8-bit core

• 4K Bytes of program memory ROM that contains a boot loader program that loads the application

firmware from external EEPROM

• 8K Bytes of program memory RAM which is loaded by the boot loader program

• 256 Bytes of internal data memory RAM

• Two GPIO ports

• MCU handles all USB control, interrupt and bulk endpoint transfers

• DMA Controller

• Four DMA channels to support streaming USB audio data to/from the codec port interface

• Each channel can support a single USB isochronous endpoint

• For I

S modes, either a single or multiple USB isochronous endpoints can be used to support multiple

DACs/ADCs

• Codec Port Interface

• Configurable to support AC’97 1.X, AC’97 2.X or I

S serial interface formats

• I2S modes can support a combination of up to 4 DACs and/or 3 ADCs

• Can be configured as a general-purpose serial interface

C Interface

• I

• Master only interface

• Does not support a multimaster bus environment

• Programmable to 100 kbit/s or 400 kbit/s data transfer speeds

• Pulse Width Modulation (PWM) Output

• Programmable frequency range from 732.4 Hz to 93.75 kHz

• Programmable duty cycle

• General Characteristics

• Available in a 52-Pin TQFP Package

• On-chip phase-locked loop (PLL) with internal oscillator is used to generate internal clocks from a 6 MHz

crystal input

• 3.3-V core and 5-V compatible input/output buffers used for codec port interface

• Reset output available which is asserted for both system and USB reset

• External MCU mode supports application firmware development

1–2

1.2 Functional Block Diagram

USB

USB Serial

Interface

Engine

SOF

IEP

OEP

DMA Controller

and

USB Buffer Manager

2K x 8 SRAM

DMA0 DMA1 DMA2 DMA3

Codec Port

Interface

C-Port

CLOCKS

6 MHz

OSC

PLL

ACG

Suspend /Resume

4K ROM

8K RAM

Logic

8052 Core

Port–3 Port–1

Control/Status

Registers

Control

PWM

Counters

I2C Bus

PWM

1–3

1.3 Terminal Assignments – Normal Mode

PAH Package

(TOP VIEW)

P3.4

MCLKO2

P3.5

PLLFILO

PWMO

PLLO DV

PUR

MRESET

TEST

EXTEN

RSTO

PLLFILI

XTALI

XTALO

AVSSMCLKI

MCLKI2

51 50 49 48 4752 46

1 2 3 4 5 6

USB Streaming Controller (STC)

7 8 9 10 11 12 13

14 15 16 17 18 19 20 21 22 23 24 25 26

P3.0

P3.1

XINT

TUSB3200A

52-pin TQFP

P3.3

1.4 Terminal Assignments – External MCU Mode

PAH Package

(TOP VIEW)

DDS

MCLKODVSCL

44 43 4245 41 40

Not Used

SDA

P1.0

P1.1

PLLOEN

CSCHNE

CRESET

CDATI

37 36

CDATO CSYNC

CSCLK

33 32

P1.7 P1.6

P1.5

P1.4

P1.3

P1.2

DDS

PLLFILO

PWMO

PLLO DV

PUR

MRESET

TEST

EXTEN

RSTO

PLLFILI

XTALI

XTALO

AVSSMCLKI

51 50 49 48 4752 46

1 2 3 4 5 6

USB Streaming Controller (STC)

7 8 9 10 11 12 13

14 15 16 17 18 19 20 21 22 23 24 25 26

MCLKI2

TUSB3200A 52-pin TQFP

XINT

MCUA8

MCUA9

MCUA10

MCUALE

MCUINTO

DDS

MCLKO2

MCLKODVSCL

44 43 4245 41 40

MCURD

MCUWR

MCUAD0

SDA

CSCHNE

39 38 37 36 35 34 33 32 31 30 29 28 27

MCUAD1

MCUAD2

CRESET CDATI DV

CDATO CSYNC CSCLK DV

MCUAD7 MCUAD6

MCUAD5 MCUAD4

MCUAD3 DV

DDS

1–4

1.5 Ordering Information

Texas Instruments

Universal Serial Bus

Peripheral Device

Package Type

TQFP

52 pins PAH

TPAH3200AUSB

Commercial Temperature Range

1.6 Terminal Functions – Normal Mode

TERMINAL

NAME NO.

CSCLK 34 I/O Codec port interface serial clock:CSCLK is the serial clock for the codec port interface used to clock the

CSYNC 35 I/O Codec port interface frame sync: CSYNC is the frame synchronization signal for the codec port interface. This

CDATO 36 I/O Codec port interface serial data output: See Section 1.9 for details. This signal uses a 5-V compatible

CDATI 38 I/O Codec port interface serial data input: See Section 1.9 for details. This signal uses a 5-V compatible

CRESET 39 I/O Codec port interface reset output: See Section 1.9 for details. This signal uses a 5-V compatible TTL/LVCMOS

CSCHNE 40 I/O Codec port interface secondary channel enable: See Section 1.9 for details. This signal uses a 5-V compatible

DP 7 I/O USB differential pair data signal plus: DP is the positive signal of the bidirectional USB differential pair used to

DM 8 I/O USB differential pair data signal minus: DM is the negative signal of the bidirectional USB differential pair used

DDS

EXTEN 12 I External MCU mode enable: Input used to enable the device for the external MCU mode. This signal luses a

MCLKI 47 I Master clock input: An input that can be used as the master clock for the codec port interface or the source for

MCLKI2 48 I Master clock input 2: An input that can be used as the master clock for the codec port interface or the source for

MCLKO 44 O Master clock output: The output of the ACG that can be used as the master clock for the codec port interface

2 3.3-V Analog supply voltage

49 Analog ground

9, 21, 37 3.3-V Digital supply voltage

27, 43 5-V Digital supply voltage

5, 16, 33,

I/O

CSYNC, CDAT O, CDA TI, CRESET input/output buffer.

signal uses a 5-V compatible TTL/LVCMOS input/output buffer.

TTL/LVCMOS input/output buf fer.

input/output buffer.

TTL/LVCMOS input/output buf fer.

connect the TUSB3200A device to the universal serial bus.

to connect the TUSB3200A device to the universal serial bus.

Digital ground

3.3-V TTL/LVCMOS input buffer.

MCLKO2. This signal uses a 5-V to 3.3-V level shifting input buffer.

and the codec. This signal uses a 3.3-V TTL/LVCMOS output buffer.

AND CSCHNE signals. This signal uses a 5-V compatible TTL/L VCMOS

DESCRIPTION

1–5

1.6 Terminal Functions – Normal Mode (Continued)

TERMINAL

NAME NO.

MCLKO2 45 O Master clock output 2: An output that can be used as the master clock for the codec port interface and the

MRESET 10 I Master reset: An active low asynchronous reset for the device that resets all logic to the default state. This

Not Used 22 I This pin is not used in the normal mode. This signal should be tied to digital ground for normal operation. P1.0 24 I/O General-purpose I/O port 1 bit 0: A bidirectional I/O port. This signal uses a 5-V compatible TTL/LVCMOS

P1.1 25 I/O General-purpose I/O port 1 bit 1: A bidirectional I/O port. This signal uses a 5-V compatible TTL/LVCMOS

P1.2 26 I/O General-purpose I/O port 1 bit 2: A bidirectional I/O port. This signal uses a 5-V compatible TTL/LVCMOS

P1.3 28 I/O General-purpose I/O port 1 bit 3: A bidirectional I/O port. This signal uses a 5-V compatible TTL/LVCMOS

P1.4 29 I/O General-purpose I/O port 1 bit 4: A bidirectional I/O port. This signal uses a 5-V compatible TTL/LVCMOS

P1.5 30 I/O General-purpose I/O port 1 bit 5: A bidirectional I/O port. This signal uses a 5-V compatible TTL/LVCMOS

P1.6 31 I/O General-purpose I/O port 1 bit 6: A bidirectional I/O port. This signal uses a 5-V compatible TTL/LVCMOS

P1.7 32 I/O General-purpose I/O port 1 bit 7: A bidirectional I/O port. This signal uses a 5-V compatible TTL/LVCMOS

P3.0 14 I/O General-purpose I/O port 3 bit 0: A bidirectional I/O port. This signal uses a 5-V compatible TTL/LVCMOS

P3.1 15 I/O General-purpose I/O port 3 bit 1: A bidirectional I/O port. This signal uses a 5-V compatible TTL/LVCMOS

P3.3 18 I/O General-purpose I/O port 3 bit 3: A bidirectional I/O port. This signal uses a 5-V compatible TTL/LVCMOS

P3.4 19 I/O General-purpose I/O port 3 bit 4: A bidirectional I/O port. This signal uses a 5-V compatible TTL/LVCMOS

P3.5 20 I/O General-purpose I/O port 3 bit 5: A bidirectional I/O port. This signal uses a 5-V compatible TTL/LVCMOS

PLLFILI 52 I PLL loop filter input: Input to on-chip PLL from external filter components. PLLFILO 1 O PLL loop filter output: Output from on-chip PLL to external filter components. PLLO 4 O PLL output: The 48-MHz output of the PLL used for diagnostic purposes only. This signal uses a 3.3-V

PLLOEN 23 I PLL output enable: An input used to enable the PLLO output signal. This signal uses a 5-V compatible input

PWMO 3 O PWM output: Output of the pulse width modulation circuit. This signal uses a 3.3-V to 5-V CMOS level shifting

PUR 6 O USB data signal plus pullup resistor connect: PUR is used to connect the pullup resistor on the DP signal to

RSTO 13 O Reset output: Output that is active while the master reset input or the USB reset is active. This signal uses a

SCL 42 O I2C interface serial clock: SCL is the clock signal for the I2C serial interface. This signal uses a 3.3-V to 5-V TTL

I/O

codec. This clock signal can also be used as a miscellaneous clock. This signal uses a 3.3-V TTL/L VCMOS output buffer.

signal uses a 3.3-V TTL/LVCMOS input buffer.

input/output buffer with an internal 100 µA active pullup.

TTL/LVCMOS output buffer.

buffer.

output buffer.

3.3-V or a 3-state. When the DP signal is connected to 3.3-V the host PC should detect the connection of the TUSB3200A device to the universal serial bus. This signal uses a 3.3-V TTL/L VCMOS output buffer.

3.3-V TTL/LVCMOS output buffer.

level shifting open drain output buffer .

DESCRIPTION

1–6

1.6 Terminal Functions – Normal Mode (Continued)

TERMINAL

NAME NO.

SDA 41 I/O I2C interface serial data input/output: SDA is the bidirectional data signal for the I2C serial interface. This signal

TEST 11 I Test mode enable: Input used to enable the device for the factory test mode. This signal uses a 3.3-V

XINT 17 I External interrrupt: An active low input used by external circuitry to interrupt the on-chip 8052 MCU. This signal

XTALI 51 I Crystal input: Input to the on-chip oscillator from an external 6-MHz crystal. XTALO 50 O Crystal Output: Output from the on-chip oscillator to an external 6-MHz crystal.

I/O

uses a 3.3-V to 5-VTTL level shifting open drain output buffer and a 5-V to 3.3-V TTL level shifting input buffer .

TTL/LVCMOS input buffer.

uses a 5-V compatible input buffer.

DESCRIPTION

1.7 Terminal Functions – External MCU Mode

TERMINAL

NAME NO.

CSCLK 34 I/O Codec port interface serial clock:CSCLK is the serial clock for the codec port interface used to clock the

CSYNC 35 I/O Codec port interface frame sync: CSYNC is the frame synchronization signal for the codec port interface. This

CDATO 36 I/O Codec port interface serial data output: See Section 1.9 for details. This signal uses a 5-V compatible TTL/

CDATI 38 I/O Codec port interface serial data input: See Section 1.9 for details. This signal uses a 5-V compatible TTL/

CRESET 39 I/O Codec port interface reset output: See Section 1.9 for details. This signal uses a 5-V compatible TTL/LVCMOS

CSCHNE 40 I/O Codec port interface secondary channel enable: See Section 1.9 for details. This signal uses a 5-V

DP 7 I/O USB differential pair data signal plus: DP is the positive signal of the bidirectional USB differential pair used to

DM 8 I/O USB differential pair data signal minus: DM is the negative signal of the bidirectional USB differential pair used

DDS

EXTEN 12 I External MCU mode enable: Input used to enable the device for the external MCU mode. This signal uses a 3.3

MCLKI 47 I Master clock input: An input that can be used as the master clock for the codec port interface or the source for

MCLKI2 48 I Master clock input 2: An input that can be used as the master clock for the codec port interface or the source for

MCLKO 44 O Master clock output: The output of the ACG that can be used as the master clock for the codec port interface

MCLKO2 45 O Master clock output 2: An output that can be used as the master clock for the codec port interface and the

MCUAD0 24 I/O MCU multiplexed address/data bit 0: Multiplexed address bit 0/data bit 0 for external MCU access to the

2 3.3-V Analog supply voltage

49 Analog ground

9, 21, 37 3.3-V Digital supply voltage

27, 43 5 V-Digital supply voltage

5, 16, 33,

I/O

CSYNC, CDAT O, CDA TI, CRESET input/output buffer.

signal uses a 5-V compatible TTL/LVCMOS input/output buffer.

LVCMOS input/output buf fer.

input/output buffer.

compatible TTL/L VCMOS input/output buffer.

connect the TUSB3200A device to the universal serial bus.

to connect the TUSB3200A device to the universal serial bus.

Digital ground

V TTL/LVCMOS input buf fer.

MCLKO2. This signal uses a 5-V to 3.3-V level shifting input buffer.

and the codec. This signal uses a 3.3-V TTL/LVCMOS output buffer

codec. This clock signal can also be used as a miscellaneous clock. This signal uses a 3.3-V TTL/L VCMOS output buffer.

TUSB3200A external data memory space.

AND CSCHNE signals. This signal uses a 5-V compatible TTL/L VCMOS

DESCRIPTION

1–7

1.7 Terminal Functions – External MCU Mode (Continued)

TERMINAL

NAME NO.

MCUAD1 25 I/O MCU multiplexed address/data bit 1: Multiplexed address bit 1/data bit 1 for external MCU access to the

MCUAD2 26 I/O MCU multiplexed address/data bit 2: Multiplexed address bit 2/data bit 2 for external MCU access to the

MCUAD3 28 I/O MCU multiplexed address/data bit 3: Multiplexed address bit 3/data bit 3 for external MCU access to the

MCUAD4 29 I/O MCU multiplexed address/data bit 4: Multiplexed address bit 4/data bit 4 for external MCU access to the

MCUAD5 30 I/O MCU multiplexed address/data bit 5: Multiplexed address bit 5/data bit 5 for external MCU access to the

MCUAD6 31 I/O MCU multiplexed address/data bit 6: Multiplexed address bit 6/data bit 6 for external MCU access to the

MCUAD7 32 I/O MCU multiplexed address/data bit 7: Multiplexed address bit 7/data bit 7 for external MCU access to the

MCUA8 14 I MCU address bit 8: Multiplexed address bit 8 for external MCU access to the TUSB3200A external data memory

MCUA9 15 I MCU address bit 9: Multiplexed address bit 9 for external MCU access to the TUSB3200A external data memory

MCUA10 18 I MCU address bit 10: Multiplexed address bit 10 for external MCU access to the TUSB3200A external data

MCUALE 19 I MCU address latch enable: Address latch enable for external MCU access to the TUSB3200A external data

MCUINTO 20 O MCU interrupt output: Interrupt output to be used for external MCU INTO input signal. All internal TUSB3200A

MCURD 23 I MCU read strobe: Read strobe for external MCU read access to the TUSB3200A external data memory space. MCUWR 22 I MCU write strobe: Write strobe for external MCU write access to the TUSB3200A external data memory space. MRESET 10 I Master reset: An active low asynchronous reset for the device that resets all logic to the default state. This signal

Not Used 4 O This pin is not used in the external MCU mode. PLLFILI 52 I PLL loop filter input: Input to on-chip PLL from external filter components. PLLFILO 1 O PLL loop filter output: Output to on-chip PLL from external filter components. PUR 6 O USB data signal plus pullup resistor connect: PUR is used to connect the pullup resistor on the DP signal to 3.3-V

PWMO 3 O PWM output: Output of the pulse width modulation circuit. This signal uses a 3.3-V to 5-V CMOS level shifting

RSTO 13 O Reset output: Output that is active while the master reset input or the USB reset is active. This signal uses a 3.3-V

SCL 42 O I2C interface serial clock: SCL is the clock signal for the I2C serial interface. This signal uses a 3.3-V to 5-V TTL

SDA 41 I/O I2C interface serial data input/output: SDA is the bidirectional data signal for the I2C serial interface. This signal

TEST 11 I Test mode enable: Input used to enable the device for the factory test mode. This signal uses a 3.3-V TTL/

XINT 17 I External interrupt: An active low input used by external circuitry to interrupt the on-chip 8052 MCU. This signal

XTALI 51 I Crystal input: Input to the on-chip oscillator from an external 6-MHz crystal. XTALO 50 O Crystal output: Output from the on-chip oscillator to an external 6-MHz crystal.

I/O

TUSB3200A external data memory space.

space.

memory space.

interrupt sources are ORed together to generate this output signal.

uses a 3.3-V TTL/LVCMOS input bufer.

or a 3-state. When the DP signal is connected to 3.3-V the host PC should detect the connection of the TUSB3200A device to the universal serial bus. This signal uses a 3.3-V TTL/L VCMOS output buffer.

output buffer.

TTL/LVCMOS output buffer.

level shifting open drain output buffer .

uses a 3.3-V to 5-V TTL level shifting open drain output buffer and a 5-V to 3.3-V TTL level shifting input buffer .

LVCMOS input buf fer.

uses a 5-V compatible input buffer.

DESCRIPTION

1–8

1.8 Device Operation Modes

I2S

The EXTEN and TEST pins define the mode that the TUSB3200A will be in after reset.

MODE EXTEN TEST

Normal mode – internal MCU 0 0 External MCU mode 1 0 Factory test 0 1 Factory test 1 1

1.9 Terminal Assignments for Codec Port Interface Modes

The codec port interface has eight modes of operation that support AC97, I2S, and AIC codecs. There is also a general-purpose mode that is not specific to a serial interface. The mode is programmed by writing to the mode select field of the codec port interface configuration register 1 (CPTCNF1). The codec port interface terminals CSYNC, CSCLK, CDATO, CDATI, CRESET shown in the following tables.

, and CSCHNE take on functionality appropriate to the mode programmed as

TERMINAL

NO. NAME

35 CSYNC CSYNC I/O FS O SYNC O SYNC O 34 CSCLK CSCLK I/O SCLK O BIT_CLK I BIT_CLK I 36 CDATO CDATO O DOUT O SD_OUT O SD_OUT O 38 CDATI CDATI I DIN I SD_IN I SD_IN1 I 39 CRESET CRESET O RESET O RESET O RESET O 40 CSCHNE NC O FC O NC O SD_IN2 I

TERMINAL

NO. NAME

35 CSYNC LRCK O LRCK O LRCK O LRCK O 34 CSCLK SCLK O SCLK O SCLK O SCLK O 36 CDATO SDOUT1 O SDOUT1 O SDOUT1 O SDOUT1 O 38 CDATI SDOUT2 O SDOUT2 O SDIN1 I SDOUT2 O 39 CRESET SDOUT3 O SDIN1 I SDIN2 I SDOUT3 O 40 CSCHNE SDIN1 I SDIN2 I SDIN3 I SDOUT4 O

NOTES: 1. Signal names and I/O direction are with respect to the TUSB3200A device. The signal names used for

the TUSB3200A terminals for the various codec port interface modes reflect the nomenclature used by the codec devices.

2. NC indicates no connection for the terminal in a particular mode. The TUSB3200A device drives the signal as an output for these cases.

3. The CSYNC and CSCLK signals can be programmed as either an input or an output in the general-purpose mode.

GP AIC AC ’97 v1.X AC ’97 v2.X

Mode 0 Mode 1 Mode 2 Mode 3

I2S I2S I2S I2S

Mode 4

Mode 5

Mode 6

Mode 7

1–9

1–10

2 Description

2.1 Architectural Overview

2.1.1 Oscillator and PLL

Using an external 6-MHz crystal, the TUSB3200A derives the fundamental 48-MHz internal clock signal using an on-chip oscillator and PLL. Using the PLL output, the other required clock signals are generated by the clock generator and adaptive clock generator.

2.1.2 Clock Generator and Sequencer Logic

Utilizing the 48-MHz input from the PLL, the clock generator logic generates all internal clock signals, except for the codec port interface master clock (MCLK) and serial clock (CSCLK) signals. The TUSB3200A internal clocks include the 48-MHz clock, a 24-MHz clock, a 12-MHz clock and a USB clock. The USB clock also has a frequency of 12-MHz. The USB clock is the same as the 12-MHz clock when the TUSB3200A is transmitting data and is derived from the data when the TUSB3200A is receiving data. To derive the USB clock when receiving USB data, the TUSB3200A utilizes an internal digital PLL (DPLL) that uses the 48-MHz clock.

The sequencer logic controls the access to the SRAM used for the USB endpoint configuration blocks and the USB endpoint buffer space. The SRAM can be accessed by the MCU, USB buffer manager (UBM) or DMA channels. The sequencer controls the access to the memory using a round robin fixed priority arbitration scheme. This basically means that the sequencer logic generates grant signals for the MCU, UBM and DMA channels at a predetermined fixed frequency.

2.1.3 Adaptive Clock Generator (ACG)

The adaptive clock generator is used to generate a master clock output signal (MCLKO) to be used by the codec port interface and the codec device. To synchronize the sample rate conversion of data by the codec to the USB frame rate, the MCLKO signal generated by the adaptive clock generator must be used. The synchronization of the MCLKO signal to the USB frame rate is controlled by the MCU by programming the adaptive clock generator frequency value. The MCLKO frequency is monitored by the MCU and updated as required. For asynchronous operation, an external source can be used to generate a master clock input signal (MCLKI) to be used by the codec port interface. In this scenario, the codec device should also use the same master clock signal (MCLKI).

2.1.4 USB Transceiver

The TUSB3200A provides an integrated transceiver for the USB port. The transceiver includes a differential output driver, a dif ferential input receiver and two single ended input buffers. The transceiver connects to the USB DP and DM signal terminals.

2.1.5 USB Serial Interface Engine (SIE)

The serial interface engine logic manages the USB packet protocol requirements for the packets being received and transmitted on the USB by the TUSB3200A device. For packets being received, the SIE decodes the packet identifier field (PID) to determine the type of packet being received and to ensure the PID is valid. For token packets and data packets being received, the SIE calculates the packet cycle redundancy check (CRC) and compares the value to the CRC contained in the packet to verify that the packet was not corrupted during transmission. For token packets and data packets being transmitted, the SIE generates the CRC that is transmitted with the packet. For packets being transmitted, the SIE also generates the synchronization field (SYNC) that is an eight bit filed at the beginning of each packet. In addition, the SIE generates the correct PID for all packets being transmitted. Another major function of the SIE is the overall serial-to-parallel conversion of the data packets being received and the parallel-to-serial conversion of the data packets being transmitted.

2–1

2.1.6 USB Buffer Manager (UBM)

The USB buffer manager provides the control logic that interfaces the SIE to the USB endpoint buffers. One of the major functions of the UBM is to decode the USB function address to determine if the host PC is addressing the TUSB3200A device USB peripheral function. In addition, the endpoint address field and direction signal are decoded to determine which particular USB endpoint is being addressed. Based on the direction of the USB transaction and the endpoint number, the UBM will either write or read the data packet to/from the appropriate USB endpoint data buffer.

2.1.7 USB Frame Timer

The USB frame timer logic receives the start of frame (SOF) packet from the host PC each USB frame. Each frame, the logic stores the 1 1-bit frame number value from the SOF packet in a register and asserts the internal SOF signal. The frame number register can be read by the MCU and the value can be used as a time stamp. For USB frames in which the SOF packet is corrupted or not received, the frame timer logic will generate a pseudo start of frame (PSOF) signal and increment the frame number register.

2.1.8 USB Suspend and Resume Logic

The USB suspend and resume logic detects suspend and resume conditions on the USB. This logic also provides the internal signals used to control the TUSB3200A device when these conditions occur. The capability to resume operation from a suspend condition with a locally generated remote wake-up event is also provided.

2.1.9 MCU Core

The TUSB3200A uses an 8-bit microcontroller core that is based on the industry standard 8052. The MCU is software compatible with the 8052, 8032, 80C52, 80C53, and 87C52 MCUs. The 8052 MCU is the processing core of the TUSB3200A and handles all USB control, interrupt and bulk endpoint transfers. In addition, the MCU can also be the source or sink for USB isochronous endpoint transfers.

2.1.10 MCU Memory

In accordance with the industry standard 8052, the TUSB3200A MCU memory is organized into program memory , external data memory and internal data memory . A 4K byte boot ROM is used to download the application code to an 8K byte RAM that is mapped to the program memory space. The external data memory includes the USB endpoint configuration blocks, USB data buffers, and memory mapped registers. The total external data memory space used is 2K bytes. A total of 256 bytes are provided for the internal data memory.

2.1.11 USB Endpoint Configuration Blocks and Endpoint Buffer Space

The USB endpoint configuration blocks are used by the MCU to configure and operate the required USB endpoints for a particular application. In addition to the control endpoint, the TUSB3200A supports a total of seven in endpoints and seven out endpoints. A set of six bytes is provided for each endpoint to specify the endpoint type, buffer address, buffer size, and data packet byte count.

The USB endpoint buffer space provided is a total of 1832 bytes. The space is totally configurable by the MCU for a particular application. Therefore, the MCU can configure each buffer based on the total number of endpoints to be used, the maximum packet size to be used for each endpoint, and the selection of single or double buffering.

2.1.12 DMA Controller

Four DMA channels are provided to support the streaming of data for USB isochronous endpoints. Each DMA channel can support one USB isochronous endpoint, either in or out. The DMA channels are used to stream data between the USB endpoint data buffers and the codec port interface. The USB endpoint number and direction can be programmed for each DMA channel. Also, the codec port interface time slots to be serviced by each DMA channel can be programmed.

2–2

2.1.13 Codec Port Interface

The TUSB3200A provides a configurable full duplex bidirectional serial interface that can be used to connect to a codec or another device for streaming USB Isochronous data. The interface can be configured to support several different industry standard protocols, including AC ’97 1.X, AC ’97 2.X and I

2.1.14 I2C Interface

The I2C interface logic provides a two-wire serial interface that can be used by the 8052 MCU to access other ICs. The TUSB3200A is an I The interface can be programmed to operate at either 100 kbps or 400 kbps. In addition, the protocol supports 8-bit or 16-bit addressing for accessing the I

C master device only and supports single byte or multiple byte read and write operations.

C slave device memory locations.

2.1.15 Pulse Width Modulation (PWM) Output

The TUSB3200A provides a pulse width modulation output with programmable frequency and pulse width. The frequency can be programmed from 732 Hz to 93.7 kHz with an 8-bit register. The pulse width of the output signal is set with a 16-bit register.

2.1.16 General-Purpose IO Ports (GPIO)

The TUSB3200A provides two general-purpose IO ports that are controlled by the internal 8052 MCU. The two ports, port 1 and port 3, are 8-bits and 5-bits, respectively . Note that port 3 bit locations 2, 6, and 7 have been used in the TUSB3200A for other functionality. Therefore these three bit locations are not available for GPIO use. Port 3 bit location 2 has been used as the external interrupt (XINT been used as the external MCU write strobe and read strobe inputs for the external MCU mode of operation.

Each bit of both ports can be independently used as either an input or output. Hence each port bit consists of an output buffer , an input buffer and a pullup resistor. The pullup resistors on the GPIO pins can be disabled using the PUDIS bit in the global control register.

) input to the TUSB3200A. Port 3 bit locations 6 and 7 have

2.1.17 Interrupt Logic

The interrupt logic monitors the various conditions that can cause an interrupt and asserts the interrupt 0 (INT0) input to the 8052 MCU accordingly . All of the TUSB3200A internal interrupt sources and the external interrupt (XINT are ORed together to generate the INT0 signal. An interrupt vector register is provided that is used by the MCU to identify the interrupt source.

) input

2.1.18 Reset Logic

An external master reset (MRESET) input signal that is asynchronous to the internal clocks is used to reset the TUSB3200A logic. In addition to the master reset, the TUSB3200A logic can be reset with the USB reset from the host PC. The TUSB3200A also provides a reset output (RSTO signal is asserted when either a master reset or USB reset occurs.

) signal that can be used by external devices. This

2.2 Device Operation

The operation of the TUSB3200A is explained in the following sections. For additional information on USB, refer to the universal serial bus Specification version 1.1.

2.2.1 Clock Generation

The TUSB3200A requires an external 6-MHz crystal and PLL loop filter components connected as shown in Figure 4-1 to derive all the clocks needed for both USB and codec operation. Using the low frequency 6-MHz crystal and generating the required higher frequency clocks internal to the IC is a major advantage regarding EMI.

2–3

2.2.2 Device Initialization

After a power-on reset is applied to the TUSB3200A device, the 8052 MCU will execute a boot loader program from the 4K byte boot ROM mapped to the program memory space. During device initialization, the boot loader program downloads the application program code from an external EEPROM through the I

C interface. This requires that a

binary image of the application code be written to the 8K byte code RAM in the TUSB3200A device. All memory mapped registers are initialized to a default value as defined in Appendix A, MCU Memory and Memory-

Mapped Registers. The TUSB3200A device powers up with a default function address of zero and disconnected from the USB.

2.2.2.1 Boot Load from EEPROM

Loading the application code from an external serial EEPROM requires a preprogrammed memory device containing an informative header and the application code. While the application code is being downloaded, the TUSB3200A will remain disconnected from the USB. When the code download is complete, execution of the application code should connect the TUSB3200A to the USB. In this situation, the TUSB3200A will enumerate using the vendor ID and product ID contained in the application code.

2.2.2.2 EEPROM Header

For both application code and USB device information stored in a EEPROM device, a common header format is used that proceeds the data payload. Table 2-1 shows the format and information contained in the header.

Table 2–1. EEPROM Header

OFFSET TYPE SIZE VALUE

0 Signature 4 0x04513200 4 Header size 1 Header size 5 Version 1 Firmware version 6 EEPROM type 1 0x01 = Reserved

7 Data type 1 0x01 = Application code

8 Data size 2 Data payload only size

10 Check sum 2 Check sum of the data payload

12 Data - Data payload

0x02 = Reserved 0x03 = Reserved 0x04 = Reserved 0x05 = Reserved 0x06 = Reserved 0x07 = Reserved 0x08 = Reserved 0x09 = 24C32 0x0A =24C64 0x0B…0xFF = Reserved

0x02…0xFF = Reserved

beginning at location Check Sum + 2

The signature field is used for the detection of a EEPROM device connected to the TUSB3200A. The header size field supports future updates of the header. Data begins right after the header . The version field identifies the header version. The EEPROM type field identifies the specific EEPROM device being used. The data type field describes the nature of data stored in the EEPROM (application code or USB device information). The data size field holds the length of the data payload starting from the end of the header. The check sum field contains the check sum for the data payload portion of the EEPROM.

2.2.2.3 EEPROM Data Type

The two types of data that are stored in the EEPROM are application code and USB device information.

2–4

2.2.2.3.1 Application Code

Application firmware is stored as a binary image of the code. The binary image is mapped to the MCU program memory space starting at address zero and is stored in the EEPROM as a continuous linear block starting after the header information. A utility program is available that converts a file in Intel hexidecimal format to a binary image data file and appends it to the header.

2.2.2.3.2 USB Device Information

The USB device information is comprised of the vendor ID and product ID. Optionally, a manufacturer string and product string can be included. The boot loader uses this information during enumeration to identify the USB peripheral device. Table 2-2 shows the format and information contained in the USB Device Information Section.

Table 2–2. USB Device Information

OFFSET TYPE SIZE CONTENTS REMARK

H+1 Vendor ID 2 Vendor ID code H+3 Product ID 2 Product ID code H+5 M Offset 1 Pointer to manufacture string String is optional H+6 P Offset 1 Pointer to product string String is optional H+M Offset Manufacture string - Null terminated H+P Offset Product string - Null terminated

2.2.2.4 EEPROM Device Type

The TUSB3200A boot loader program supports several different types of serial EEPROM devices. The boot loader program will automatically identify the EEPROM type from the header information and use the correct serial interface protocol accordingly. The boot loader program uses an I device.

These EEPPROM devices require an I require the full 7-bit I

C device address. Depending on the memory size of the EEPROM device being used, the most

C device address in addition to a two byte data word address. These devices

significant three or four bits of the two byte data word address are don’t care bits. The EEPROM types supported are: 24C32 and 24C64

All of these EEPROM devices can be used for storing and loading application code. However most applications will use devices which are capable of storing up to 8K bytes of program code.

C slave device address of A0h for the serial EEPROM

2.2.3 USB Enumeration

USB enumeration is accomplished by interaction between the host PC software and the TUSB3200A code. After power-on reset the boot loader code first reads the information from the EEPROM, then runs the application code. The application code connects the TUSB3200A to the USB. During the enumeration, the application code identifies the device as an application specific device and the host loads the appropriate host driver(s). The boot loader and application code both use the CONT , SDW , and FRSTE bits to control the enumeration process. The function connect (CONT) bit is set to a 1 by the MCU to connect the TUSB3200A device to the USB. When this bit is set to a 1, the USB data plus pullup resistor (PUR) output signal is enabled, which will connect the pullup on the PCB to the TUSB3200A 3.3-V digital supply voltage. When this bit is cleared to a 0, the PUR output is in the 3-state mode. This bit is not affected by a USB reset. The shadow the boot ROM (SDW) bit is set to a 1 by the MCU to switch the MCU memory configuration from boot loader mode to normal operating mode. The function reset enable (FRSTE) bit is set to a 1 by the MCU to enable the USB reset to reset all internal logic including the MCU. However, the shadow the ROM (SDW) and the USB function connect (CONT) bits will not be reset. When this bit is set, the reset output (RSTO

) signal from the TUSB3200A device will also be active when a USB reset occurs. This bit is not affected by

USB reset.

2.2.4 USB Reset

The TUSB3200A can detect a USB reset condition. When the reset occurs, the TUSB3200A responds by setting the function reset (RSTR) bit in the USB status register (USBSTA). If the corresponding function reset bit in the USB

2–5

interrupt mask register is set, an MCU interrupt will be generated and the USB function reset (0x17) vector will appear in the interrupt vector register (VECINT).

The function reset enable bit (FRSTE) in the USB control register (USBCTL) is used to control the extent to which the internal logic is reset. The function reset enable bit is set to a 1 by the MCU to enable the USB reset to reset all internal logic including the MCU. However, the shadow the ROM (SDW) and the USB function connect (CONT) bits will not be reset. When this bit is set, the reset output (RSTO reset occurs. This bit is not affected by USB reset.

) signal from the device will also be active when a USB

2.2.5 USB Suspend and Resume Modes

All USB devices must support the suspend and resume modes. During the suspend mode, USB devices that are bus powered must enter a low power suspend state. If the USB peripheral device is not bus powered, then entering the low power suspend state is not required. A suspend condition is defined as a constant idle state on the bus for more than 3.0ms. A USB device must actually be in the suspend state no more than 10 ms after the suspend condition is detected. There are two ways for the TUSB3200A device to exit the suspend mode, which are 1) detection of USB resume signaling and 2) detection of a local remote wake-up event.

2.2.5.1 USB Suspend Mode

When a suspend condition is detected on the USB, the suspend/resume logic will set the function suspend request bit (SUSR) in the USB status register. As a result, the function suspend request interrupt (SUSR) will be generated. To enter the low power suspend state and disable all TUSB3200A device clocks, the MCU firmware should set the idle mode bit (IDL), which is bit 0 in the MCU power control (PCON) register. The instruction that sets the IDL bit will be the last instruction executed before the MCU goes to idle mode. In idle mode, the MCU status is preserved. Note that the low power suspend state is a state in which the TUSB3200A clocks are disabled and the IC will consume the least amount of power possible.

2.2.5.2 USB Resume Mode

When the TUSB3200A is in a suspend state, any non-idle signaling on the USB will be detected by the suspend/resume logic and device operation will be resumed. As a result of the resume signaling being detected, the TUSB3200A clocks will be enabled, the function resume request bit (RESR) will be set, and the function resume request interrupt (RESR) will be generated. The function resume request interrupt to the MCU will automatically clear the idle mode bit in the PCON register. As a result, MCU operation will resume with servicing the new interrupt. After the RETI from the ISR, the next instruction to be executed will be the one following the instruction that set the IDL bit. Note that if the low power suspend state was not entered by setting the IDL bit, the clocks will already be enabled and the IDL bit will already be cleared.

2.2.5.3 USB Remote Wake-Up Mode

The TUSB3200A device has the capability to remotely wake-up the USB by generating resume signaling upstream. Note that this feature must be enabled by the host software with the SET_FEA TURE DEVICE_REMOTE_W AKEUP request. The remote wake-up resume signaling should not be generated until the suspend state has been active for at least 5 ms. In addition, the remote wake-up resume signaling must be generated for at least 1ms but for no more than 15 ms. When the TUSB3200A is in the low power suspend state, asserting the external interrupt input (XINT to the device will enable the clocks and generate the XINT interrupt. The XINT interrupt to the MCU will automatically clear the idle mode bit in the PCON register. As a result, MCU operation will resume with servicing the new interrupt. After the RETI from the ISR, the next instruction to be executed will be the one following the instruction that set the IDL bit. Please note that if the low power suspend state was not entered by setting the IDL bit, the clocks will already be enabled and the IDL bit will already be cleared. When the firmware sets the remote wake-up request bit (RWUP) in the USB control register, the suspend/resume logic will generate the resume signaling upstream on the USB.

2.2.6 Power Supply Sequencing

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Turning power supplies on and off with a mixed 5-V/3.3-V system is an important consideration. To avoid possible damage to the TUSB3200A device, proper power sequencing is required. The turnon requirement is that the 5-V and

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3.3-V power supplies should start ramping from 0 volts and reach 95 percent of the final voltage values within 25 ms of each other. The turnoff requirement is that the 5-V and 3.3-V power supplies should start ramping from the steady-state voltage and reach 5 percent of these values within 25 ms of each other. In addition, the difference between the two voltages should never exceed 3.6-V while turning on or off. Normally, in a mixed voltage system, the 3.3-V supply is generated from a voltage regulator running from the 5-V supply . A voltage regulator , such as the Texas Instrument’s TP7133, can be used to meet these power sequencing requirements.

2.2.7 USB Transfers

The TUSB3200A device supports all the USB data transfer types, which are control, bulk, interrupt, and isochronous. In accordance with the USB specification, endpoint zero is reserved for the control endpoint and is bidirectional. In addition to the control endpoint, the TUSB3200A is capable of supporting up to 7 in endpoints and 7 out endpoints. These additional endpoints can be configured as bulk, interrupt, or isochronous endpoints. The MCU handles all control, bulk, and interrupt endpoint transactions. In addition the MCU can handle isochronous endpoint transactions, such as a rate feedback endpoint to the host PC. However, for streaming isochronous data between the host PC and the codec interface port, the DMA channels are provided.

2.2.7.1 Controls Transfers

Control transfers are used for configuration, command, and status communication between the host PC and the TUSB3200A device. Control transfers to the TUSB3200A device use in endpoint 0 and out endpoint 0. The three types of control transfers are control write, control write with no data stage, and control read. Note that the control endpoint must be initialized before connecting the TUSB3200A device to the USB.

2.2.7.1.1 Control Write Transfer (Out Transfer)

The host PC uses a control write transfer to write data to the USB function. A control write transfer consists of a setup stage transaction, at least one out data stage transaction, and an in status stage transaction.

The steps to be followed for a control write transfer are as follows:

1. MCU initializes in endpoint 0 and out endpoint 0 by programming the appropriate USB endpoint configuration blocks. This entails programming the buffer size and buffer base address, selecting the buffer mode, enabling the endpoint interrupt, initializing the TOGGLE bit, enabling the endpoint, and clearing the NACK bit for both in endpoint 0 and out endpoint 0.

Setup Stage Transaction:

2. The host PC sends a setup token packet followed by the setup data packet addressed to out endpoint 0. If the data is received without an error, then the UBM will write the data to the setup data packet buf fer , set the setup stage transaction (SETUP) bit to a 1 in the USB status register, return an ACK handshake to the host PC, and assert the setup stage transaction interrupt. Note that as long as the setup transaction (SETUP) bit is set to a 1, the UBM will return a NAK handshake for any data stage or status stage transactions regardless of the endpoint 0 NACK or STALL bit values.

3. The MCU services the interrupt and reads the setup data packet from the buffer then decodes the command. If the command is not supported or valid, the MCU should set the ST ALL bit in the out endpoint 0 configuration byte and the in endpoint 0 configuration byte before clearing the setup stage transaction (SETUP) bit. This will cause the device to return a STALL handshake for any data stage or status stage transactions. After reading the data packet and decoding the command, the MCU should clear the interrupt, which will automatically clear the setup stage transaction status bit. The MCU should also set the TOGGLE bit in the out endpoint 0 configuration byte to a 1. For control write transfers, the PID used by the host for the first out data packet will be a DATA1 PID and the TOGGLE bit must match.

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Data Stage Transaction(s):

1. The host PC sends an out token packet followed by a data packet addressed to out endpoint 0. If the data is received without an error, then the UBM will write the data to the endpoint buf fer, update the data count value, toggle the TOGGLE bit, set the NACK bit to a 1, return an ACK handshake to the host PC, and assert the endpoint interrupt.

2. The MCU services the interrupt and reads the data packet from the buf fer. T o read the data packet, the MCU first needs to obtain the data count value. After reading the data packet, the MCU should clear the interrupt and clear the NACK bit to allow the reception of the next data packet from the host PC.

3. If the NACK bit is set to a 1 when the data packet is received, the UBM simply returns a NAK handshake to the host PC. IF the ST ALL bit is set to a 1 when the data packet is received, the UBM simply returns A ST ALL handshake to the host PC. If a CRC or bit stuff error occurs when the data packet is received, then no handshake is returned to the host PC.

Status Stage Transaction:

1. For in endpoint 0, the MCU updates the data count value to zero, sets the T OGGLE bit to 1, then clears the NACK bit to a 0 to enable the data packet to be sent to the host PC. Note that for a status stage transaction a null data packet with a DATA1 PID is sent to the host PC.

2. The host PC sends an in token packet addressed to in endpoint 0. After receiving the in token, the UBM transmits a null data packet to the host PC. If the data packet is received without errors by the host PC, then an ACK handshake is returned. The UBM will then toggle the TOGGLE bit, set the NACK bit to a 1, and assert the endpoint interrupt.

3. If the NACK bit is set to a 1 when the in token packet is received, the UBM simply returns a NAK handshake to the host PC. IF the ST ALL bit is set to a 1 when the in token packet is received, the UBM simply returns a STALL handshake to the host PC. If no handshake packet is received from the host PC, then the UBM prepares to retransmit the same data packet again.

2.2.7.1.2 Control Write With No Data Stage Transfer (Out Transfer)

The host PC uses a control write transfer to write data to the USB function. A control write with no data stage transfer consists of a setup stage transaction and an in status stage transaction. For this type of transfer, the data to be written to the USB function is contained in the two byte value field of the setup stage transaction data packet.

The steps to be followed for a control write with no data stage transfer are as follows:

Setup Stage Transaction:

2. The host PC sends a setup token packet followed by the setup data packet addressed to out endpoint 0. If the data is received without an error then the UBM will write the data to the setup data packet buffer , set the setup stage transaction (SETUP) bit to a 1 in the USB status register, return an ACK handshake to the host PC, and assert the setup stage transaction interrupt. Note that as long as the setup transaction (SETUP) bit is set to a 1, the UBM will return a NAK handshake for any data stage or status stage transactions regardless of the endpoint 0 NACK or STALL bit values.

3. The MCU services the interrupt and reads the setup data packet from the buffer then decodes the command. If the command is not supported or valid, the MCU should set the ST ALL bit in the out endpoint 0 configuration byte and the in endpoint 0 configuration byte before clearing the setup stage transaction (SETUP) bit. This will cause the device to return a STALL handshake for an data stage or status stage transactions. After reading the data packet and decoding the command, the MCU should clear the interrupt, which will automatically clear the setup stage transaction status bit.

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Data Stage Transaction:(s): Note, there are NO data stage transactions for this type of transfer. Status Stage Transaction:

2.2.7.1.3 Control Read Transfer (In Transfer)

The host PC uses a control read transfer to read data to the USB function. A control read transfer consists of a setup stage transaction, at least one in data stage transaction and an out status stage transaction.

The steps to be followed for a control read transfer are as follows:

Setup Stage Transaction:

2. The host PC sends a setup token packet followed by the setup data packet addressed to out endpoint 0. If the data is received without an error then the UBM will write the data to the setup data packet buffer , set the setup stage transaction (SETUP) bit to a 1 in the USB status register, return an ACK handshake to the host PC and assert the setup stage transaction interrupt. Note that as long as the setup transaction (SETUP) bit is set to a 1, the UBM will return a NAK handshake for any data stage or status stage transactions regardless of the endpoint 0 NACK or STALL bit values.

3. The MCU services the interrupt and reads the setup data packet fro the buf fer then decodes the command. If the command is not supported or valid, the MCU should set the STALL bit in the out endpoint 0 configuration byte and the in endpoint 0 configuration byte before clearing the setup stage transaction (SETUP) bit. This will cause the device to return a STALL handshake for any data stage or status stage transactions. After reading the data packet and decoding the command, the MCU should clear the interrupt, which will automatically clear the setup stage transaction status bit. The MCU should also set the TOGGLE bit in the in endpoint 0 configuration byte to a 1. For control read transfers, the PID used by the host for the first in data packet will be a DATA1 PID.

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Data Stage Transaction(s):

1. The data packet to be sent to the host PC is written to the in endpoint 0 buf fer by the MCU. The MCU also updates the data count value then clears the in endpoint 0 NACK bit to a 0 to enable the data packet to be sent to the host PC.

2. The host PC sends an in token packet addressed to the in endpoint 0. After receiving the in token, the UBM transmits the data packet to the host PC. IF the data packet is received without errors by the host PC, then an ACK handshake is returned. The UBM will then toggle the TOGGLE bit, set the NACK bit to a 1 and assert the endpoint interrupt.

3. The MCU services the interrupt and prepares to send the next data packet to the host PC.

4. If the NACK bit is set to a 1 when the in token packet is received, the UBM simply returns a NAK handshake to the host PC. IF the ST ALL bit is set to a 1 when the in token packet is received, the UBM simply returns a ST ALL handshake to the host PC. If a no handshake packet is received from the host PC, then the UBM prepares to retransmit the same data packet again.

5. MCU continues to send data packets until all data has been sent to the host PC.

Status Stage Transaction:

1. For out endpoint 0, the MCU sets the T OGGLE bit to 1, then clears the NACK bit to a 0 to enable the data packet to be sent to the host PC. Note that for a status stage transaction a null data packet with a DA TA1 PID is sent to the host PC.

2. The host PC sends an out token packet addressed to out endpoint 0. If the data packet is received without an error then the UBM will update the data count value, toggle the TOGGLE bit, set the NACK bit to a 1, return an ACK handshake to the host PC and assert the endpoint interrupt.

3. The MCU services the interrupt. If the status stage transaction completed successfully, then the MCU should clear the interrupt and clear the NACK bit.

4. If the NACK bit is set to a 1 when the in data packet is received, the UBM simply returns a NAK handshake to the host PC. If the STALL bit is set to a 1 when the in data packet is received, the UBM simply returns a ST ALL handshake to the host PC. If a CRC or bit stuff error occurs when the data packet is received, then no handshake is returned to the host PC.

2.2.7.2 Interrupt Transfers

The TUSB3200A supports interrupt data transfers both to and from the host PC. Devices that need to send or receive a small amount of data with a specified service period should use the interrupt transfer type. In endpoints 1 through 7 and out endpoints 1 through 7 can all be configured as interrupt endpoints.

2.2.7.2.1 Interrupt Out Transaction

The steps to be followed for an interrupt out transaction are as follows:

1. MCU initializes one of the out endpoints as an out interrupt endpoint by programming the appropriate USB endpoint configuration block. This entails programming the buffer size and buffer base address, selecting the buffer mode, enabling the endpoint interrupt, initializing the toggle bit, enabling the endpoint, and clearing the NACK bit.

2. The host PC sends an out token packet followed by a data packet addressed to the out endpoint. If the data is received without an error then the UBM will write the data to the endpoint buffer , update the data count value, toggle the toggle bit, set the NACK bit to a 1, return an ACK handshake to the host PC and assert the endpoint interrupt.

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3. The MCU services the interrupt and reads the data packet from the buf fer. T o read the data packet, the MCU first needs to obtain the data count value. After reading the data packet, the MCU should clear the interrupt and clear the NACK bit to allow the reception of the next data packet from the host PC.

4. If the NACK bit is set to a 1 when the data packet is received, the UBM simply returns a NAK handshake to the host PC. If the STALL bit is set to a 1 when the data packet is received, the UBM simply returns a ST ALL handshake to the host PC. If a CRC or bit stuff error occurs when the data packet is received, then no handshake is returned to the host PC.

NOTE: In double buffer mode for interrupt out transactions, the UBM selects between the X and Y buffer based on the value of the toggle bit. If the toggle bit is a 0, the UBM will write the data packet to the X buffer . If the toggle bit is a 1, the UBM will write the data packet to the Y buffer. When a data packet is received, the MCU could determine which buffer contains the data packet by reading the toggle bit. However, when using double buf fer mode, the possibility exists for data packets to be received and written to both the X and Y buffer before the MCU responds to the endpoint interrupt. In this case, by simply using the toggle bit to determine which buffer contains the data packet would not work. Hence, in double buffer mode, the MCU should read the X buffer NACK bit, the Y buffer NACK bit and the toggle bit to determine the status of the buffers.

2.2.7.2.2 Interrupt In Transaction

The steps to be followed for an interrupt in transaction are as follows:

1. MCU initializes one of the in endpoints as an in interrupt endpoint by programming the appropriate USB endpoint configuration block. This entails programming the buffer size and buffer base address, selecting the buffer mode, enabling the endpoint interrupt, initializing the toggle bit, enabling the endpoint, and setting the NACK bit.

2. The data packet to be sent to the host PC is written to the buf fer by the MCU. The MCU also updates the data count value then clears the NACK bit to a 0 to enable the data packet to be sent to the host PC.

3. The host PC sends an in token packet addressed to the in endpoint. After receiving the in token, the UBM transmits the data packet to the host PC. If the data packet is received without errors by the host PC, then an ACK handshake is returned. The UBM will then toggle the toggle bit, set the NACK bit to a 1 and assert the endpoint interrupt.

4. The MCU services the interrupt and prepares to send the next data packet to the host PC.

5. If the NACK bit is set to a 1 when the in token packet is received, the UBM simply returns a NAK handshake to the host PC. If the ST ALL bit is set to a 1 when the In token packet is received, the UBM simply returns a STALL handshake to the host PC. If no handshake packet is received from the host PC, then the UBM prepares to retransmit the same data packet again.

NOTE: In double buffer mode for interrupt in transactions, the UBM selects between the X and Y buffer based on the value of the toggle bit. If the toggle bit is a 0, the UBM will read the data packet from the X buffer . If the toggle bit is a 1, the UBM will read the data packet from the Y buffer.

2.2.7.3 Bulk Transfers

The TUSB3200A supports bulk data transfers both to and from the host PC. Devices that need to send or receive a large amount of data without a suitable bandwidth should use the bulk transfer type. In endpoints 1 through 7 and out endpoints 1 through 7 can all be configured as bulk endpoints.

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2.2.7.3.1 Bulk Out Transaction

The steps to be followed for a bulk out transaction are as follows:

1. MCU initializes one of the out endpoints as an out bulk endpoint by programming the appropriate USB endpoint configuration block. This entails programming the buffer size and buffer base address, selecting the buffer mode, enabling the endpoint interrupt, initializing the toggle bit, enabling the endpoint, and clearing the NACK bit.

NOTE: In double buffer mode for bulk out transactions, the UBM selects between the X and Y buffer based on the value of the toggle bit. If the toggle bit is a 0, the UBM will write the data packet to the X buffer . If the toggle bit is a 1, the UBM will write the data packet to the Y buffer . When a data packet is received, the MCU could determine which buffer contains the data packet by reading the toggle bit. However, when using double buf fer mode, data packets may be received and written to both the X and Y buffer before the MCU responds to the endpoint interrupt. In this case, simply using the toggle bit to determine which buffer contains the data packet would not work. Hence, in double buffer mode, the MCU should read the X buffer NACK bit, the Y buffer NACK bit, and the toggle bit to determine the status of the buffers.

2.2.7.3.2 Bulk In Transaction

The steps to be followed for a bulk in transaction are as follows:

1. MCU initializes one of the in endpoints as an in bulk endpoint by programming the appropriate USB endpoint configuration block. This entails programming the buffer size and buffer base address, selecting the buffer mode, enabling the endpoint interrupt, initializing the toggle bit, enabling the endpoint, and setting the NACK bit.

4. The MCU services the interrupt and prepares to send the next data packet to the host PC.

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NOTE: In double buffer mode for bulk in transactions, the UBM selects between the X and Y buffer based on the value of the toggle bit. If the toggle bit is a 0, the UBM will read the data packet from the X buffer . If the toggle bit is a 1, the UBM will read the data packet from the Y buffer.

2.2.7.4 Isochronous Transfers

The TUSB3200A supports isochronous data transfers both to and from the host PC. Devices that need to send or receive constant-rate data with a suitable USB bandwidth should use the isochronous transfer type. In endpoints 1 through 7 and out endpoints 1 through 7 can all be configured as isochronous endpoints.

The transfer of isochronous data on the USB requires the use of double buffering. The TUSB3200A provides an X buffer and Y buffer for each isochronous endpoint.

Four DMA channels are also provided to support streaming isochronous data to/from the host PC to/from a codec. For isochronous endpoints handled by the MCU, the DMA channels are not used.

2.2.7.4.1 Isochronous Out Transaction (host PC as source and codec as destination)

The steps to be followed for an isochronous out transaction are as follows:

1. MCU initializes one of the out endpoints as an out isochronous endpoint by programming the appropriate USB endpoint configuration block. This entails programming the buffer size and the buffer base address for both the X and Y buffers and the bytes per sample bits, setting the isochronous endpoint bit, enabling the endpoint, and clearing the NACK bit.

2. The MCU initializes one of the four DMA channels to support the isochronous out endpoint by programming the appropriate DMA configuration registers.

3. The host PC sends an out token packet followed by a data packet addressed to the out endpoint. The UBM writes the data packet to the X (or Y) endpoint buffer , updates the sample count in the data count byte, and sets the X (or Y) buffer NACK bit to a 1. Note that the number of audio samples and not the number of bytes is written to the data count byte. Also, note that there is no endpoint interrupt generated for isochronous endpoints. If a buffer overflow occurs, the UBM will set the overflow bit in the endpoint configuration byte.

4. The DMA channel reads the X (or Y) buf fer data count byte to verify that the NACK bit is set and to obtain the sample count in the new data packet. The DMA channel then clears the NACK bit and streams the data to the codec port interface. Note that if a new data packet has not been received, the NACK bit will not be set, and the DMA channel will not move any data to the codec port interface.

2.2.7.4.2 Isochronous Out Transaction (host PC as source and MCU as destination)

The steps to be followed for an isochronous out transaction are as follows:

5. MCU initializes one of the out endpoints as an out isochronous endpoint by programming the appropriate USB endpoint configuration block. This entails programming the buffer size and the buffer base address for both the X and Y buffers and the bytes per sample bits, setting the isochronous endpoint bit, enabling the endpoint, and clearing the NACK bit.

6. The host PC sends an out token packet followed by a data packet addressed to the out endpoint. The UBM writes the data packet to the X (or Y) endpoint buffer , updates the sample count in the data count byte, and sets the X (or Y) buffer NACK bit to a 1. Note that the number of audio samples and not the number of bytes is written to the data count byte. Also, note that there is not an endpoint interrupt generated for isochronous endpoints. If a buffer overflow occurs, the UBM will set the overflow bit in the endpoint configuration byte.

7. After an SOF or PSOF interrupt, the MCU reads the USB frame number register and uses the least significant bit (bit 0) value as the buffer select bit. If bit 0 is a 0 for the current USB frame, then the MCU should access the Y buffer. If bit 0 is a 1 for the current USB frame, then the MCU should access the X buffer.

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