Texas instruments TUSB3200A Data Manual
TUSB3200A
USB Streaming Controller (STC)
Data Manual
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Literature Number: SLES018A
October 2001–Revised July 2010
TUSB3200A
SLES018A–OCTOBER 2001–REVISED JULY 2010
www.ti.com
Contents
1 Introduction ........................................................................................................................ 9
1.1 Features .................................................................................................................... 10
1.2 Functional Block Diagram ................................................................................................ 11
1.3 Terminal Assignments − Normal Mode ................................................................................. 12
1.4 Terminal Assignments − External MCU Mode ......................................................................... 13
1.5 Ordering Information ...................................................................................................... 13
1.6 Terminal Functions − Normal Mode ..................................................................................... 14
1.7 Terminal Functions − External MCU Mode ............................................................................ 16
1.8 Device Operation Modes ................................................................................................. 17
1.9 Terminal Assignments for Codec Port Interface Modes .............................................................. 18
2 Description ....................................................................................................................... 19
2.1 Architectural Overview .................................................................................................... 19
2.1.1 Oscillator and PLL .............................................................................................. 19
2.1.2 Clock Generator and Sequencer Logic ...................................................................... 19
2.1.3 Adaptive Clock Generator (ACG) ............................................................................. 19
2.1.4 USB Transceiver ................................................................................................ 19
2.1.5 USB Serial Interface Engine (SIE) ........................................................................... 19
2.1.6 USB Buffer Manager (UBM) .................................................................................. 20
2.1.7 USB Frame Timer .............................................................................................. 20
2.1.8 USB Suspend and Resume Logic ............................................................................ 20
2.1.9 MCU Core ....................................................................................................... 20
2.1.10 MCU Memory ................................................................................................... 20
2.1.11 USB Endpoint Configuration Blocks and Endpoint Buffer Space ........................................ 20
2.1.12 DMA Controller .................................................................................................. 20
2.1.13 Codec Port Interface ........................................................................................... 21
2.1.14 I
2.1.15 Pulse Width Modulation (PWM) Output ...................................................................... 21
2.1.16 General-Purpose IO Ports (GPIO) ............................................................................ 21
2.1.17 Interrupt Logic ................................................................................................... 22
2.1.18 Reset Logic ...................................................................................................... 22
2.2 Device Operation .......................................................................................................... 22
2.2.1 Clock Generation ............................................................................................... 22
2.2.2 Device Initialization ............................................................................................. 22
2.2.3 USB Enumeration .............................................................................................. 24
2.2.4 USB Reset ....................................................................................................... 24
2.2.5 USB Suspend and Resume Modes .......................................................................... 24
2.2.6 Power Supply Sequencing .................................................................................... 25
2
C Interface ..................................................................................................... 21
2.1.16.1 External Pullup Macro ............................................................................. 21
2.2.2.1 Boot Load from EEPROM ........................................................................ 22
2.2.2.2 EEPROM Header .................................................................................. 23
2.2.2.3 Application Code ................................................................................... 23
2.2.2.4 EEPROM Device Type ............................................................................ 23
2.2.5.1 USB Suspend Mode ............................................................................... 24
2.2.5.2 USB Resume Mode ................................................................................ 25
2.2.5.3 USB Remote Wake-Up Mode .................................................................... 25
2 Contents Copyright © 2001–2010, Texas Instruments Incorporated
TUSB3200A
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SLES018A–OCTOBER 2001–REVISED JULY 2010
2.2.7 USB Transfers .................................................................................................. 25
2.2.7.1 Controls Transfers ................................................................................. 25
2.2.7.2 Interrupt Transfers ................................................................................. 28
2.2.7.3 Bulk Transfers ...................................................................................... 30
2.2.7.4 Isochronous Transfers ............................................................................. 31
2.2.8 Adaptive Clock Generator (ACG) ............................................................................. 33
2.2.8.1 Programmable Frequency Synthesizer ......................................................... 33
2.2.8.2 Capture Counter and Register ................................................................... 34
2.2.9 Microcontroller Unit ............................................................................................. 34
2.2.10 External MCU Mode Operation ............................................................................... 35
2.2.11 Interrupt Logic ................................................................................................... 35
2.2.12 DMA Controller .................................................................................................. 35
2.2.13 Codec Port Interface ........................................................................................... 36
2.2.13.1 Audio Codec (AC) '97 1.0 Mode of Operation ................................................. 36
2.2.13.2 Audio Codec (AC) '97 2.0 Mode of Operation ................................................. 38
2.2.13.3 Inter-IC Sound (I
2
S) Modes of Operation ....................................................... 38
2.2.13.4 General-Purpose Mode of Operation ............................................................ 40
2.2.14 I
2
C Interface ..................................................................................................... 40
2.2.14.1 Data Transfers ...................................................................................... 41
2.2.14.2 Single Byte Write ................................................................................... 41
2.2.14.3 Multiple Byte Write ................................................................................. 42
2.2.14.4 Single Byte Read ................................................................................... 42
2.2.14.5 Multiple Byte Read ................................................................................. 42
2.2.15 General-Purpose I/O (GPIO) Ports ........................................................................... 43
2.2.15.1 Port 3 GPIO Bits ................................................................................... 45
3 Electrical Specifications ..................................................................................................... 46
3.1 ABSOLUTE MAXIMUM RATINGS ...................................................................................... 46
3.2 RECOMMENDED OPERATING CONDITIONS ....................................................................... 46
3.3 ELECTRICAL CHARACTERISTICS .................................................................................... 47
3.4 TIMING CHARACTERISTICS ........................................................................................... 47
3.5 Clock and Control Signals ................................................................................................ 47
3.6 USB Transceiver Signals ................................................................................................. 48
3.7 Codec Port Interface Signals (AC '97 Modes) ......................................................................... 48
3.8 Codec Port Interface Signals (I2S Modes) ............................................................................. 49
3.9 Codec Port Interface Signals (General Purpose Mode) .............................................................. 50
3.10 I
2
C Interface Signals ...................................................................................................... 50
4 Application Information ...................................................................................................... 52
A MCU Memory and Memory Mapped Registers ....................................................................... 53
A.1 MCU Memory Space ...................................................................................................... 53
A.2 Internal Data Memory ..................................................................................................... 54
A.3 External MCU Mode Memory Space .................................................................................... 55
A.4 USB Endpoint Configuration Blocks and Data Buffers Space ....................................................... 56
A.4.1 USB Endpoint Confiuration Blocks ........................................................................... 56
A.4.2 Data Buffers Space ............................................................................................. 56
A.4.3 USB Out Endpoint Configuration Bytes ...................................................................... 60
A.4.3.1 USB Out Endpoint − Y Buffer Data Count Byte (OEPDCNTYx) ............................. 60
A.4.3.2 USB Out Endpoint − Y Buffer Base Address Byte (OEPBBAYx) ............................ 60
Copyright © 2001–2010, Texas Instruments Incorporated Contents 3
TUSB3200A
SLES018A–OCTOBER 2001–REVISED JULY 2010
A.4.3.3 USB Out Endpoint − X Buffer Data Count Byte (OEPDCNTXx) ............................. 61
A.4.3.4 USB Out Endpoint − X and Y Buffer Size Byte (OEPBSIZx) ................................ 61
A.4.3.5 USB Out Endpoint − X Buffer Base Address Byte (OEPBBAXx) ............................ 61
A.4.3.6 USB Out Endpoint − Configuration Byte (OEPCNFx) ......................................... 62
A.4.4 USB In Endpoint Configuration Bytes ........................................................................ 63
A.4.4.1 USB In Endpoint − Y Buffer Data Count Byte (IEPDCNTYx) ................................ 63
A.4.4.2 USB In Endpoint − Y Buffer Base Address Byte (IEPBBAYx) ............................... 64
A.4.4.3 USB In Endpoint − X Buffer Data Count Byte (IEPDCNTXx) ................................ 64
A.4.4.4 USB In Endpoint − X and Y Buffer Size Byte (IEPBSIZx) .................................... 64
A.4.4.5 USB In Endpoint − X Buffer Base Address Byte (IEPBBAXx) ............................... 65
A.4.4.6 USB In Endpoint − Configuration Byte (IEPCNFx) ............................................ 65
A.4.5 USB Control Endpoint Setup Stage Data Packet Buffer .................................................. 66
A.5 Memory-Mapped Registers .............................................................................................. 67
A.5.1 USB Registers .................................................................................................. 69
A.5.1.1 USB Function Address Register (USBFADR − Address FFFFh) ............................ 69
A.5.1.2 USB Status Register (USBSTA − Address FFFEh) ........................................... 70
A.5.1.3 USB Interrupt Mask Register (USBMSK − Address FFFDh) ................................. 71
A.5.1.4 USB Control Register (USBCTL − Address FFFCh) .......................................... 71
A.5.1.5 USB Frame Number Register (Low Byte) (USBFNL − Address FFFBh) ................... 72
A.5.1.6 USB Frame Number Register (High Byte) (USBFNH − Address FFFAh) .................. 72
A.5.2 DMA Registers .................................................................................................. 72
A.5.2.1 DMA Channel 3 Time Slot Assignment Register (Low Byte) (DMATSL3 − Address FFF9h)
........................................................................................................ 72
A.5.2.2 DMA Channel 3 Time Slot Assignment Register (High Byte) (DMATSH3 − Address FFF8h)
........................................................................................................ 73
A.5.2.3 DMA Channel 3 Control Register (DMACTL3 − Address FFF7h) ........................... 73
A.5.2.4 DMA Channel 2 Time Slot Assignment Register (Low Byte) (DMATSL2 − Address FFF6h)
........................................................................................................ 74
A.5.2.5 DMA Channel 2 Time Slot Assignment Register (High Byte) (DMATSH2 − Address FFF5h)
........................................................................................................ 74
A.5.2.6 DMA Channel 2 Control Register (DMATCTL2 − Address FFF4h) ......................... 75
A.5.2.7 DMA Channel 1 Time Slot Assignment Register (Low Byte) (DMATSL1 − Address FFF0h)
........................................................................................................ 75
A.5.2.8 DMA Channel 1 Time Slot Assignment Register (High Byte) (DMATSH1 − Address FFEFh)
........................................................................................................ 76
A.5.2.9 DMA Channel 1 Control Register (DMACTL1 − Address FFEEh) .......................... 76
A.5.2.10 DMA Channel 0 Time Slot Assignment Register (Low Byte) (DMATSL0 − Address FFEAh)
........................................................................................................ 77
A.5.2.11 DMA Channel 0 Time Slot Assignment Register (High Byte) (DMATSH0 − Address FFE9h)
........................................................................................................ 77
A.5.2.12 DMA Channel 0 Control Register (DMACTL0 − Address FFE8h) ........................... 78
A.5.3 Adaptive Clock Generator Registers ......................................................................... 79
A.5.3.1 Adaptive Clock Generator Frequency Register (Byte 0) (ACGFRQ0 − Address FFE7h) 79
A.5.3.2 Adaptive Clock Generator Frequency Register (Byte 1) (ACGFRQ1 − Address FFE6h) 79
A.5.3.3 Adaptive Clock Generator Frequency Register (Byte 2) (ACGFRQ2 − Address FFE5h) 79
A.5.3.4 Adaptive Clock Generator MCLK Capture Register (Low Byte) (ACGCAPL − Address
FFE4h) .............................................................................................. 80
A.5.3.5 Adaptive Clock Generator MCLK Capture Register (High Byte) (ACGCAPH − Address
FFE3h) .............................................................................................. 80
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4 Contents Copyright © 2001–2010, Texas Instruments Incorporated
TUSB3200A
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SLES018A–OCTOBER 2001–REVISED JULY 2010
A.5.3.6 Adaptive Clock Generator Divider Control Register (ACGDCTL − Address FFE2h) ..... 80
A.5.3.7 Adaptive Clock Generator Control Register (ACGCTL − Address FFE1h) ................. 81
A.5.4 Codec Port Interface Registers ............................................................................... 82
A.5.4.1 Codec Port Interface Configuration Register 1 (CPTCNF1 − Address FFE0h) ............ 82
A.5.4.2 Codec Port Interface Configuration Register 2 (CPTCNF2 − Address FFDFh) ........... 83
A.5.4.3 Codec Port Interface Configuration Register 3 (CPTCNF2 − Address FFDEh) ........... 84
A.5.4.4 Codec Port Interface Configuration Register 4 (CPTCNF4 − Address FFDDh) ........... 85
A.5.4.5 Codec Port Interface Control and Status Register (CPTCTL − Address FFDCh) ......... 86
A.5.4.6 Codec Port Interface Address Register (CPTADR − Address FFDBh) ..................... 87
A.5.4.7 Codec Port Interface Data Register (Low Byte) (CPTDATL − Address FFDAh) .......... 87
A.5.4.8 Codec Port Interface Data Register (High Byte) (CPTDATH − Address FFD9h) ......... 88
A.5.4.9 Codec Port Interface Valid Time Slots Register (Low Byte) (CPTVSLL − Address FFD8h)
........................................................................................................ 88
A.5.4.10 Codec Port Interface Valid Time Slots Register (High Byte) (CPTVSLH − Address FFD7h)
........................................................................................................ 89
A.5.5 I
A.5.6 PWM Registers ................................................................................................. 91
A.5.7 Miscellaneous Registers ....................................................................................... 92
2
C Interface Registers ......................................................................................... 89
A.5.5.1 I
A.5.5.2 I
A.5.5.3 I
A.5.5.4 I
2
C Interface Address Register (I2CADR − Address FFC3h) ................................ 89
2
C Interface Receive Data Register (I2CDATI − Address FFC2h) ......................... 90
2
C Interface Transmit Data Register (I2CDATO − Address FFC1h) ....................... 90
2
C Interface Control and status register (I2CCTL − Address FFC0h) ...................... 91
A.5.6.1 PWM Frequency Register (PWMFRQ − Address FFBFh) ................................... 91
A.5.6.2 PWM Pulse Width Register (Low Byte) (PWMPWL − Address FFBEh) .................... 92
A.5.6.3 PWM Pulse Width Register (High Byte) (PWMPWH − Address FFBDh) .................. 92
A.5.7.1 USB Out Endpoint Interrupt Register (OEPINT − Address FFB4h) ......................... 92
A.5.7.2 USB In Endpoint Interrupt Register (IEPINT − Address FFB3h) ............................ 93
A.5.7.3 Interrupt Vector Register (VECINT − Address FFB2H) ....................................... 94
A.5.7.4 Global Control Register (GLOBCTL − Address FFB1h) ...................................... 95
A.5.7.5 Memory Configuration Register (MEMCFG − Address FFB0h) .............................. 95
Copyright © 2001–2010, Texas Instruments Incorporated Contents 5
TUSB3200A
SLES018A–OCTOBER 2001–REVISED JULY 2010
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List of Figures
2-1 Adaptive Clock Generator....................................................................................................... 33
2-2 Connection of the TUSB3200A to an AC '97 Codec ........................................................................ 37
2-3 Connection of the TUSB3200A to Multiple AC '97 Codecs................................................................. 38
2-4 Single Byte Write Transfer ...................................................................................................... 42
2-5 Multiple Byte Write Transfer .................................................................................................... 42
2-6 Single Byte Read Transfer...................................................................................................... 42
2-7 Multiple Byte Read Transfer .................................................................................................... 43
2-8 GPIO Port 1 and Port 3 Functionality.......................................................................................... 44
3-1 External Interrupt Timing Waveform........................................................................................... 48
3-2 USB Differential Driver Timing Waveform..................................................................................... 48
3-3 BIT_CLK Timing Waveform..................................................................................................... 49
3-4 SYNC Timing Waveform ........................................................................................................ 49
3-5 Delay Time, Setup Time, and Hold Time Timing Waveform ............................................................... 49
3-6 I
3-7 General-Purpose Mode Driver Timing Waveform............................................................................ 50
3-8 SCL and SDA Driver Timing Waveform....................................................................................... 51
3-9 Start and Stop Conditions Timing Waveform................................................................................. 51
3-10 Acknowledge Timing Waveform................................................................................................ 51
4-1 Typical TUSB3200A Device Connections..................................................................................... 52
A-1 Boot Loader Mode Memory Map............................................................................................... 55
A-2 Normal Operating Mode Memory Map ........................................................................................ 55
A-3 USB Endpoint Configuration Blocks and Buffer Space Memory Map..................................................... 56
2
S Mode Driver Timing Waveform............................................................................................. 50
6 List of Figures Copyright © 2001–2010, Texas Instruments Incorporated
TUSB3200A
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SLES018A–OCTOBER 2001–REVISED JULY 2010
List of Tables
2-1 Electrical Characteristics of Pullup Resistors................................................................................. 21
2-2 EEPROM Header ................................................................................................................ 23
2-3 Terminal Assignments for Codec Port Interface AC '97 1.0 Mode ........................................................ 37
2-4 Terminal Assignments for Codec Port Interface AC '97 2.0 Mode ........................................................ 38
2-5 Terminal Assignments for Codec Port Interface I
2-6 SLOT Assignments for Codec Port Interface I
2-7 SLOT Assignments for Codec Port Interface I
2-8 Channel Order for 6-Channel Application in I
2-9 Terminal Assignments for Codec Port Interface General-Purpose Mode................................................. 40
A-1 USB Endpoint Configuration Blocks Address Map .......................................................................... 57
A-2 USB Control Endpoint Setup Data Packet Buffer Address Map........................................................... 66
A-3 Memory Mapped Registers Address Map..................................................................................... 67
2
S Modes................................................................ 39
2
S Mode (Output) .......................................................... 40
2
S Mode (Input) ............................................................ 40
2
S Mode 4 (Output) ......................................................... 40
Copyright © 2001–2010, Texas Instruments Incorporated List of Tables 7
TUSB3200A
SLES018A–OCTOBER 2001–REVISED JULY 2010
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8 List of Tables Copyright © 2001–2010, Texas Instruments Incorporated
TUSB3200A
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1 Introduction
The TUSB3200A integrated circuit (IC) is a universal serial bus (USB) peripheral interface device
designed specifically for applications that require isochronous data streaming. Applications include digital
speakers, which require the streaming of digital audio data between the host PC and the speaker system
via the USB connection. The TUSB3200A device is fully compatible with the USB Specification Version
1.1 and the USB Audio Class 1.0 Specification.
The TUSB3200A uses a standard 8052 microcontroller unit (MCU) core with on-chip memory. The MCU
memory includes 4K bytes of program memory ROM that contains a boot loader program. At initialization,
the boot loader program downloads the application program code to an 8K RAM from a nonvolatile
memory on the printed-circuit board (PCB). The MCU handles all USB control, interrupt and bulk endpoint
transactions. In addition, the MCU can handle USB isochronous endpoint transactions.
The USB interface includes an integrated transceiver that supports 12 Mb/s (full speed) data transfers. In
addition to the USB control endpoint, support is provided for up to seven in endpoints and seven out
endpoints. The USB endpoints are fully configurable by the MCU application code using a set of endpoint
configuration blocks that reside in on-chip RAM. All USB data transfer types are supported.
The TUSB3200A device also includes a codec port interface (C-Port) that can be configured to support
several industry standard serial interface protocols. These protocols include the audio codec (AC) '97
Revision 1.X, the audio codec (AC) '97 Revision 2.X and several Inter-IC sound (I2S) modes.
SLES018A–OCTOBER 2001–REVISED JULY 2010
USB Streaming Controller (STC)
Check for Samples: TUSB3200A
A direct memory access (DMA) controller with four channels is provided for streaming the USB
isochronous data packets to/from the codec port interface. Each DMA channel can support one USB
isochronous endpoint.
An on-chip phase lock loop (PLL) and adaptive clock generator (ACG) provide support for the USB
synchronization modes, which include asynchronous, synchronous and adaptive.
Other on-chip MCU peripherals include an Inter-IC control (I2C) serial interface, two general-purpose
input/output (GPIO) ports, and a pulse width modulation (PWM) output.
The TUSB3200A device is implemented in a 3.3-V 0.25 µm CMOS technology. In addition, the use of 5-V
compatible input/output buffers for the codec port interface allows the TUSB3200A device to be connected
to either 3.3-V or 5-V codec devices.
1
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2001–2010, Texas Instruments Incorporated
TUSB3200A
SLES018A–OCTOBER 2001–REVISED JULY 2010
1.1 Features
• Universal Serial Bus (USB) • DMA Controller
– USB Specification version 1.1 compatible – Four DMA channels to support streaming
– USB Audio Class Specification 1.0
compatible
– Integrated USB transceiver
– Supports 12 Mb/s data rate (full speed)
– Supports suspend/resume and remote
wake-up
– Supports control, interrupt, bulk and
isochronous data transfer types
– Supports up to a total of 7 in endpoints and
7 out endpoints in addition to the control
endpoint
– Data transfer type, data buffer size, single or
double buffering is programmable for each
endpoint
– On-chip adaptive clock generator (ACG)
supports asynchronous, synchronous and – Master only interface
adaptive synchronization modes for
isochronous endpoints
– To support synchronization for streaming
USB audio data, the ACG can be used to
generate the master clock for the codec
• Micro-Controller Unit (MCU)
– Standard 8052 8-bit core
– 4K Bytes of program memory ROM that
contains a boot loader program that loads
the application firmware from external
EEPROM
– 8K Bytes of program memory RAM which is
loaded by the boot loader program
– 256 Bytes of internal data memory RAM
– Two GPIO ports
– MCU handles all USB control, interrupt and
bulk endpoint transfers
USB audio data to/from the codec port
interface
– Each channel can support a single USB
isochronous endpoint
– For I2S modes, either a single or multiple
USB isochronous endpoints can be used to
support multiple DACs/ADCs
• Codec Port Interface
– Configurable to support AC'97 1.X, AC'97 2.X
or I2S serial interface formats
– I2S modes can support a combination of up
to 4 DACs and/or 3 ADCs
– Can be configured as a general-purpose
serial interface
• I2C Interface
– Does not support a multimaster bus
environment
– Programmable to 100 kbit/s or 400 kbit/s
data transfer speeds
• Pulse Width Modulation (PWM) Output
– Programmable frequency range from 732.4
Hz to 93.75 kHz
– Programmable duty cycle
• General Characteristics
– Available in a 52-Pin TQFP Package
– On-chip phase-locked loop (PLL) with
internal oscillator is used to generate
internal clocks from a 6 MHz crystal input
– 3.3-V core and 5-V compatible input/output
buffers used for codec port interface
– Reset output available which is asserted for
both system and USB reset
– External MCU mode supports application
firmware development
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10 Introduction Copyright © 2001–2010, Texas Instruments Incorporated
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Product Folder Link(s): TUSB3200A
8052 Core
PWM
Counters
I
2
C
Control
Control/Status
Registers
Codec Port
Interface
2K x 8
SRAM
DMA0
DMA1
DMA2
DMA3
OEP
IEP
DMA Controller
and
USB Buffer Manager
4K ROM
8K RAM
USB Serial
OSC
PLL
ACG
Suspend
/Resume
Logic
PWM
I2C Bus
C-Port
Port3 Port1
USB
SOF
CLOCKS
6 MHz
Interface
Engine
TUSB3200A
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1.2 Functional Block Diagram
SLES018A–OCTOBER 2001–REVISED JULY 2010
Copyright © 2001–2010, Texas Instruments Incorporated Introduction 11
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PAH Package
MCLKO2
MCLKO
DV
SCL
PLLFILI
XTALI
XTALO
AV
SS
MCLKI
DV
PLLOEN
P1.0
P1.1
P1.2
DV
SS
P3.3
P3.4
P3.5
DV
Dd
P3.0
P3.1
SDA
CSCHNE
38
37
36
35
34
33
32
31
30
29
28
27
1
2
3
4
5
6
7
8
9
10
11
12
13
(TOP VIEW)
MCLKI2
SS
DDS
CDATI
DV
DD
CDATO
CSYNC
CSCLK
DV
SS
P1.7
P1.6
P1.5
P1.4
P1.3
DV
DDS
PLLFILO
AV
DD
PWMO
PLLO
DV
SS
PUR
DP
DM
DV
DD
MRESET
TEST
EXTEN
RSTO
XINT
TUSB3200A
USB Streaming Controller (STC)
52-pin TQFP
CRESET
39
52 45 41 40
42
51 50
4849
47
44
43
46
14 21 25 26
24
15
16
1817 19
22 23
20
TUSB3200A
SLES018A–OCTOBER 2001–REVISED JULY 2010
1.3 Terminal Assignments − Normal Mode
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12 Introduction Copyright © 2001–2010, Texas Instruments Incorporated
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PAH Package
MCLKO2
MCLKO
DV
SCL
51 50
PLLFILI
XTALI
XTALO
AV
SS
MCLKI
DV
MCURD
MCUAD0
MCUAD1
MCUAD2
DV
SS
MCUA10
MCUALE
MCUINTO
DV
DD
MCUA8
MCUA9
SDA
CSCHNE
38
37
36
35
34
33
32
31
30
29
28
27
1
2
3
4
5
6
7
8
9
10
11
12
13
(TOP VIEW)
MCLKI2
SS
DDS
CDATI
DV
DD
CDATO
CSYNC
CSCLK
DV
SS
MCUAD7
MCUAD6
MCUAD5
MCUAD4
MCUAD3
DV
DDS
PLLFILO
AV
DD
PWMO
PLLO
DV
SS
PUR
DP
DM
DV
DD
MRESET
TEST
EXTEN
RSTO
XINT
MCUWR
USB Streaming Controller (STC)
52-pin TQFP
CRESET
TUSB3200A
52 45 41 40
42
51 50
4849
47
44
43
46
14 21 25 26
24
15
16
1817 19
22 23
20
TQFP
Texas Instruments
PackageType
Peripheral Device
Universal Serial Bus
52 pins PAH
T
3200A
USB PAH
Commercial Temperature Range
C
TUSB3200A
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1.4 Terminal Assignments − External MCU Mode
SLES018A–OCTOBER 2001–REVISED JULY 2010
1.5 Ordering Information
Copyright © 2001–2010, Texas Instruments Incorporated Introduction 13
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1.6 Terminal Functions − Normal Mode
TERMINAL
NAME NO.
AV
AV
DD
SS
2 3.3-V Analog supply voltage
49 Analog ground
CSCLK 34 I/O Codec port interface serial clock: CSCLK is the serial clock for the codec port interface used to clock
CSYNC 35 I/O Codec port interface frame sync: CSYNC is the frame synchronization signal for the codec port
CDATO 36 I/O Codec port interface serial data output: See Section 1.9 for details. This signal uses a 5-V compatible
CDATI 38 I/O Codec port interface serial data input: See Section 1.9 for details. This signal uses a 5-V compatible
CRESET 39 I/O Codec port interface reset output: See Section 1.9 for details. This signal uses a 5-V compatible
CSCHNE 40 I/O Codec port interface secondary channel enable: See Section 1.9 for details. This signal uses a 5-V
DP 7 I/O USB differential pair data signal plus: DP is the positive signal of the bidirectional USB differential pair
DM 8 I/O USB differential pair data signal minus: DM is the negative signal of the bidirectional USB differential
DV
DV
DV
DD
DDS
SS
9, 21, 3.3-V digital supply voltage
37
27, 43 5-V Digital supply voltage
5, 16, Digital ground
33, 46
EXTEN 12 I External MCU mode enable: Input used to enable the device for the external MCU mode. This signal
MCLKI 47 I Master clock input: An input that can be used as the master clock for the codec port interface or the
MCLKI2 48 I Master clock input 2: An input that can be used as the master clock for the codec port interface or the
MCLKO 44 O Master clock output: The output of the ACG that can be used as the master clock for the codec port
MCLKO2 45 O Master clock output 2: An output that can be used as the master clock for the codec port interface and
MRESET 10 I Master reset: An active low asynchronous reset for the device that resets all logic to the default state.
Not Used 22 I This pin is not used in the normal mode. This signal should be tied to digital ground for normal
P1.0 24 I/O General-purpose I/O port 1 bit 0: A bidirectional I/O port. This signal uses a 5-V compatible
P1.1 25 I/O General-purpose I/O port 1 bit 1: A bidirectional I/O port. This signal uses a 5-V compatible
P1.2 26 I/O General-purpose I/O port 1 bit 2: A bidirectional I/O port. This signal uses a 5-V compatible
P1.3 28 I/O General-purpose I/O port 1 bit 3: A bidirectional I/O port. This signal uses a 5-V compatible
P1.4 29 I/O General-purpose I/O port 1 bit 4: A bidirectional I/O port. This signal uses a 5-V compatible
P1.5 30 I/O General-purpose I/O port 1 bit 5: A bidirectional I/O port. This signal uses a 5-V compatible
P1.6 31 I/O General-purpose I/O port 1 bit 6: A bidirectional I/O port. This signal uses a 5-V compatible
P1.7 32 I/O General-purpose I/O port 1 bit 7: A bidirectional I/O port. This signal uses a 5-V compatible
I/O DESCRIPTION
the CSYNC, CDATO, CDATI, CRESET and CSCHNE signals. This signal uses a 5-V compatible
TTL/LVCMOS input/output buffer.
interface. This signal uses a 5-V compatible TTL/LVCMOS input/output buffer.
TTL/LVCMOS input/output buffer.
TTL/LVCMOS input/output buffer.
TTL/LVCMOS input/output buffer.
compatible TTL/LVCMOS input/output buffer.
used to connect the TUSB3200A device to the universal serial bus.
pair used to connect the TUSB3200A device to the universal serial bus.
uses a 3.3-V TTL/LVCMOS input buffer.
source for MCLKO2. This signal uses a 5-V to 3.3-V level shifting input buffer.
source for MCLKO2. This signal uses a 5-V to 3.3-V level shifting input buffer.
interface and the codec. This signal uses a 3.3-V TTL/LVCMOS output buffer.
the codec. This clock signal can also be used as a miscellaneous clock. This signal uses a 3.3-V
TTL/LVCMOS output buffer.
This signal uses a 3.3-V TTL/LVCMOS input buffer.
operation.
TTL/LVCMOS input/output buffer with an internal 100-µA active pullup.
TTL/LVCMOS input/output buffer with an internal 100-µA active pullup.
TTL/LVCMOS input/output buffer with an internal 100-µA active pullup.
TTL/LVCMOS input/output buffer with an internal 100-µA active pullup.
TTL/LVCMOS input/output buffer with an internal 100-µA active pullup.
TTL/LVCMOS input/output buffer with an internal 100-µA active pullup.
TTL/LVCMOS input/output buffer with an internal 100-µA active pullup.
TTL/LVCMOS input/output buffer with an internal 100-µA active pullup.
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TERMINAL
NAME NO.
P3.0 14 I/O General-purpose I/O port 3 bit 0: A bidirectional I/O port. This signal uses a 5-V compatible
P3.1 15 I/O General-purpose I/O port 3 bit 1: A bidirectional I/O port. This signal uses a 5-V compatible
P3.3 18 I/O General-purpose I/O port 3 bit 3: A bidirectional I/O port. This signal uses a 5-V compatible
P3.4 19 I/O General-purpose I/O port 3 bit 4: A bidirectional I/O port. This signal uses a 5-V compatible
P3.5 20 I/O General-purpose I/O port 3 bit 5: A bidirectional I/O port. This signal uses a 5-V compatible
PLLFILI 52 I PLL loop filter input: Input to on-chip PLL from external filter components.
PLLFILO 1 O PLL loop filter output: Output from on-chip PLL to external filter components.
PLLO 4 O PLL output: The 48-MHz output of the PLL used for diagnostic purposes only. This signal uses a 3.3-V
PLLOEN 23 I PLL output enable: An input used to enable the PLLO output signal. This signal uses a 5-V compatible
PWMO 3 O PWM output: Output of the pulse width modulation circuit. PWMO This signal uses a 3.3-V to 5-V
PUR 6 O USB data signal plus pullup resistor connect: PUR is used to connect the pullup resistor on the DP
RSTO 13 O Reset output: Output that is active while the master reset input or the USB reset is active. This signal
SCL 42 O I2C interface serial clock: SCL is the clock signal for the I2C serial interface. This signal uses a 3.3-V to
SDA 41 I/O I2C interface serial data input/output: SDA is the bidirectional data signal for the I2C serial interface.
TEST 11 I Test mode enable: Input used to enable the device for the factory test mode. This signal uses a 3.3-V
XINT 17 I External interrupt: An active low input used by external circuitry to interrupt the on-chip 8052 MCU.
XTALI 51 I Crystal input: Input to the on-chip oscillator from an external 6-MHz crystal.
XTALO 50 O Crystal Output: Output from the on-chip oscillator to an external 6-MHz crystal.
I/O DESCRIPTION
TTL/LVCMOS input/output buffer with an internal 100-µA active pullup. Can also be used as UART
RxD.
TTL/LVCMOS input/output buffer with an internal 100-µA active pullup. Can also be used as UART
TxD.
TTL/LVCMOS input/output buffer with an internal 100-µA active pullup.
TTL/LVCMOS input/output buffer with an internal 100-µA active pullup.
TTL/LVCMOS input/output buffer with an internal 100-µA active pullup.
TTL/LVCMOS output buffer.
input buffer.
CMOS level shifting output buffer.
signal to 3.3-V or a 3-state. When the DP signal is connected to 3.3-V the host PC should detect the
connection of the TUSB3200A device to the universal serial bus. This signal uses a 3.3-V
TTL/LVCMOS output buffer.
uses a 3.3-V TTL/LVCMOS output buffer.
5-V TTL level shifting open drain output buffer.
This signal uses a 3.3-V to 5-VTTL level shifting open drain output buffer and a 5-V to 3.3-V TTL level
shifting input buffer.
TTL/LVCMOS input buffer.
This signal uses a 5-V compatible input buffer.
SLES018A–OCTOBER 2001–REVISED JULY 2010
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1.7 Terminal Functions − External MCU Mode
TERMINAL
NAME NO.
AV
AV
DD
SS
2 3.3-V Analog supply voltage
49 Analog ground
CSCLK 34 I/O Codec port interface serial clock: CSCLK is the serial clock for the codec port interface used to clock
CSYNC 35 I/O Codec port interface frame sync: CSYNC is the frame synchronization signal for the codec port
CDATO 36 I/O Codec port interface serial data output: See Section 1.9 for details. This signal uses a 5-V compatible
CDATI 38 I/O Codec port interface serial data input: See Section 1.9 for details. This signal uses a 5-V compatible
CRESET 39 I/O Codec port interface reset output: See Section 1.9 for details. This signal uses a 5-V compatible
CSCHNE 40 I/O Codec port interface secondary channel enable: See Section 1.9 for details. This signal uses a 5-V
DP 7 I/O USB differential pair data signal plus: DP is the positive signal of the bidirectional USB differential pair
DM 8 I/O USB differential pair data signal minus: DM is the negative signal of the bidirectional USB differential
DV
DV
DV
DD
DDS
SS
9, 21, 37 3.3-V digital supply voltage
27, 43 5-V Digital supply voltage
5, 16, 33, Digital ground
46
EXTEN 12 I External MCU mode enable: Input used to enable the device for the external MCU mode. This signal
MCLKI 47 I Master clock input: An input that can be used as the master clock for the codec port interface or the
MCLKI2 48 I Master clock input 2: An input that can be used as the master clock for the codec port interface or the
MCLKO 44 O Master clock output: The output of the ACG that can be used as the master clock for the codec port
MCLKO2 45 O Master clock output 2: An output that can be used as the master clock for the codec port interface and
MCUAD0 24 I/O MCU Multiplexed address/data bit 0: Multiplexed address bit 0/data bit 0 for external MCU access to
MCUAD1 25 I/O MCU multiplexed address/data bit 1: Multiplexed address bit 1/data bit 1 for external MCU access to
MCUAD2 26 I/O MCU multiplexed address/data bit 2: Multiplexed address bit 2/data bit 2 for external MCU access to
MCUAD3 28 I/O MCU multiplexed address/data bit 3: Multiplexed address bit 3/data bit 3 for external MCU access to
MCUAD4 29 I/O MCU multiplexed address/data bit 4: Multiplexed address bit 4/data bit 4 for external MCU access to
MCUAD5 30 I/O MCU multiplexed address/data bit 5: Multiplexed address bit 5/data bit 5 for external MCU access to
MCUAD6 31 I/O MCU multiplexed address/data bit 6: Multiplexed address bit 6/data bit 6 for external MCU access to
MCUAD7 32 I/O MCU multiplexed address/data bit 7: Multiplexed address bit 7/data bit 7 for external MCU access to
MCUA8 14 I MCU address bit 8: Multiplexed address bit 8 for external MCU access to the TUSB3200A external
MCUA9 15 I MCU address bit 9: Multiplexed address bit 9 for external MCU access to the TUSB3200A external
I/O DESCRIPTION
the CSYNC, CDATO, CDATI, CRESET and CSCHNE signals. This signal uses a 5-V compatible
TTL/LVCMOS input/output buffer.
interface. This signal uses a 5-V compatible TTL/LVCMOS input/output buffer.
TTL/LVCMOS input/output buffer.
TTL/LVCMOS input/output buffer.
TTL/LVCMOS input/output buffer.
compatible TTL/LVCMOS input/output buffer.
used to connect the TUSB3200A device to the universal serial bus.
pair used to connect the TUSB3200A device to the universal serial bus.
uses a 3.3-V TTL/LVCMOS input buffer.
source for MCLKO2. This signal uses a 5-V to 3.3-V level shifting input buffer.
source for MCLKO2. This signal uses a 5-V to 3.3-V level shifting input buffer.
interface and the codec. This signal uses a 3.3-V TTL/LVCMOS output buffer.
the codec. This clock signal can also be used as a miscellaneous clock. This signal uses a 3.3-V
TTL/LVCMOS output buffer.
the TUSB3200A external data memory space.
the TUSB3200A external data memory space.
the TUSB3200A external data memory space.
the TUSB3200A external data memory space.
the TUSB3200A external data memory space.
the TUSB3200A external data memory space.
the TUSB3200A I/O external data memory space.
the TUSB3200A external data memory space.
data memory space.
data memory space.
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TERMINAL
NAME NO.
MCUA10 18 I MCU address bit 10: Multiplexed address bit 10 for external MCU access to the TUSB3200A external
MCUALE 19 I MCU address latch enable: Address latch enable for external MCU access to the TUSB3200A external
MCUINTO 20 O MCU interrupt output: Interrupt output to be used for external MCU INTO input signal. All internal
MCURD 23 I MCU read strobe: Read strobe for external MCU read access to the TUSB3200A external data
MCUWR 22 I MCU write strobe: Write strobe for external MCU write access to the TUSB3200A external data
MRESET 10 I Master reset: An active low asynchronous reset for the device that resets all logic to the default state.
Not Used 4 O This pin is not used in the external MCU mode.
PLLFILI 52 I PLL loop filter input: Input to on-chip PLL from external filter components.
PLLFILO 1 O PLL loop filter output: Output to on-chip PLL from external filter components.
PUR 6 O USB data signal plus pullup resistor connect: PUR is used to connect the pullup resistor on the DP
PWMO 3 O PWM output: Output of the pulse width modulation circuit. This signal uses a 3.3-V to 5-V CMOS level
RSTO 13 O Reset output: Output that is active while the master reset input or the USB reset is active. This signal
SCL 42 O I2C interface serial clock: SCL is the clock signal for the I2C serial interface. This signal uses a 3.3-V
SDA 41 I/O I2C interface serial data input/output: SDA is the bidirectional data signal for the I2C serial interface.
TEST 11 I Test mode enable: Input used to enable the device for the factory test mode. This signal uses a 3.3-V
XINT 17 I External interrupt: An active low input used by external circuitry to interrupt the on-chip 8052 MCU.
XTALI 51 I Crystal input: Input to the on-chip oscillator from an external 6-MHz crystal.
XTALO 50 O Crystal output: Output from the on-chip oscillator to an external 6-MHz crystal.
I/O DESCRIPTION
data memory space.
data memory space.
TUSB3200A interrupt sources are ORed together to generate this output signal.
memory space.
memory space.
This signal uses a 3.3-V TTL/LVCMOS input buffer.
signal to 3.3-V or a 3-state. When the DP signal is connected to 3.3-V the host PC should detect the
connection of the TUSB3200A device to the universal serial bus. This signal uses a 3.3-V
TTL/LVCMOS output buffer.
shifting output buffer.
uses a 3.3-V TTL/LVCMOS output buffer.
to 5-V TTL level shifting open drain output buffer.
This signal uses a 3.3-V to 5-V TTL level shifting open drain output buffer and a 5-V to 3.3-V TTL level
shifting input buffer.
TTL/LVCMOS input buffer.
This signal uses a 5-V compatible input buffer.
SLES018A–OCTOBER 2001–REVISED JULY 2010
1.8 Device Operation Modes
The EXTEN and TEST pins define the mode that the TUSB3200A will be in after reset.
MODE EXTEN TEST
Normal mode – internal MCU 0 0
External MCU mode 1 0
Factory test 0 1
Factory test 1 1
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1.9 Terminal Assignments for Codec Port Interface Modes
The codec port interface has eight modes of operation that support AC97, I2S, and AIC codecs. There is
also a general-purpose mode that is not specific to a serial interface. The mode is programmed by writing
to the mode select field of the codec port interface configuration register 1 (CPTCNF1). The codec port
interface terminals CSYNC, CSCLK, CDATO, CDATI, CRESET, and CSCHNE take on functionality
appropriate to the mode programmed as shown in the following tables.
TERMINAL
NO. NAME
35 CSYNC CSYNC
34 CSCLK CSCLK
36 CDATO CDATO O DOUT O SD_OUT O SD_OUT O
38 CDATI CDATI I DIN I SD_IN I SD_IN1 I
39 CRESET CRESET O RESET O RESET O RESET O
40 CSCHNE NC
(1) Signal names and I/O direction are with respect to the TUSB3200A device. The signal names used for
the TUSB3200A terminals for the various codec port interface modes reflect the nomenclature used by
the codec devices.
(2) The CSYNC and CSCLK signals can be programmed as either an input or an output in the
general-purpose mode.
(3) NC indicates no connection for the terminal in a particular mode. The TUSB3200A device drives the
signal as an output for these cases.
(1)
GP AIC AC '97 v1.X AC '97 v2.X
MODE 0 MODE 1 MODE 2 MODE 3
(2)
I/O FS O SYNC O SYNC O
(2)
(3)
I/O SCLK O BIT_CLK I BIT_CLK I
O FC O NC
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(3)
O SD_IN2 I
TERMINAL
NO. NAME
35 CSYNC LRCK O LRCK O LRCK O LRCK O
34 CSCLK SCLK O SCLK O SCLK O SCLK O
36 CDATO SDOUT1 O SDOUT1 O SDOUT1 O SDOUT1 O
38 CDATI SDOUT2 O SDOUT2 O SDIN1 I SDOUT2 O
39 CRESET SDOUT3 O SDIN1 I SDIN2 I SDOUT3 O
40 CSCHNE SDIN1 I SDIN2 I SDIN3 I SDOUT4 O
I2S I2S I2S I2S
MODE 4 MODE 5 MODE 6 MODE 7
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2 Description
2.1 Architectural Overview
2.1.1 Oscillator and PLL
Using an external 6-MHz crystal, the TUSB3200A derives the fundamental 48-MHz internal clock signal
using an on-chip oscillator and PLL. Using the PLL output, the other required clock signals are generated
by the clock generator and adaptive clock generator.
2.1.2 Clock Generator and Sequencer Logic
Utilizing the 48-MHz input from the PLL, the clock generator logic generates all internal clock signals,
except for the codec port interface master clock (MCLK) and serial clock (CSCLK) signals. The
TUSB3200A internal clocks include the 48-MHz clock, a 24-MHz clock, a 12-MHz clock and a USB clock.
The USB clock also has a frequency of 12-MHz. The USB clock is the same as the 12-MHz clock when
the TUSB3200A is transmitting data and is derived from the data when the TUSB3200A is receiving data.
To derive the USB clock when receiving USB data, the TUSB3200A utilizes an internal digital PLL (DPLL)
that uses the 48-MHz clock.
The sequencer logic controls the access to the SRAM used for the USB endpoint configuration blocks and
the USB endpoint buffer space. The SRAM can be accessed by the MCU, USB buffer manager (UBM) or
DMA channels. The sequencer controls the access to the memory using a round robin fixed priority
arbitration scheme. This basically means that the sequencer logic generates grant signals for the MCU,
UBM and DMA channels at a predetermined fixed frequency.
SLES018A–OCTOBER 2001–REVISED JULY 2010
2.1.3 Adaptive Clock Generator (ACG)
The adaptive clock generator is used to generate a master clock output signal (MCLKO) to be used by the
codec port interface and the codec device. To synchronize the sample rate conversion of data by the
codec to the USB frame rate, the MCLKO signal generated by the adaptive clock generator must be used.
The synchronization of the MCLKO signal to the USB frame rate is controlled by the MCU by
programming the adaptive clock generator frequency value. The MCLKO frequency is monitored by the
MCU and updated as required. For asynchronous operation, an external source can be used to generate
a master clock input signal (MCLKI) to be used by the codec port interface. In this scenario, the codec
device should also use the same master clock signal (MCLKI).
2.1.4 USB Transceiver
The TUSB3200A provides an integrated transceiver for the USB port. The transceiver includes a
differential output driver, a differential input receiver and two single ended input buffers. The transceiver
connects to the USB DP and DM signal terminals.
2.1.5 USB Serial Interface Engine (SIE)
The serial interface engine logic manages the USB packet protocol requirements for the packets being
received and transmitted on the USB by the TUSB3200A device. For packets being received, the SIE
decodes the packet identifier field (PID) to determine the type of packet being received and to ensure the
PID is valid. For token packets and data packets being received, the SIE calculates the packet cycle
redundancy check (CRC) and compares the value to the CRC contained in the packet to verify that the
packet was not corrupted during transmission. For token packets and data packets being transmitted, the
SIE generates the CRC that is transmitted with the packet. For packets being transmitted, the SIE also
generates the synchronization field (SYNC) that is an eight bit filed at the beginning of each packet. In
addition, the SIE generates the correct PID for all packets being transmitted. Another major function of the
SIE is the overall serial-to-parallel conversion of the data packets being received and the parallel-to-serial
conversion of the data packets being transmitted.
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2.1.6 USB Buffer Manager (UBM)
The USB buffer manager provides the control logic that interfaces the SIE to the USB endpoint buffers.
One of the major functions of the UBM is to decode the USB function address to determine if the host PC
is addressing the TUSB3200A device USB peripheral function. In addition, the endpoint address field and
direction signal are decoded to determine which particular USB endpoint is being addressed. Based on
the direction of the USB transaction and the endpoint number, the UBM will either write or read the data
packet to/from the appropriate USB endpoint data buffer.
2.1.7 USB Frame Timer
The USB frame timer logic receives the start of frame (SOF) packet from the host PC each USB frame.
Each frame, the logic stores the 11-bit frame number value from the SOF packet in a register and asserts
the internal SOF signal. The frame number register can be read by the MCU and the value can be used
as a time stamp. For USB frames in which the SOF packet is corrupted or not received, the frame timer
logic will generate a pseudo start of frame (PSOF) signal and increment the frame number register.
2.1.8 USB Suspend and Resume Logic
The USB suspend and resume logic detects suspend and resume conditions on the USB. This logic also
provides the internal signals used to control the TUSB3200A device when these conditions occur. The
capability to resume operation from a suspend condition with a locally generated remote wake-up event is
also provided.
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2.1.9 MCU Core
The TUSB3200A uses an 8-bit microcontroller core that is based on the industry standard 8052. The MCU
is software compatible with the 8052, 8032, 80C52, 80C53, and 87C52 MCUs. The 8052 MCU is the
processing core of the TUSB3200A and handles all USB control, interrupt and bulk endpoint transfers. In
addition, the MCU can also be the source or sink for USB isochronous endpoint transfers.
2.1.10 MCU Memory
In accordance with the industry standard 8052, the TUSB3200A MCU memory is organized into program
memory, external data memory and internal data memory. A 4K byte boot ROM is used to download the
application code to an 8K byte RAM that is mapped to the program memory space. The external data
memory includes the USB endpoint configuration blocks, USB data buffers, and memory mapped
registers. The total external data memory space used is 2K bytes. A total of 256 bytes are provided for the
internal data memory.
2.1.11 USB Endpoint Configuration Blocks and Endpoint Buffer Space
The USB endpoint configuration blocks are used by the MCU to configure and operate the required USB
endpoints for a particular application. In addition to the control endpoint, the TUSB3200A supports a total
of seven in endpoints and seven out endpoints. A set of six bytes is provided for each endpoint to specify
the endpoint type, buffer address, buffer size, and data packet byte count.
The USB endpoint buffer space provided is a total of 1832 bytes. The space is totally configurable by the
MCU for a particular application. Therefore, the MCU can configure each buffer based on the total number
of endpoints to be used, the maximum packet size to be used for each endpoint, and the selection of
single or double buffering.
2.1.12 DMA Controller
Four DMA channels are provided to support the streaming of data for USB isochronous endpoints. Each
DMA channel can support one USB isochronous endpoint, either in or out. The DMA channels are used to
stream data between the USB endpoint data buffers and the codec port interface. The USB endpoint
number and direction can be programmed for each DMA channel. Also, the codec port interface time slots
to be serviced by each DMA channel can be programmed.
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2.1.13 Codec Port Interface
The TUSB3200A provides a configurable full-duplex bidirectional serial interface that can connect to a
codec or another device for streaming USB Isochronous data. The interface can be configured to support
several different industry standard protocols, including AC '97 1.X, AC '97 2.X, and I2S.
2.1.14 I2C Interface
The I2C interface logic provides a two-wire serial interface that can be used by the 8052 MCU to access
other ICs. The TUSB3200A is an I2C master device only and supports single byte or multiple byte read
and write operations. The interface can be programmed to operate at either 100 kbps or 400 kbps. The
protocol supports 8-bit or 16-bit addressing for accessing the I2C slave device memory locations.
2.1.15 Pulse Width Modulation (PWM) Output
The TUSB3200A provides a pulse width modulation output with programmable frequency and pulse width.
The frequency can be programmed from 732 Hz to 93.7 kHz with an 8-bit register. The pulse width of the
output signal is set with a 16-bit register.
2.1.16 General-Purpose IO Ports (GPIO)
The TUSB3200A provides two general-purpose IO ports that are controlled by the internal 8052 MCU. The
two ports, port 1 and port 3, are 8-bits and 5-bits, respectively. Note that port 3 bit locations 2, 6, and 7
have been used in the TUSB3200A for other functionality. Therefore these three bit locations are not
available for GPIO use. Port 3 bit location 2 has been used as the external interrupt (XINT) input to the
TUSB3200A. Port 3 bit locations 6 and 7 have been used as the external MCU write strobe and read
strobe inputs for the external MCU mode of operation.
SLES018A–OCTOBER 2001–REVISED JULY 2010
Each bit of both ports can be independently used as either an input or output. Hence each port bit consists
of an output buffer, an input buffer, and a pullup resistor (the pullups are not, strictly speaking, resistors;
they are 100-µA pullup active terminators). The pullup resistors on the GPIO pins can be disabled using
the PUDIS bit in the global control register.
2.1.16.1 External Pullup Macro
This is the equivalent circuit of the pullup "resistor", from the silicon library used to implement the
TUSB3200A.
Logic Symbol (Positive Logic)
Table 2-1. Electrical Characteristics of Pullup Resistors
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I
FI Input loading factor TAP 1.65 pF
FI Input loading factor PWRDN 2.50 SL
C
(1) When PWRDN = H, the current source is turned off.
Output current VO= 0 V –35.98 –90.67 –197.38 µA
O
Equivalent power dissipation capacitance 0.04 pF
pd
(1)
NOTE: For use with 3-V I/Os only.
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2.1.17 Interrupt Logic
The interrupt logic monitors the various conditions that can cause an interrupt and asserts the interrupt 0
(INT0) input to the 8052 MCU accordingly. All of the TUSB3200A internal interrupt sources and the
external interrupt (XINT) input are ORed together to generate the INT0 signal. An interrupt vector register
is provided that is used by the MCU to identify the interrupt source.
2.1.18 Reset Logic
An external master reset (MRESET) input signal that is asynchronous to the internal clocks is used to
reset the TUSB3200A logic. In addition to the master reset, the TUSB3200A logic can be reset with the
USB reset from the host PC. The TUSB3200A also provides a reset output (RSTO) signal that can be
used by external devices. This signal is asserted when either a master reset or USB reset occurs.
2.2 Device Operation
The operation of the TUSB3200A is explained in the following sections. For additional information on USB,
see the universal serial bus Specification version 1.1.
2.2.1 Clock Generation
The TUSB3200A requires an external 6-MHz crystal and PLL loop filter components connected as shown
in Figure 4-1 to derive all the clocks needed for both USB and codec operation. Using the low frequency
6-MHz crystal and generating the required higher frequency clocks internal to the IC is a major advantage
regarding EMI.
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2.2.2 Device Initialization
After a power-on reset is applied to the TUSB3200A device, the 8052 MCU will execute a boot loader
program from the 4k or 8k byte boot ROM mapped to the program memory space. During device
initialization, the boot loader program downloads the application program code from an external EEPROM
through the I2C interface. This requires that a binary image of the application code be written to the 8K
byte code RAM in the TUSB3200A device.
All memory mapped registers are initialized to a default value as defined in Section A, MCU Memory and
Memory- Mapped Registers. The TUSB3200A device powers up with a default function address of zero
and disconnected from the USB.
2.2.2.1 Boot Load from EEPROM
Loading the application code from an external serial EEPROM requires a preprogrammed memory device
containing an informative header and the application code. While the application code is being
downloaded, the TUSB3200A will remain disconnected from the USB. When the code download is
complete, execution of the application code should connect the TUSB3200A to the USB. In this situation,
the TUSB3200A will enumerate using the vendor ID and product ID contained in the application code.
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2.2.2.2 EEPROM Header
An EEPROM header precedes the application code in the EEPROM device. The bootloader uses the
information in the header as it loads the application code into RAM. Table 2-2 shows the format and
information contained in the header.
OFFSET TYPE SIZE VALUE
0 Signature 4 0x04513200
4 Header size 1 Header size
5 Version 1 Firmware version
6 1
EEPROM type
7 1
Data type
8 Data size 2 Data payload only size
10 2 Check sum of the data payload beginning at location Check Sum
Check sum
12 Data Data payload
SLES018A–OCTOBER 2001–REVISED JULY 2010
Table 2-2. EEPROM Header
0x01 = Reserved
0x02 = Reserved
0x03 = Reserved
0x04 = Reserved
0x05 = Reserved
0x06 = Reserved
0x07 = Reserved
0x08 = Reserved
0x09 = 24C32
0x0A =24C64
0x0B…0xFF = Reserved
0x01 = Application code
0x02…0xFF = Reserved
+ 2
The signature field is used for the detection of a EEPROM device connected to the TUSB3200A. The
header size field supports future updates of the header. Data begins right after the header. The version
field identifies the header version. The EEPROM type field identifies the specific EEPROM device being
used. The data type field describes the nature of data stored in the EEPROM (application code). The data
size field holds the length of the data payload starting from the end of the header. The check sum field
contains the check sum for the data payload portion of the EEPROM.
2.2.2.3 Application Code
Application firmware is stored as a binary image of the code. The binary image is mapped to the MCU
program memory space starting at address zero and is stored in the EEPROM as a continuous linear
block starting after the header information. A utility program is available that converts a file in Intel
hexidecimal format to a binary image data file and appends it to the header.
2.2.2.4 EEPROM Device Type
The TUSB3200A boot loader program supports several different types of serial EEPROM devices. The
boot loader program will automatically identify the EEPROM type from the header information and use the
correct serial interface protocol accordingly. The boot loader program uses an I2C slave device address of
A0h for the serial EEPROM device.
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These EEPPROM devices require an I2C device address in addition to a two byte data word address.
These devices require the full 7-bit I2C device address. Depending on the memory size of the EEPROM
device being used, the most significant three or four bits of the two byte data word address are don't care
bits. The EEPROM types supported are: 24C32 and 24C64
All of these EEPROM devices can be used for storing and loading application code. However most
applications will use devices which are capable of storing up to 8K bytes of program code.
2.2.3 USB Enumeration
USB enumeration is accomplished by interaction between the host PC software and the TUSB3200A
code. After power-on reset the boot loader code first reads the information from the EEPROM, then runs
the application code. The application code connects the TUSB3200A to the USB. During the enumeration,
the application code identifies the device as an application specific device and the host loads the
appropriate host driver(s). The boot loader and application code both use the CONT, SDW, and FRSTE
bits to control the enumeration process. The function connect (CONT) bit is set to a 1 by the MCU to
connect the TUSB3200A device to the USB. When this bit is set to a 1, the USB data plus pullup resistor
(PUR) output signal is enabled, which will connect the pullup on the PCB to the TUSB3200A 3.3-V digital
supply voltage. When this bit is cleared to a 0, the PUR output is in the 3-state mode. This bit is not
affected by a USB reset. The shadow the boot ROM (SDW) bit is set to a 1 by the MCU to switch the
MCU memory configuration from boot loader mode to normal operating mode. The function reset enable
(FRSTE) bit is set to a 1 by the MCU to enable the USB reset to reset all internal logic including the MCU.
However, the shadow the ROM (SDW) and the USB function connect (CONT) bits will not be reset. When
this bit is set, the reset output (RSTO) signal from the TUSB3200A device will also be active when a USB
reset occurs. This bit is not affected by USB reset.
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2.2.4 USB Reset
The TUSB3200A can detect a USB reset condition. When the reset occurs, the TUSB3200A responds by
setting the function reset (RSTR) bit in the USB status register (USBSTA). If the corresponding function
reset bit in the USB interrupt mask register is set, an MCU interrupt will be generated and the USB
function reset (0x17) vector will appear in the interrupt vector register (VECINT).
The function reset enable bit (FRSTE) in the USB control register (USBCTL) is used to control the extent
to which the internal logic is reset. The function reset enable bit is set to a 1 by the MCU to enable the
USB reset to reset all internal logic including the MCU. However, the shadow the ROM (SDW) and the
USB function connect (CONT) bits will not be reset. When this bit is set, the reset output (RSTO) signal
from the device will also be active when a USB reset occurs. This bit is not affected by USB reset.
2.2.5 USB Suspend and Resume Modes
All USB devices must support the suspend and resume modes. During the suspend mode, USB devices
that are bus powered must enter a low power suspend state. If the USB peripheral device is not bus
powered, then entering the low power suspend state is not required. A suspend condition is defined as a
constant idle state on the bus for more than 3.0ms. A USB device must actually be in the suspend state
no more than 10 ms after the suspend condition is detected. There are two ways for the TUSB3200A
device to exit the suspend mode, which are 1) detection of USB resume signaling and 2) detection of a
local remote wake-up event.
2.2.5.1 USB Suspend Mode
When a suspend condition is detected on the USB, the suspend/resume logic will set the function suspend
request bit (SUSR) in the USB status register. As a result, the function suspend request interrupt (SUSR)
will be generated. To enter the low power suspend state and disable all TUSB3200A device clocks, the
MCU firmware should set the idle mode bit (IDL), which is bit 0 in the MCU power control (PCON) register.
The instruction that sets the IDL bit will be the last instruction executed before the MCU goes to idle mode.
In idle mode, the MCU status is preserved. Note that the low power suspend state is a state in which the
TUSB3200A clocks are disabled and the IC will consume the least amount of power possible.
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2.2.5.2 USB Resume Mode
When the TUSB3200A is in a suspend state, any non-idle signaling on the USB will be detected by the
suspend/resume logic and device operation will be resumed. As a result of the resume signaling being
detected, the TUSB3200A clocks will be enabled, the function resume request bit (RESR) will be set, and
the function resume request interrupt (RESR) will be generated. The function resume request interrupt to
the MCU will automatically clear the idle mode bit in the PCON register. As a result, MCU operation will
resume with servicing the new interrupt. After the RETI from the ISR, the next instruction to be executed
will be the one following the instruction that set the IDL bit. Note that if the low power suspend state was
not entered by setting the IDL bit, the clocks will already be enabled and the IDL bit will already be
cleared.
2.2.5.3 USB Remote Wake-Up Mode
The TUSB3200A device has the capability to remotely wake-up the USB by generating resume signaling
upstream. Note that this feature must be enabled by the host software with the SET_FEATURE
DEVICE_REMOTE_WAKEUP request. The remote wake-up resume signaling should not be generated
until the suspend state has been active for at least 5 ms. In addition, the remote wake-up resume
signaling must be generated for at least 1ms but for no more than 15 ms. When the TUSB3200A is in the
low power suspend state, asserting the external interrupt input (XINT) to the device will enable the clocks
and generate the XINT interrupt. The XINT interrupt to the MCU will automatically clear the idle mode bit
in the PCON register. As a result, MCU operation will resume with servicing the new interrupt. After the
RETI from the ISR, the next instruction to be executed will be the one following the instruction that set the
IDL bit. Please note that if the low power suspend state was not entered by setting the IDL bit, the clocks
will already be enabled and the IDL bit will already be cleared. When the firmware sets the remote
wake-up request bit (RWUP) in the USB control register, the suspend/resume logic will generate the
resume signaling upstream on the USB.
SLES018A–OCTOBER 2001–REVISED JULY 2010
2.2.6 Power Supply Sequencing
Turning power supplies on and off with a mixed 5-V/3.3-V system is an important consideration. To avoid
possible damage to the TUSB3200A device, proper power sequencing is required. The turnon
requirement is that the 5-V and 3.3-V power supplies should start ramping from 0 volts and reach 95
percent of the final voltage values within 25 ms of each other. The turnoff requirement is that the 5-V and
3.3-V power supplies should start ramping from the steady-state voltage and reach 5 percent of these
values within 25 ms of each other. In addition, the difference between the two voltages should never
exceed 3.6-V while turning on or off. Normally, in a mixed voltage system, the 3.3-V supply is generated
from a voltage regulator running from the 5-V supply. A voltage regulator, such as the Texas Instrument's
TP7133, can be used to meet these power sequencing requirements.
2.2.7 USB Transfers
The TUSB3200A device supports all the USB data transfer types, which are control, bulk, interrupt, and
isochronous. In accordance with the USB specification, endpoint zero is reserved for the control endpoint
and is bidirectional. In addition to the control endpoint, the TUSB3200A is capable of supporting up to 7 in
endpoints and 7 out endpoints. These additional endpoints can be configured as bulk, interrupt, or
isochronous endpoints. The MCU handles all control, bulk, and interrupt endpoint transactions. In addition
the MCU can handle isochronous endpoint transactions, such as a rate feedback endpoint to the host PC.
However, for streaming isochronous data between the host PC and the codec interface port, the DMA
channels are provided.
2.2.7.1 Controls Transfers
Control transfers are used for configuration, command, and status communication between the host PC
and the TUSB3200A device. Control transfers to the TUSB3200A device use in endpoint 0 and out
endpoint 0. The three types of control transfers are control write, control write with no data stage, and
control read. Note that the control endpoint must be initialized before connecting the TUSB3200A device
to the USB.
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2.2.7.1.1 Control Write Transfer (Out Transfer)
The host PC uses a control write transfer to write data to the USB function. A control write transfer
consists of a setup stage transaction, at least one out data stage transaction, and an in status stage
transaction.
The steps to be followed for a control write transfer are as follows:
1. MCU initializes in endpoint 0 and out endpoint 0 by programming the appropriate USB endpoint
configuration blocks. This entails programming the buffer size and buffer base address, selecting the
buffer mode, enabling the endpoint interrupt, initializing the TOGGLE bit, enabling the endpoint, and
clearing the NACK bit for both in endpoint 0 and out endpoint 0.
Setup Stage Transaction:
2. The host PC sends a setup token packet followed by the setup data packet addressed to out endpoint
0. If the data is received without an error, then the UBM will write the data to the setup data packet
buffer, set the setup stage transaction (SETUP) bit to a 1 in the USB status register, return an ACK
handshake to the host PC, and assert the setup stage transaction interrupt. Note that as long as the
setup transaction (SETUP) bit is set to a 1, the UBM will return a NAK handshake for any data stage or
status stage transactions regardless of the endpoint 0 NACK or STALL bit values.
3. The MCU services the interrupt and reads the setup data packet from the buffer then decodes the
command. If the command is not supported or valid, the MCU should set the STALL bit in the out
endpoint 0 configuration byte and the in endpoint 0 configuration byte before clearing the setup stage
transaction (SETUP) bit. This will cause the device to return a STALL handshake for any data stage or
status stage transactions. After reading the data packet and decoding the command, the MCU should
clear the interrupt, which will automatically clear the setup stage transaction status bit. The MCU
should also set the TOGGLE bit in the out endpoint 0 configuration byte to a 1. For control write
transfers, the PID used by the host for the first out data packet will be a DATA1 PID and the TOGGLE
bit must match.
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Data Stage Transaction(s):
1. The host PC sends an out token packet followed by a data packet addressed to out endpoint 0. If the
data is received without an error, then the UBM will write the data to the endpoint buffer, update the
data count value, toggle the TOGGLE bit, set the NACK bit to a 1, return an ACK handshake to the
host PC, and assert the endpoint interrupt.
2. The MCU services the interrupt and reads the data packet from the buffer. To read the data packet,
the MCU first needs to obtain the data count value. After reading the data packet, the MCU should
clear the interrupt and clear the NACK bit to allow the reception of the next data packet from the host
PC.
3. If the NACK bit is set to a 1 when the data packet is received, the UBM simply returns a NAK
handshake to the host PC. IF the STALL bit is set to a 1 when the data packet is received, the UBM
simply returns A STALL handshake to the host PC. If a CRC or bit stuff error occurs when the data
packet is received, then no handshake is returned to the host PC.
Status Stage Transaction:
1. For in endpoint 0, the MCU updates the data count value to zero, sets the TOGGLE bit to 1, then
clears the NACK bit to a 0 to enable the data packet to be sent to the host PC. Note that for a status
stage transaction a null data packet with a DATA1 PID is sent to the host PC.
2. The host PC sends an in token packet addressed to in endpoint 0. After receiving the in token, the
UBM transmits a null data packet to the host PC. If the data packet is received without errors by the
host PC, then an ACK handshake is returned. The UBM will then toggle the TOGGLE bit, set the
NACK bit to a 1, and assert the endpoint interrupt.
3. If the NACK bit is set to a 1 when the in token packet is received, the UBM simply returns a NAK
handshake to the host PC. IF the STALL bit is set to a 1 when the in token packet is received, the
UBM simply returns a STALL handshake to the host PC. If no handshake packet is received from the
host PC, then the UBM prepares to retransmit the same data packet again.
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2.2.7.1.2 Control Write With No Data Stage Transfer (Out Transfer)
The host PC uses a control write transfer to write data to the USB function. A control write with no data
stage transfer consists of a setup stage transaction and an in status stage transaction. For this type of
transfer, the data to be written to the USB function is contained in the two byte value field of the setup
stage transaction data packet.
The steps to be followed for a control write with no data stage transfer are as follows:
1. MCU initializes in endpoint 0 and out endpoint 0 by programming the appropriate USB endpoint
configuration blocks. This entails programming the buffer size and buffer base address, selecting the
buffer mode, enabling the endpoint interrupt, initializing the TOGGLE bit, enabling the endpoint, and
clearing the NACK bit for both in endpoint 0 and out endpoint 0.
Setup Stage Transaction:
2. The host PC sends a setup token packet followed by the setup data packet addressed to out endpoint
0. If the data is received without an error then the UBM will write the data to the setup data packet
buffer, set the setup stage transaction (SETUP) bit to a 1 in the USB status register, return an ACK
handshake to the host PC, and assert the setup stage transaction interrupt. Note that as long as the
setup transaction (SETUP) bit is set to a 1, the UBM will return a NAK handshake for any data stage or
status stage transactions regardless of the endpoint 0 NACK or STALL bit values.
3. The MCU services the interrupt and reads the setup data packet from the buffer then decodes the
command. If the command is not supported or valid, the MCU should set the STALL bit in the out
endpoint 0 configuration byte and the in endpoint 0 configuration byte before clearing the setup stage
transaction (SETUP) bit. This will cause the device to return a STALL handshake for an data stage or
status stage transactions. After reading the data packet and decoding the command, the MCU should
clear the interrupt, which will automatically clear the setup stage transaction status bit.
SLES018A–OCTOBER 2001–REVISED JULY 2010
Data Stage Transaction:(s): N/A
Status Stage Transaction:
1. For in endpoint 0, the MCU updates the data count value to zero, sets the TOGGLE bit to 1, then
clears the NACK bit to a 0 to enable the data packet to be sent to the host PC. Note that for a status
stage transaction a null data packet with a DATA1 PID is sent to the host PC.
2. The host PC sends an in token packet addressed to in endpoint 0. After receiving the in token, the
UBM transmits a null data packet to the host PC. If the data packet is received without errors by the
host PC, then an ACK handshake is returned. The UBM will then toggle the TOGGLE bit, set the
NACK bit to a 1 and assert the endpoint interrupt.
3. If the NACK bit is set to a 1 when the in token packet is received, the UBM simply returns a NAK
handshake to the host PC. IF the STALL bit is set to a 1 when the in token packet is received, the
UBM simply returns a STALL handshake to the host PC. If no handshake packet is received from the
host PC, then the UBM prepares to retransmit the same data packet again.
2.2.7.1.3 Control Read Transfer (In Transfer)
The host PC uses a control read transfer to read data to the USB function. A control read transfer consists
of a setup stage transaction, at least one in data stage transaction and an out status stage transaction.
The steps to be followed for a control read transfer are as follows:
1. MCU initializes in endpoint 0 and out endpoint 0 by programming the appropriate USB endpoint
configuration blocks. This entails programming the buffer size and buffer base address, selecting the
buffer mode, enabling the endpoint interrupt, initializing the TOGGLE bit, enabling the endpoint, and
clearing the NACK bit for both in endpoint 0 and out endpoint 0.
Setup Stage Transaction:
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2. The host PC sends a setup token packet followed by the setup data packet addressed to out endpoint
0. If the data is received without an error then the UBM will write the data to the setup data packet
buffer, set the setup stage transaction (SETUP) bit to a 1 in the USB status register, return an ACK
handshake to the host PC and assert the setup stage transaction interrupt. Note that as long as the
setup transaction (SETUP) bit is set to a 1, the UBM will return a NAK handshake for any data stage or
status stage transactions regardless of the endpoint 0 NACK or STALL bit values.
3. The MCU services the interrupt and reads the setup data packet fro the buffer then decodes the
command. If the command is not supported or valid, the MCU should set the STALL bit in the out
endpoint 0 configuration byte and the in endpoint 0 configuration byte before clearing the setup stage
transaction (SETUP) bit. This will cause the device to return a STALL handshake for any data stage or
status stage transactions. After reading the data packet and decoding the command, the MCU should
clear the interrupt, which will automatically clear the setup stage transaction status bit. The MCU
should also set the TOGGLE bit in the in endpoint 0 configuration byte to a 1. For control read
transfers, the PID used by the host for the first in data packet will be a DATA1 PID.
Data Stage Transaction:(s):
1. The data packet to be sent to the host PC is written to the in endpoint 0 buffer by the MCU. The MCU
also updates the data count value then clears the in endpoint 0 NACK bit to a 0 to enable the data
packet to be sent to the host PC.
2. The host PC sends an in token packet addressed to the in endpoint 0. After receiving the in token, the
UBM transmits the data packet to the host PC. IF the data packet is received without errors by the host
PC, then an ACK handshake is returned. The UBM will then toggle the TOGGLE bit, set the NACK bit
to a 1 and assert the endpoint interrupt.
3. The MCU services the interrupt and prepares to send the next data packet to the host PC.
4. If the NACK bit is set to a 1 when the in token packet is received, the UBM simply returns a NAK
handshake to the host PC. IF the STALL bit is set to a 1 when the in token packet is received, the
UBM simply returns a STALL handshake to the host PC. If a no handshake packet is received from the
host PC, then the UBM prepares to retransmit the same data packet again.
5. MCU continues to send data packets until all data has been sent to the host PC.
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Status Stage Transaction:
1. For out endpoint 0, the MCU sets the TOGGLE bit to 1, then clears the NACK bit to a 0 to enable the
data packet to be sent to the host PC. Note that for a status stage transaction a null data packet with a
DATA1 PID is sent to the host PC.
2. The host PC sends an out token packet addressed to out endpoint 0. If the data packet is received
without an error then the UBM will update the data count value, toggle the TOGGLE bit, set the NACK
bit to a 1, return an ACK handshake to the host PC and assert the endpoint interrupt.
3. The MCU services the interrupt. If the status stage transaction completed successfully, then the MCU
should clear the interrupt and clear the NACK bit.
4. If the NACK bit is set to a 1 when the in data packet is received, the UBM simply returns a NAK
handshake to the host PC. If the STALL bit is set to a 1 when the in data packet is received, the UBM
simply returns a STALL handshake to the host PC. If a CRC or bit stuff error occurs when the data
packet is received, then no handshake is returned to the host PC.
2.2.7.2 Interrupt Transfers
The TUSB3200A supports interrupt data transfers both to and from the host PC. Devices that need to
send or receive a small amount of data with a specified service period should use the interrupt transfer
type. In endpoints 1 through 7 and out endpoints 1 through 7 can all be configured as interrupt endpoints.
2.2.7.2.1 Interrupt Out Transaction
The steps to be followed for an interrupt out transaction are as follows:
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1. MCU initializes one of the out endpoints as an out interrupt endpoint by programming the appropriate
2. The host PC sends an out token packet followed by a data packet addressed to the out endpoint. If the
3. The MCU services the interrupt and reads the data packet from the buffer. To read the data packet,
4. If the NACK bit is set to a 1 when the data packet is received, the UBM simply returns a NAK
SLES018A–OCTOBER 2001–REVISED JULY 2010
USB endpoint configuration block. This entails programming the buffer size and buffer base address,
selecting the buffer mode, enabling the endpoint interrupt, initializing the toggle bit, enabling the
endpoint, and clearing the NACK bit.
data is received without an error then the UBM will write the data to the endpoint buffer, update the
data count value, toggle the toggle bit, set the NACK bit to a 1, return an ACK handshake to the host
PC and assert the endpoint interrupt.
the MCU first needs to obtain the data count value. After reading the data packet, the MCU should
clear the interrupt and clear the NACK bit to allow the reception of the next data packet from the host
PC.
handshake to the host PC. If the STALL bit is set to a 1 when the data packet is received, the UBM
simply returns a STALL handshake to the host PC. If a CRC or bit stuff error occurs when the data
packet is received, then no handshake is returned to the host PC.
NOTE
In double buffer mode for interrupt out transactions, the UBM selects between the X and Y
buffer based on the value of the toggle bit. If the toggle bit is a 0, the UBM will write the data
packet to the X buffer. If the toggle bit is a 1, the UBM will write the data packet to the Y
buffer. When a data packet is received, the MCU could determine which buffer contains the
data packet by reading the toggle bit. However, when using double buffer mode, the
possibility exists for data packets to be received and written to both the X and Y buffer before
the MCU responds to the endpoint interrupt. In this case, by simply using the toggle bit to
determine which buffer contains the data packet would not work. Hence, in double buffer
mode, the MCU should read the X buffer NACK bit, the Y buffer NACK bit and the toggle bit
to determine the status of the buffers.
2.2.7.2.2 Interrupt In Transaction
The steps to be followed for an interrupt in transaction are as follows:
1. MCU initializes one of the in endpoints as an in interrupt endpoint by programming the appropriate
USB endpoint configuration block. This entails programming the buffer size and buffer base address,
selecting the buffer mode, enabling the endpoint interrupt, initializing the toggle bit, enabling the
endpoint, and setting the NACK bit.
2. The data packet to be sent to the host PC is written to the buffer by the MCU. The MCU also updates
the data count value then clears the NACK bit to a 0 to enable the data packet to be sent to the host
PC.
3. The host PC sends an in token packet addressed to the in endpoint. After receiving the in token, the
UBM transmits the data packet to the host PC. If the data packet is received without errors by the host
PC, then an ACK handshake is returned. The UBM will then toggle the toggle bit, set the NACK bit to a
1 and assert the endpoint interrupt.
4. The MCU services the interrupt and prepares to send the next data packet to the host PC.
5. If the NACK bit is set to a 1 when the in token packet is received, the UBM simply returns a NAK
handshake to the host PC. If the STALL bit is set to a 1 when the In token packet is received, the UBM
simply returns a STALL handshake to the host PC. If no handshake packet is received from the host
PC, then the UBM prepares to retransmit the same data packet again.
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In double buffer mode for interrupt in transactions, the UBM selects between the X and Y
buffer based on the value of the toggle bit. If the toggle bit is a 0, the UBM will read the data
packet from the X buffer. If the toggle bit is a 1, the UBM will read the data packet from the Y
buffer.
2.2.7.3 Bulk Transfers
The TUSB3200A supports bulk data transfers both to and from the host PC. Devices that need to send or
receive a large amount of data without a suitable bandwidth should use the bulk transfer type. In
endpoints 1 through 7 and out endpoints 1 through 7 can all be configured as bulk endpoints.
2.2.7.3.1 Bulk Out Transaction
The steps to be followed for a bulk out transaction are as follows:
1. MCU initializes one of the out endpoints as an out bulk endpoint by programming the appropriate USB
endpoint configuration block. This entails programming the buffer size and buffer base address,
selecting the buffer mode, enabling the endpoint interrupt, initializing the toggle bit, enabling the
endpoint, and clearing the NACK bit.
2. The host PC sends an out token packet followed by a data packet addressed to the out endpoint. If the
data is received without an error then the UBM will write the data to the endpoint buffer, update the
data count value, toggle the toggle bit, set the NACK bit to a 1, return an ACK handshake to the host
PC and assert the endpoint interrupt.
3. The MCU services the interrupt and reads the data packet from the buffer. To read the data packet,
the MCU first needs to obtain the data count value. After reading the data packet, the MCU should
clear the interrupt and clear the NACK bit to allow the reception of the next data packet from the host
PC.
4. If the NACK bit is set to a 1 when the data packet is received, the UBM simply returns a NAK
handshake to the host PC. If the STALL bit is set to a 1 when the data packet is received, the UBM
simply returns a STALL handshake to the host PC. If a CRC or bit stuff error occurs when the data
packet is received, then no handshake is returned to the host PC.
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NOTE
NOTE
In double buffer mode for bulk out transactions, the UBM selects between the X and Y buffer
based on the value of the toggle bit. If the toggle bit is a 0, the UBM will write the data packet
to the X buffer. If the toggle bit is a 1, the UBM will write the data packet to the Y buffer.
When a data packet is received, the MCU could determine which buffer contains the data
packet by reading the toggle bit. However, when using double buffer mode, data packets
may be received and written to both the X and Y buffer before the MCU responds to the
endpoint interrupt. In this case, simply using the toggle bit to determine which buffer contains
the data packet would not work. Hence, in double buffer mode, the MCU should read the X
buffer NACK bit, the Y buffer NACK bit, and the toggle bit to determine the status of the
buffers.
2.2.7.3.2 Bulk In Transaction
The steps to be followed for a bulk in transaction are as follows:
1. MCU initializes one of the in endpoints as an in bulk endpoint by programming the appropriate USB
endpoint configuration block. This entails programming the buffer size and buffer base address,
selecting the buffer mode, enabling the endpoint interrupt, initializing the toggle bit, enabling the
endpoint, and setting the NACK bit.
2. The data packet to be sent to the host PC is written to the buffer by the MCU. The MCU also updates
the data count value then clears the NACK bit to a 0 to enable the data packet to be sent to the host
PC.
30 Description Copyright © 2001–2010, Texas Instruments Incorporated
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