Texas Instruments TUSB2036VF Datasheet

Universal Serial Bus (USB) Version 1.1 Compliant

Integrated USB Transceivers

3.3-V Low Power ASIC Logic

One Upstream Port and 2-3 Programmable Downstream Ports – Total Number of Ports (2 or 3) Selected

by Input Pin

– Total Number of Permanently Connected

Ports Is Selected by 2 Input Pins

Two Power Source Modes – Self-Powered Mode – Bus-Powered Mode

All Downstream Ports Support Full-Speed and Low-Speed Operations

Power Switching and Overcurrent Reporting Is Provided Per Port or Ganged

Supports Suspend and Resume Operations

Suspend Status Terminal Available for External Logic Power Down

TUSB2036

2/3-PORT HUB FOR THE UNIVERSAL SERIAL BUS

WITH OPTIONAL SERIAL EEPROM INTERFACE

SLLS372 – MARCH 2000

Supports Custom Vendor ID and Product ID With External Serial EEPROM

3-State EEPROM Interface Allows EEPROM Sharing

Push-Pull Outputs for PWRON Eliminate the Need for External Pullup Resistors

Noise Filtering on OVRCUR Provides Immunity to Voltage Spikes

Supports 6 MHz Operation Through Crystal Input or 48 MHz Input Clock

Output Pin Available to Disable External Pullup Resister on DP0 for 3 ms After Reset or After Change on BUSPWR and Enable Easy Implementation of On-Board Bus/Self Power Dynamic Switching Circuitry

Available in 32-Pin LQFP Package With a

0.8 mm Pin Pitch (JEDEC – S-PQFP-G For Low-Profile Quad Flat Pack)

VF PACKAGE

(TOP VIEW)

SUSPND

MODE

XTAL1/CLK48

XTAL2

GND

31 30 29 28 27

32 26

DP0 DM0 VCC

RESET EECLK

EEDATA/GANGED

GND

BUSPWR

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1 2 3 4 5 6 7 8

910

11 12 13

PWRON1

OVRCUR1

DM1

14 15

DP1

PWRON2

DP0PUR

EXTMEM

24 23 22 21 20 19 18 17

DP2

DM2

OVRCUR2

NP3 NPINT1 NPINT0 OCPROT DP3 DM3 OVRCUR3 PWRON3

/PWRSW

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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TUSB2036 2/3-PORT HUB FOR THE UNIVERSAL SERIAL BUS WITH OPTIONAL SERIAL EEPROM INTERFACE

SLLS372 – MARCH 2000

description

The TUSB2036 hub is a 3.3-V CMOS device that provides up to three down stream ports in compliance with the USB version 1.1 specification. Because this device is implemented with a digital state machine instead of a microcontroller, no firmware programming is required. Fully compliant USB transceivers are integrated into the ASIC for all upstream and downstream ports. The downstream ports support both full-speed and low-speed devices by automatically setting the slew rate according to the speed of the device attached to the ports. The configuration of the BUSPWR introduction of the DP0 pull-up resistor disable pin, DP0PUR, makes it much easier to implement an on-board bus/self-power dynamic-switching circuitry. With the new function pin, the end equipment vendor can reduce the total board cost while adding additional product value.

The EXTMEM (Pin 26) enables or disables the optional EEPROM interface. When EXTMEM is high, the vendor and product IDs (VID and PID) use defaults, such that the message displayed during enumeration is

Purpose USB Hub

unused. If custom VID and PID descriptors are desired, the EXTMEM must be tied low (EXTMEM = 0) and a SGS Thompson M93C46 or equivalent EEPROM must be used to store the programmable VID, PID and GANGED EECLK and pin 6 as EEDATA respectively.

The TUSB2036 supports both bus-powered and self-powered modes. External power management devices such as the TPS2044 are required to control the 5 V-power source switching (on/of f) to the downstream ports and detect over-current condition from the downstream ports individually or ganged. Outputs from external power devices provide over-current inputs to the TUSB2036 OVRCUR pins in case of an over-current condition, the corresponding PWRON pins will be disabled by the TUSB2036. In the ganged mode, all PWRON signals transitions simultaneously , and any OVRCUR input can be used. In the nonganged mode, the PWRON outputs and OVRCUR

value. For this configuration, pin 5 and pin 6 function as the EEPROM interface signals with pin 5 as

. For this configuration, pin 6 functions as the GANGED input pin and the EECLK (Pin 5) is

inputs operate on a per port basis.

terminal selects either the bus-powered or the self-powered mode. The

General

The TUSB2036 provides the flexibility of using either a 6-MHz or a 48-MHz clock. The logic level of the MODE terminal controls the selection of the clock source. When MODE is low, the output of the internal APLL circuitry is selected to drive the internal core of the chip. When MODE is high, the XT AL1 input is selected as the input clock source and the APLL circuitry is powered down and bypassed. The internal oscillator cell is also powered down while MODE is high. For 6-MHz operation, TUSB2036 requires a 6-MHz clock signal on XT AL1 pin (with XT AL2 for a crystal) from which its internal APLL circuitry generates a 48 MHz internal clock to sample the data from the upstream port. For 48-MHz operation, the clock cannot be generated with a crystal, using the XT AL2 output, since the internal oscillator cell only supports fundamental frequency . If low power suspend and resume are desired, a passive crystal or resonator must be used, although the hub supports the flexibility of using any device that generates a 6-MHz clock. Because most oscillators cannot be stopped while power is on, their use prohibits low-power suspend, which depends on disabling the clock. When the oscillator is used, by connecting its output to XTAL1 terminal and leaving XTAL2 terminal open, its TTL output level can not exceed 3.6 V. If a 6 MHz oscillator is used, it must be stopped at logic low whenever SUSPND is high. For crystal or resonator implementations, the XT AL1 terminal is the input and the XTAL2 terminal is used as the feedback path. A sample crystal tuning circuit is shown in Figure 7.

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2/3-PORT HUB FOR THE UNIVERSAL SERIAL BUS

WITH OPTIONAL SERIAL EEPROM INTERFACE

SLLS372 – MARCH 2000

description (continued)

The hub silicon can accurately reflect the system port configuration by the NP3 and NPINT1-0 pins. When NP3 is low, the hub is configured as a 3-port hub; when it is high, the hub is configured as a 2-port hub. The NPINT1-0 pins tell the hub silicon how many ports have permanently attached devices, according to Table 1.

Table 1. System Port Configuration

TUSB2036

NPINT1-0 PORT AVAILABILITY

00 All ports are available through external USB connectors 00000000 01 Port 1 has a permanently attached device; ports 2 and 3 are externally available 00000010 10 Ports 1 and 2 have permanently attached devices; port 3 is externally available 000001 10 11 All ports have permanently attached devices NP3 high: 00000110

NP3

NPINT1-0 COMPOUND DEVICE OR NOT

00 Hub is not part of a compound device 0

01, 10, 11 Hub is part of a compound device 1

HUB DESCRIPTOR

DEVICE REMOVABLE FIELD (7–0)

low: 00001110

HUB DESCRIPTOR WITH HUB

CHARACTERISTICS FIELD BIT 2

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TUSB2036 2/3-PORT HUB FOR THE UNIVERSAL SERIAL BUS WITH OPTIONAL SERIAL EEPROM INTERFACE

SLLS372 – MARCH 2000

functional block diagram

DP0 DM0

USB

Transceiver

Suspend/Resume

Hub Repeater

Logic and

Frame Timer

SIE Interface

Logic

SIE

M U X

Serial

EEPROM

Interface

OSC/PLL

DP0PUR

SUSPND

XTAL1/CLK48

XTAL2

MODE

RESET

EXTMEM

EEDATA/GANGED

EECLK

Port 3

Logic

USB

Transceiver

20 19

Port 2 Logic

USB

Transceiver

16 15

DP2 DM2DP3 DM3

Port 1

Logic

Transceiver

12 11

DP1 DM1

USB

Hub/Device

Command

Decoder

Hub

Power

Logic

10, 14, 18

9, 13, 17

23, 22

OVRCUR1 – OVRCUR3

PWRON1 – PWRON3

NP3 NPINT(1–0)

OCPROT/PWRSW

BUSPWR

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I/O

DESCRIPTION

TUSB2036

2/3-PORT HUB FOR THE UNIVERSAL SERIAL BUS

WITH OPTIONAL SERIAL EEPROM INTERFACE

SLLS372 – MARCH 2000

Terminal Functions

TERMINAL

NAME VF

BUSPWR 8 I Power source indicator. BUSPWR is an active low input that indicates whether the downstream ports source

DM0 2 I/O Root port USB differential data minus. DM0 paired with DP0 constitutes the upstream USB port. DM1 – DM3 11, 15,19I/O USB differential data minus. DM1 – DM3 paired with DP1 – DP3 support up to three downstream USB ports.

DP0 1 I/O Root port USB differential data plus. DP0 paired with DM0 constitutes the upstream USB port. DP0PUR 27 O Pull-up resistor connection. Whenever a system reset occurs (RESET being driven to low, but not USB reset)

DP1 – DP3 12, 16,20I/O USB differential data plus. DP1 – DP3 paired with DM1 – DM3 support up to three downstream USB ports.

their power from the USB cable or a local power supply. For the bus-power mode, this pin should be pulled low, and for the self-powered mode, this pin should be pulled to 3.3 V. Input must not change dynamically during operation.

or any logic level change on BUSPWR terminal, DP0PUR output goes to inactive Low until the internal counter reaches a 3 ms time period. After the counter expires, DP0PUR is driven to the VCC (3.3 V) level thereafter until the next system reset event or BUSPWR

logic level change.

EECLK 5 O EEPROM serial clock. When EXTMEM is high, the EEPROM interface is disabled. The EECLK pin is disabled

EEDATA/ GANGED

EXTMEM 26 I EEPROM read enable. When EXTMEM is high, the serial EEPROM interface of the device is disabled. When

GND 7, 28 Ground. GND terminals must be tied to ground for proper operation. OCPROT/

PWRSW

OVRCUR1 – OVRCUR3

NOTES: 1. If the hub is implemented to be bus-powered (via BUSPWR tying to GND):

2. If the hub is implemented to be self-powered (via BUSPWR

6 I/O EEPROM serial data/power management mode indicator. When EXTMEM is high, EEDATA/GANGED

21 I Overcurrent Protection for bus-powered hub (active low). /Power Switching for self-powered hub (active low).

10, 14,18I overcurrent input. OVRCUR1 – OVRCUR3 are active low. For per-port overcurrent detection, one overcurrent

– TUSB2036 reports to the host that the hub end-product downstream ports are power-switched (this is required by the USB 1.1 Specification). Hub end product vendor has to ensure the actual end product implementation meets this specification requirement.

– Pin 21 acts as overcurrent protection (OCPROT protection implementation is reported through the wHubCharacteristics. D4-bit in the hub descriptor.

– When OCPROT wHubCharacteristics. D4-bit is set to 0.

– When OCPROT and the wHubCharacteristics. D4-bit is set to 1.

– TUSB2036 reports to the host that the hub end-product provides overcurrent protection to the downstream ports (this is required by the USB 1.1 Specification). Hub end product vendor has to ensure the actual end-product implementation meets this specification requirement.

– Pin 21 acts as power switching (PWRSW) implementation indication pin for the self-powered hub. The power switching implementation is reported through the bPwrOn2PwrGood field in the hub descriptor.

– When PWRSW ports and the bPwrOn2PwrGood is set to 50 units (100 ms).

– When PWRSW downstream ports and the bPwrOn2PwrGood is set to 0 units (0 ms).

and should be left floating (unconnected). When EXTMEM to the EEPROM with a 100 µA internal pulldown.

selects between gang and per-port power overcurrent detection for the downstream ports. When EXTMEM is low, EEDATA/GANGED acts as a serial data I/O for the EEPROM and is internally pulled down with a 100 µA pulldown. This standard TTL input must not change dynamically during operation.

EXTMEM respectively.

The pin has a different meaning for the bus or self-powered hub. If the pin is logic-high the internal pull-down is disabled. (see Notes 1 and 2 ).

input is available for each of the three downstream ports. In the ganged mode, any OVRCUR used and all OVRCUR logic. OVRCUR3

is low, the TUSB2036 reports to the host that the hub end-product has port power switching at the downstream

is high, the TUSB2036 reports to the host that the hub end-product does not have port power switching at the

is low, terminals 5 and 6 are configured as the clock and data pins of the serial EEPROM interface,

pins should be tied together. OVRCUR pins are active low inputs with noise filtering

has an internal pull-up that can be enabled for the 2-port operation.

) implementation indication pin for the bus-powered hub. The overcurrent

is low, the TUSB2036 reports to the host that the hub end-product provides overcurrent protection and the

is high, the TUSB2036 reports to the host that the hub end-product does not provide overcurrent protection

tying to 3.3-V VCC),:

is low, EECLK acts as a 3-state serial clock output

input may be

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TUSB2036

I/O

DESCRIPTION

2/3-PORT HUB FOR THE UNIVERSAL SERIAL BUS WITH OPTIONAL SERIAL EEPROM INTERFACE

SLLS372 – MARCH 2000

Terminal Functions (Continued)

TERMINAL

NAME VF

PWRON1 – PWRON3

RESET 4 I Reset. RESET is an active low TTL input with hysteresis and must be asserted at power up. When RESET

SUSPND 32 O Suspend status. SUSPND is an active high output available for external logic power-down operations. During

MODE 31 I Mode select. When MODE is low, the APLL output clock is selected as the clock source to drive the internal

NP3 24 I Number of ports is 3. Active low input. A logic 0 configures the system to use 3 ports. A logic 1, configures

NPINT1–0 23, 22 I Number of ports internal to hub system, which are permanently attached (see Table 1) VCC 3, 25 3.3-V supply voltage XTAL1/CLK48 30 I Crystal 1/48-MHz Clock Input. When MODE is low, XTAL1/CLK48 is a 6-MHz crystal input with 50% duty

XTAL2 29 O Crystal 2. XTAL2 is a 6-MHz crystal output. This terminal should be left open when using an oscillator.

9, 13,17O Power-on/-off control signals. PWRON1 – PWRON3 are active low, push-pull outputs. Push-pull outputs

eliminate the pullup resistors which open-drain outputs require. However, the external power switches that connect to these pins must be able to operate with 3.3-V inputs because these outputs cannot drive 5-V signals.

is asserted, all logic is initialized. Generally, a reset with a pulse width between 100 µs and 1 ms is recommended after 3.3-V VCC reaching its 90%. The clock signal must be active during the last 60 µs of the reset window.

the suspend mode, SUSPND is high. SUSPND is low for normal operation.

core of the chip and 6-MHz crystal or oscillator can be used. When MODE is high, the clock on XTAL1/CLK48 is selected as the clock source and 48-MHz oscillator or other on-board clock source can be used.

the system to use 2 ports.

cycle. An internal APLL generates the 48-MHz and 12-MHz clocks used internally by the ASIC logic. When MODE is high, XTAL1/CLK48 acts as the input of the 48 MHz clock and the internal APLL logic is bypassed.

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