Texas Instruments TSW14J56 User Manual
TSW14J56 JESD204B High-Speed Data Capture and
The TI TSW14J56 evaluation module (EVM) is a next generation pattern generator and data capture card
used to evaluate performances of the new TI JESD204B device family of high-speed analog-to-digital
converters (ADC) and digital-to-analog converters (DAC). For an ADC, by capturing the sampled data over
a JESD204B interface when using a high-quality, low-jitter clock, and a high-quality input frequency, the
TSW14J56 can be used to demonstrate datasheet performance specifications. Using Altera JESD204B IP
cores, the TSW14J56 can be dynamically configurable to support lane speeds from 600 Mbps to 12.5
Gbps, from 1 to 8 lanes, 1 to 16 converters, and 1 to 4 octets per frame with one firmware build. Together
with the accompanying High-Speed Data Converter Pro Graphic User Interface (GUI), it is a complete
system that captures and evaluates data samples from ADC EVMs and generates and sends desired test
patterns to DAC EVMs.
Trademarks
Windows is a trademark of Microsoft Corporation.
1 Functionality
The TSW14J56EVM has a single industry standard FMC connector that interfaces directly with TI
JESD204B ADC and DAC EVM's. When used with an ADC EVM, high-speed serial data is captured, deserialized and formatted by an Altera Arria V GZ FPGA. The data is then stored into an external DDR3
memory bank, enabling the TSW14J56 to store up to 2G 16-bit data samples. To acquire data on a host
PC, the FPGA reads the data from memory and transmits it on a high speed 32 bit parallel interface. An
onboard high-speed USB 3.0 to parallel converter bridges the FPGA interface to the host PC and GUI.
In pattern generator mode, the TSW14J56 generates desired test patterns for DAC EVMs under test.
These patterns are sent from the host PC over the USB interface to the TSW14J56. The FPGA stores the
data received into the board DDR3 memory module. The data from memory is then read by the FPGA and
transmitted to a DAC EVM across the JESD204B interface connector. The board contains a 100-MHz
oscillator used to generate the DDR3 reference clock and a option for a 10-MHz oscillator for general
purpose use. Figure 1 shows the TI ADS58J63EVM plugged into the TSW14J56EVM.
User's Guide
SLWU086C–November 2013–Revised January 2016
Pattern Generator Card User's Guide
SLWU086C–November 2013–Revised January 2016
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TSW14J56 JESD204B High-Speed Data Capture and Pattern Generator
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Functionality
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Figure 1. TSW14J56EVM Interfacing with an ADS58J63EVM
The major features of the TSW14J56 are:
• Subclasses: 0 (backward compatible), 1, 2
• Support for deterministic latency
• Serial lanes speeds up to 12.5 Gbps
• 10 routed transceiver channels
• 32 Gb DDR3 SDRAM (split into four independent 512×164 Gb SDRAMs, total of 512M samples each).
Quarter rate DDR3 controllers supporting up to 800-MHz operation
• 256K 16-bit samples of internal FPGA memory
• Supports 1.8, 2.5 and 3-V adjustable CMOS IO standard
• Option for general purposed 10 MH oscillator
• Onboard UCD90120A for power sequencing and monitoring
• Onboard Cypress CYUSB301X USB 3.0 device for JTAG and parallel interface to the FPGA
• Reference clocking for transceivers available through FMC port or SMAs
• Supported by TI HSDC PRO software
• FPGA firmware developed with Quartus II 14.0 and QSYS
2
TSW14J56 JESD204B High-Speed Data Capture and Pattern Generator
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+5 VDC Input
32Gb DDR III
RAM
ALTERA
Arria V GZ
(Firmware)
USB
to
Parallel
32 Bit 100 MHz
Parallel Interface
USB 3.0
Port
TSW14J56 EVM
ADC or DAC EVM
FMC Connector
JESD204B Interface
Data, Device CLK,
SYSREF, SYNC, GPIO
Power Sequencer/
Monitor
LDO and Switch
Regulators
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Figure 2 shows a block diagram of the TSW14J56 EVM.
Functionality
– JESD RX IP core with support for:
• USB and JTAG reconfigurable JESD core parameters: L, M, K, F, HD, S, and more
• ILA configuration data accessible through USB and JTAG
• Lane alignment and character replacement enabled or disabled through USB and JTAG
– JESD TX IP core with support for:
• USB and JTAG reconfigurable JESD core parameters: L, M, K, F, HD, S, and more
• ILA data configured through USB and JTAG
• Character replacement enabled or disabled through USB and JTAG
– Dynamically reconfigurable transceiver data rate. Operating range from 0.600 to 12.5 Gbps
Figure 2. TSW14J56 EVM Block Diagram
1.1 ADC EVM Data Capture
New TI high-speed ADCs and DACs now have high-speed serial data that meets the JESD204B standard.
These devices are generally available on an EVM that connects directly to the TSW14J56EVM. The
common connector between the EVMs and the TSW14J56EVM is a Samtec high-speed, high-density
FMC connector (SEAF-40-05.0-S-10-2-A-K) suitable for high-speed differential pairs up to 21 Gbps. A
common pinout for the connector across a family of EVMs has been established. At present, the interface
between the EVMs and the TSW14J56EVM has defined connections for 10 lanes of serial differential
data, two device clock pairs, two JESD204B SYSREF and SYNC pairs. There are four over-range singleended indicators, 12 spare general purpose CMOS I/O pins, and 29 spare differential LVDS or 58 singleended CMOS signals. The board has a spare SMA interface to the FPGA, 4 spare dip switches, a
pushbutton switch, several spare test points routed to the FPGA and 8 status LED's.
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Functionality
The data format for JESD204B ADCs and DACs is a serialized format, where individual bits of the data
are presented on the serial pairs commonly referred to as lanes. Devices designed around the JESD204B
spec can have up to 8 lanes for transmitting or receiving data. The firmware in the FPGA on the
TSW14J56 is designed to accommodate any of TI's ADC or DAC operating with any number of lanes from
1 to 8.
The GUI loads the FPGA with the appropriate firmware and a specific JESD204B configuration, based on
the ADC device selected in the device drop down window. Each ADC device that appears in this window
has an initialization file (.ini) associated to it. This .ini file contains JESD information, such as number of
lanes, number of converters, octets per frame, and other parameters. This information is loaded into the
FPGA registers after the user clicks on the capture button. After the parameters are loaded,
synchronization is established between the data converter and FPGA and valid data is then captured into
the on-board memory. See the High-Speed Data Capture Pro GUI Software User's Guide SLWU087 and
section 2.3 in the guide for more information. Several .ini files are available to allow the user to load predetermined ADC JESD204B interfaces. For example, if the user selects the ADC called
"ADS42JB69_LMF_421", the FPGA will be configured to capture data from the ADS42JB69EVM with the
ADC JESD interface configured for 4 lanes, 2 converters, and 1 octet per frame.
The TSW14J56 device can capture up to 2G 16-bit samples at a maximum line rate of 12.5 Gbps that are
stored inside the on-board DDR3 memory. To acquire data on a host PC, the FPGA reads the data from
memory and transmits parallel data to the on-board high-speed parallel-to-USB converter.
1.2 DAC EVM Pattern Generator
In pattern generator mode, the TSW14J56EVM generates desired test patterns for DAC EVMs under test.
These patterns are sent from the host PC over the USB interface to the TSW14J56. The FPGA stores the
data received into the on-board DDR3 memory. The data from the memory is then read by the FPGA,
converted to JESD204B serial format, then transmitted to a DAC EVM. The TSW14J56 can generate
patterns up to 2G 16-bit samples at a line rate up to 12.5 Gbps.
The GUI comes with several existing test patterns that can be download immediately. The GUI also has a
pattern generation tool that allows the user to generate a custom pattern, then download it to the on-board
memory. See the High-Speed Data Capture Pro Software User's Guide SLWU087 for more information.
Like the ADC capture mode, the DAC pattern generator mode uses .ini files to load predetermined
JESD204B interface information to the FPGA.
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2 Hardware Configuration
This section describes the various portions of the TSW14J56EVM hardware.
2.1 Power Connections
The TSW14J56EVM hardware is designed to operate from a single supply voltage of +5 V DC. The power
input is controlled by the on and off switch, SW6. Make sure this switch is in the off position before
inserting the provided power cable. Insert the connector end of the power cable into J11 of the EVM.
Connect the positive red wire end of the power cable to +5V +/- 0.3VDC output of a +5VDC power supply
rated for at least 3 Amps. Connect the negative black wire to the RETURN or GND of the power supply.
The board can also be powered up by providing +5 V DC to the red test point, TP34, and the return to any
black GND test point. The TSW14J56 draws approximately 0.6 A at power-up and 1.6 A when capturing 4
lanes of data from an ADS42JB69EVM at a line rate of 2.5 Gpbs.
4
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2.2 Switches, Jumpers, and LEDs
2.2.1 Switches and Pushbuttons
The TSW14J56 contains several switches and pushbuttons that enable certain functions on the board.
The description of the switches can be found in Table 1.
Table 1. Switch Description of the TSW14J56 Device
Component Description
SW6 Board main power switch
SW1 Spare dip switches that are connected to spare FPGA inputs
SW2 Spare pushbutton that are connected to spare FPGA inputs
SW7 (CPU RESET) FPGA hardware reset
SW10 Dip switch to set VAR adjustable regulator output voltage. Default is 1.8V
(switches 1,3,4 off, 2 on)
SW11 USB hardware reset
SW9 (UCD Reset) Power monitor U13 reset
2.2.2 Jumpers
The TSW14J56 contains several jumpers (JP) and solder jumpers (SJP) that enable certain functions on
the board. The description of the jumpers can be found in Table 2.
Hardware Configuration
Table 2. Jumper Description of the TSW14J56 Device
Component Description Default
SJP1 Power enable to general purpose 10-MHz oscillator Y1 1 to 2
SJP19 - SJP21 Address for spare I2C controller U42 2 to 3
SJ14, SJ15, SJ18 Sets programming mode for FPGA 2 to 3
SJ16, SJ17 Sets programming mode for FPGA 1 to 2
JP4, JP5, JP6, and JP7 USB or JTAG control of FPGA programming. Default is USB control 2 to 3
JP16
JP14 5-V supply for U39. Default is no power Not installed
JP15 U39 output used for power. Default is disabled Not installed
JP17 U39 enable. 2 to 3
SJP2, SJP3 Direction control for buffer U29. Default is B to A 2 to 3
SJP9 Direction control for buffer U30. Default is B to A 2 to 3
SJP10, SJP11 Direction control for buffer U41. Default is B to A 2 to 3
SJP12, SJ13 Direction control for buffer U28. Default is B to A 2 to 3
JP11 Programming mode for USB controller U33 1 to 2
JP12 Programming mode for USB controller U33 Not installed
JP13 Programming mode for USB controller U33 2 to 3
JP10 USB TCK routing option 2 to 3
J17 USB Controller U33 to Flash U36 interface. 3 to 4, 5 to 6, 7 to 8, 9 to 10
USB cable or internal 5-V power for USB interface. Default is USB
cable power
2 to 3
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