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TSW14J50
User Manual
18 pgs1.62 Mb0

Texas Instruments TSW14J50 User Manual

User's Guide
SLAU576–May 2014
TSW14J50 JESD204B High-Speed Data Capture and
Pattern Generator Card User's Guide
This user's guide describes the characteristics, operation, and use of the TSW14J50 JESD204B high­speed data capture and pattern generator card. This document details the TSW14J50 functionality, hardware configuration, the software start-up instructions, and how to download the firmware.
Contents
2.1 ADC EVM Data Capture .......................................................................................... 4
2.2 DAC EVM Pattern Generator (currently, function is not available)........................................... 5
3.1 Power Connections ................................................................................................ 5
3.2 Switches, Jumpers, and LEDs .................................................................................... 6
3.3 LEDs ................................................................................................................. 7
3.4 Connectors .......................................................................................................... 7
4 Software Start-Up .......................................................................................................... 10
4.1 Installation Instructions ........................................................................................... 10
4.2 USB Interface and Drivers ....................................................................................... 10
4.3 Downloading Firmware ........................................................................................... 12
List of Figures
1 TSW14J50EVM ............................................................................................................. 2
2 TSW14J50 EVM Block Diagram........................................................................................... 4
3 GUI Installation ............................................................................................................. 10
4 TSW14J50EVM Serial Number .......................................................................................... 11
5 High-Speed Data Converter Pro GUI Top Level....................................................................... 11
6 Hardware Device Manager................................................................................................ 12
7 Select ADC Firmware to be Loaded..................................................................................... 12
8 Download Firmware Error Message ..................................................................................... 13
9 HSDC Pro GUI with ADS42JBxx EVM GUI Tab....................................................................... 13
List of Tables
3 Power and Configuration LED Description of the TSW14J50 Device ................................................ 7
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Card User's Guide
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Introduction
1 Introduction
The TI TSW14J50 evaluation module (EVM) is a low-cost pattern generator and data capture card used to evaluate performances of the new TI JESD204B device family of high-speed analog-to-digital converters (ADC) and digital-to-analog converters (DAC). For an ADC, by capturing the sampled data over a JESD204B interface when using a high-quality, low-jitter clock, and a high-quality input frequency, the TSW14J50 can be used to demonstrate datasheet performance specifications. Using Altera JESD204B IP cores, the TSW14J50 can be dynamically configurable to support lane speeds from 600 Mbps to 6.5 Gbps, from 1 to 8 lanes, multiple converters, and multiple octets per frame with one firmware build. Together with the accompanying High-Speed Data Converter Pro Graphic User Interface (GUI), it is a complete system that captures and evaluates data samples from ADC EVMs and generates and sends desired test patterns to DAC EVMs.
2 Functionality
The TSW14J50EVM has a single industry-standard FMC connector that interfaces directly with TI JESD204B ADC and DAC EVMs. When used with an ADC EVM, high-speed serial data is captured, de­serialized and formatted by an Altera Arria V GX FPGA. The data is then stored into an external DDR3 memory bank, enabling the TSW14J50 to store up to 256M 16-bit data samples. To acquire data on a host PC, the FPGA reads the data from memory and transmits it on a serial peripheral interface (SPI). An onboard high-speed USB-to-SPI converter bridges the FPGA SPI interface to the host PC and GUI.
In pattern generator mode, the TSW14J50 generates desired test patterns for DAC EVMs under test. These patterns are sent from the host PC over the USB interface to the TSW14J50. The FPGA stores the data received into the board DDR3 memory module. The data from memory is then read by the FPGA and transmitted to a DAC EVM across the JESD204B interface connector. The board contains a 100-MHz oscillator used to generate the DDR3 reference clock.
Figure 1 shows the TI TSW14J50EVM.
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Microsoft, Windows are registered trademarks of Microsoft Corporation.
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TSW14J50 JESD204B High-Speed Data Capture and Pattern Generator SLAU576–May 2014 Card User's Guide
Figure 1. TSW14J50EVM
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The major features of the TSW14J50 are:
• Subclasses: 0 (backward compatible), 1
• Support for deterministic latency
• Serial lane speeds up to 6.5 Gbps (4 lanes or less)
• 8 routed transceiver channels
• 4Gb DDR3 SDRA. Quarter-rate DDR3 controllers supporting up to 667-MHz operation
• 256K 16-bit samples of internal FPGA memory
• Supports 1.8-V to 3.3-V CMOS IO standard
• Onboard FT4232HL USB device for JTAG and SPI emulation
• Reference clocking for transceivers available through FMC port or SMAs
• Supported by TI HSDC PRO software
• FPGA firmware developed with Quartus II 13.0 and QSYS
Functionality
– JESD RX IP core with support for:
• SPI and JTAG reconfigurable JESD core parameters: L, M, K, F, HD, S, and more
• ILA configuration data accessible through SPI and JTAG
• Lane alignment and character replacement enabled or disabled through SPI and JTAG
– JESD TX IP core with support for:
• SPI and JTAG reconfigurable JESD core parameters: L, M, K, F, HD, S, and more
• ILA data configured through SPI and JTAG
• Character replacement enabled or disabled through SPI and JTAG
– Dynamically reconfigurable transceiver data rate. Operating range from 0.600–6.5 Gbps
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Functionality
Figure 2 shows a block diagram of the TSW14J50 EVM.
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2.1 ADC EVM Data Capture
New TI high-speed ADCs and DACs now have high-speed serial data that meets the JESD204B standard. These devices are generally available on an EVM that connects directly to the TSW14J50EVM. The common connector between the EVMs and the TSW14J50EVM is a Samtec high-speed, high-density FMC connector (SEAF-40-05.0-S-10-2-A-K) suitable for high-speed differential pairs up to 21 Gbps. A common pinout for the connector across a family of EVMs has been established. At present, the interface between the EVMs and the TSW14J50EVM has defined connections for 8 lanes of serial differential data, two device clock pairs, two SYSREF pairs, two SYNC pairs, four over-range single-ended indicators, and 26 spare general purpose signals that can be used as CMOS I/O pins or differential LVDS signals. There are also two differential clock input pairs.
The data format for JESD204B ADCs and DACs is a serialized format, where individual bits of the data are presented on the serial pairs commonly referred to as lanes. Devices designed around the JESD204B specification can have up to 8 lanes for transmitting or receiving data. The firmware in the FPGA on the TSW14J50 is designed to accommodate any of TI's ADC or DAC operating with any number of lanes from 1 to 8.
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TSW14J50 JESD204B High-Speed Data Capture and Pattern Generator SLAU576–May 2014 Card User's Guide
Figure 2. TSW14J50 EVM Block Diagram
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The GUI loads the FPGA with the appropriate firmware and a specific JESD204B configuration, based on the ADC device selected in the device drop-down window. Each ADC device that appears in this window has an initialization file (.ini) associated to it. This .ini file contains JESD information, such as number of lanes, number of converters, octets per frame, and other parameters. This information is loaded into the FPGA registers after the capture button is clicked. After the parameters are loaded, synchronization is established between the data converter and FPGA and valid data is then captured into the on-board memory. See the High-Speed Data Capture Pro GUI Software User's Guide (SLWU087) and section 2.3 in the guide for more information. Several .ini files are available to allow the user to load pre-determined ADC JESD204B interfaces. For example, if the ADC called "ADS42JB69_LMF_421" is selected, the FPGA will be configured to capture data from the ADS42JB69EVM with the ADC JESD interface configured for 4 lanes, 2 converters, and 1 octet per frame.
The TSW14J50 device can capture up to 256M 16-bit samples at a maximum line rate of 6.5 Gbps that are stored inside the on-board DDR3 memory. To acquire data on a host PC, the FPGA reads the data from memory and transmits it on a serial protocol interface (SPI). An on-board high-speed USB-to-SPI converter bridges the FPGA SPI interface to the host PC and GUI.
2.2 DAC EVM Pattern Generator (currently, function is not available)
In pattern generator mode, the TSW14J50EVM generates desired test patterns for DAC EVMs under test. These patterns are sent from the host PC over the USB interface to the TSW14J50. The FPGA stores the data received into the on-board DDR3 memory. The data from the memory is then read by the FPGA, converted to JESD204B serial format, then transmitted to a DAC EVM. The TSW14J50 can generate patterns up to 256M 16-bit samples at a line rate up to 6.5 Gbps.
The GUI comes with several existing test patterns that can be download immediately. The GUI also has a pattern generation tool that allows the user to generate a custom pattern, then download it to the on-board memory. See the High-Speed Data Capture Pro Software User's Guide (SLWU087) for information. Like the ADC capture mode, the DAC pattern generator mode uses .ini files to load predetermined JESD204B interface information to the FPGA.
Functionality
3 Hardware Configuration
This section describes the various portions of the TSW14J50EVM hardware.
3.1 Power Connections
The TSW14J50EVM hardware is designed to operate from a single supply voltage of +5 V DC. Connect the +5 V DC output of the provided AC-to-DC power supply to J11 of the EVM. Connect the other power supply cable to 100-240 VAC, 50 to 60-Hz source. The board can also be powered up by providing +5 V DC to the red test point, TP34, and the return to any black GND test point. The TSW14J50 draws approximately 0.2 A at power-up and 0.8 A when capturing 4 lanes of data from an ADS42JB69EVM at a line rate of 2.5 Gpbs.
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Hardware Configuration
3.2 Switches, Jumpers, and LEDs
3.2.1 Switches and Pushbuttons
The TSW14J50 contains several switches and pushbuttons that enable certain functions on the board. The description of the switches is found in Table 1.
Table 1. Switch Description of the TSW14J50 Device
Component Description
SW1 Spare dip switches that are connected to spare FPGA inputs SW2 and SW3 Spare pushbutton that are connected to spare FPGA inputs SW4 (CPU RESET) FPGA hardware reset SW5 Sets IO voltage of FPGA bank 5. All switches open, IO voltage = 1.4 V . Default
is switch 2 closed only to provide 1.8 V to IO of Bank 5. SW5 switch 1 closed adds 0.2 V to 1.4 V IO voltage SW5 switch 2 closed adds 0.4 V to 1.4 V IO voltage SW5 switch 3 closed adds 0.8 V to 1.4 V IO voltage SW5 switch 4 closed adds 1.6 V to 1.4 V IO voltage
3.2.2 Jumpers
The TSW14J50 contains several jumpers (JP) and solder jumpers (SJP) that enable certain functions on the board. The description of the jumpers is found in Table 2.
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Table 2. Jumper Description of the TSW14J50 Device
Component Description Default
JP4, JP5, JP6, and JP7 USB or JTAG control of FPGA programming. Default is USB control. 1 to 2 JP8 USB or internal 5-V power for USB interface. Default is internal power. 1 to 2 JP9 USB 3.3 V regulator enable. Default is enabled. 2 to 3 SJP2 Direction control for PIO_9 signal of buffer U29. Default is B to A. 1 to 2 SJP3 Direction control for PRESENT signal of buffer U29. Default is B to A. 2 to 3 JP10 Selects either external power or Variable power (default) net for FPGA bank 5 IO 1 to 2
supply. This is the IO voltage set by SW5.
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TSW14J50 JESD204B High-Speed Data Capture and Pattern Generator SLAU576–May 2014 Card User's Guide
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