Texas Instruments TSB82AA2 (FireWire 800 PCI ctrl.) TSB82AA2 1394b OHCI-Lynx Controller Data Manual

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TSB82AA2-EP

1394b OHCI-Lynx Controller

Data Manual

Literature Number: SCPS167A

September 2006

Printed on Recycled Paper

Contents

Section Title Page

1 Introduction 1--1......................................................

1.1 Description 1--1.................................................

1.2 Features 1--3...................................................

1.3 Related Documents 1--4..........................................

1.4 Trademarks 1--4.................................................

1.5 Ordering Information 1--4.........................................

1.6 TSB82AA2-EP Data Manual Document History 1--4..................

2 Terminal Descriptions 2--1.............................................

3 TSB82AA2 Controller Programming Model 3--1..........................

3.1 PCI Configuration Registers 3--3...................................

3.2 Vendor ID Register 3--4..........................................

3.3 Device ID Register 3--4...........................................

3.4 Command Register 3--5..........................................

3.5 Status Register 3--6..............................................

3.6 Class Code and Revision ID Register 3--7..........................

3.7 Latency Timer and Class Cache Line Size Register 3--7..............

3.8 Header Type and BIST Register 3--8...............................

3.9 OHCI Base Address Register 3--8.................................

3.10 TI Extension Base Address Register 3--9...........................

3.11 CardBus Cis Base Address Register 3--10...........................

3.12 CardBus CIS Pointer Register 3--11.................................

3.13 Subsystem Identification Register 3--12..............................

3.14 Power Management Capabilities Pointer Register 3--12................

3.15 Interrupt Line and Pin Register 3--13................................

3.16 MIN_GNT and MAX_LAT Register 3--13.............................

3.17 OHCI Control Register 3--14.......................................

3.18 Capability ID and Next Item Pointer Register 3--14....................

3.19 Power Management Capabilities Register 3--15.......................

3.20 Power Management Control and Status Register 3--16................

3.21 Power Management Extension Register 3--16........................

3.22 Multifunction Select Register 3--17..................................

3.23 Miscellaneous Configuration Register 3--18..........................

3.24 Link Enhancement Control Register 3--19............................

3.25 Subsystem Access Register 3--21..................................

3.26 GPIO Control Register 3--22.......................................

4 OHCI Registers 4--1...................................................

4.1 OHCI Version Register 4--4.......................................

iii

4.2 GUID ROM Register 4--5.........................................

4.3 Asynchronous Transmit Retries Register 4--6.......................

4.4 CSR Data Register 4--6..........................................

4.5 CSR Compare Register 4--7......................................

4.6 CSR Control Register 4--7........................................

4.7 Configuration ROM Header Register 4--8...........................

4.8 Bus Identification Register 4--8....................................

4.9 Bus Options Register 4--9........................................

4.10 GUID High Register 4--10..........................................

4.11 GUID Low Register 4--10..........................................

4.12 Configuration ROM Mapping Register 4--11..........................

4.13 Posted Write Address Low Register 4--11............................

4.14 Posted Write Address High Register 4--12...........................

4.15 Vendor ID Register 4--13..........................................

4.16 Host Controller Control Register 4--14...............................

4.17 Self-ID Buffer Pointer Register 4--15................................

4.18 Self-ID Count Register 4--16.......................................

4.19 Isochronous Receive Channel Mask High Register 4--17...............

4.20 Isochronous Receive Channel Mask Low Register 4--18...............

4.21 Interrupt Event Register 4--19......................................

4.22 Interrupt Mask Register 4--21......................................

4.23 Isochronous Transmit Interrupt Event Register 4--23..................

4.24 Isochronous Transmit Interrupt Mask Register 4--24...................

4.25 Isochronous Receive Interrupt Event Register 4--25...................

4.26 Isochronous Receive Interrupt Mask Register 4--26...................

4.27 Initial Bandwidth Available Register 4--26............................

4.28 Initial Channels Available High Register 4--27........................

4.29 Initial Channels Available Low Register 4--27.........................

4.30 Fairness Control Register 4--28.....................................

4.31 Link Control Register 4--29.........................................

4.32 Node Identification Register 4--30...................................

4.33 PHY Layer Control Register 4--31...................................

4.34 Isochronous Cycle Timer Register 4--32.............................

4.35 Asynchronous Request Filter High Register 4--33.....................

4.36 Asynchronous Request Filter Low Register 4--35.....................

4.37 Physical Request Filter High Register 4--36..........................

4.38 Physical Request Filter Low Register 4--38...........................

4.39 Physical Upper Bound Register (Optional Register) 4--38..............

4.40 Asynchronous Context Control Register 4--39........................

4.41 Asynchronous Context Command Pointer Register 4--40..............

4.42 Isochronous Transmit Context Control Register 4--41..................

4.43 Isochronous Transmit Context Command Pointer Register 4--42........

4.44 Isochronous Receive Context Control Register 4--42..................

4.45 Isochronous Receive Context Command Pointer Register 4--44........

4.46 Isochronous Receive Context Match Register 4--45...................

5 TI Extension Registers 5--1............................................

5.1 DV Timestamp Enhancements 5--1................................

5.2 MPEG2 Timestamp Procedure 5--1................................

5.3 Isochronous Receive Digital Video Enhancements 5--2...............

5.4 Isochronous Receive Digital Video Enhancements Register 5--2.......

5.5 Link Enhancement Register 5--4...................................

5.6 Timestamp Offset Register 5--6....................................

6 GPIO Interface 6--1....................................................

7 Serial EEPROM Interface 7--1..........................................

8 Electrical Characteristics 8--1..........................................

8.1 Absolute Maximum Ratings Over Operating Temperature Ranges 8--1.

8.2 Recommended Operating Conditions 8--2..........................

8.3 Electrical Characteristics Over Recommended Operating Conditions 8--3

8.4 Switching Characteristics for PCI Interface 8--3......................

8.5 Switching Characteristics for PHY-Link Interface 8--3.................

9 Mechanical Information 9--1...........................................

List of Illustrations

Figure Title Page

2--1 Terminal Assignments 2--1...........................................

3--1 TSB82AA2 Block Diagram 3--2.......................................

6--1 GPIO Logic Diagram 6--1............................................

List of Tables

Table Title Page

2--1 Signals Sorted by Terminal Number 2--2...............................

2--2 Signal Names Sorted Alphanumerically to Terminal Number 2--3..........

2--3 Power Supply Terminals 2--4.........................................

2--4 Reset and Miscellaneous Terminals 2--4...............................

2--5 32-Bit PCI Bus Terminals 2--5........................................

2--6 PCI 64-Bit Bus Extension Terminals 2--7...............................

2--7 PHY-Link Interface Terminals 2--8.....................................

3--1 Bit Field Access Tag Descriptions 3--1.................................

3--2 PCI Configuration Register Map 3--3..................................

3--3 Command Register Description 3--5...................................

3--4 Status Register Description 3--6......................................

3--5 Class Code and Revision ID Register Description 3--7...................

3--6 Latency Timer and Class Cache Line Size Register Description 3--7.......

3--7 Header Type and BIST Register Description 3--8........................

3--8 OHCI Base Address Register Description 3--8..........................

3--9 TI Base Address Register Description 3--9.............................

3--10 CardBus CIS Base Address Register Description 3--10...................

3--11 CardBus CIS Pointer Register Description 3--11.........................

3--12 Subsystem Identification Register Description 3--12......................

3--13 Interrupt Line and Pin Register Description 3--13.........................

3--14 MIN_GNT and MAX_LAT Register Description 3--13......................

3--15 OHCI Control Register Description 3--14................................

3--16 Capability ID and Next Item Pointer Register Description 3--14.............

3--17 Power Management Capabilities Register Description 3--15...............

3--18 Power Management Control and Status Register Description 3--16.........

3--19 Power Management Extension Register Description 3--16.................

3--20 Multifunction Select Register 3--17.....................................

3--21 Miscellaneous Configuration Register 3--18.............................

3--22 Link Enhancement Control Register Description 3--19....................

3--23 Subsystem Access Register Description 3--21...........................

3--24 GPIO Control Register Description 3--22................................

4--1 OHCI Register Map 4--1.............................................

4--2 OHCI Version Register Description 4--4................................

4--3 GUID ROM Register Description 4--5..................................

4--4 Asynchronous Transmit Retries Register Description 4--6................

4--5 CSR Control Register Description 4--7.................................

4--6 Configuration ROM Header Register Description 4--8....................

vii

4--7 Bus Options Register Description 4--9.................................

4--8 Configuration ROM Mapping Register Description 4--11...................

4--9 Posted Write Address Low Register Description 4--11....................

4--10 Posted Write Address High Register Description 4--12....................

4--11 Vendor ID Register Description 4--13...................................

4--12 Host Controller Control Register Description 4--14........................

4--13 Self-ID Count Register Description 4--16................................

4--14 Isochronous Receive Channel Mask High Register Description 4--17.......

4--15 Isochronous Receive Channel Mask Low Register Description 4--18........

4--16 Interrupt Event Register Description 4--19...............................

4--17 Interrupt Mask Register Description 4--21...............................

4--18 Isochronous Transmit Interrupt Event Register Description 4--23...........

4--19 Isochronous Receive Interrupt Event Register Description 4--25............

4--20 Initial Bandwith Available Register Description 4--26......................

4--21 Initial Channels Available High Register Description 4--27.................

4--22 Initial Channels Available Low Register Description 4--27..................

4--23 Fairness Control Register Description 4--28.............................

4--24 Link Control Register Description 4--29.................................

4--25 Node Identification Register Description 4--30...........................

4--26 PHY Control Register Description 4--31.................................

4--27 Isochronous Cycle Timer Register Description 4--32......................

4--28 Asynchronous Request Filter High Register Description 4--33..............

4--29 Asynchronous Request Filter Low Register Description 4--35..............

4--30 Physical Request Filter High Register Description 4--36...................

4--31 Physical Request Filter Low Register Description 4--38...................

4--32 Asynchronous Context Control Register Description 4--39.................

4--33 Asynchronous Context Command Pointer Register Description 4--40.......

4--34 Isochronous Transmit Context Control Register Description 4--41..........

4--35 Isochronous Receive Context Control Register Description 4--42...........

4--36 Isochronous Receive Context Match Register Description 4--45............

5--1 TI Extension Register Map 5--1.......................................

5--2 Isochronous Receive Digital Video Enhancements Register Description 5--2

5--3 Link Enhancement Register Description 5--4...........................

5--4 Timestamp Offset Register Description 5--6............................

7--1 Serial EEPROM Map 7--2............................................

viii

1 Introduction

This chapter provides an overview of the Texas Instruments TSB82AA2 device and its features.

1.1 Description

The TSB82AA2 OHCI-Lynx is a discrete 1394b link-layer device, which has been designed to meet the demanding requirements of today’s 1394bus designs. The TSB82AA2 device is capable of exceptional 800M bits/s performance; thus, providing the throughput and bandwidth to move data efficiently and quickly between the PCI and 1394 buses. The TSB82AA2 device also provides outstanding ultra-low power operation and intelligent power management capabilities. The device provides the IEEE 1394 link function and is compatible with 100M bits/s, 200M bits/s, 400M bits/s, and 800M bits/s serial bus data rates.

The TSB82AA2 improved throughput and increased bandwidth make it ideal for today’s high-end PCs and open the door for the development of S800 RAID- and SAN-based peripherals.

The TSB82AA2 OHCI-Lynx operates as the interface between a 33-MHz/64-bit or 33-MHz/32-bit PCI local bus and a compatible 1394b PHY-layer device (such as the TSB81BA3 device) that is capable of supporting serial data rates at 98.304M, 196.608M, 393.216M, or 786.432M bits/s (referred to as S100, S200, S400, or S800 speeds, respectively). When acting as a PCI bus master, the TSB82AA2 device is capable of multiple cacheline bursts of data, which can transfer at 264M bytes/s for 64-bit transfers or 132M bytes/s for 32-bit transfers after connecting to the memory controller.

Due to the high throughput potential of the TSB82AA2 device, it possible to encounter large PCI and legacy 1394 bus latencies, which can cause the 1394 data to be overrun. To overcome this potential problem, the TSB82AA2 implements deep transmit and receive FIFOs (see Section 1.2, Features, for FIFO size information) to buffer the 1394 data, thus preventing possible problems due to bus latency. This also ensures that the device can transmit and receive sustained maximum size isochronous or asynchronous data payloads at S800.

The TSB82AA2 device implements other performance enhancements to improve overall performance of the device, such as: a highly tuned physical data path for enhanced SBP-2 performance, physical post writing buffers, multiple isochronous contexts, and advanced internal arbitration.

The TSB82AA2 device also implements hardware enhancements to better support digital video (DV) and MPEG data stream reception and transmission. These enhancements are enabled through the isochronous receive digital video enhancements register at TI extension offset A80h (see Section 5.4, Isochronous Receive Digital Video Enhancements Register). These enhancements include automatic time stamp insertion for transmitted DV and MPEG-formatted streams and common isochronous packet (CIP) header stripping for received DV streams.

The CIP format is defined by the IEC 61883-1:1998 specification. The enhancements to the isochronous data contexts are implemented as hardware support for the synchronization timestamp for both DV and audio/video CIP formats. The TSB82AA2 device supports modification of the synchronization timestamp field to ensure that the value inserted via software is not stale—that is, less than the current cycle timer when the packet is transmitted.

The TSB82AA2 performance and enhanced throughput make it an excellent choice for today’s 1394 PC mark et; however, the portable, mobile, and even today’s des ktop PCs power management schemes continue to require devices to use less and less power, and Texas Instrument’s 1394 OHCI-Lynx product line has continued to raise the bar by providing the lowest power 1394 link-layers in the industry. The TSB82AA2 device represents the next evolution of Texas Instruments commitment to meet the challenge of power-sensitive applications. The TSB82AA2 device has ultra-low operational power requirements and intelligent power management capabilities that allow it to autonomously conserve power based on the device usage.

One of the key elements for reducing the TSB82AA2 operational power requirements is Texas Instrument’s advanced CMOS process and the implementation of an internal 1.8-V core, which is supplied by an improved integrated 3.3-V to 1.8-V voltage regulator. The TSB82AA2 device implements a next generation voltage regulator which is more

1--1

efficient than its predecessors, thus providing an overall reduction in the device’s operational power requirements especially when operating in D3 and D3

hot/cold

power states as specified in the PC 2001 Design Guide requirements and the PCI Power Management

using auxiliary power. In fact, the TSB82AA2 device fully supports D0, D1, D2,

cold

Specification. PME wake event support is subject to operating system support and implementation.

As required by the 1394 Open Host Controller Interface Specification (OHCI) and IEEE Std 1394a--2000, internal control registers are memory-mapped and nonprefetchable. The PCI configuration header is accessed through configuration cycles as specified by the PCI Local Bus Specification, and provides plug-and-play (PnP) compatibility. Furthermore, the TSB82AA2 device is fully compliant with the latest PCI Local Bus Specification, PCI Bus Power

Management Interface Specification, IEEE Draft Std 1394b, IEEE Std 1394a--2000, and 1394 Open Host Controller Interface Specification (see Section 1.3, Related Documents, for a complete list).

1--2

1.2 Features

The TSB82AA2-EP device supports the following features:

• Controlled Baseline

-- One Assembly/Test Site, One Fabrication Site

• Extended Temperature Performance of --40°Cto85°C

• Enhanced Diminishing Manufacturing Sources (DMS) Support

• Enhanced Product-Change Notification

• Qualification Pedigree

• Single 3.3-V supply (1.8-V internal core voltage with regulator)

• 3.3-V and 5-V PCI signaling environments

• Serial bus data rates of 100M bits/s, 200M bits/s, 400M bits/s, and 800M bits/s

• Physical write posting of up to three outstanding transactions

• Serial ROM or boot ROM interface supports 2-wire serial EEPROM devices

• 33-MHz/64-bit and 33-MHz/32-bit selectable PCI interface

• Multifunction terminal (MFUNC terminal 1):

†

-- PCI_CLKRUN

protocol per the PCI Mobile Design Guide

-- General-purpose I/O

-- CYCLEIN/CYCLEOUT for external cycle timer control for customized synchronization

• PCI burst transfers and deep FIFOs to tolerate large host latency:

-- Transmit FIFO—5K asynchronous

-- Transmit FIFO—2K isochronous

-- Receive FIFO—2K asynchronous

-- Receive FIFO—2K isochronous

• D0, D1, D2, and D3 power states and PME

events per the PCI Bus Power Management Interface

Specification

• Programmable asynchronous transmit threshold

• Isochronous receive dual-buffer mode

• Out-of-order pipelining for asynchronous transmit requests

• Register access fail interrupt when the PHY SYSCLK is not active

• Initial bandwidth available and initial channels available registers

• Digital video and audio performance enhancements

• Fabricated in advanced low-power CMOS process

• Packaged in 144-terminal LQFP (PGE)

†

Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

1--3

1.3 Related Documents

• 1394 Open Host Controller Interface Specification (Revision 1.2)

• IEEE Standard for a High Performance Serial Bus (IEEE Std 1394--1995)

• IEEE Standard for a High Performance Serial Bus—Amendment 1 (IEEE Std 1394a-2000)

• P1394b Draft Standard for High Performance Serial Bus (Supplement)

• PC 2001 Design Guide

• PCI Bus Power Management Interface Specification (Revision 1.1)

• PCI Local Bus Specification (Revision 2.3)

• Serial Bus Protocol 2 (SBP--2)

• Microsoft Windows Logo Program System and Device Requirements (Version 0.5)

• Microsoft Windows Logo Program Desktop and Mobile PC Requirements (Version 1.1)

• Digital Interface for Consumer Electronic Audio/Video Equipment Draft (Version 2.1) (IEC 61883)

1.4 Trademarks

OHCI-Lynx is a trademark of Texas Instruments.

Intel is a trademark of Intel Corporation.

Other trademarks are the property of their respective owners.

1.5 Ordering Information

ORDERING NUMBER NAME VO LTA G E PACKAGE

TSB82AA2IPGEEP OHCI-Lynxt PCI-Based IEEE 1394 Host Controller,

Enhanced Plastic

3.3V-, 5V-tolerant I/Os PGE

1.6 TSB82AA2-EP Data Manual Document History

DATE REVISION PAG E PARAGRAPH DESCRIPTION

09/2003 Initial release

1--4

2 Terminal Descriptions

This section provides the terminal descriptions for the TSB82AA2 device. Figure 2--1 shows the signal assigned to each terminal in the package. Table 2--1 and Table 2--2 provide a cross-reference between each terminal number and the name of the signal on that terminal. Table 2--1 is arranged in terminal number order, and Table 2--2 lists the signals in alphanumerical order.

PCI_AD42 PCI_AD41 PCI_AD40

GND PCI_AD39 PCI_AD38 PCI_AD37 PCI_AD36

CCP

PCI_AD35 PCI_AD34 PCI_AD33 PCI_AD32

GND

PHY_D7

PHY_D6

PHY_D5

GND

PHY_D4 PHY_D3

PHY_D2 PHY_D1

PHY_D0

PHY_CTL1

PHY_CTL0

PHY_LCLK

GND

PHY_PCLK

GND

PHY_LREQ

PHY_LINKON

PHY_PINT

PHY_LPS

PCI_AD45

PCI_AD44

PCI_AD43

106

107

108

109 110

111 112 113 114

115 116

117 118

119 120 121 122

123 124

125 126

127 128 129 130

131 132

133 134

135 136 137 138

139 140

141 142

143 144

1234567891011121314151617181920212223242526272829303132333435

105

104

103

102

101

100

PCI_AD50

PCI_AD49

PCI_AD48

GND

PCI_AD47

PCI_AD46

PCI_AD53

PCI_AD52

PCI_AD51

PCI_AD54

PCI_AD56

PCI_AD55

GND

CCP

PCI_AD57

PCI_AD59

PCI_AD58

REG18

PCI_AD60

PCI_AD62

PCI_AD61

PCI_AD63

GND

PCI_PAR64

PCI_C/BE4

GND

PCI_C/BE6

PCI_C/BE5

PCI_C/BE7

PCI_REQ64

71 70

69 68

67 66

65 64

63 62

61 60

59 58

57 56

55 54

53 52

51 50

49 48

47 46

45 44

43 42

41 40

39 38

PCI_ACK64 PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 GND

BE0

PCI_C/ PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12

CCP

PCI_AD13 PCI_AD14

GND PCI_AD15 PCI_C/

BE1

PCI_PAR PCI_SERR

PCI_PERR

PCI_ST

PCI_DEVSEL

PCI_TRDY GND V

PCI_IRDY PCI_FRAME PCI_C/

BE2

PCI_AD16 PCI_AD17

MFUNC

REG_EN

SCL

SDA

PCI_RST

PCI_INTA

PCI_GNT

PCI_REQ

PCI_PME

REG18

PCI_AD31

PCI_AD30

PCI_AD28

PCI_AD29

CCP

GND

G_RST

GND

PCI_CLK

Figure 2 --1. Terminal Assignments

PCI_AD27

PCI_AD26

PCI_AD25

PCI_AD24

PCI_C/BE3

PCI_IDSEL

PCI_AD23

PCI_AD22

GND

PCI_AD21

PCI_AD18

PCI_AD20

PCI_AD19

2--1

Table 2--1. Signals Sorted by Terminal Number

NO. TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME

1 MFUNC 37 PCI_AD17 73 PCI_REQ64 109 PCI_AD42

2 REG_EN 38 PCI_AD16 74 PCI_C/BE7 11 0 PCI_AD41

3 SCL 39 PCI_C/BE2 75 V

4 SDA 40 PCI_FRAME 76 GND 112 GND

5 PCI_INTA 41 PCI_IRDY 77 PCI_C/BE6 113 PCI_AD39

6 PCI_RST 42 V

78 PCI_C/BE5 114 PCI_AD38

7 G_RST 43 GND 79 PCI_C/BE4 11 5 PCI_AD37

8 V

44 PCI_TRDY 80 PCI_PAR64 11 6 PCI_AD36

9 GND 45 PCI_DEVSEL 81 GND 117 V

10 PCI_CLK 46 PCI_STOP 82 PCI_AD63 118 PCI_AD35

11 NC 47 PCI_PERR 83 PCI_AD62 11 9 PCI_AD34

12 PCI_GNT 48 PCI_SERR 84 PCI_AD61 120 PCI_AD33

13 PCI_REQ 49 PCI_PAR 85 PCI_AD60 121 PCI_AD32

14 PCI_PME 50 PCI_C/BE1 86 V

15 V

51 PCI_AD15 87 REG18 123 PHY_D7

16 REG18 52 GND 88 PCI_AD59 124 PHY_D6

17 PCI_AD31 53 PCI_AD14 89 PCI_AD58 125 PHY_D5

18 PCI_AD30 54 PCI_AD13 90 PCI_AD57 126 V

19 PCI_AD29 55 V

CCP

91 V

CCP

20 PCI_AD28 56 PCI_AD12 92 PCI_AD56 128 PHY_D4

21 V

CCP

57 PCI_AD11 93 GND 129 PHY_D3

22 GND 58 PCI_AD10 94 PCI_AD55 130 PHY_D2

23 PCI_AD27 59 PCI_AD9 95 PCI_AD54 131 PHY_D1

24 PCI_AD26 60 PCI_AD8 96 PCI_AD53 132 PHY_D0

25 PCI_AD25 61 PCI_C/BE0 97 PCI_AD52 133 PHY_CTL1

26 PCI_AD24 62 V

98 PCI_AD51 134 PHY_CTL0

27 PCI_C/BE3 63 GND 99 PCI_AD50 135 V

28 PCI_IDSEL 64 PCI_AD7 100 PCI_AD49 136 PHY_LCLK

29 PCI_AD23 65 PCI_AD6 101 PCI_AD48 137 GND

30 PCI_AD22 66 PCI_AD5 102 V

31 V

67 PCI_AD4 103 GND 139 V

32 GND 68 PCI_AD3 104 PCI_AD47 140 GND

33 PCI_AD21 69 PCI_AD2 105 PCI_AD46 141 PHY_LREQ

34 PCI_AD20 70 PCI_AD1 106 PCI_AD45 142 PHY_LINKON

35 PCI_AD19 71 PCI_AD0 107 PCI_AD44 143 PHY_PINT

36 PCI_AD18 72 PCI_ACK64 108 PCI_AD43 144 PHY_LPS

111 PCI_AD40

CCP

122 GND

127 GND

138 PHY_PCLK

2--2

Table 2--2. Signal Names Sorted Alphanumerically to Terminal Number

TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME NO.

GND 9 PCI_AD17 37 PCI_AD53 96 PHY_CTL0 134

GND 22 PCI_AD18 36 PCI_AD54 95 PHY_CTL1 133

GND 32 PCI_AD19 35 PCI_AD55 94 PHY_D0 132

GND 43 PCI_AD20 34 PCI_AD56 92 PHY_D1 131

GND 52 PCI_AD21 33 PCI_AD57 90 PHY_D2 130

GND 63 PCI_AD22 30 PCI_AD58 89 PHY_D3 129

GND 76 PCI_AD23 29 PCI_AD59 88 PHY_D4 128

GND 81 PCI_AD24 26 PCI_AD60 85 PHY_D5 125

GND 93 PCI_AD25 25 PCI_AD61 84 PHY_D6 124

GND 103 PCI_AD26 24 PCI_AD62 83 PHY_D7 123

GND 112 PCI_AD27 23 PCI_AD63 82 PHY_LCLK 136

GND 122 PCI_AD28 20 PCI_CLK 10 PHY_LINKON 142

GND 127 PCI_AD29 19 PCI_C/BE0 61 PHY_LPS 144

GND 137 PCI_AD30 18 PCI_C/BE1 50 PHY_LREQ 141

GND 140 PCI_AD31 17 PCI_C/BE2 39 PHY_PCLK 138

G_RST 7 PCI_AD32 121 PCI_C/BE3 27 PHY_PINT 143

MFUNC 1 PCI_AD33 120 PCI_C/BE4 79 REG_EN 2

NC 11 PCI_AD34 11 9 PCI_C/BE5 78 REG18 16

PCI_ACK64 72 PCI_AD35 11 8 PCI_C/BE6 77 REG18 87

PCI_AD0 71 PCI_AD36 11 6 PCI_C/BE7 74 SCL 3

PCI_AD1 70 PCI_AD37 11 5 PCI_DEVSEL 45 SDA 4

PCI_AD2 69 PCI_AD38 11 4 PCI_FRAME 40 V

PCI_AD3 68 PCI_AD39 11 3 PCI_GNT 12 V

PCI_AD4 67 PCI_AD40 111 PCI_IDSEL 28 V

PCI_AD5 66 PCI_AD41 11 0 PCI_INTA 5 V

PCI_AD6 65 PCI_AD42 109 PCI_IRDY 41 V

PCI_AD7 64 PCI_AD43 108 PCI_PAR 49 V

PCI_AD8 60 PCI_AD44 107 PCI_PAR64 80 V

PCI_AD9 59 PCI_AD45 106 PCI_PERR 47 V

PCI_AD10 58 PCI_AD46 105 PCI_PME 14 V

PCI_AD11 57 PCI_AD47 104 PCI_REQ 13 V

PCI_AD12 56 PCI_AD48 101 PCI_REQ64 73 V

PCI_AD13 54 PCI_AD49 100 PCI_RST 6 V

PCI_AD14 53 PCI_AD50 99 PCI_SERR 48 V

PCI_AD15 51 PCI_AD51 98 PCI_STOP 46 V

PCI_AD16 38 PCI_AD52 97 PCI_TRDY 44 V

CCP

102

126

135

139

117

2--3

The terminals are grouped in tables by functionality, such as PCI system function and power supply function (see

Table 2--3 through Table 2--7). The terminal numbers are also listed for convenient reference.

Table 2--3. Power Supply Terminals

TERMINAL

NAME NO.

9, 22, 32, 43,

52, 63, 76, 81,

GND

93, 103, 112,

122, 127, 137,

140

REG18

16 87

REG_EN 2 I

8, 15, 31, 42,

62, 75, 86,

102, 126, 135,

139

CCP

21, 55, 91, 117 --

O DESCRIPTION

-- Ground terminals. These terminals must be tied together to the low-impedance circuit board ground plane.

The REG18 terminals are connected to the internal 1.8-V core voltage. They provide a mechanism to provide local bypass for the internal core voltage or to externally provide the 1.8 V to the core if the internal

-regulator is disabled.

Regulator enable. When this terminal is low, the internal regulator is enabled and generates the 1.8-V internal core voltage from the 3.3-V supply voltage. If it is disabled, then 1.8 V must be provided to the REG18 terminals for normal operation.

3.3-V power supply terminals. A parallel combination of high frequency decoupling capacitors near each terminal is suggested, such as 0.1 µF and 0.001 µF. Lower frequenc y 10- µ F filtering capacitors are also

-recommended. They must be tied to a low-impedance point on the circuit board.

PCI signaling clamp voltage power input. PCI signals are clamped per the PCI Local Bus Specification.In addition, if a 5-V ROM is used, then the V

terminal must be connected to 5 V.

CCP

Table 2--4. Reset and Miscellaneous Terminals

TERMINAL

NAME NO.

G_RST 7 I

PCI_RST 6 I

MFUNC 1 I/O

SCL 3 I/O

SDA 4 I/O

O DESCRIPTION

Global power reset. This reset brings all of the TSB82AA2 internal registers to their default states, including those registers not reset by PCI_RST input (PCI_CLK) is required before deasserting G_RST

. When G_RST is asserted, the device is completely nonfunctional. A valid clock

to reset some device functionality. Additionally, G_RST

must be asserted a minimum of 2 ms after both 3.3 V and 1.8 V are valid at the device.

When implementing wake capabilities from the 1394 host controller, it is necessary to implement two resets to the TSB82AA2 device. G_RST PCI bus RST

is designed to be a one-time power-on reset, and PCI_RST must be connected to the

PCI reset. When this bus reset is asserted, the TSB82AA2 device places all output buffers in a high-impedance state and resets all internal registers except device power management context and vendor-specific bits initialized by host power-on software. When PCI_RST is asserted, the device is completely nonfunctional. This terminal must be connected to PCI bus RST

Multifunction terminal. MFUNC is a multifunction terminal whose function is selected via the multifunction select register:

Bits 2--0

Function 000 General-purpose input/output (GPIO) 001 CYCLEIN 010 CYCLEOUT 011 PCI_CLKRUN

100--111 Reserved

Serial clock. This terminal provides the SCL serial clock signaling.

ROM is implemented: Connect terminal 3 to the SCL terminal on the ROM; the 2.7-kΩ resistor pulls this signal to the ROM V

. (SDA is implemented as open-drain.)

ROM is not implemented. Connect terminal 3 to ground with a 220-Ω resistor.

Serial data. This terminal provides the SDA serial data signaling. This terminal is sampled at G_RST to determine if a serial ROM is implemented; thus if no ROM is implemented, then this terminal must be connected to ground.

ROM is implemented: Connect terminal 4 to the SDA terminal on the ROM; the 2.7-kΩ resistor pulls this signal to the ROM V

. (SDA is implemented as open-drain.)

ROM is not implemented. Connect terminal 4 to ground with a 220-Ω resistor.

2--4

TERMINAL

NAME NO.

PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD17 PCI_AD16 PCI_AD15 PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 PCI_AD10 PCI_AD9 PCI_AD8 PCI_AD7 PCI_AD6 PCI_AD5 PCI_AD4 PCI_AD3 PCI_AD2 PCI_AD1 PCI_AD0

PCI_C/BE0 PCI_C/

BE1

PCI_C/

BE2

PCI_C/

BE3

PCI_CLK 10 I

PCI_DEVSEL 45 I/O

PCI_FRAME 40 I/O

PCI_GNT 12 I

PCI_IDSEL 28 I

PCI_INTA 5 O

PCI_IRDY 41 I/O

17 18 19 20 23 24 25 26 29 30 33 34 35 36 37 38 51 53 54 56 57 58 59 60 64 65 66 67 68 69 70 71

61 50 39 27

I/O

Table 2--5. 32-Bit PCI Bus Terminals

O DESCRIPTION

PCI address/data bus for the lower DWORD. These signals make up the multiplexed PCI address and data bus for the lower 32 bits on the PCI interface. During the address phase of a PCI cycle, AD31--AD0 contain a 32-bit address or other destination information. During the data phase, AD31--AD0 contain data.

PCI bus commands and byte enables for lower DWORD. The command and byte enable signals are multiplexed on the same PCI terminals. During the address phase of a bus cycle, PCI_C/BE3 define the bus command. During the data phase, this 4-bit bus is used as byte enables for the lower 32 bits of data.

PCI bus clock. Provides timing for all transac tions on the PCI bus. All PCI signals are sampled at the rising edge of PCI_CLK.

PCI device select. The TSB82AA2 device asserts this signal to claim a PCI cycle as thetargetdevice. As a PCI initiator,the TSB82AA2 device monitors this signal until a target responds. If no target responds before time-out occurs, then the TSB82AA2 device terminates the cycle with an initiator abort.

PCI cycle frame. This signal is driven by the initiator of a PCI bus cycle. PCI_FRAME is asserted to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. When PCI_FRAME is deasserted, the PCI bus transaction is in the final data phase.

PCI bus grant. This signal is driven by the PCI bus arbiter to grant the TSB82AA2 device access to the PCI bus after the current data transaction has completed. This signal may or may not follow a PCI bus request, depending upon the PCI bus parking algorithm.

Initialization device select. PCI_IDSEL selects the TSB82AA2 device during configuration space accesses. PCI_IDSEL can be connected to 1 of the upper 24 PCI address lines on the PCI bus.

Interrupt signal. This output indicates interrupts from the TSB82AA2 device to the host. This terminal is implemented as open-drain.

PCI initiator ready. PCI_IRDY indicates the ability of the PCI bus initiator to complete the current data phase of the transaction. A data phase is completed upon a rising edge of PCI_CLK where both PCI_IRDY PCI_TRDY

are asserted.

--PCI_C/BE0

and

2--5

Table 2--5. 32-Bit PCI Bus Terminals (Continued)

TERMINAL

NAME NO.

PCI_PAR 49 I/O

PCI_PERR 47 I/O

PCI_PME 14 O

PCI_REQ 13 O

PCI_SERR 48 O

PCI_STOP 46 I/O

PCI_TRDY 44 I/O

O DESCRIPTION

PCI parity. In all PCI bus read and write cycles, the TSB82AA2 device calculates even parity across the PCI_AD31--PCI_AD0 and PCI_C/BE0 device outputs this parity indicator with a one-PCI_CLK delay. As a target during PCI cycles, the calculated parity is compared to the initiator parity indicator; a miscompare can result in a parity error assertion (PCI_PERR

PCI parity error indicator. This signal is driven by a PCI device to indicate that calculated parity does not match PCI_PAR and/or PCI_PAR64 when PERR_ENB (bit 6) is set to 1 in the command register at offset 04h in the PCI configuration space (see Section 3.4, Command Register).

This terminal indicates wake events to the host. It is an open-drain signal which is asserted when PME_STS is asserted and bit 8 (PME_ENB) in the PCI power management control and status register at offset 48h in the PCI configuration space (see Section 3.20, Power Management Control and Status Register) has been set. Bit 15 (PME_STS) in the PCI power management control and status register is set due to any unmasked interrupt in the D0 (active) or D1 power state, and on a PHY_LINKON indication in the D2, D3, or D0 (uninitialized) power state.

PCI bus request. Asserted by the TSB82AA2 device to request access to the bus as an initiator. The host arbiter asserts PCI_GNT

PCIsystem error. When SERR_ENB(bit 8)in the command register at offset04h inthe PCI configuration space (see Section 3.4, Command Register) is set to 1, the output is pulsed, indicating an address parity error has occurred. The TSB82AA2 device need not be the target of the PCI cycle to assert this signal. This terminal is implemented as open-drain.

PCI cycle stop signal. This signal is driven by a PCI target to request the initiator to stop the current PCI bus transaction. This signal is used for target disconnects, and is commonly asserted by target devices which do not support burst data transfers.

PCI target ready. PCI_TRDY indicates the ability of the PCI bus target to complete the current data phase of the transaction. A data phase is completed upon a rising edge of PCI_CLK where both PCI_IRDY PCI_TRDY

when the TSB82AA2 device has been granted access to the bus.

are asserted.

--PCI_C/BE3 buses. As an initiator during PCI cycles, the TSB82AA2

and

2--6

TERMINAL

NAME NO.

PCI_ACK64 72 I

PCI_AD63 PCI_AD62 PCI_AD61 PCI_AD60 PCI_AD59 PCI_AD58 PCI_AD57 PCI_AD56 PCI_AD55 PCI_AD54 PCI_AD53 PCI_AD52 PCI_AD51 PCI_AD50 PCI_AD49 PCI_AD48 PCI_AD47 PCI_AD46 PCI_AD45 PCI_AD44 PCI_AD43 PCI_AD42 PCI_AD41 PCI_AD40 PCI_AD39 PCI_AD38 PCI_AD37 PCI_AD36 PCI_AD35 PCI_AD34 PCI_AD33 PCI_AD32

PCI_C/BE7 PCI_C/

BE6

PCI_C/

BE5

PCI_C/

BE4

PCI_PAR64 80 I

PCI_REQ64 73 I

82 83 84 85 88 89 90 92 94 95 96 97 98

99 100 101 104 105 106 107 108 109 110 111 113 114 115 116 118 119 120 121

Table 2--6. PCI 64-Bit Bus Extension Terminals

O DESCRIPTION

PCI bus 64-bit transfer acknowledge. Asserted by a target if it is willing to accept a 64-bit data transfer when it positively decodes its address for a memory transaction and the master has requested a 64-bit data transfer by asserting PCI_REQ64 bus master, it monitors PCI_REQ64 If the target asserts PCI_REQ64 64 bits. As a target, the TSB82AA2 does not support 64-bit data transfers and never asserts PCI_REQ64 another master has requested 64-bit transfer.

PCI address/data bus for the upper DWORD. These signals make up the multiplexed PCI address and data bus for the upper 32 bits of the PCI interface. During the address phase of a dual address command with PCI_REQ64

I/O

AD63--AD32 contain data when a 64-bit transfer has been negotiated by the assertion of PCI_REQ64 master and PCI_ACK64

PCI bus commands and byte enables for the upper DWORD. During the address phase of a bus cycle, PCI_C/BE7 address command. During the data phase, this 4-bit bus is used as byte enables for the upper 32 bits when

I/O

a 64-bit transfer has been negotiated by the assertion of PCI_REQ64 target.

PCI parity for the upper DWORD. In all PCI bus read and write cycles, the TSB82AA2 device calculates even parity across the PCI_AD63--PCI_AD32 and PCI_C/BE4 the TSB82AA2 device outputs this parity indicator with a one-PCI_CLK delay. As a target during PCI cycles, the calculated parity is compared to the initiator parity indicator; a miscompare can result in a parity error assertion (PCI_PERR

PCI bus request for 64-bit transfer. Asserted by a bus master to request a 64-bit transfer for a memory transaction. The timing of PCI_REQ64 master, it asserts PCI_REQ64 only requests a 64-bit transfer for a memory transaction. The target asserts PCI_ACK64 data using 64 bits.

asserted, AD63--AD32 contain the upper 32 bits of a 64-bit address. During the data phase,

--PCI_C/BE4 are reserved and indeterminate since the TSB82AA2 does not support the dual

. PCI_REQ64 has identical timing to PCI_DEVSEL. When the TSB82AA2 device is

when it has requested a 64-bit data transfer for the current transaction.

when it claims the cycle, then the TSB82AA2 device transfers data using

by the target. Note, the TSB82AA2 does not support the dual address command.

by the master and PCI_ACK64 by the

--PCI_C/BE7 buses. As an initiatorduring PCIcycles,

is identical to PCI_FRAME. When the TSB82AA2 device is the bus

to request a 64-bit transfer on the current transaction. The TSB82AA2 device

if it is willing to transfer

when

by the

2--7

TERMINAL

NAME NO.

PHY_CTL1 PHY_CTL0

PHY_D7 PHY_D6 PHY_D5 PHY_D4 PHY_D3 PHY_D2 PHY_D1 PHY_D0

PHY_LINKON 142 I/O

PHY_LPS 144 I/O

PHY_LREQ 141 O

PHY_LCLK 136 O

PHY_PCLK 138 I

PHY_PINT 143 I

133 134

123 124 125 128 129 130 131 132

I/O

Table 2--7. PHY-Link Interface Terminals

O DESCRIPTION

PHY-link interface control. These bidirectional control bus signals indicate the phase of operation of the PHY-link interface. Upon a reset of the interface, this bus is driven by the PHY. When driven by the PHY, information on PHY_CTL0 and PHY_CTL1 is synchronous to PHY_PCLK. When driven by the link, information on PHY_CTL0 and PHY_CTL1 is synchronous to PHY_LCLK.

PHY-link interface data. These bidirectional data bus signals carry 1394 packet data, packet speed, and grant type information between the PHY and the link. Upon a reset of the interface, this bus is driven by the PHY. When driven by the PHY, information on PHY_D7 through PHY_D0 is synchronous to PHY_PCLK. When driven by the link, information on PHY_D7 through PHY_D0 is synchronous to PHY_LCLK.

Link-on notification. PHY_LINKON is an input to the TSB82AA2 device from the PHY that is used to provide notification that a link-on packet has been received, or, if the PHY is configured properly, an event such as a port connection has occurred. This input only has meaning when LPS is disabled. This includes the D0 (uninitialized), D2, and D3 power states. If PHY_LINKON becomes active in the D0 (uninitialized), D2, or D3 power state, then the TSB82AA2 device sets bit 15 (PME_STS) in the power management control and status register in the PCI configuration space at offset 48h (see Section 3.20, Power Management Control and Status Register).

Link power status. PHY_LPS is an output from the TSB82AA2 device that, when active, indicates that the link is powered and capable of maintaining communications over the PHY-link interface. When this signal is inactive, it indicates that the link is not powered or that the link has not been initialized by software. This signal is active when bit 19 (LPS) in the host controller control register at OHCI offset 50h/54h (see Section 4.16, Host

Controller Control Register) has been set by software according to the initialization as specified in the 1394 Open Host Controller Interface specification. When active, the signal is nominally a 2-MHz pulse.

Link request. PHY_LREQ is a serial output from the TSB82AA2 device to the PHY used to request packet transmissions, read and write PHY registers, and to indicate the occurrence of certain link events that are relevant to the PHY. Information encoded on PHY_LREQ is synchronous to PHY_LCLK.

Link clock. PHY_LCLK is an output from the TSB82AA2 device that is generated from the incoming PHY_PCLK signal. PHY_LCLK is freqency-locked to PHY_PCLK and synchronizes data and information generated by the link.

PHY clock. PHY_PCLK is an input to the TSB82AA2 device from the PHY that, when active, provides a nominal

98.304-MHz clock with a nominal 50% duty cycle.

PHY interrupt. PHY_PINT is a serial input to the TSB82AA2 device from the PHY that is used to transfer status, register, interrupt, and other information to the link. Information encoded on PHY_PINT is synchronous to PHY_PCLK.

2--8

3 TSB82AA2 Controller Programming Model

This section describes the internal PCI configuration registers used to program the TSB82AA2 device. All registers are detailed in the same format: a brief description for each register, followed by the register offset and a bit table describing the reset state for each register.

A bit description table, typically included when the register contains bits of more than one type or purpose, indicates bit field names, field access tags which appear in the type column, and a detailed field description. Table 3--1 describes the field access tags.

Table 3--1. Bit Field Access Tag Descriptions

ACCESS TAG NAME MEANING

R Read Field can be read by software.

W Write Field can be written by software to any value.

S Set Field can be set by a write of 1. Writes of 0 have no effect.

C Clear Field can be cleared by a write of 1. Writes of 0 have no effect.

U Update Field can be autonomously updated by the TSB82AA2 device.

Figure 3--1 shows a simplified block diagram of the TSB82AA2 device.

3--1

PCI

Target

Internal

Registers

OHCI PCI Power

Mgmt and CLKRUN

Serial

ROM

GPIOs

PCI

Host

Bus

Interface

Central Arbiter

and PCI

Initiator

ISO Transmit

Contexts

Async Transmit

Contexts

Physical DMA

and Response

Response

Timeout

PHY

Access

& Status

Monitor

Request

Filters

General

Request Receive

Transmit

FIFO

Receive

Acknowledge

Cycle Start Generator and Cycle Monitor

Synthesized

Bus Reset

Misc

Interface

Link

Transmit

CRC

PHY /

Link

Interface

Link

Receive

Async Response

Receive

ISO Receive

Contexts

Receive

FIFO

Figure 3 --1. TSB82AA2 Block Diagram

3--2

3.1 PCI Configuration Registers

The TSB82AA2 device is a single-function PCI device. The configuration header is compliant with the PCI Local Bus Specification as a standard header. Table 3--2 illustrates the PCI configuration header that includes both the

predefined portion of the configuration space and the user-definable registers.

Table 3--2. PCI Configuration Register Map

Device ID Vendor ID 00h

Status Command 04h

Class code Revision ID 08h

BIST Header type Latency timer Cache line size 0Ch

OHCI registers base address 10h

TI extension registers base address 14h

CardBus CIS base address 18h

Reserved 1Ch--27h

CardBus CIS pointer 28h

Subsystem ID Subsystem vendor ID 2Ch

Reserved 30h

Power

Reserved

Reserved 38h

Maximum latency Minimum grant Interrupt pin Interrupt line 3Ch

OHCI control 40h

Power management capabilities Next item pointer Capability ID 44h

PM data Power

Subsystem device ID alias Subsystem vendor ID alias F8h

GPIO3 GPIO2 Reserved FCh

management

extension

Miscellaneous configuration F0h

Link enhancement control F4h

Power management control and status 48h

Reserved 4Ch--ECh

management

capabilities pointer

34h

3--3

3.2 Vendor ID Register

The vendor ID register contains a value allocated by the PCI SIG and identifies the manufacturer of the PCI device. The vendor ID assigned to Texas Instruments is 104Ch.

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Vendor ID

Typ e R R R R R R R R R R R R R R R R

Default 0 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0

3.3 Device ID Register

The device ID register contains a value assigned to the TSB82AA2 device by Texas Instruments. The device identification for the TSB82AA2 device is 8025h.

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Device ID

Typ e R R R R R R R R R R R R R R R R

Default 1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1

3--4

3.4 Command Register

The command register provides control over the TSB82AA2 interface to the PCI bus. All bit functions adhere to the definitions in the PCI Local Bus Specification, as seen in the following bit descriptions. See Table 3--3 for a complete description of the register contents.

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Command

Typ e R R R R R R/W R R/W R R/W R R/W R R/W R/W R

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 3--3. Command Register Description

BIT FIELD NAME TYPE DESCRIPTION

15--11 RSVD R Reserved. Bits 15--11 return 0s when read.

10 INT_DISABLE R/W INTx disable. When set to 1, this bit disables the function from asserting interrupts on the INTx signals.

9 FBB_ENB R Fast back-to-back enable. The TSB82AA2 device does not generate fast back-to-back transactions;

8 SERR_ENB R/W PCI_SERR enable. When bit 8 is set to 1, the TSB82AA2 PCI_SERR driver is enabled. PCI_SERR can

7 STEP_ENB R Address/data stepping control. The TSB82AA2 device does not support address/data stepping;

6 PERR_ENB R/W Parity error enable. When bit 6 is set to 1, the TSB82AA2 device is enabled to drive PCI_PERR

5 VGA_ENB R VGApalette snoop enable. The TSB82AA2 device does not feature VGA palette snooping; therefore,

4 MWI_ENB R/W Memory write and invalidate enable. When bit 4 is set to 1, the TSB82AA2 device is enabled to

3 SPECIAL R Special cycle enable. The TSB82AA2 function does not respond to special cycle transactions;

2 MASTER_ENB R/W Bus master enable. When bit 2 is set to 1, the TSB82AA2 device is enabled to initiate cycles on the PCI

1 MEMORY_ENB R/W Memory response enable. Setting bit 1 to 1 enables the TSB82AA2 device to respond to memory

0 IO_ENB R I/O space enable. The TSB82AA2 device does not implement any I/O-mapped functionality; therefore,

0 = INTx 1 = INTx

This bit has been defined as part of the PCI Local Bus Specification (Revision 2.3).

therefore, bit 9 returns 0 when read.

be asserted after detecting an address parity error on the PCI bus.

therefore, bit 7 is hardwired to 0.

response to parity errors through the PCI_PERR signal.

bit 5 returns 0 when read.

generate MWI PCI bus commands. If this bit is cleared, then the TSB82AA2 device generates memory write commands instead.

therefore, bit 3 returns 0 when read.

bus.

cycles on the PCI bus. This bit must be set to access OHCI registers.

bit 0 returns 0 when read.

assertion is enabled (default) assertion is disabled

3--5

3.5 Status Register

The status register provides status over the TSB82AA2 interface to the PCI bus. All bit functions adhere to the definitions in the PCI Local Bus Specification . See Table 3 --4 for a complete description of the register contents.

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Status

Typ e RCU RCU RCU RCU RCU R R RCU R R R R RU R R R

Default 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0

Table 3--4. Status Register Description

BIT FIELD NAME TYPE DESCRIPTION

15 PAR_ERR RCU Detected parity error. Bit 15 is set to 1 when either an address parity or data parity error is detected.

14 SYS_ERR RCU Signaled system error. Bit 14 is set to 1 when PCI_SERR is enabled and the TSB82AA2 device has

13 MABORT RCU Received master abort. Bit 13 is set to 1 when a cycle initiatedby the TSB82AA2 device on the PCI bus

12 TABORT_REC RCU Received target abort. Bit 12 is set to 1 when a cycle initiatedby the TSB82AA2 device on the PCI bus is

11 TABORT_SIG RCU Signaled target abort. Bit 11 is s et to 1 by the TSB82AA2 device when it terminates a transaction on the

10--9 PCI_SPEED R DEVSEL timing. Bits 10 and 9 encode the timing of PCI_DEVSEL and are hardwired to 01b, indicating

8 DATAPAR RCU Data parity error detected. Bit 8 is set to 1 when the following conditions have been met:

7 FBB_CAP R Fast back-to-back capable. The TSB82AA2 device cannot accept fast back-to-back transactions;

6 UDF R User-definable features (UDF) supported. The TSB82AA2 device does not support the UDF;

5 66MHZ R 66-MHz capable. The TSB82AA2 device operates at a maximum PCI_CLK frequency of 33 MHz;

4 CAPLIST R Capabilities list. Bit 4 returns 1 when read, indicating that capabilities additional to standard PCI are

3 INT_STATUS RU

2--0 RSVD R Reserved. Bits 2--0 return 0s when read.

signaled a system error to the host.

is terminated by a master abort.

terminated by a target abort.

PCI bus with a target abort.

that the TSB82AA2 device asserts this signal at a medium speed on nonconfiguration cycle accesses.

a. PCI_PERR b. The TSB82AA2 device was the bus master during the data parity error. c. Bit 6 (PERR_ENB) in the command register at offset 04h in the PCI configuration space

(see Section 3.4, Command Register) is set to 1.

therefore, bit 7 is hardwired to 0.

therefore, bit 6 is hardwired to 0.

therefore, bit 5 is hardwired to 0.

implemented. The linked list of PCI power-management capabilities is implemented in this function.

Interrupt status. This bit reflects the interrupt status of the function. Only when bit 10 (INT_DISABLE) in the command register (PCI offset 04h, see Section 3.4) is a 0 and this bit is a 1, is the function’s INTx signal asserted. Setting the INT_DISABLE bit to a 1 has no effect on the state of this bit. This bit has been defined as part of the PCI Local Bus Specification (Revision 2.3).

was asserted by any PCI device including the TSB82AA2 device.

3--6

3.6 Class Code and Revision ID Register

The class code and revision ID register categorizes the TSB82AA2 device as a serial bus controller (0Ch), controlling an IEEE 1394 bus (00h), with an OHCI programming model (10h). Furthermore, the TI chip revision is indicated in the least significant byte. See Table 3--5 for a complete description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Class code and revision ID

Typ e R R R R R R R R R R R R R R R R

Default 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Class code and revision ID

Typ e R R R R R R R R R R R R R R R R

Default 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1

Table 3--5. Class Code and Revision ID Register Description

BIT FIELD NAME TYPE DESCRIPTION

31--24 BASECLASS R Base class. This field returns 0Ch when read, which broadly classifies the function as a serial bus

23--16 SUBCLASS R Subclass. This field returns 00h when read, which specifically classifies the function as controlling an

15--8 PGMIF R Programming interface. This field returns 10h when read, which indicates that the programming model

7--0 CHIPREV R Silicon revision. This field returns 01h when read, indicating the silicon revision of the TSB82AA2

controller.

IEEE 1394 serial bus.

is compliant with the 1394 Open Host Controller Interface Specification.

device.

3.7 Latency Timer and Class Cache Line Size Register

The latency timer and class cache line size register is programmed by host BIOS to indicate system cache line size and the latency timer associated with the TSB82AA2 device. See Table 3--6 for a c omplete description of the register contents.

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Latency timer and class cache line size

Typ e R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 3--6. Latency Timer and Class Cache Line Size Register Description

BIT FIELD NAME TYPE DESCRIPTION

15--8 LATENCY_TIMER R/W PCI latency timer. The value in this register specifies the latency timer for the TSB82AA2 device, in

unitsof PCI clock cycles. When the TSB82AA2 device is a PCI bus initiator and asserts PCI_FRAME the latency timer begins counting from zero. If the latency timer expires before the TSB82AA2 transaction has terminated, then the TSB82AA2 device terminates the transaction when its PCI_GNT is deasserted.

7--0 CACHELINE_SZ R/W Cache line size. This value is used by the TSB82AA2 device during memory write and invalidate,

memory-read line, and memory-read multiple transactions.

3--7

3.8 Header Type and BIST Register

The header type and built-in self-test (BIST) register indicates the TSB82AA2 PCI header type, and indicates no built-in self test. See Table 3--7 for a complete description of the register contents.

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Header type and BIST

Typ e R R R R R R R R R R R R R R R R

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 3--7. Header Type and BIST Register Description

BIT FIELD NAME TYPE DESCRIPTION

15--8 BIST R Built-in self test. The TSB82AA2 device does not include a BIST; therefore, this field returns 00h when

7--0 HEADER_TYPE R PCI header type. The TSB82AA2 device includes the standard PCI header, which is communicated by

read.

returning 00h when this field is read.

3.9 OHCI Base Address Register

The OHCI base address register is programmed with a base address referencing the memory-mapped OHCI control. When BIOS writes all 1s to this register, the v alue read back is FFFF F800h, indicating that at least 2K bytes of memory address space are required for the OHCI registers. See Table 3--8 for a complete description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name OHCI base address

Typ e R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name OHCI address

Typ e R/W R/W R/W R/W R/W R R R R R R R R R R R

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 3--8. OHCI Base Address Register Description

BIT FIELD NAME TYPE DESCRIPTION

31--11 OHCIREG_PTR R/W OHCI register pointer. This field specifies the upper 21 bits of the 32-bit OHCI base address register.

10--4 OHCI_SZ R OHCI register size. This field returns 0s when read, indicating that the OHCI registers require a

3 OHCI_PF R OHCI register prefetch. Bit 3 returns 0 when read, indicating that the OHCI registers are

2--1 OHCI_MEMTYPE R OHCImemory type. This field returns 0s when read, indicating that the OHCI base address register is

0 OHCI_MEM R OHCI memory indicator. Bit 0 returns 0 when read, indicating that the OHCI registers are mapped into

2K-byte region of memory.

nonprefetchable.

32 bits wide and mapping can be done anywhere in the 32-bit memory space.

system memory space.

3--8

3.10 TI Extension Base Address Register

The TI extension base address register is programmed with a base address referencing the memory-mapped TI extension registers. When BIOS writes all 1s to this register, the value read back is FFFF F800h, indicating that at least 2K bytes of memory address space are required for the TI registers. See Table 3--9 for a complete description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name TI extension base address

Typ e R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name TI extension base address

Typ e R/W R/W R/W R/W R/W R R R R R R R R R R R

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 3--9. TI Base Address Register Description

BIT FIELD NAME TYPE DESCRIPTION

31--11 TIREG_PTR R/W TI register pointer. This field specifies the upper 21 bits of the 32-bit TI base address register.

10--4 TI_SZ R TI register size. This field returns 0s when read, indicating that the TI registers require a 2K-byte

3 TI_PF R TI register prefetch. Bit 3 returns 0 when read, indicating that the TI registers are nonprefetchable.

2--1 TI_MEMTYPE R TI memory type. This field returns 0s when read, indicating that the TI base address register is 32 bits

0 TI_MEM R TImemory indicator. Bit 0 returns 0 when read, indicating that the TI registers are mapped into system

region of memory.

wide and mapping can be done anywhere in the 32-bit memory space.

memory space.

3--9

3.11 CardBus CIS Base Address Register

The TSB82AA2 device may be configured to support CardBus registers via bit 6 (CARDBUS) in the PCI miscellaneous configuration register at offset F0h in the PCI configuration space (see Section 3.23, Miscellaneous Configuration Register). If CARDBUS is low (default), then this 32-bit register returns 0s when read. If CARDBUS is high, then this register is to be programmed with a base address referencing the memory-mapped card information structure (CIS). This register must be programmed with a nonzero value before the CIS may be accessed. See Table 3--10 for a complete description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name CardBus CIS base address

Typ e R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name CardBus CIS base address

Typ e R/W R/W R/W R/W R/W R R R R R R R R R R R

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 3--10. CardBus CIS Base Address Register Description

BIT FIELD NAME TYPE DESCRIPTION

31--11 CIS_BASE R/W CIS base address. This field specifies the upper 21 bits of the 32-bit CIS base address. If CARDBUS is

10--4 CIS_SZ R CIS address space size. This field returns 0s when read, indicating that the CIS space requires a

3 CIS_PF R CIS prefetch. Bit 3 returns 0 when read, indicating that the CIS is nonprefetchable. Furthermore, the

2--1 CIS_MEMTYPE R CIS memory type. This field returns 0s when read, indicating that the CardBus CIS base address

0 CIS_MEM R CIS memory indicator. This bit returns 0 when read, indicating that the CIS is mapped into system

sampledhighonaG_RST

2K-byte region of memory.

CIS is a byte-accessible address space, and either a doubleword or 16-bit word access yields indeterminate results.

memory space.

, then this field is read-only, returning 0s when read.

3--10

3.12 CardBus CIS Pointer Register

The TSB82AA2 device may be configured to support CardBus registers via bit 6 (CARDBUS) in the PCI miscellaneous configuration register at offset F0h in the PCI configuration space (see Section 3.23, Miscellaneous Configuration Register). If CARDBUS is low (default), then this register is read-only returning 0s when read. If CARDBUS is high, then this register contains the pointer to the CardBus card information structure (CIS). See Table 3--11 for a complete description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name CardBus CIS pointer

Typ e R R R R R R R R R R R R R R R R

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name CardBus CIS pointer

Typ e R R R R R R R R R R R R R R R R

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 X X X

Table 3--11. CardBus CIS Pointer Register Description

BIT FIELD NAME TYPE DESCRIPTION

31--28 ROM_IMAGE R Since the CIS is not implemented as a ROM image, this field returns 0s when read.

27--3 CIS_OFFSET R This field indicates the offset into the CIS address space where the CIS begins, and bits 7--3 are loaded

2--0 CIS_INDICATOR R This field indicates the addres s space where the CIS resides and returns 011b if bit 6 (CARDBUS) in

from the serial EEPROM field CIS_Offset (7--3). This implementation allows the TSB82AA2 device to produce serial EEPROM addresses equal to the lower PCI address byte to acquire data from the serial EEPROM.

the PCI miscellaneous configuration register is high, then 011b indicates that CardBus CIS base address register at offset 18h in the PCI configuration header contains the CIS base address. If CARDBUS is low, then this field returns 000b when read.

3--11

3.13 Subsystem Identification Register

The subsystem identification register is used for system and option card identification purposes. This register can be initialized from the serial EEPROM or programmed via the subsystem access register at offset F8h in the PCI configuration space (see Section 3.25, Subsystem Access Register). See Table 3--12 for a complete description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Subsystem identification

Typ e RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Subsystem identification

Typ e RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 3--12. Subsystem Identification Register Description

BIT FIELD NAME TYPE DESCRIPTION

31--16 OHCI_SSID RU Subsystem device ID. This field indicates the subsystem device ID.

15--0 OHCI_SSVID RU Subsystem vendor ID. This field indicates the subsystem vendor ID.

3.14 Power Management Capabilities Pointer Register

The power management capabilities pointer register provides a pointer into the PCI configuration header where the power-management register block resides. The TSB82AA2 configuration header doublewords at offsets 44h and 48h provide the power-management registers. This register is read-only and returns 44h when read.

Bit 7 6 5 4 3 2 1 0

Name Power management capabilities pointer

Typ e R R R R R R R R

Default 0 1 0 0 0 1 0 0

3--12

3.15 Interrupt Line and Pin Register

The interrupt line and pin register communicates interrupt line routing information. See Table 3--13 for a complete description of the register contents.

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Interrupt line and pin

Typ e R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W

Default 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0

Table 3--13. Interrupt Line and Pin Register Description

BIT FIELD NAME TYPE DESCRIPTION

15--8 INTR_PIN R Interrupt pin. Returns 01h when read, indicating that the TSB82AA2 PCI function signals interrupts on

7--0 INTR_LINE R/W Interrupt line. This fieldis programmed by the system and indicates to software which interrupt line the

the PCI_INTA

TSB82AA2 PCI_INTA

terminal.

is connected to.

3.16 MIN_GNT and MAX_LAT Register

The MIN_GNT and MAX_LATregister communicates to the system the desiredsetting of bits 15-- 8 in the latency timer and class cache line size register at offset 0Ch in the PCI configuration space (see Section 3.7, Latency Timer and Class Cache Line Size Register). If a serial EEPROM is detected, then the contents of this register are loaded through the serial EEPROM interface after a PCI_RST

. If no serial EEPROM is detected, then this register returns a default value that corresponds to the MIN_GNT = 2, MAX_LAT = 4. See Table 3--14 for a complete description of the register contents.

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name MIN_GNT and MAX_LAT

Typ e RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU

Default 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0

Table 3--14. MIN_GNT and MAX_LAT Register Description

BIT FIELD NAME TYPE DESCRIPTION

15--8 MAX_LAT RU Maximum latency.The contents of this field may be used by host BIOS to assign an arbitration priority level

7--0 MIN_GNT RU Minimum grant. The contents of this field may be used by host BIOS to assign a latency timer register value

to the TSB82AA2 device. The default for this field indicates that the TSB82AA2 device may need to acc ess the PCI bus as often as every 0.25 µs; thus, an extremely high priority level is requested. The contents of this field may also be loaded through the serial EEPROM.

to the TSB82AA2 device. The default for this field indicates that the TSB82AA2 device may need to sustain burst transfers for nearly 64 µs and thus request a large value be programmed in bits 15--8 of the TSB82AA2 latency timer and class cache line size register at offset 0Ch in the PCI configuration space (see Section 3.7, Latency Timer and Class Cache Line Size Register).

3--13

3.17 OHCI Control Register

The OHCI control register is defined by the 1394 Open Host Controller Interface Specification and provides a bit for big endian PCI support. See Table 3--15 for a complete description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name OHCI control

Typ e R R R R R R R R R R R R R R R R

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name OHCI control

Typ e R R R R R R R R R R R R R R R R/W

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 3--15. OHCI Control Register Description

BIT FIELD NAME TYPE DESCRIPTION

31--1 RSVD R Reserved. Bits 31--1 return 0s when read.

0 GLOBAL_SWAP R/W When bit 0 is set to 1, all quadlets read from and written to the PCI interface are byte-swapped (big

endian). This bit is loaded from serial EEPROM and must be cleared to 0 for normal operation.

3.18 Capability ID and Next Item Pointer Register

The capability ID and next item pointer register identifies the linked-list capability item and provides a pointer to the next capability item, respectively. See Table 3--16 for a complete description of the register contents.

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Capability ID and next item pointer

Typ e R R R R R R R R R R R R R R R R

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Table 3--16. Capability ID and Next Item Pointer Register Description

BIT FIELD NAME TYPE DESCRIPTION

15--8 NEXT_ITEM R Next item pointer. The TSB82AA2 device supports only one additional capability that is

7--0 CAPABILITY_ID R Capability identification. This field returns 01h when read, which is the unique ID assigned by the PCI

communicated to the system through the extended capabilities list; therefore, this field returns 00h when read.

SIG for PCI power-management capability.

3--14

3.19 Power Management Capabilities Register

The power management capabilities register indicates the capabilities of the TSB82AA2 device related to PCI power management. See Table 3--17 for a complete description of the register contents.

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Power management capabilities

Typ e RU R R R R R R R R R R R R R R R

Default 0 1 1 1 1 1 1 0 0 0 0 0 0 0 1 0

Table 3--17. Power Management Capabilities Register Description

BIT FIELD NAME TYPE DESCRIPTION

15 PME_D3COLD RU PCI_PME support from D3

14--11 PME_SUPPORT R PCI_PME support. This 4-bit field indicates the power states from which the TSB82AA2 device may

10 D2_SUPPORT R D2 support. Bit 10 is hardwired to 1, indicating that the function supports the D2 device power state.

9 D1_SUPPORT R D1 support. Bit 9 is hardwired to 1, indicating that the TSB82AA2 device supports the D1 power state.

8--6 AUX_CURRENT R Auxiliary current. This 3-bit field reports the 3.3-V

5 DSI R Device-specific initialization. Bit 5 returns 0 when read, indicating that the TSB82AA2 device does not

4 RSVD R Reserved. Bit 4 returns 0 when read.

3 PME_CLK R PME clock . Bit 3 returns 0 when read, indicating that no host bus clock is required for the TSB82AA2

2--0 PM_VERSION R Power-management version. This field returns 010b when read, indicating that the TSB82AA2 device

the miscellaneous configuration register at offset F0h in the PCI configuration space (see Section 3.23, Miscellaneous Configuration Register). The miscellaneous configuration register is loaded from ROM. When this bit is set to 1, it indicates that the TSB82AA2 device is capable of generating a PCI_PME wake event from D3 may be configured by using bit 15 (PME_D3COLD) in the miscellaneous configuration register (see Section 3.23).

assert PCI_PME the D3

Bit 14 contains the value 1 to indicate that the PCI_PME state. Bit 13 contains the value 1 to indicate that the PCI_PME Bit 12 contains the value 1 to indicate that the PCI_PME Bit 11 contains the value 1 to indicate that the PCI_PME

(PME_D3COLD) is cleared, this field returns 000b; otherwise, it returns 001b.

require special initialization beyond the standard PCI configuration header before a generic class driver is able to use it.

device to generate PCI_PME

is compatible with the registers described in the PCI Bus Power Management Interface Specification (Revision 1.1).

, D2, D1, and D0 power states.

hot

000b = Self-powered 001b = 55 mA (3.3-V

cold

. This field returns a value of 1111b, indicating that PCI_PME may be asserted from

. This bit can be set to 1 or cleared to 0 via bit 15 (PME_D3COLD) in

cold

. This bit state is dependent upon the TSB82AA2 V

signal can be asserted from the D3

signal can be asserted from the D2 state. signal can be asserted from the D1 state. signal can be asserted from the D0 state.

auxiliary current requirements. When bit 15

AUX

maximum current required)

AUX

implementation and

AUX

hot

3--15

3.20 Power Management Control and Status Register

The power management control and status register implements the control and status of the PCI power management function. This register is not affected by the internally generated reset caused by the transition from the D3 state. See Table 3--18 for a complete description of the register contents.

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Power management control and status

Typ e RC R R R R R R R/W R R R R R R R/W R/W

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 3--18. Power Management Control and Status Register Description

BIT FIELD NAME TYPE DESCRIPTION

15 PME_STS RC Bit15 is set to 1 when the TSB82AA2 device normally asserts the PME signal, independent of the state

14--9 RSVD R Reserved. Bits 14--9 return 0s when read.

8 PME_ENB R/W Whenbit8issetto1,PMEassertion is enabled. When bit 8 is cleared, PME assertion is disabled. This

7--2 RSVD R Reserved. Bits 7--2 return 0s when read.

1--0 PWR_STATE R/W Power state. This 2-bit field is used to set the TSB82AA2 device power state and is encoded as follows:

of bit 8 (PME_ENB). This bit is cleared by a writeback of 1, which also clears the PCI_PME driven by the TSB82AA2 device. Writinga0tothisbithasnoeffect.

bit defaults to 0 if the function does not support PME PME

from D3 it is initially loaded. Functions that do not support PME in the power management capabilities register at offset 46h in the PCI configuration space (see Section 3.19, Power Management Capabilities Register) equal 00000b), may hardwire this bit to be read-only, always returninga0whenreadbysystem software.

00 = Current power state is D0. 01 = Current power state is D1. 10 = Current power state is D2. 11 = Current power state is D3.

, then this bit is sticky and must be explicitly cleared by the operating systemeachtime

cold

generation from D3

generation from any D-state (that is, bits 15--11

. If the function supports

cold

hot

to D0

signal

3.21 Power Management Extension Register

The power management extension register provides extended power-management features not applicable to the TSB82AA2 device; thus, it is read-only and returns 0s when read. See Table 3--19 for a complete description of the register contents.

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Power management extension

Typ e R R R R R R R R R R R R R R R R

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 3--19. Power Management Extension Register Description

BIT FIELD NAME TYPE DESCRIPTION

15--0 RSVD R Reserved. Bits 15--0 return 0s when read.

3--16

3.22 Multifunction Select Register

The multifunction select register provides a method. See Table 3--20 for a complete description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Multifunction select

Typ e R R R R R R R R R R R R R R R R

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Multifunction select

Typ e R R R R R R R R R R R R RWU RWU RWU RWU

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 3--20. Multifunction Select Register

BIT FIELD NAME TYPE DESCRIPTION

31--8 RSVD R Reserved. Bits 31--8 return 0s when read.

7 RSVD R Reserved. This read-only bit is for internal use only.

6--4 RSVD R Reserved. Bits 6--4 return 0s when read.

3--0 MFUNC_SEL R/W/U Power state. This 2-bit field is used to set the TSB82AA2 device power state and is encoded as follows:

000 = General-purpose input/output 001 = CYCLEIN 010 = CYCLEOUT 011 =

PCI_CLKRUN 100 = Reserved 101 = Reserved 110 = Res e r v e d 111 = Reserved

3--17

3.23 Miscellaneous Configuration Register

The miscellaneous configuration register provides miscellaneous PCI-related configuration. See Table 3--21 for a complete description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Miscellaneous configuration

Typ e R R R R R R R R R R R R R R R R

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Miscellaneous configuration

Typ e R/W R R R R R/W R/W R/W R R/W R R/W R R/W R/W R/W

Default 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0

Table 3--21. Miscellaneous Configuration Register

BIT FIELD NAME TYPE DESCRIPTION

31--16 RSVD R Reserved. Bits 31--16 return 0s when read.

15 PME_D3COLD R/W PCI_PME support from D3

14--11 RSVD R Reserved. Bits 14--11 return 0s when read.

10 Ignore

IntMask.masterInt

Enable_for_pme

9--8 MR_ENHANCE R/W This field selects the read command behavior of the PCI master.

7 RSVD R Reserved. Bit 7 returns 0 when read.

6 CARDBUS R/W CardBus. When bit 6 is set to 1, CardBus register support is enabled, that is, the CardBus base

5 RSVD R Reserved. Bit 5 returns 0 when read.

4 DIS_TGT_ABT R/W Bit 4 defaults to 1 disabling the target abort behavior when accesses are made to PHY clock

3 RSVD R Reserved. Bit 3 returns 0 when read.

management capabilities register at offset 46h in the PCI configuration space (see Section 3.19, Power Management Capabilities Register).

R/W Ignore IntMask.masterIntEnable for PME generation. When set to 1, this bit causes PME

generation behavior to be changed. Also, when set to 1, this bit causes bit 26 of the OHCI vendor ID register at OHCI offset 40h to read 1; otherwise, bit 26 reads 0.

0 = PME behavior generated from unmasked interrupt bits and bit 31 (masterIntEnable) in the

interrupt mask register at OHCI offset 88h (see Section 4.22, Interrupt Mask Register) (default)

1 = PME behavior does not depend on the value of bit 31 (masterIntEnable)

00 = Memory read line (default) 01 = Memory read 10 = Memory read multiple 11 = Reserved

register and CardBus CIS pointer are valid. Bit 6 is only set if a serial EEPROM is present and contains a valid CIS. If bit 6 is set to 1, then a valid CIS must be implemented in the EEPROM at an offset pointed to in EEPROM word 0x14, bits 7--3.

domain registers when no clock is present. Bit 4 can be set to 0 to provide OHCI-Lynxt compatible target abort signaling. When this bit is set to 1, it enables the no-target-abort mode, in which the TSB82AA2 device returns indeterminate data instead of signaling target abort.

The TSB82AA2 LLC is divided into the PCI_CLK and SCLK domains. If software tries to access registers in the link that are not active because the SCLK is disabled, then a target abort is issued by the link. On some systems, this can cause a problem resulting in a fatal system error. Enabling this bit allows the link to respond to these types of requests by returning FFh.

It is recommended that this bit be set to 1.

. This bit programs bit 15 (PME_D3COLD) in the power

cold

3--18

Table 3--21. Miscellaneous Configuration Register (Continued)

BIT FIELD NAME TYPE DESCRIPTION

2 DISABLE_SCLKGATE R/W When bit 2 is set to 1, the internal SCLK runs identically with the chip input. This is a test

1 DISABLE_PCIGATE R/W When bit 1 is set to 1, the internal PCI clock runs identically with the chip input. This is a test

0 KEEP_PCLK R/W When bit 0 is set to 1, the PCI clock always is kept running through the PCI_CLKRUN

feature only and must be cleared to 0 (all applications).

protocol. When this bit is cleared, the PCI clock can be stopped using PCI_CLKRUN.

3.24 Link Enhancement Control Register

The link enhancement control register implements TI proprietary bits that are initialized by software or by a serial EEPROM, if present. After these bits are set to 1, their functionality is enabled only if bit 22 (aPhyEnhanceEnable) in the host controller control register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control Register)is set to 1. See Table 3--22 for a complete description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Link enhancement control

Typ e R R R R R R R R R R R R R R R R

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Link enhancement control

Typ e R/W R R/W R/W R R R/W R/W R/W R R R R R/W R/W R

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 3--22. Link Enhancement Control Register Description

BIT FIELD NAME TYPE DESCRIPTION

31--16 RSVD R Reserved. Bits 31--16 return 0s when read.

15 DisableATPipelining R/W Disable AT pipelining. When bit 15 is set to 1, out-of-order AT pipelining is disabled.

14 EnableDraft R/W Enable OHCI 1.2 draft features. When bit 14 is set to 1, it enables some features beyond the OHCI

1.1 specification. Specifically, this enables HCControl.LPS to be cleared by writing a 1 to the HCControlClear.LPS bit and enables the link to set bit 9 in the xferStatus field of AR and IR ContextControl registers.

3--19

Table 3--22. Link Enhancement Control Register Description (Continued)

BIT FIELD NAME TYPE DESCRIPTION

13--12 atx_thresh R/W This field sets the initial AT threshold value, which is used until the AT FIFO is underrun. When the

11- -10 RSVD R Reserved. Bits 11--10 return 0s when read.

9 enab_aud_ts R/W Enable audio/music CIP timestamp enhancement. When bit 9 is set to 1, the enhancement is enabled

8 enab_dv_ts R/W Enable DV CIP timestamp enhancement. When bit 8 is set to 1, the enhancement is enabled for DV

7 enab_unfair R/W Enable asynchronous priority requests. OHCI-Lynxt compatible. Setting bit 7 to 1 enables the link to

6 RSVD R Bit 6 is not assigned in the TSB82AA2 follow-on products since this location, which is loaded by the

5--3 RSVD R Reserved. Bits 5--3 return 0s when read.

2 enab_insert_idle R/W Enable insert idle. OHCI-Lynxt compatible. When the PHY device has control of the

1 enab_accel R/W Enable acceleration enhancements. OHCI-Lynxt compatible. When bit 1 is set to 1, the PHY device

0 RSVD R Reserved. Bit 0 returns 0 when read.

TSB82AA2 device retries the packet, it uses a 2K-byte threshold resulting in a store-and-forward operation.

00 = Threshold ~ 4K bytes resulting in a store-and-forward operation (default) 01 = Threshold ~ 1.7K bytes 10 = Threshold ~ 1K bytes 11 = Threshold ~ 512 bytes

These bits fine-tune the asynchronous transmit threshold. Changing this value may increase or decrease the 1394 latency depending on the average PCI bus latency.

Setting the ATthreshold to 1.7K, 1K, or 512 bytes results in data being transmitted at these thresholds or when an entire packet has been checked into the FIFO. If the packet to be transmitted is larger than the ATthreshold, then the remaining data must be received before the AT FIFO is emptied; otherwise, an underrun condition occurs, resulting in a pack et error at the receiving node. As a result, the link then commences store-and-forward operation—that is, wait until it has the complete packet in the FIFO before retransmitting it on the second attempt, to ensure delivery.

An AT threshold of 4K results in store-and-forward operation, which means that asynchronous data is not transmitted until an end-of-packet token is received. Restated, setting the AT threshold to 4K results in only complete packets being transmitted.

Note that this device always uses store-and-forward when the asynchronous transmit retries register at OHCI offset 08h (see Section 4.3, Asynchronous Transmit Retries Register) is cleared.

for audio/music CIP transmit streams (FMT = 10h).

CIP transmit streams (FMT = 00h).

respond to requests with priority arbitration. It is recommended that this bit be set to 1.

serial EEPROM from the enhancements field, corresponds to bit 23 (programPhyEnable) in the host controller control register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control Register).

PHY_CTL0--PHY_CTL1 control lines and PHY_DATA0--PHY_DATA7 data lines and the link requests control, the PHY device drives 11bon the PHY_CTL0--PHY_CTL1 lines. The link c an then start driving these lines immediately. Setting bit 2 to 1 inserts an idle state, so the link waits one clock cycle before it starts driving the lines (turnaround time).

is notified that the link supports the IEEE Std 1394a-2000 ac celeration enhancements, that is, ack-accelerated, fly-by concatenation, etc. It is recommended that bit 1 be set to 1.

3--20

3.25 Subsystem Access Register

Write access to the subsystem access regis ter updates the subsystem identification registers identically to OHCI-Lynxt. The system ID value written to this register may also be read back from this register. See Table 3--23 for a complete description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Subsystem access

Typ e R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Subsystem access

Typ e R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 3--23. Subsystem Access Register Description

BIT FIELD NAME TYPE DESCRIPTION

31--16 SUBDEV_ID R/W Subsystem device ID alias. This field indicates the subsystem device ID.

15--0 SUBVEN_ID R/W Subsystem vendor ID alias. This field indicates the subsystem vendor ID.

3--21

3.26 GPIO Control Register

The GPIO control register has the control and status bits for the GPIO2 and GPIO3 ports. See Table 3--24 for a complete description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name GPIO control

Typ e R R R R R R R R R/W R R/W R/W R R R RWU

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name GPIO control

Typ e R R R R R R R R R R R R R R R R

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 3--24. GPIO Control Register Description

BIT FIELD NAME TYPE DESCRIPTION

31--24 RSVD R Reserved. Bits 31--24 return 0s when read.

23 INT_EN R/W When bit 23 is set to 1, a TSB82AA2 general-purpose interrupt event occurs on a level change of the

22 RSVD R Reserved. Bit 22 returns 0 when read.

21 GPIO_INV R/W GPIO polarity invert. When bit 21 is set to 1, the polarity of GPIO is inverted.

20 GPIO_ENB R/W GPIO enable control. When bit 20 is set to 1, the output is enabled. Otherwise, the output is high

19--17 RSVD R Reserved. Bits 19--17 return 0s when read.

16 GPIO_DATA RWU GPIO data. Reads from bit 16 return the logical value of the input to GPIO. Writes to this bit update the

15--0 RSVD R Reserved. Bits 15--0 return 0s when read.

GPIO input. This event may generate an interrupt, with mask and event status reported through the interrupt mask register at OHCI offset 88h/8Ch (see Section 4.22, Interrupt Mask Register) and the interrupt event register at OHCI offset 80h/84h (see Section 4.21, Interrupt Event Register).

impedance.

value to drive to GPIO when the output is enabled.

3--22

4 OHCI Registers

The OHCI registers defined by the 1394 Open Host Controller Interface Specification are memory-mapped into a 2K-byte region of memory pointed to by the OHCI base address register at offset 10h in PCI configuration space (see Section 3.9, OHCI Base Address Register). These registers are the primary interface for controlling the TSB82AA2 IEEE 1394 link function.

This section provides the register interface and bit descriptions. Several set/clear register pairs in this programming model are implemented to solve various issues with typical read-modify-write control registers. There are two addresses for a set/clear register: RegisterSet and RegisterClear. See Table 4--1 for a register listing. A 1 bit written to RegisterSet causes the corresponding bit in the set/clear register to be set to 1; a 0 bit leaves the corresponding bit unaffected. A 1 bit written to RegisterClear causes the corresponding bit in the set/clear regis ter to be cleared; a 0 bit leaves the corresponding bit in the set/clear register unaffected.

Typically, a read from either RegisterSet or RegisterClear returns the contents of the set or clear register, respectively. However, sometimes reading the RegisterClear provides a masked version of the set or clear register. The interrupt event register is an example of this behavior.

Table 4--1. OHCI Register Map

DMA CONTEXT REGISTER NAME ABBREVIATION OFFSET

— OHCI version Ve rsio n 00h

GUID ROM GUID_ROM 04h

Asynchronous transmit retries ATRetries 08h

CSR data CSRData 0Ch

CSR compare data CSRCompareData 10h

CSR control CSRControl 14h

Configuration ROM header ConfigROMhdr 18h

Bus identification BusID 1Ch

Bus options BusOptions 20h

GUID high GUIDHi 24h

GUID low GUIDLo 28h

Reserved — 2Ch--30h

Configuration ROM map ConfigROMmap 34h

Posted write address low PostedWriteAddressLo 38h

Posted write address high PostedWriteAddressHi 3Ch

Vendor identification VendorID 40h

Reserved — 44h--4Ch

Host controller control

Reserved — 58h--5Ch

HCControlSet 50h

HCControlClr 54h

4--1

Table 4--1. OHCI Register Map (Continued)

DMA CONTEXT REGISTER NAME ABBREVIATION OFFSET

Self ID Reserved — 60h

Self ID buffer SelfIDBuffer 64h

Self ID count SelfIDCount 68h

Reserved — 6Ch

—

Isochronous receive channel mask high

Isochronous receive channel mask low

Interrupt event

Interrupt mask

Isochronous transmit interrupt event

Isochronous transmit interrupt mask

Isochronous receive interrupt event

Isochronous receive interrupt mask

Initial bandwidth available IntBandwidthAvailable B0h

Initial channels high available IntChannelHiAvailable B4h

Initial channels low available IntChannelLoAvailable B8h

Reserved — BCh--D8h

Fairness control FairnessControl DCh

Link control

Node identification NodeID E8h

PHY layer control PhyControl ECh

Isochronous cycle timer Isocyctimer F0h

Reserved — F4h--FCh

Asynchronous requestfilter high

Asynchronous requestfilter low

Physical requestfilter high

Physical requestfilter low

Physical upper bound PhysicalUpperBound 120h

Reserved — 124h--17Ch

IRChannelMaskHiSet 70h

IRChannelMaskHiClear 74h

IRChannelMaskLoSet 78h

IRChannelMaskLoClear 7Ch

IntEventSet 80h

IntEventClear 84h

IntMaskSet 88h

IntMaskClear 8Ch

IsoXmitIntEventSet 90h

IsoXmitIntEventClear 94h

IsoXmitIntMaskSet 98h

IsoXmitIntMaskClear 9Ch

IsoRecvIntEventSet A0h

IsoRecvIntEventClear A4h

IsoRecvIntMaskSet A8h

IsoRecvIntMaskClear ACh

LinkControlSet E0h

LinkControlClear E4h

AsyncRequestFilterHiSet 100h

AsyncRequestFilterHiClear 104h

AsyncRequestFilterLoSet 108h

AsyncRequestFilterloClear 10Ch

PhysicalRequestFilterHiSet 110h

PhysicalRequestFilterHiClear 114h

PhysicalRequestFilterLoSet 118h

PhysicalRequestFilterloClear 11C h

4--2

Table 4--1. OHCI Register Map (Continued)

Asychronous

RequestTransmit

Asychronous

ResponseTransmi

Asychronous

RequestReceiv

Asychronous

ResponseReceive

DMA CONTEXT REGISTER NAME ABBREVIATION OFFSET

ContextControlSet 180h

ContextControlClear 184h

ContextControlSet 1A0h

ContextControlClear 1A4h

ContextControlSet 1C0h

ContextControlClear 1C4h

ContextControlSet 1E0h

ContextControlClear 1E4h

ContextControlSet 200h + 16*n

ContextControlClear 204h + 16*n

CommandPtr 20Ch + 16*n

ContextControlSet 400h + 32*n

ContextControlClear 404h + 32*n

CommandPtr 40Ch + 32*n

Request Transmit

[ATRQ]

Response Transmit

[ATRS]

Request Receive

[ ARRQ ]

Response Receive

[ ARRS ]

Isochronous TransmitContextn n = 0, 1, 2, 3, …,7

Isochronous

ReceiveContextn

n = 0, 1, 2, 3

Asynchronous context control

Reserved — 188h

Asynchronous context command pointer CommandPtr 18Ch

Reserved — 190h--19Ch

Asynchronous context control

Reserved — 1A8h

Asynchronous context command pointer CommandPtr 1ACh

Reserved — 1B0h--1BCh

Asynchronous context control

Reserved — 1C8h

Asynchronous context command pointer CommandPtr 1CCh

Reserved — 1D0h--1DCh

Asynchronous context control

Reserved — 1E8h

Asynchronous context command pointer CommandPtr 1ECh

Reserved — 1F0h--1FCh

Isochronous transmit context control

Reserved — 208h + 16*n

Isochronous transmit context command pointer

Reserved — 280h--3FCh

Isochronous receive context control

Reserved — 408h + 32*n

Isochronous receive context command pointer

Context match ContextMatch 410h + 32*n

4--3

4.1 OHCI Version Register

The OHCI version register indicates the OHCI version support and whether or not the serial EEPROM is present. See Table 4--2 for a complete description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name OHCI version

Typ e R R R R R R R R R R R R R R R R

Default 0 0 0 0 0 0 0 X 0 0 0 0 0 0 0 1

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name OHCI version

Typ e R R R R R R R R R R R R R R R R

Default 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0

Table 4--2. OHCI Version Register Description

BIT FIELD NAME TYPE DESCRIPTION

31--25 RSVD R Reserved. Bits 31--25 return 0s when read.

24 GUID_ROM R The TSB82AA2 device sets bit 24 to 1 if the serial EEPROM is detected. If the serial EEPROM is

23--16 version R Major version of the OHCI. The TSB82AA2 device is compliant with the 1394 Open Host Controller

15--8 RSVD R Reserved. Bits 15--8 return 0s when read.

7--0 revision R Minor version of the OHCI. The TSB82AA2 device is compliant with the 1394 Open Host Controller

present, then the Bus_Info_Block is automatically loaded on system (hardware) reset.

Interface Specification (Revision 1.1); thus, this field reads 01h.

Interface Specification (Revision 1.1); thus, this field reads 10h.

4--4

4.2 GUID ROM Register

The GUID ROM register accesses the serial EEPROM and is only applicable if bit 24 (G UID_ROM) in the O HCI version register at OHCI offset 00h (see Section 4.1, OHCI Version Register) is set to 1. See Table 4--3 for a complete description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name GUID ROM

Typ e RSU R R R R R RSU R RU RU RU RU RU RU RU RU

Default 0 0 0 0 0 0 0 0 X X X X X X X X

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name GUID ROM

Typ e R R R R R R R R R R R R R R R R

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 4--3. GUID ROM Register Description

BIT FIELD NAME TYPE DESCRIPTION

31 addrReset RSU Software sets bit 31 to 1 to reset the GUID ROM address to 0. When the TSB82AA2 device completes

30--26 RSVD R Reserved. Bits 30--26 return 0s when read.

25 rdStart RSU A read of the currently addressed byte is started when bit 25 is set to 1. This bit is automatically cleared

24 RSVD R Reserved. Bit 24 returns 0 when read.

23--16 rdData RU This field represents the data read from the GUID ROM.

15--8 RSVD R Reserved. Bits 15--8 return 0s when read.

7--0 miniROM R Mini-ROM. The TSB82AA2 device uses bits 7--0 to indicate the first byte location of the mini-ROM

the reset, it clears this bit. The TSB82AA2 device does not automatically fill bits 23--16 (rdData field) with the 0

when the TSB82AA2 device completes the read of the currently addressed GUID ROM byte.

image in the GUID ROM. A value of 00h in this field indicates that no mini-ROM is implemented.

byte.

4--5

4.3 Asynchronous Transmit Retries Register

The asynchronous transmit retries register indicates the number of times the TSB82AA2 device attempts a retry for asynchronous DMA request transmit and for asynchronous physical and DMA response transmit. See Table 4--4 for a complete description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Asynchronous transmit retries

Typ e R R R R R R R R R R R R R R R R

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Asynchronous transmit retries

Typ e R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 4--4. Asynchronous Transmit Retries Register Description

BIT FIELD NAME TYPE DESCRIPTION

31--29 secondLimit R The second limit field returns 0s when read, because outbound dual-phase retry is not

28--16 cycleLimit R Thecycle limit field returns 0s when read, because outbound dual-phase retry is not implemented.

15--12 RSVD R Reserved. Bits 15--12 return 0s when read.

11- -8 maxPhysRespRetries R/W This field tells the physical response unit how many times to attempt to retry the transmit operation

7--4 maxATRespRetries R/W This field tells the asynchronous transmit response unit how many times to attempt to retry the

3--0 maxATReqRetries R/W This field tells the asy nchronous transmit DMA request unit how many times to attempt to retry the

implemented.

for the response packet when a busy acknowledge or ac k_data_error is received from the target node.

transmit operation for the response packet when a busy acknowledge or ack_data_error is received from the target node.

4.4 CSR Data Register

The CSR data register accesses the bus management CSR registers from the host through compare-swap operations. This register contains the data to be stored in a CSR if the compare is successful.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name CSR data

Typ e R R R R R R R R R R R R R R R R

Default X X X X X X X X X X X X X X X X

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name CSR data

Typ e R R R R R R R R R R R R R R R R

Default X X X X X X X X X X X X X X X X

4--6

4.5 CSR Compare Register

The CSR compare register accesses the bus management CSR registers from the host through compare-swap operations. This register contains the data to be compared with the existing value of the CSR resource.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name CSR compare

Typ e R R R R R R R R R R R R R R R R

Default X X X X X X X X X X X X X X X X

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name CSR compare

Typ e R R R R R R R R R R R R R R R R

Default X X X X X X X X X X X X X X X X

4.6 CSR Control Register

The CSR control register accesses the bus management CSR registers from the host through compare-swap operations. This register controls the compare-swap operation and selects the CSR resource. See Table 4--5 for a complete description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name CSR control

Typ e RU R R R R R R R R R R R R R R R

Default 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name CSR control

Typ e R R R R R R R R R R R R R R R/W R/W

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X X

Table 4--5. CSR Control Register Description

BIT FIELD NAME TYPE DESCRIPTION

31 csrDone RU Bit 31 is set to 1 by the TSB82AA2 device when a compare-swap operation is complete. It is cleared

30--2 RSVD R Reserved. Bits 30--2 return 0s when read.

1--0 csrSel R/W This field selects the CSR resource as follows:

whenever this register is written.

00 = BUS_MANAGER_ID 01 = BANDWIDTH_AVAILABLE 10 = CHANNELS_AVAILABLE_HI 11 = CHANNELS_AVAILABLE_LO

4--7

4.7 Configuration ROM Header Register

The configuration ROM header register externally maps to the first quadlet of the 1394 configuration ROM, offset FFFF F000 0400h. See Table 4--6 for a complete description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Configuration ROM header

Typ e R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Configuration ROM header

Typ e R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Default X X X X X X X X X X X X X X X X

Table 4--6. Configuration ROM Header Register Description

BIT FIELD NAME TYPE DESCRIPTION

31--24 info_length R/W IEEE 1394 bus-management field. Must be valid when bit 17 (linkEnable) in the host controller control

23--16 crc_length R/W IEEE 1394 bus-management field. Must be valid when bit 17 (linkEnable) in the host controller control

15--0 rom_crc_value R/W IEEE 1394 bus-management field. Must be valid at any time bit 17 (linkEnable) in the host controller

control register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control Register)issetto

1. The reset value is undefined if no serial EEPROM is present. If a serial EEPROM is present, then this field is loaded from the serial EEPROM.

4.8 Bus Identification Register

The bus identification register externally maps to the first quadlet in the Bus_Info_Block and contains the constant 3133 3934h, which is the ASCII value of 1394.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Bus identification

Typ e R R R R R R R R R R R R R R R R

Default 0 0 1 1 0 0 0 1 0 0 1 1 0 0 1 1

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Bus identification

Typ e R R R R R R R R R R R R R R R R

Default 0 0 1 1 1 0 0 1 0 0 1 1 0 1 0 0

4--8

4.9 Bus Options Register

The bus options register externally maps to the second quadlet of the Bus_Info_Block. See Table 4--7 for a complete description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Bus options

Typ e R/W R/W R/W R/W R/W R R R R/W R/W R/W R/W R/W R/W R/W R/W

Default X X X X 0 0 0 0 X X X X X X X X

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Bus options

Typ e R/W R/W R/W R/W R R R R R/W R/W R R R R R R

Default 1 0 1 1 0 0 0 0 X X 0 0 0 0 1 0

Table 4--7. Bus Options Register Description

BIT FIELD NAME TYPE DESCRIPTION

31 irmc R/W Isochronous resource-manager capable. IEEE 1394 bus-management field. Must be valid when bit 17

30 cmc R/W Cycle master capable. IEEE 1394 bus-management field. Must be valid when bit 17 (linkEnable) in the

29 isc R/W Isochronous support capable. IEEE 1394 bus-management field. Must be valid when bit 17

28 bmc R/W Bus manager capable. IEEE 1394 bus-management field. Must be valid when bit 17 (linkEnable) in

27 pmc R/W Power-management capable. IEEE 1394 bus-management field. When bit 27 is set to 1, this indicates

26--24 RSVD R Reserved. Bits 26--24 return 0s when read.

23--16 cyc_clk_acc R/W Cycle master clock accuracy, in parts per million. IEEE 1394 bus-management field. Must be valid

15--12 max_rec R/W Maximum request. IEEE 1394 bus-management field. Hardware initializes this field to indicate the

11- -8 RSVD R Reserved. Bits 11--8 return 0s when read.

7--6 g R/W Generation counter. This field is incremented if any portion of the configuration ROM has been

5--3 RSVD R Reserved. Bits 5--3 return 0s when read.

2--0 Lnk_spd R Link speed. This field returns 010, indicating that the link speeds of 100M bits/s, 200M bits/s, and

(linkEnable) in the host controller control register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control Register) is set to 1.

host controller control register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control Register) is set to 1.

(linkEnable) in the host controller control register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control Register) is set to 1.

the host controller control register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control Register) is set to 1.

that the node is power-management capable. Must be valid when bit 17 (linkEnable) in the host controller control register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control Register) is set to 1.

when bit 17 (linkEnable) in the host controller control register at OHCI offset 50h/54h (seeSection 4.16, Host Controller Control Register) is set to 1.

maximum number of bytes in a block request packet that is supported by the implementation. This value, max_rec_bytes must be 512 or greater, and is calculated by 2^(max_rec + 1). Software may change this field; however, this field must be valid at any time bit 17 (linkEnable) in the host controller control register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control Register)issetto

1. A received block write request packet with a length greater than max_rec_bytes may generate an ack_type_error. This field is not affected by a software reset, and defaults to a value indicating 4096 bytes on a system (hardware) reset.

incremented since the prior bus reset.

400M bits/s are supported.

4--9

4.10 GUID High Register

The GUID high register represents the upper quadlet in a 64-bit global unique ID (GUID) whic h maps to the third quadlet in the Bus_Info_Block. This register contains node_vendor_ID and chip_ID_hi fields. This register initializes to 0s on a system (hardware) reset, which is an illegal GUID value. If a serial EEPROM is detected, then the contents of this register are loaded through the serial EEPROM interface after a PCI_RST

. At that point, the contents of this register cannot be changed. If no serial EEPROM is detected, then the contents of this register are loaded by the BIOS after a PCI_RST

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name GUID high

Typ e R R R R R R R R R R R R R R R R

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name GUID high

Typ e R R R R R R R R R R R R R R R R

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

. At that point, the contents of this register cannot be changed.

4.11 GUID Low Register

The GUID low register represents the lower quadlet in a 64-bit global unique ID (GUID) which maps to chip_ID_lo in the Bus_Info_Block. This register initializes to 0s on a system (hardware) reset and behaves identically to the GUID high register at OHCI offset 24h (see Section 4.10, GUID High Register).

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name GUID low

Typ e R R R R R R R R R R R R R R R R

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name GUID low

Typ e R R R R R R R R R R R R R R R R

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

4--10

4.12 Configuration ROM Mapping Register

The configuration ROM mapping register contains the start address within system memory that maps to the start address of 1394 configuration ROM for this node. See Table 4--8 for a complete description of the register contents .

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Configuration ROM mapping

Typ e R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Configuration ROM mapping

Typ e R/W R/W R/W R/W R/W R/W R R R R R R R R R R

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 4--8. Configuration ROM Mapping Register Description

BIT FIELD NAME TYPE DESCRIPTION

31--10 configROMaddr R/W If a quadlet read request to 1394 offset FFFF F000 0400h through offset FFFF F000 07FFh is

9--0 RSVD R Reserved. Bits 9--0 return 0s when read.

received, then the low-order 10 bits of the offset are added to this regis ter to determine the host memory address of the read request.

4.13 Posted Write Address Low Register

The posted write address low register communicates error information if a write request is posted and an error occurs while writing the posted data packet. See Table 4--9 for a complete description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Posted write address low

Typ e RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU

Default X X X X X X X X X X X X X X X X

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Posted write address low

Typ e RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU

Default X X X X X X X X X X X X X X X X

Table 4--9. Posted Write Address Low Register Description

BIT FIELD NAME TYPE DESCRIPTION

31--0 offsetLo RU The lower 32 bits of the 1394 destination offset of the write request that failed.

4--11

4.14 Posted Write Address High Register

The posted write address high register communicates error information if a write request is posted and an error occurs while writing the posted data packet. See Table 4--10 for a complete description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Posted write address high

Typ e RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU

Default X X X X X X X X X X X X X X X X

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Posted write address high

Typ e RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU

Default X X X X X X X X X X X X X X X X

Table 4--10. Posted Write Address High Register Description

BIT FIELD NAME TYPE DESCRIPTION

31--16 sourceID RU This field is the 10-bit bus number (bits 31--22) and 6-bit node number (bits 21--16) of the node that

15--0 offsetHi RU The upper 16 bits of the 1394 destination offset of the write request that failed.

issued the write request that failed.

4--12

4.15 Vendor ID Register

The vendor ID register provides the company ID of an organiz ation that specifies any vendor-unique registers or features. The TSB82AA2 device implements several unique features with regards to OHCI. Therefore, bits 23--0 are programmed with Texas Instruments OUI, 0X08 0028.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Vendor ID

Typ e R R R R R RU RU R R R R R R R R R

Default 0 0 0 0 0 X X 0 0 0 0 0 1 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Vendor ID

Typ e R R R R R R R R R R R R R R R R

Default 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0

Table 4--11. Vendor ID Register Description

BIT FIELD NAME TYPE DESCRIPTION

31--27 RSVD R Reserved. Bits 31--27 return 0s when read.

26 PME_Enhance RU Bit 26 is conditionally set based on the value of bit 10 (Ignore IntMask.masterIntEnable_for_pme) in

25 OHCI12_draft RU OHCI 1.2 draft features. Bit 25 is conditionally set based on the value of bit 14 (EnableDraft) in the

24 Iso_enhancements R Isochronous enhancements. Bit 24 is set to 1 indicating that it supports the isochronous

23--0 vendorCompanyID R Vendor company organizational unique ID. This field returns Texas Instruments OUI, 24’h080028,

the miscellaneous configuration register at offset F0h in the PCI configuration space (see Section 3.23, Miscellaneous Configuration Register). If bit 10 is set to 1, then bit 26 is set to 1 to indicate that the device supports the generation of PME (masterIntEnable) in the interrupt mask register at OHCI offset 88h (see Section 4.22, Interrupt Mask Register). If bit 10 is not set, then bit 26 returns 0.

link enhancement control register at offset F4h in the PCI configuration space (see Section 3.24, Link Enhancement Control Register). If bit 14 is set to 1, then bit 25 is set to 1 to indicate that the device supports some features which have been defined in the OHCI 1.2 specification draft. If bit 14 is not set, then bit 25 returns 0.

enhancements defined in Sections 4.4 and 4.5.

indicating that the device supports unique features defined by TI.

regardless of the status of bit 31

4--13

4.16 Host Controller Control Register

The host controller control set/clear register pair provides flags for controlling the TSB82AA2 device. See Table 4--12 for a complete description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Host controller control

Typ e RSU RSC RSC R R R R R RC RSC R R RSC RSC RSC RSCU

Default 0 X 0 0 0 0 0 0 0 0 0 0 0 X 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Host controller control

Typ e R R R R R R R R R R R R R R R R

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: Host controller control Type: Read/Set/Clear/Update, Read/Set/Clear, Read/Clear, Read-only Offset: 50h set register

54h clear register

Default: X00X 0000h

Table 4--12. Host Controller Control Register Description

BIT FIELD NAME TYPE DESCRIPTION

31 BIBimageValid RSU When bit 31 is set to 1, the TSB82AA2 physical response unit is enabled to respond to block read

30 noByteSwapData RSC Bit 30 controls whether physical accesses to locations outside the TSB82AA2 device itself, as

29 ack_Tardy_enable RSC Bit 29 controls the acknowledgement of ack_tardy. When bit 29 is set to 1, ack_tardy may be

28--24 RSVD R Reserved. Bits 28--24 return 0s when read.

23 programPhyEnable RC Bit23 informs upper-level software that lower-level software has consistently configured the IEEE

requests to host configuration ROM and to the mechanism for atomically updating configuration ROM. Software creates a valid image of the bus_info_block in host configuration ROM before setting this bit.

When this bit is cleared, the TSB82AA2 device returns ack_type_error on block read requests to host configuration ROM. Also, when this bit is cleared and a 1394 bus reset occurs, the configuration ROM mapping register at OHCI offset 34h (see Section 4.12, Configuration ROM

Mapping Register), configuration ROM header register at OHCI offset 18h (see Section 4.7, Configuration ROM Header Register), and bus options register at OHCI offset 20h (see

Section 4.9, Bus Options Register) are not updated.

Software can set this bit only when bit 17 (linkEnable) is 0. Once bit 31 is set to 1, it can be cleared by a system (hardware) reset, a software reset, or if a fetch error occurs when the TSB82AA2 device loads bus_info_block registers from host memory.

well as any other DMA data accesses, are byte swapped.

returned as an acknowledgment to configuration ROM accesses from 1394 to the TSB82AA2 device, including accesses to the bus_info_block. The TSB82AA2 device returns ack_tardy to all other asynchronous packets addressed to the TSB82AA2 node. When the TSB82AA2 device sends ack_tardy, bit 27 (ack_tardy) in the interrupt event register at OHCI offset 80h/84h (see Section 4.21, Interrupt Event Register) is set to 1 to indicate the attempted asynchronous access.

Software ensures that bit 27 (ack_tardy) in the interrupt event register is 0. Software also unmasks wake-up interrupt events such as bit 19 (phy) and bit 27 (ack_tardy) in the interrupt event register before placing the device into D1.

Software does not set this bit if the TSB82AA2 node is the 1394 bus manager.

1394a-2000 enhancements in the link and PHY devices. When this bit is 1, generic software such as the OHCI driver is responsible for configuring IEEE 1394a-2000 enhancements in the PHY device and bit 22 (aPhyEnhanceEnable) in the TSB82AA2 device. When this bit is 0, the generic software may not modify the IEEE 1394a-2000 enhancements in the TSB82AA2 or PHY device and cannot interpret the setting of bit 22 (aPhyEnhanceEnable). This bit is initialized from the serial EEPROM.

4--14

Table 4--12. Host Controller Control Register Description (Continued)

BIT FIELD NAME TYPE DESCRIPTION

22 aPhyEnhanceEnable RSC When bits 23 (programPhyEnable) and 17 (linkEnable) are 1, the OHCI driver can set bit 22 to

21--20 RSVD R Reserved. Bits 21--20 return 0s when read.

19 LPS RSC Bit 19 controls the link power status. Software must set this bit to 1 to permit link-PHY

18 postedWriteEnable RSC Bit 18 enables (1) or disables (0) posted writes. Software changes this bit only when bit 17

17 linkEnable RSC Bit 17 is cleared to 0 by either a system (hardware) or software reset. Software must set this bit

16 SoftReset RSCU When bit 16 is set to 1, all TSB82AA2 states are reset, all FIFOs are flushed, and all OHCI

15--0 RSVD R Reserved. Bits 15--0 return 0s when read.

1 to use all IEEE 1394a-2000 enhancements. When bit 23 (programPhyEnable) is cleared to 0, the software does not change PHY enhancements or this bit.

communication. A 0 prevents link-PHY communication.

The OHCI-link is divided into two clock domains (PCI_CLK and PHY_SCLK). If software tries to access any register in the PHY_SCLK domain while the PHY_SCLK is disabled, then a target abort is issued by the link. This problem can be avoided by setting bit 4 (DIS_TGT_ABT) in the miscellaneous configuration register at offset F0h in the PCI configuration space (see Section 3.23, Miscellaneous Configuration Register). This allows the link to respond to these types of request by returning all Fs (hex).

OHCI registers at offsets DCh--F0h and 100h--11Ch are in the PHY_SCLK domain.

After setting LPS, software must wait approximately 10 ms before attempting to access any of the OHCI registers. This gives the PHY_SCLK time to stabilize.

(linkEnable) is 0.

to 1 when the system is ready to begin operation and then force a bus reset. This bit is necessary to keep other nodes from sending transactions before the local system is ready. When this bit is cleared, the TSB82AA2 device is logically and immediately dis connected from the 1394 bus, no packets are received or processed, nor are packets transmitted.

registers are set to their system (hardware) reset values, unless otherwise specified. PCI registers are not affected by this bit. This bit remains set to 1 while the software reset is in progress and reverts back to 0 when the reset has completed.

4.17 Self-ID Buffer Pointer Register

The self-ID buffer pointer register points to the 2K-byte aligned base address of the buffer in host memory where the self-ID packets are stored during bus initialization. Bits 31--11 are read/write accessible. Bits 10--0 are reserved, and return 0s when read.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Self-ID buffer pointer

Typ e R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Default X X X X X X X X X X X X X X X X

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Self-ID buffer pointer

Typ e R/W R/W R/W R/W R/W R R R R R R R R R R R

Default X X X X X 0 0 0 0 0 0 0 0 0 0 0

4--15

4.18 Self-ID Count Register

The self-ID count register keeps a count of the number of times the bus self-ID process has occurred, flags self-ID packet errors, and keeps a count of the self-ID data in the self-ID buffer. See Table 4--13 for a complete description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Self-ID count

Typ e RU R R R R R R R RU RU RU RU RU RU RU RU

Default X 0 0 0 0 0 0 0 X X X X X X X X

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Self-ID count

Typ e R R R R R RU RU RU RU RU RU RU RU RU R R

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 4--13. Self-ID Count Register Description

BIT FIELD NAME TYPE DESCRIPTION

31 selfIDError RU When bit 31 is set to 1, an error was detected during the most recent self-ID packet reception. The

30--24 RSVD R Reserved. Bits 30--24 return 0s when read.

23--16 selfIDGeneration RU The value in this field increments each time a bus reset is detected. This field rolls over to 0 after

15--11 RSVD R Reserved. Bits 15--11 return 0s when read.

10--2 selfIDSize RU This field indicates the number of quadlets that have been written into the self-ID buffer for the current

1--0 RSVD R Reserved. Bits 1--0 return 0s when read.

contents of the self-ID buffer are undefined. This bit is cleared after a self-ID reception in which no errors are detected. Note that an error can be a hardware error or a host bus write error.

reaching 255.

bits 23--16 (selfIDGeneration field). This includes the header quadlet and the self-ID data. This field is cleared to 0s when the self-ID reception begins.

4--16

4.19 Isochronous Receive Channel Mask High Register

The isochronous receive channel mask high set/clear register enables packet receives from the upper 32 isochronous data channels. A read from either the set register or clear register returns the content of the isochronous receive channel mask high register. See Table 4--14 for a complete description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Isochronous receive channel mask high

Typ e RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC

Default X X X X X X X X X X X X X X X X

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Isochronous receive channel mask high

Typ e RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC

Default X X X X X X X X X X X X X X X X

74h clear register

Default: XXXX XXXXh

Table 4--14. Isochronous Receive Channel Mask High Register Description

BIT FIELD NAME TYPE DESCRIPTION

31 isoChannel63 RSC When bit 31 is set to 1, the TSB82AA2 device is enabled to receive from isochronous channel number 63.

30 isoChannel62 RSC When bit 30 is set to 1, the TSB82AA2 device is enabled to receive from isochronous channel number 62.

29 isoChannel61 RSC When bit 29 is set to 1, the TSB82AA2 device is enabled to receive from isochronous channel number 61.

28 isoChannel60 RSC When bit 28 is set to 1, the TSB82AA2 device is enabled to receive from isochronous channel number 60.

27 isoChannel59 RSC When bit 27 is set to 1, the TSB82AA2 device is enabled to receive from isochronous channel number 59.

26 isoChannel58 RSC When bit 26 is set to 1, the TSB82AA2 device is enabled to receive from isochronous channel number 58.

25 isoChannel57 RSC When bit 25 is set to 1, the TSB82AA2 device is enabled to receive from isochronous channel number 57.

24 isoChannel56 RSC When bit 24 is set to 1, the TSB82AA2 device is enabled to receive from isochronous channel number 56.

23 isoChannel55 RSC When bit 23 is set to 1, the TSB82AA2 device is enabled to receive from isochronous channel number 55.

22 isoChannel54 RSC When bit 22 is set to 1, the TSB82AA2 device is enabled to receive from isochronous channel number 54.

21 isoChannel53 RSC When bit 21 is set to 1, the TSB82AA2 device is enabled to receive from isochronous channel number 53.

20 isoChannel52 RSC When bit 20 is set to 1, the TSB82AA2 device is enabled to receive from isochronous channel number 52.

19 isoChannel51 RSC When bit 19 is set to 1, the TSB82AA2 device is enabled to receive from isochronous channel number 51.

18 isoChannel50 RSC When bit 18 is set to 1, the TSB82AA2 device is enabled to receive from isochronous channel number 50.

17 isoChannel49 RSC When bit 17 is set to 1, the TSB82AA2 device is enabled to receive from isochronous channel number 49.

16 isoChannel48 RSC When bit 16 is set to 1, the TSB82AA2 device is enabled to receive from isochronous channel number 48.

15 isoChannel47 RSC When bit 15 is set to 1, the TSB82AA2 device is enabled to receive from isochronous channel number 47.

14 isoChannel46 RSC When bit 14 is set to 1, the TSB82AA2 device is enabled to receive from isochronous channel number 46.

13 isoChannel45 RSC When bit 13 is set to 1, the TSB82AA2 device is enabled to receive from isochronous channel number 45.

12 isoChannel44 RSC When bit 12 is set to 1, the TSB82AA2 device is enabled to receive from isochronous channel number 44.

11 isoChannel43 RSC When bit 11 is set to 1, the TSB82AA2 device is enabled to receive from isochronous channel number 43.

10 isoChannel42 RSC When bit 10 is set to 1, the TSB82AA2 device is enabled to receive from isochronous channel number 42.

9 isoChannel41 RSC When bit 9 is set to 1, the TSB82AA2 device is enabled to receive from isochronous channel number 41.

8 isoChannel40 RSC When bit 8 is set to 1, the TSB82AA2 device is enabled to receive from isochronous channel number 40.

7 isoChannel39 RSC When bit 7 is set to 1, the TSB82AA2 device is enabled to receive from isochronous channel number 39.

4--17

Table 4--14. Isochronous Receive Channel Mask High Register Description (Continued)

BIT FIELD NAME TYPE DESCRIPTION

6 isoChannel38 RSC When bit 6 is set to 1, the TSB82AA2 device is enabled to receive from isochronous channel number 38.

5 isoChannel37 RSC When bit 5 is set to 1, the TSB82AA2 device is enabled to receive from isochronous channel number 37.

4 isoChannel36 RSC When bit 4 is set to 1, the TSB82AA2 device is enabled to receive from isochronous channel number 36.

3 isoChannel35 RSC When bit 3 is set to 1, the TSB82AA2 device is enabled to receive from isochronous channel number 35.

2 isoChannel34 RSC When bit 2 is set to 1, the TSB82AA2 device is enabled to receive from isochronous channel number 34.

1 isoChannel33 RSC When bit 1 is set to 1, the TSB82AA2 device is enabled to receive from isochronous channel number 33.

0 isoChannel32 RSC When bit 0 is set to 1, the TSB82AA2 device is enabled to receive from isochronous channel number 32.

4.20 Isochronous Receive Channel Mask Low Register

The isochronous receive channel mask low set/clear register enables packet receives from the lower 32 isochronous data channels. See Table 4--15 for a complete description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Isochronous receive channel mask low

Typ e RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC

Default X X X X X X X X X X X X X X X X

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Isochronous receive channel mask low

Typ e RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC

Default X X X X X X X X X X X X X X X X

7Ch clear register

Default: XXXX XXXXh

Table 4--15. Isochronous Receive Channel Mask Low Register Description

BIT FIELD NAME TYPE DESCRIPTION

31 isoChannel31 RSC When bit 31 is set to 1, the TSB82AA2 device is enabled to receive from isochronous channel number 31.

30 isoChannel30 RSC When bit 30 is set to 1, the TSB82AA2 device is enabled to receive from isochronous channel number 30.

29--2 isoChanneln RSC Bits 29 through 2 (isoChanneln, where n = 29, 28, 27, …, 2) follow the same pattern as bits 31 and 30.

1 isoChannel1 RSC When bit 1 is set to 1, the TSB82AA2 device is enabled to receive from isochronous channel number 1.

0 isoChannel0 RSC When bit 0 is set to 1, the TSB82AA2 device is enabled to receive from isochronous channel number 0.

4--18

4.21 Interrupt Event Register

The interrupt event set/clear register reflects the state of the various TSB82AA2 interrupt sources. The interrupt bits are set to 1 by an asserting edge of the corresponding interrupt signal or by writinga1inthecorresponding bit in the set register. The only mechanis m to clear a bit in this register is to write a 1 to the corresponding bit in the clear register.

This register is fully compliant with 1394 Open Host Controller Interface Specification, and the TSB82AA2 device adds a vendor-specific interrupt function to bit 30. When the interrupt event register is read, the return value is the bit-wise AND function of the interrupt event and interrupt mask registers. See Table 4--16 for a complete description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Interrupt event

Typ e R RSC RSC R RSCU RSCU RSCU RSCU RSCU RSCU RSCU RSCU RSCU RSCU RSCU RSCU

Default 0 X 0 0 0 X X X X X X X X 0 X X

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Interrupt event

Typ e RSCU R R R R R RSCU RSCU RU RU RSCU RSCU RSCU RSCU RSCU RSCU

Default 0 0 0 0 0 0 X X X X X X X X X X

84h clear register [returns the content of the interrupt event register bit-wise ANDed with

the interrupt mask register when read]

Default: XXXX 0XXXh

Table 4--16. Interrupt Event Register Description

BIT FIELD NAME TYPE DESCRIPTION

31 RSVD R Reserved. Bit 31 returns 0 when read.

30 vendorSpecific RSC This vendor-specific interrupt event is reported when either of the general-purpose interrupts are

29 SoftInterrupt RSC Software interrupt. Bit 29 is used by software to generate a TSB82AA2 interrupt for its own use.

28 RSVD R Reserved. Bit 28 returns 0 when read.

27 ack_Tardy RSCU Bit 27 is set to 1 when bit 29 (ack_Tardy_enable) in the host controller control register at OHCI offset

26 phyRegRcvd RSCU The TSB82AA2 device has received a PHY register data byte which can be read from bits 23--16 in

25 cycleTooLong RSCU If bit 21 (cycleMaster) in the link control register at OHCI offset E0h/E4h (see Section 4.31, Link

24 unrecoverableError RSCU This event occurs when the TSB82AA2 device encounters any error that forces it to stop operations

23 cycleInconsistent RSCU A cycle start was received that had values for cycleSeconds and cycleCount fields that are different

asserted. The general-purpose interrupts are enabled by setting the corresponding bits INT_3EN and INT_2EN (bits 31 and 23, respectively) to 1 in the GPIO control register at offset FCh in the PCI configuration space (see Section 3.26, GPIO Control Register).

50h/54h (see Section 4.16, Host Controller Control Register) is set to 1 and any of the following conditions occur:

a. Data is present in the receive FIFO that is to be delivered to the host. b. The physical response unit is busy processing requests or sending responses. c. The TSB82AA2 device sent an ack_tardy acknowledgement.

the PHY layer control register at OHCI offset ECh (see Section 4.33, PHY Layer Control Register).

Control Register) is set to 1, then this indicates that over 125 µs have elapsed between the start of sending a cycle start packet and the end of a subaction gap. Bit 21 (cycleMaster) in the link control register is cleared by this event.

on any or all of its subunits, for example, when a DMA context sets its dead bit to 1. While bit 24 is set to 1, all normal interrupts for the context(s) that caused this interrupt are blocked from being set to 1.

from the values in bits 31--25 (cycleSeconds field) and bits 24--12 (cycleCount field) in the isochronous cycle timer register at OHCI offset F0h (see Section 4.34, Isochronous Cy cle Timer Register).

4--19

Table 4--16. Interrupt Event Register Description (Continued)

BIT FIELD NAME TYPE DESCRIPTION

22 cycleLost RSCU A lost cycle is indicated when no cycle_start packet is sent or received between two successive

21 cycle64Seconds RSCU Indicates that the 7thbit of the cycle second counter has changed.

20 cycleSynch RSCU Indicates that a new isochronous cycle has started. Bit 20 is set to 1 when the low order bit of the

19 phy RSCU Indicates that the PHY device requests an interrupt through a status transfer.

18 regAccessFail RSCU Indicates that a TSB82AA2 register access has failed due to a missing SCLK clock signal from the

17 busReset RSCU Indicates that the PHY device has entered bus reset mode.

16 selfIDcomplete RSCU A self-ID packet stream has been received. It is generated at the end of the bus initialization process.

15 selfIDcomplete2 RSCU Secondary indication of the end of a self-ID packet stream. Bit 15 is set to 1 by the TSB82AA2 device

14--10 RSVD R Reserved. Bits 14--10 return 0s when read.

9 lockRespErr RSCU Indicates that the TSB82AA2 device sent a lock response for a lock request to a serial bus register,

8 postedWriteErr RSCU Indicates that a host bus error oc curred while the TSB82AA2 device was trying to write a 1394 write

7 isochRx RU Isochronous receive DMA interrupt. Indicates that one or more isochronous receive contexts have

6 isochTx RU Isochronous transmit DMA interrupt. Indicates that one or more isochronous transmit contexts hav e

5 RSPkt RSCU Indic ates that a packet was sent to an asynchronous receive response context buffer and the

4 RQPkt RSCU Indicates that a packet was sent to an asynchronous receive request context buffer and the

3 ARRS RSCU Asynchronous receive response DMA interrupt. Bit 3 is conditionally set to 1 upon completion of an

2 ARRQ RSCU Asynchronous receive request DMA interrupt. Bit 2 is conditionally set to 1 upon completion of an

1 respTxComplete RSCU Asynchronous response transmit DMA interrupt. Bit 1 is conditionally set to upon completion of an

0 reqTxComplete RSCU Asynchronous request transmit DMA interrupt. Bit 0 is conditionally set to 1 upon completion of an

cycleSynch events. A lost cycle can be predicted when a cycle_start packet does not immediately follow the first subaction gap after the cycleSynchevent or if an arbitration reset gap is detected after a cycleSynch event without an intervening cycle start. Bit 22 may be set either when a lost cycle occurs or when logic predicts that one will occur.

cycle count toggles.

PHY device. When a register access fails, bit 18 is set to 1 before the next register acc ess.

Bit 16 is turned off simultaneously when bit 17 (busReset) is turned on.

when it sets bit 16 (selfIDcomplete), and retains its state, independent of bit 17 (busReset).

but did not receive an ack_complete.

request, which had already been given an ack_complete, into system memory.

generated an interrupt. This is not a latched event; it is the logical OR of all bits in the isochronous receive interrupt event register at OHCI offset A0h/A4h (see Section 4.25, Isochronous Receive Interrupt Event Register) and isochronous receive interrupt mask register at OHCI offset A8h/ACh (see Section 4.26, Isochronous Receive Interrupt Mask Register). The isochronous receive interrupt event register indicates which contexts have been interrupted.

generated an interrupt. This is not a latched event, it is the logical OR of all bits in the isochronous transmit interrupt event register at OHCI offset 90h/94h (see Section 4.23, Isochronous Transmit Interrupt Event Register) and isochronous transmit interrupt mask register at OHCI offset 98h/9Ch (see Section 4.24, Isochronous Transmit Interrupt Mask Register). The isochronous transmit interrupt event register indicates which contexts have been interrupted.

descriptor’s xferStatus and resCount fields have been updated.

ARRS DMA context command descriptor.

ARRQ DMA context command descriptor.

ATRS DMA command.

ATRQ DMA command.

4--20

4.22 Interrupt Mask Register

The interrupt mask set/clear register enables the various TSB82AA2 interrupt sources. Reads from either the set register or the clear register always return the contents of the interrupt mask register. In all cases except bit 31 (masterIntEnable) and bit 30 (VendorSpecific), the enables for each interrupt event align with the interrupt event register bits detailed in Table 4--16.

This register is fully compliant with 1394 Open Host Controller Interface Specification, and the TSB82AA2 device adds a vendor-specific interrupt function to bit 30. See Table 4--17 for a description of bits 31 and 30.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Interrupt mask

Typ e RSCU RSC RSC R RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC

Default X X 0 0 0 X X X X X X X X 0 X X

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Interrupt mask

Typ e RSC R R R R R RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC

Default 0 0 0 0 0 0 X X X X X X X X X X

8Ch clear register

Default: XXXX 0XXXh

Table 4--17. Interrupt Mask Register Description

BIT FIELD NAME TYPE DESCRIPTION

31 masterIntEnable RSCU Master interrupt enable. If bit 31 is set to 1, then the external interrupts are generated in accordance

30 VendorSpecific RSC When this bit and bit 30 (vendorSpecific) in the interrupt event register at OHCI offset 80h/84h (see

29 SoftInterrupt RSC When this bit and bit 29 (SoftInterrupt) in the interrupt event register at OHCI offset 80h/84h (see

28 RSVD R Reserved. Bit 28 returns 0 when read.

27 ack_tardy RSC When this bit and bit 27 (ack_tardy) in the interrupt event register at OHCI offset 80h/84h (see

26 phyRegRcvd RSC When this bit and bit 26 (phyRegRcvd) in the interrupt event register at OHCI offset 80h/84h (see

25 cycleTooLong RSC When this bit and bit 25 (cycleTooLong) in the interrupt event register at OHCI offset 80h/84h (see

24 unrecoverableError RSC When this bit and bit 24 (unrecoverableError) in the interrupt event register at OHCI offset 80h/84h

23 cycleInconsistent RSC When this bit and bit23 (cycleInconsistent) in the interrupt event registerat OHCI offset 80h/84h (see

22 cycleLost RSC When this bit and bit 22 (cycleLost) in the interrupt event register at OHCI offset 80h/84h (see

with the interrupt mask register. If bit 31 is cleared, then the external interrupts are not generated regardless of the interrupt mask register settings.

Section 4.21, Interrupt Event Register) are set to 1, this vendor-specific interrupt mask enables interrupt generation.

Section 4.21, Interrupt Event Register) are set to 1, this soft-interrupt mask enables interrupt generation.

Section 4.21, Interrupt Event Register) are set to 1, this acknowledge-tardy interrupt mask enables interrupt generation.

Section 4.21, Interrupt Event Register) are set to 1, this PHY-registerinterrupt mask enables interrupt generation.

Section 4.21, Interrupt Event Register) are set to 1, this cycle-too-long interrupt mask enables interrupt generation.

(see Section 4.21, Interrupt Event Register) are set to 1, this unrecoverable-error interrupt mask enables interrupt generation.

Section 4.21, Interrupt Event Register) are set to 1, this inconsistent-cycle interrupt mask enables interrupt generation.

Section 4.21, Interrupt Event Register) are set to 1, this lost-cycle interrupt mask enables interrupt generation.

4--21

Table 4--17. Interrupt Mask Register Description (Continued)

BIT FIELD NAME TYPE DESCRIPTION

21 cycle64Seconds RSC When this bit and bit 21 (cycle64Seconds) in the interrupt event register at OHCI offset 80h/84h (see

20 cycleSynch RSC When this bit and bit 20 (cycleSynch) in the interrupt event register at OHCI offset 80h/84h (see

19 phy RSC When this bit and bit 19 (phy) in the interrupt event register at OHCI offset 80h/84h (see Section 4.21,

18 regAccessFail RSC When this bit and bit 18 (regAccessFail) in the interrupt event register at OHCI offset 80h/84h (see

17 busReset RSC When this bit and bit 17 (busReset) in the interrupt event register at OHCI offset 80h/84h (see

16 selfIDcomplete RSC When this bit and bit 16 (selfIDcomplete) in the interrupt event register at OHCI offset 80h/84h (see

15 selfIDcomplete2 RSC When this bit and bit 15 (selfIDcomplete2) in the interrupt event register at OHCI offset 80h/84h (see

14--10 RSVD R Reserved. Bits 14--10 return 0s when read.

9 lockRespErr RSC When this bit and bit 9 (lockRespErr) in the interrupt event register at OHCI offset 80h/84h (see

8 postedWriteErr RSC When this bit and bit 8 (postedWriteErr) in the interrupt event register at OHCI offset 80h/84h (see

7 isochRx RSC When this bit and bit 7 (isochRx) in the interrupt event register at OHCI offset 80h/84h (see

6 isochTx RSC When this bit and bit 6 (isochTx) in the interrupt event register at OHCI offset 80h/84h (see

5 RSPkt RSC When this bit and bit 5 (RSPkt) in the interrupt event register at OHCI offset 80h/84h (see Section 4.21,

4 RQPkt RSC When this bit and bit 4 (RQPkt) in the interrupt event register at OHCI offset 80h/84h (see Section 4.21,

3 ARRS RSC When this bit and bit 3 (ARRS) in the interrupt event register at OHCI offset 80h/84h (see Section 4.21,

2 ARRQ RSC When this bit and bit 2 (ARRQ) in the interrupt event register at OHCI offset 80h/84h (see Section 4.21,

1 respTxComplete RSC When this bit and bit 1 (respTxComplete) in the interrupt event register at OHCI offset 80h/84h (see

0 reqTxComplete RSC When this bit and bit 0 (reqTxComplete) in the interrupt event register at OHCI offset 80h/84h (see

Section 4.21, Interrupt Event Register) are set to 1, this 64-second-cycle interrupt mask enables interrupt generation.

Section 4.21, Interrupt Event Register) are set to 1, this isochronous-cycle interrupt mask enables interrupt generation.

Interrupt Event Register) are set to 1, this PHY-status-transfer interrupt mask enables interrupt generation.

Section 4.21, Interrupt Event Register) are set to 1, this register-access-failed interrupt mask enables interrupt generation.

Section 4.21, Interrupt Event Register) are set to 1, this bus-reset interrupt mask enables interrupt generation.

Section 4.21, Interrupt Event Register) are set to 1, this self-ID-complete interrupt mask enables interrupt generation.

Section 4.21, Interrupt Event Register) are set to 1, this second-self-ID-complete interrupt mask enables interrupt generation.

Section 4.21, Interrupt Event Register) are set to 1, this lock-response-error interrupt mask enables interrupt generation.

Section 4.21, Interrupt Event Register) are set to 1, this posted-write-error interrupt mask enables interrupt generation.

Section 4.21, Interrupt Event Register) are set to 1, this isochronous-receive-DMA interrupt mask enables interrupt generation.

Section 4.21, Interrupt Event Register) are set to 1, this isochronous-transmit-DMA interrupt mask enables interrupt generation.

Interrupt Event Register) are set to 1, this receive-response-packet interrupt mask enables interrupt generation.

Interrupt Event Register) are set to 1, this receive-request-packet interrupt mask enables interrupt generation.

Interrupt Event Register) are set to 1, this asynchronous-receive-response-DMA interrupt mask enables interrupt generation.

Interrupt Event Register) are set to 1, this asy nchronous-receive-request-DMA interrupt mask enables interrupt generation.

Section 4.21, Interrupt Event Register) are set to 1, this response-transmit-complete interrupt mask enables interrupt generation.

Section 4.21, Interrupt Event Register) are set to 1, this request-transmit-complete interrupt mask enables interrupt generation.

4--22

4.23 Isochronous Transmit Interrupt Event Register

The isochronous transmit interrupt event set/clear register reflects the interrupt state of the isochronous transmit contexts. An interrupt is generated on behalf of an isochronous transmit context if an OUTPUT_LAST* command completes and its interrupt bits are set to 1. Upon determining that the isochTx (bit 6) interrupt has occurred in the interrupt event register at OHCI offset 80h/84h (see Section 4.21, Interrupt Event Register), software can check this register to determine which context(s) caused the interrupt. The interrupt bits are set to 1 by an asserting edge of the corresponding interrupt signal, or by writinga1inthecorresponding bit in the set register. The only mechanism to clear a bit in this register is to write a 1 to the corresponding bit in the clear register. See Table 4--18 for a complete description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Isochronous transmit interrupt event

Typ e R R R R R R R R R R R R R R R R

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Isochronous transmit interrupt event

Typ e R R R R R R R R RSC RSC RSC RSC RSC RSC RSC RSC

Default 0 0 0 0 0 0 0 0 X X X X X X X X

94h clear register [returns the contents of the isochronous transmit interrupt event

Default: 0000 00XXh

Table 4--18. Isochronous Transmit Interrupt Event Register Description

BIT FIELD NAME TYPE DESCRIPTION

31--8 RSVD R Reserved. Bits 31--8 return 0s when read.

7 isoXmit7 RSC Isochronous transmit channel 7 caused the interrupt event register bit 6 (isochTx) interrupt.

6 isoXmit6 RSC Isochronous transmit channel 6 caused the interrupt event register bit 6 (isochTx) interrupt.

5 isoXmit5 RSC Isochronous transmit channel 5 caused the interrupt event register bit 6 (isochTx) interrupt.

4 isoXmit4 RSC Isochronous transmit channel 4 caused the interrupt event register bit 6 (isochTx) interrupt.

3 isoXmit3 RSC Isochronous transmit channel 3 caused the interrupt event register bit 6 (isochTx) interrupt.

2 isoXmit2 RSC Isochronous transmit channel 2 caused the interrupt event register bit 6 (isochTx) interrupt.

1 isoXmit1 RSC Isochronous transmit channel 1 caused the interrupt event register bit 6 (isochTx) interrupt.

0 isoXmit0 RSC Isochronous transmit channel 0 caused the interrupt event register bit 6 (isochTx) interrupt.

4--23

4.24 Isochronous Transmit Interrupt Mask Register

The isochronous transmit interrupt mask set/clear register enables the isochTx interrupt source on a per-c hannel basis. Reads from either the set register or the clear register always return the contents of the isochronous transmit interrupt mask register. In all cases, the enables for each interrupt event align with the event register bits detailed in Table 4--18.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Isochronous transmit interrupt mask

Typ e R R R R R R R R R R R R R R R R

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Isochronous transmit interrupt mask

Typ e R R R R R R R R RSC RSC RSC RSC RSC RSC RSC RSC

Default 0 0 0 0 0 0 0 0 X X X X X X X X

9Ch clear register

Default: 0000 00XXh

4--24

4.25 Isochronous Receive Interrupt Event Register

The isochronous receive interrupt event set/clear register reflects the interrupt state of the isochronous receive contexts. An interrupt is generated on behalf of an isochronous receive context if an INPUT_* command completes and its interrupt bits are set to 1. Upon determining that the isochRx (bit 7) interrupt in the interrupt event register at OHCI offset 80h/84h (see Section 4.21, Interrupt Event Register) has occurred, software can check this register to determine which context(s) caused the interrupt. The interrupt bits are set to 1 by an asserting edge of the corresponding interrupt signal, or by writinga1inthecorresponding bit in the set register. The only mechanism to clear a bit in this register is to write a 1 to the corresponding bit in the clear register. See Table 4--19 for a complete description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Isochronous receive interrupt event

Typ e R R R R R R R R R R R R R R R R

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Isochronous receive interrupt event

Typ e R R R R R R R R R R R R RSC RSC RSC RSC

Default 0 0 0 0 0 0 0 0 0 0 0 0 X X X X

A4h clear register [returns the contents of isochronous receive interrupt event register

bit-wise ANDed with the isochronous receive mask register when read]

Default: 0000 000Xh

Table 4--19. Isochronous Receive Interrupt Event Register Description

BIT FIELD NAME TYPE DESCRIPTION

31--4 RSVD R Reserved. Bits 31--4 return 0s when read.

3 isoRecv3 RSC Isochronous receive channel 3 caused the interrupt event register bit 7 (isochRx) interrupt.

2 isoRecv2 RSC Isochronous receive channel 2 caused the interrupt event register bit 7 (isochRx) interrupt.

1 isoRecv1 RSC Isochronous receive channel 1 caused the interrupt event register bit 7 (isochRx) interrupt.

0 isoRecv0 RSC Isochronous receive channel 0 caused the interrupt event register bit 7 (isochRx) interrupt.

4--25

4.26 Isochronous Receive Interrupt Mask Register

The isochronous receive interrupt mask set/clear register enables the isochRx interrupt source on a per-channel basis. Reads from either the set register or the clear register always return the contents of the isochronous receive interrupt mask register. In all cases, the enables for each interrupt event align with the isochronous receive interrupt event register bits detailed in Table 4--19.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Isochronous receive interrupt mask

Typ e R R R R R R R R R R R R R R R R

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Isochronous receive interrupt mask

Typ e R R R R R R R R R R R R RSC RSC RSC RSC

Default 0 0 0 0 0 0 0 0 0 0 0 0 X X X X

ACh clear register

Default: 0000 000Xh

4.27 Initial Bandwidth Available Register

The initial bandwidth available register value is loaded into the corresponding bus management CSR register on a system (hardware) or software reset. See Table 4--20 for a complete description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Initial bandwidth available

Typ e R R R R R R R R R R R R R R R R

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Initial bandwidth available

Typ e R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Default 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1

Table 4--20. Initial Bandwith Available Register Description

BIT FIELD NAME TYPE DESCRIPTION

31--13 RSVD R Reserved. Bits 31--13 return 0s when read.

12--0 InitBWAvailable R/W This field is reset to 1333h on a system (hardware)or software reset, and is not affected by a 1394 bus

reset. The value of this field is loaded into the BANDWIDTH_AVAILABLECSR register upon a G_RST PCI_RST

, or a 1394 bus reset.

4--26

4.28 Initial Channels Available High Register

The initial channels available high register value is loaded into the corresponding bus management CSR register on a system (hardware) or software reset. See Table 4--21 for a complete description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Initial channels available high

Typ e R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Default 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Initial channels available high

Typ e R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Default 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Table 4--21. Initial Channels Available High Register Description

BIT FIELD NAME TYPE DESCRIPTION

31--0 InitChanAvailHi R/W This field is reset to FFFF_FFFFh on a system (hardware) or software reset, and is not affected by

a 1394 bus reset. The value of this field is loaded into the CHANNELS_AVAILABLE_HI CSR register upon a G_RST

, PCI_RST, or a 1394 bus reset.

4.29 Initial Channels Available Low Register

The initial channels available low register value is loaded into the corresponding bus management CSR register on a system (hardware) or software reset. See Table 4--22 for a complete description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Initial channels available low

Typ e R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Default 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Initial channels available low

Typ e R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Default 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Table 4--22. Initial Channels Available Low Register Description

BIT FIELD NAME TYPE DESCRIPTION

31--0 InitChanAvailLo R/W This field is reset to FFFF_FFFFh on a system (hardware) or software reset, and is not affected by

a 1394 bus reset. The value of this field is loaded into the CHANNELS_AVAILABLE_LO CSR register upon a G_RST

, PCI_RST, or a 1394 bus reset.

4--27

4.30 Fairness Control Register

The fairness control register provides a mechanism by which software can direct the host controller to transmit multiple asynchronous requests during a fairness interval. See Table 4--23 for a complete description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Fairness control

Typ e R R R R R R R R R R R R R R R R

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Fairness control

Typ e R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 4--23. Fairness Control Register Description

BIT FIELD NAME TYPE DESCRIPTION

31--8 RSVD R Reserved. Bits 31--8 return 0s when read.

7--0 pri_req R/W This field specifies the maximum number of priority arbitration requests for asynchronous request

packets that the link is permitted to make of the PHY device during a fairness interval.

4--28

4.31 Link Control Register

The link control set/clear register provides the control flags that enable and configure the link core protocol portions of the TSB82AA2 device. It contains controls for the receiver and cycle timer. See Table 4--24 for a complete description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Link control

Typ e R R R R R R R R R RSC RSCU RSC R R R R

Default 0 0 0 0 0 0 0 0 0 X X X 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Link control

Typ e R R R R R RSC RSC R R RS R R R R R R

Default 0 0 0 0 0 X X 0 0 0 0 0 0 0 0 0

E4h clear register

Default: 00X0 0X00h

Table 4--24. Link Control Register Description

BIT FIELD NAME TYPE DESCRIPTION

31--23 RSVD R Reserved. Bits 31--23 return 0s when read.

22 cycleSource RSC When bit 22 is set to 1, the cycle timer uses an externalsource (CYCLEIN) to determine when to roll

21 cycleMaster RSCU When bit 21 is set to 1 and the PHY device has notified the TSB82AA2 device that PHY device is

20 CycleTimerEnable RSC When bit 20 is set to 1, the cycle timer offset counts cycles of the 24.576-MHz clock and rolls over

19--11 RSVD R Reserved. Bits 19--11 return 0s when read.

10 RcvPhyPkt RSC When bit 10 is set to 1, the receiver accepts incoming PHY packets into the AR request context if

9 RcvSelfID RSC When bit 9 is set to 1, the receiver accepts incoming self-ID packets. Before setting this bit to 1,

8--7 RSVD R Reserved. Bits 8--7 return 0s when read.

6 tag1SyncFilterLock RS When this bit is set to 1, bit 6 (tag1SyncFilter) in the isochronous receive c ontext match register (see

5--0 RSVD R Reserved. Bits 5--0 return 0s when read.

over the cycle timer. When this bit is cleared, the cycle timer rolls over when the timer reaches 3072 cycles of the 24.576-MHz clock (125 µs).

root, the TSB82AA2 device generates a cycle start packet every time the cycle timerrolls over, based on the setting of bit 22 (cycleSource). When bit 21 is cleared, the OHCI-Lynxt accepts received cycle start packets to maintain synchronization with the node which is sending them. Bit 21 is automatically cleared when bit 25 (cycleTooLong) in the interrupt event register at OHCI offset 80h/84h (see Section 4.21, Interrupt Event Register) is set to 1. Bit 21 cannot be set to 1 until bit 25 (cycleTooLong) is cleared.

at the appropriate time, based on the settings of the above bits. When this bit is cleared, the cycle timer offset does not count.

the AR request context is enabled. This bit does not control receipt of self-ID packets.

software must ensure that the self-ID buffer pointer register contains a valid address.

Section 4.46, Isochronous Receive Context Match Register) is set to 1 for all isochronous receive contexts. When this bit is cleared, bit 6 (tag1SyncFilter) in the isochronous receive context match register has Read/Write access. This bit is cleared when G_RST

is asserted.

4--29

4.32 Node Identification Register

The node identification register contains the address of the node on which the OHCI-Lynxt chip resides, and indicates the valid node number status. The 16-bit combination of the busNumber field (bits 15--6) and the NodeNumber field (bits 5--0) is referred to as the node ID. See Table 4--25 for a complete desc ription of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Node identification

Typ e RU RU R R RU R R R R R R R R R R R

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Node identification

Typ e RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RU RU RU RU RU RU

Default 1 1 1 1 1 1 1 1 1 1 X X X X X X

Table 4--25. Node Identification Register Description

BIT FIELD NAME TYPE DESCRIPTION

31 iDValid RU Bit 31 indicates whether or not the TSB82AA2 device has a valid node number. It is cleared when a

30 root RU Bit 30 is set to 1 during the bus reset process if the attached PHY device is root.

29--28 RSVD R Reserved. Bits 29--28 return 0s when read.

27 CPS RU Bit 27 is set to 1 if the PHY device is reporting that cable power status is OK.

26--16 RSVD R Reserved. Bits 26--16 return 0s when read.

15--6 BusNumber RWU This field identifies the specific 1394 bus the TSB82AA2 device belongs to when multiple

5--0 NodeNumber RU This field is the physical node number established by the PHY device during self-identification. It is

1394 bus reset is detected, and set to 1 when the TSB82AA2 device receives a new node number from its PHY device.

1394-compatible buses are connected via a bridge.

automatically set to the value received from the PHY device after the self-identification phase. If the PHY device sets the NodeNumber to 63, then software must not set bit 15 (run) in the asynchronous context control register (see Section 4.40, Asynchronous Context Control Register) for either of the AT DMA contexts.

4--30

4.33 PHY Layer Control Register

The PHY layer control register reads from or writes to a PHY register. See Table 4--26 for a complete description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name PHY layer control

Typ e RU R R R RU RU RU RU RU RU RU RU RU RU RU RU

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name PHY layer control

Typ e RWU RWU R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 4--26. PHY Control Register Description

BIT FIELD NAME TYPE DESCRIPTION

31 rdDone RU Bit 31 is cleared to 0 by the TSB82AA2 device when either bit 15 (rdReg) or bit 14 (wrReg) is set to

30--28 RSVD R Reserved. Bits 30--28 return 0s when read.

27--24 rdAddr RU This field is the address of the register most recently received from the PHY device.

23--16 rdData RU This field is the contents of a PHY register that has been read.

15 rdReg RWU Bit 15 is set to 1 by software to initiate a read request to a PHY register, and is cleared by hardware

14 wrReg RWU Bit 14 is set to 1 by software to initiate a write request to a PHY register, and is cleared by hardware

13--12 RSVD R Reserved. Bits 13--12 return 0s when read.

11- -8 regAddr R/W This field is the address of the PHY register to be written or read.

7--0 wrData R/W This field is the data to be written to a PHY register and is ignored for reads.

1. This bit is set to 1 when a register transfer is received from the PHY device.

when the request has been sent. Bits 14 (wrReg) and 15 (rdReg) must not both be set to 1 simultaneously.

4--31

4.34 Isochronous Cycle Timer Register

The isochronous cycle timer register indicates the current cycle number and offset. When the TSB82AA2 device is cycle master,this register is transmitted with the cycle start message. When the TSB82AA2 device is not cycle master, this register is loaded with the data field in an incoming cycle start. In the event that the cycle start message is not received, the fields can continue incrementing on their own (if programmed) to maintain a local time reference. See Table 4--27 for a complete description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Isochronous cycle timer

Typ e RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU

Default X X X X X X X X X X X X X X X X

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Isochronous cycle timer

Typ e RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU

Default X X X X X X X X X X X X X X X X

Table 4--27. Isochronous Cycle Timer Register Description

BIT FIELD NAME TYPE DESCRIPTION

31--25 cycleSeconds RWU This field counts seconds [rollovers from bits 24--12 (cycleCount field)] modulo 128.

24--12 cycleCount RWU This field counts cycles [rollovers from bits 11--0 (cycleOffset field)] modulo 8000.

11- -0 cycleOffset RWU This field counts 24.576-MHz clocks modulo 3072, that is, 125 µs. If an external 8-kHz clock

configuration is being used, then this field must be cleared to 0s at each tick of the external clock.

4--32

4.35 Asynchronous Request Filter High Register

The asynchronous request filter high set/clear register enables asynchronous receive requests on a per-node basis, and handles the upper node IDs. When a packet is destined for either the physical request context or the ARRQ context, the source node ID is examined. If the bit corresponding to the node ID is not set to 1 in this register, then the packet is not acknowledged and the request is not queued. The node ID comparison is done if the source node is on the same bus as the TSB82AA2 device. Nonlocal bus-sourced packets are not acknowledged unless bit 31 in this register is set to 1. See Table 4--28 for a complete description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Asynchronous request filter high

Typ e RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Asynchronous request filter high

Typ e RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

104h clear register

Default: 0000 0000h

Table 4--28. Asynchronous Request Filter High Register Description

BIT FIELD NAME TYPE DESCRIPTION

31 asynReqAllBuses RSC If bit 31 is set to 1, all asynchronous requests received by the TSB82AA2 device from nonlocal bus

30 asynReqResource62 RSC If bit 30 is set to 1 for local bus node number 62, asynchronous requests received by the TSB82AA2

29 asynReqResource61 RSC If bit 29 is set to 1 for local bus node number 61, asynchronous requests received by the TSB82AA2

28 asynReqResource60 RSC If bit 28 is set to 1 for local bus node number 60, asynchronous requests received by the TSB82AA2

27 asynReqResource59 RSC If bit 27 is set to 1 for local bus node number 59, asynchronous requests received by the TSB82AA2

26 asynReqResource58 RSC If bit 26 is set to 1 for local bus node number 58, asynchronous requests received by the TSB82AA2

25 asynReqResource57 RSC If bit 25 is set to 1 for local bus node number 57, asynchronous requests received by the TSB82AA2

24 asynReqResource56 RSC If bit 24 is set to 1 for local bus node number 56, asynchronous requests received by the TSB82AA2

23 asynReqResource55 RSC If bit 23 is set to 1 for local bus node number 55, asynchronous requests received by the TSB82AA2

22 asynReqResource54 RSC If bit 22 is set to 1 for local bus node number 54, asynchronous requests received by the TSB82AA2

21 asynReqResource53 RSC If bit 21 is set to 1 for local bus node number 53, asynchronous requests received by the TSB82AA2

20 asynReqResource52 RSC If bit 20 is set to 1 for local bus node number 52, asynchronous requests received by the TSB82AA2

19 asynReqResource51 RSC If bit 19 is set to 1 for local bus node number 51, asynchronous requests received by the TSB82AA2

nodes are accepted.

device from that node are accepted.

4--33

Table 4--28. Asynchronous Request Filter High Register Description (Continued)

BIT FIELD NAME TYPE DESCRIPTION

18 asynReqResource50 RSC If bit 18 is set to 1 for local bus node number 50, asynchronous requests received by the TSB82AA2

17 asynReqResource49 RSC If bit 17 is set to 1 for local bus node number 49, asynchronous requests received by the TSB82AA2

16 asynReqResource48 RSC If bit 16 is set to 1 for local bus node number 48, asynchronous requests received by the TSB82AA2

15 asynReqResource47 RSC If bit 15 is set to 1 for local bus node number 47, asynchronous requests received by the TSB82AA2

14 asynReqResource46 RSC If bit 14 is set to 1 for local bus node number 46, asynchronous requests received by the TSB82AA2

13 asynReqResource45 RSC If bit 13 is set to 1 for local bus node number 45, asynchronous requests received by the TSB82AA2

12 asynReqResource44 RSC If bit 12 is set to 1 for local bus node number 44, asynchronous requests received by the TSB82AA2

11 asynReqResource43 RSC If bit 11 is set to 1 for local bus node number 43, asynchronous requests rec eived by the TSB82AA2

10 asynReqResource42 RSC If bit 10 is set to 1 for local bus node number 42, asynchronous requests received by the TSB82AA2

9 asynReqResource41 RSC If bit 9 is set to 1 for local bus node number 41, asynchronous requests received by the TSB82AA2

8 asynReqResource40 RSC If bit 8 is set to 1 for local bus node number 40, asynchronous requests received by the TSB82AA2

7 asynReqResource39 RSC If bit 7 is set to 1 for local bus node number 39, asynchronous requests received by the TSB82AA2

6 asynReqResource38 RSC If bit 6 is set to 1 for local bus node number 38, asynchronous requests received by the TSB82AA2

5 asynReqResource37 RSC If bit 5 is set to 1 for local bus node number 37, asynchronous requests received by the TSB82AA2

4 asynReqResource36 RSC If bit 4 is set to 1 for local bus node number 36, asynchronous requests received by the TSB82AA2

3 asynReqResource35 RSC If bit 3 is set to 1 for local bus node number 35, asynchronous requests received by the TSB82AA2

2 asynReqResource34 RSC If bit 2 is set to 1 for local bus node number 34, asynchronous requests received by the TSB82AA2

1 asynReqResource33 RSC If bit 1 is set to 1 for local bus node number 33, asynchronous requests received by the TSB82AA2

0 asynReqResource32 RSC If bit 0 is set to 1 for local bus node number 32, asynchronous requests received by the TSB82AA2

device from that node are accepted.

4--34

4.36 Asynchronous Request Filter Low Register

The asynchronous request filter low set/clear register enables asynchronous receive requests on a per-node basis, and handles the lower node IDs. Other than filtering different node IDs, this register behaves identically to the asynchronous request filter high register. See Table 4--29 for a complete description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Asynchronous request filter low

Typ e RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Asynchronous request filter low

Typ e RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

10Ch clear register

Default: 0000 0000h

Table 4--29. Asynchronous Request Filter Low Register Description

BIT FIELD NAME TYPE DESCRIPTION

31 asynReqResource31 RSC If bit 31 is set to 1 for local bus node number 31, asynchronous requests received by the TSB82AA2

30 asynReqResource30 RSC If bit 30 is set to 1 for local bus node number 30, asynchronous requests received by the TSB82AA2

29--2 asynReqResourcen RSC Bits 29 through 2 (asynReqResourcen, where n = 29, 28, 27, …, 2) follow the same pattern as

1 asynReqResource1 RSC If bit 1 is set to 1 for local bus node number 1, asynchronous requests received by the TSB82AA2

0 asynReqResource0 RSC If bit 0 is set to 1 for local bus node number 0, asynchronous requests received by the TSB82AA2

device from that node are accepted.

bits 31 and 30.

device from that node are accepted.

4--35

4.37 Physical Request Filter High Register

The physical request filter high set/clear register enables physical receive requests on a per-node basis, and handles the upper node IDs. When a packet is destined for the physical request context, and the node ID has been compared against the ARRQ registers, then the comparison is done again with this register. If the bit corresponding to the node ID is not set to 1 in this register, then the request is handled by the ARRQ context instead of the phys ical request context. The node ID comparison is done if the source node is on the same bus as the TSB82AA2 device. Nonlocal bus sourced packets are not acknowledged unless bit 31 in this register is set to 1. See Table 4--30 for a complete description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Physical request filter high

Typ e RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Physical request filter high

Typ e RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

114h clear register

Default: 0000 0000h

Table 4--30. Physical Request Filter High Register Description

BIT FIELD NAME TYPE DESCRIPTION

31 physReqAllBusses RSC If bit 31 is set to 1, all physical requests received by the TSB82AA2 device from non-local bus

30 physReqResource62 RSC If bit 30 is set to 1 for local bus node number 62, physical requests received by the TSB82AA2

29 physReqResource61 RSC If bit 29 is set to 1 for local bus node number 61, physical requests received by the TSB82AA2

28 physReqResource60 RSC If bit 28 is set to 1 for local bus node number 60, physical requests received by the TSB82AA2

27 physReqResource59 RSC If bit 27 is set to 1 for local bus node number 59, physical requests received by the TSB82AA2

26 physReqResource58 RSC If bit 26 is set to 1 for local bus node number 58, physical requests received by the TSB82AA2

25 physReqResource57 RSC If bit 25 is set to 1 for local bus node number 57, physical requests received by the TSB82AA2

24 physReqResource56 RSC If bit 24 is set to 1 for local bus node number 56, physical requests received by the TSB82AA2

23 physReqResource55 RSC If bit 23 is set to 1 for local bus node number 55, physical requests received by the TSB82AA2

22 physReqResource54 RSC If bit 22 is set to 1 for local bus node number 54, physical requests received by the TSB82AA2

21 physReqResource53 RSC If bit 21 is set to 1 for local bus node number 53, physical requests received by the TSB82AA2

20 physReqResource52 RSC If bit 20 is set to 1 for local bus node number 52, physical requests received by the TSB82AA2

nodes are accepted. Bit 31 is not cleared by a PCI_RST

device from that node are handled through the physical request context.

4--36

Table 4--30. Physical Request Filter High Register Description (Continued)

BIT FIELD NAME TYPE DESCRIPTION

19 physReqResource51 RSC If bit 19 is set to 1 for local bus node number 51, physical requests received by the TSB82AA2

18 physReqResource50 RSC If bit 18 is set to 1 for local bus node number 50, physical requests received by the TSB82AA2

17 physReqResource49 RSC If bit 17 is set to 1 for local bus node number 49, physical requests received by the TSB82AA2

16 physReqResource48 RSC If bit 16 is set to 1 for local bus node number 48, physical requests received by the TSB82AA2

15 physReqResource47 RSC If bit 15 is set to 1 for local bus node number 47, physical requests received by the TSB82AA2

14 physReqResource46 RSC If bit 14 is set to 1 for local bus node number 46, physical requests received by the TSB82AA2

13 physReqResource45 RSC If bit 13 is set to 1 for local bus node number 45, physical requests received by the TSB82AA2

12 physReqResource44 RSC If bit 12 is set to 1 for local bus node number 44, physical requests received by the TSB82AA2

11 physReqResource43 RSC If bit 11 is set to 1 for local bus node number 43, physical requests received by the TSB82AA2

10 physReqResource42 RSC If bit 10 is set to 1 for local bus node number 42, physical requests received by the TSB82AA2

9 physReqResource41 RSC If bit 9 is set to 1 for local bus node number 41, physical requests received by the TSB82AA2

8 physReqResource40 RSC If bit 8 is set to 1 for local bus node number 40, physical requests received by the TSB82AA2

7 physReqResource39 RSC If bit 7 is set to 1 for local bus node number 39, physical requests received by the TSB82AA2

6 physReqResource38 RSC If bit 6 is set to 1 for local bus node number 38, physical requests received by the TSB82AA2

5 physReqResource37 RSC If bit 5 is set to 1 for local bus node number 37, physical requests received by the TSB82AA2

4 physReqResource36 RSC If bit 4 is set to 1 for local bus node number 36, physical requests received by the TSB82AA2

3 physReqResource35 RSC If bit 3 is set to 1 for local bus node number 35, physical requests received by the TSB82AA2

2 physReqResource34 RSC If bit 2 is set to 1 for local bus node number 34, physical requests received by the TSB82AA2

1 physReqResource33 RSC If bit 1 is set to 1 for local bus node number 33, physical requests received by the TSB82AA2

0 physReqResource32 RSC If bit 0 is set to 1 for local bus node number 32, physical requests received by the TSB82AA2

device from that node are handled through the physical request context.

4--37

4.38 Physical Request Filter Low Register

The physical request filter low set/clear register enables physical receive requests on a per-node basis, and handles the lower node IDs. When a packet is destined for the physical request context, and the node ID has been compared against the asynchronous request filter registers, then the node ID comparison is done again with this register. If the bit corresponding to the node ID is not s et to 1 in this register, then the request is handled by the asynchronous request context instead of the physical request context. See Table 4--31 for a complete description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Physical request filter low

Typ e RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Physical request filter low

Typ e RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

11Ch clear register

Default: 0000 0000h

Table 4--31. Physical Request Filter Low Register Description

BIT FIELD NAME TYPE DESCRIPTION

31 physReqResource31 RSC If bit 31 is set to 1 for local bus node number 31, physical requests received by the TSB82AA2

30 physReqResource30 RSC If bit 30 is set to 1 for local bus node number 30, physical requests received by the TSB82AA2

29--2 physReqResourcen RSC Bits 29 through 2 (physReqResourcen, where n = 29, 28, 27, …, 2) follow the same pattern as

1 physReqResource1 RSC If bit 1 is set to 1 for local bus node number 1, physical requests received by the TSB82AA2 device

0 physReqResource0 RSC If bit 0 is set to 1 for local bus node number 0, physical requests received by the TSB82AA2 device

device from that node are handled through the physical request context.

bits 31 and 30.

from that node are handled through the physical request context.

4.39 Physical Upper Bound Register (Optional Register)

The physical upper bound register is an optional register and is not implemented. This register returns all 0s when read.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Physical upper bound

Typ e R R R R R R R R R R R R R R R R

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Physical upper bound

Typ e R R R R R R R R R R R R R R R R

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

4--38

4.40 Asynchronous Context Control Register

The asynchronous context control set/clear register controls the state and indicates status of the DMA context. See Table 4--32 for a complete description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Asynchronous context control

Typ e R R R R R R R R R R R R R R R R

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Asynchronous context control

Typ e RSCU R R RSU RU RU RU R RU RU RU RU RU RU RU RU

Default 0 0 0 X 0 0 0 0 X X X X X X X X

Register: Asynchronous context control Type: Read/Set/Clear/Update, Read/Set/Update, Read/Update, Read-only Offset: 180h set register [ATRQ]

184h clear register [ATRQ] 1A0h set register [ATRS] 1A4h clear register [ATRS] 1C0h set register [ARRQ] 1C4h clear register [ARRQ] 1E0h set register [ARRS] 1E4h clear register [ARRS]

Default: 0000 X0XXh

Table 4--32. Asynchronous Context Control Register Description

BIT FIELD NAME TYPE DESCRIPTION

31--16 RSVD R Reserved. Bits 31--16 return 0s when read.

15 run RSCU Bit 15 is set to 1 by software to enable descriptor process ing for the context and cleared by software

14--13 RSVD R Reserved. Bits 14--13 return 0s when read.

12 wake RSU Software sets bit 12 to 1 to cause the TSB82AA2 device to continue or resume descriptor processing.

11 dead RU The TSB82AA2 device sets bit 11 when it encounters a fatal error, and clears the bit when software

10 active RU The TSB82AA2 device sets bit 10 to 1 when it is processing descriptors.

9 betaFrame RU Bit 9 is set to 1 when the PHY indicates that the received packet is sent in Beta format. A response

8 RSVD R Reserved. Bit 8 returns 0 when read.

7--5 spd RU This field indicates the speed at which a packet was received or transmitted and only contains

4--0 eventcode RU This field holds the acknowledge sent by the link core for this packet or holds an internally generated

to stop descriptor processing. The TSB82AA2 device changes this bit only on a system (hardware) or software reset.

The TSB82AA2 device clears this bit on every descriptor fetch.

clears bit 15 (run). Asynchronous contexts supporting out-of-order pipelining provide unique contextControl.dead functionality. See Section 7.7 in the 1394 Open Host Controller Interface Specification (Revision 1.1) for more information.

to a request sent using Beta format also uses Beta format.

meaningful information for receive contexts. This field is encoded as:

000 = 100M bits/sec 001 = 200M bits/sec 010 = 400M bits/sec 011 = 800M bits/sec

All other values are reserved.

error code if the packet was not transferred successfully.

4--39

4.41 Asynchronous Context Command Pointer Register

The asynchronous context command pointer register contains a pointer to the address of the first descriptor block that the TSB82AA2 device accesses when software enables the context by setting bit 15 (run) of the asynchronous context control register (see Section 4.40, Asynchronous Context Control Register) to 1. See Table 4--33 for a complete description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Asynchronous context command pointer

Typ e RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU

Default X X X X X X X X X X X X X X X X

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Asynchronous context command pointer

Typ e RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU

Default X X X X X X X X X X X X X X X X

1ACh [ATRS] 1CCh [ArRQ] 1ECh [ArRS]

Default: XXXX XXXXh

Table 4--33. Asynchronous Context Command Pointer Register Description

BIT FIELD NAME TYPE DESCRIPTION

31--4 descriptorAddress RWU Contains the upper 28 bits of the address of a 16-byte aligned descriptor block.

3--0 Z RWU Indicates the number of contiguous descriptors at the address pointed to by the descriptor address.

If Z is 0, then it indicates that the descriptorAddress field (bits 31--4) is not valid.

4--40

4.42 Isochronous Transmit Context Control Register

The isochronous transmit context control set/clear register controls options, state, and status for the is ochronous transmit DMA contexts. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3, …, 7). See Table 4--34 for a complete description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Isochronous transmit context control

Typ e RSCU RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC

Default X X X X X X X X X X X X X X X X

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Isochronous transmit context control

Typ e RSC R R RSU RU RU R R R R R RU RU RU RU RU

Default 0 0 0 X 0 0 0 0 X X X X X X X X

Register: Isochronous transmit context control Type: Read/Set/Clear/Update, Read/Set/Clear, Read/Update, Read-only Offset: 200h + (16 * n) set register

204h + (16 * n) clear register

Default: XXXX X0XXh

Table 4--34. Isochronous Transmit Context Control Register Description

BIT FIELD NAME TYPE DESCRIPTION

31 cycleMatchEnable RSCU When bit 31 is set to 1, processing occurs such that the packet described by the context firs t

30--16 cycleMatch RSC This field contains a 15-bit value, corresponding to the low-order two bits of the isochronous cycle

15 run RSC Bit 15 is set to 1 by software to enable descriptor processing for the context and cleared by software

14--13 RSVD R Reserved. Bits 14--13 return 0s when read.

12 wake RSU Software sets bit 12 to 1 to cause the TSB82AA2 device to continue or resume descriptor processing.

11 dead RU The TSB82AA2 device sets bit 11 to 1 when it encounters a fatal error, and clears the bit when

10 active RU The TSB82AA2 device sets bit 10 to 1 when it is processing descriptors.

9--5 RSVD R Reserved. Bits 9--5 return 0s when read.

4--0 event code RU Followingan OUTPUT_LAST* command, the error code is indicated in this field. Possible values are:

†

On an overflow for each running context, the isochronous transmit DMA supports up to 7 cycle skips, when the following are true:

1. Bit 11 (dead) in either the isochronous transmit or receive context control register is set to 1.

2. Bits 4--0 (eventcode field) in either the isochronous transmit or receive context control register is set to evt_timeout.

3. Bit 24 (unrecoverableError) in the interrupt event register at OHCI offset 80h/84h (see Section 4.21, Interrupt Event Register)issetto1.

descriptor block is transmitted in the cycle whose number is specified in the cycleMatch field (bits 30--16). The cycleMatch field (bits 30--16) must match the low-order two bits of cycleSeconds and the 13-bit cycleCount field in the cycle start packet that is sent or received immediately before isochronous transmission begins. Since the isochronous trans mit DMA controller may work ahead, the processing of the first descriptor block may begin slightly in advance of the actual cycle in which the first packet is transmitted.

The effects of this bit, however, are impacted by the values of other bits in this register and are explained in the 1394 Open Host Controller Interface Specification. Once the context has become active, hardware clears this bit.

timer register at OHCI offset F0h (see Section 4.34, Isochronous Cycle Timer Register) cycleSeconds field (bits 31--25) and the cycleCount field (bits 24--12). If bit 31 (cycleMatchEnable) is set to 1, then this isochronous transmit DMA context becomes enabled for transmits when the low-order two bits of the isochronous cycle timer register cycleSeconds field (bits 31--25) and the cycleCount field (bits 24--12) value equal this field (cycleMatch) value.

to stop descriptor processing. The TSB82AA2 device changes this bit only on a system (hardware) or software reset.

The TSB82AA2 device clears this bit on every descriptor fetch.

software clears bit 15 (run) to 0.

ack_complete, evt_descriptor_read, evt_data_read, and evt_unknown.

4--41

4.43 Isochronous Transmit Context Command Pointer Register

The isochronous transmit context command pointer register contains a pointer to the address of the first descriptor block that the TSB82AA2 device accesses when software enables an isochronous transmit context by setting bit 15 (run) in the isochronous transmit context control register (see Section 4.42, Isochronous Transmit Context Control Register) to 1. The isochronous transmit DMA context command pointer can be read when a context is active. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3, …, 7).

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Isochronous transmit context command pointer

Typ e R R R R R R R R R R R R R R R R

Default X X X X X X X X X X X X X X X X

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Isochronous transmit context command pointer

Typ e R R R R R R R R R R R R R R R R

Default X X X X X X X X X X X X X X X X

4.44 Isochronous Receive Context Control Register

The isochronous receive context control set/clear register controls options, state, and status for the isochronous receive DMA contexts. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3). See Table 4--35 for a complete description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Isochronous receive context control

Typ e RSC RSC RSCU RSC RSC R R R R R R R R R R R

Default X X X X X 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Isochronous receive context control

Typ e RSCU R R RSU RU RU RU R RU RU RU RU RU RU RU RU

Default 0 0 0 X 0 0 0 0 X X X X X X X X

Register: Isochronous receive context control Type: Read/Set/Clear/Update, Read/Set/Clear, Read/Update, Read-only Offset: 400h + (32 * n) set register

404h + (32 * n) clear register

Default: XX00 X0XXh

Table 4--35. Isochronous Receive Context Control Register Description

BIT FIELD NAME TYPE DESCRIPTION

31 bufferFill RSC When bit 31 is set to 1, received packets are placed back-to-back to completely fill each receive

30 isochHeader RSC When bit 30 is set to 1, received isochronous packets include the complete 4-byte isochronous

buffer. When this bit is cleared, each received packet is placed in a single buffer. If bit 28 (multiChanMode) is set to 1, then this bit must also be set to 1. The value of this bit must not be changed while bit 10 (active) or bit 15 (run) is set to 1.

packet header seen by the link layer. The end of the packet is marked with xferStatus in the first doublet, and a 16-bit timeStamp indicating the time of the most recently received (or sent) cycleStart packet.

When this bit is cleared, the packet header is stripped from received isochronous packets. The packet header, if received, immediately precedes the packet payload. The value of this bit must not be changed while bit 10 (active) or bit 15 (run) is set to 1.

4--42

Table 4--35. Isochronous Receive Context Control Register Description (Continued)

BIT FIELD NAME TYPE DESCRIPTION

29 cycleMatchEnable RSCU When bit 29 is set to 1 andthe 13-bit cycleMatch field(bits 24 --12) in theisochronous receive context

28 multiChanMode RSC When bit 28 is set to 1, the corresponding isochronous receive DMA context receives packets for

27 dualBufferMode RSC When bit 27 is set to 1, receive packets are separated into first and second payload and streamed

26--16 RSVD R Reserved. Bits 27--16 return 0s when read.

15 run RSCU Bit 15 is set to 1 by software to enable descriptor processing for the context and cleared by software

14--13 RSVD R Reserved. Bits 14 and 13 return 0s when read.

12 wake RSU Software sets bit 12 to 1 to cause the TSB82AA2 device to continue or resume descriptor

11 dead RU The TSB82AA2 device sets bit 11 to 1 when it encounters a fatal error, and clears the bit when

10 active RU The TSB82AA2 device sets bit 10 to 1 when it is processing desc riptors.

9 betaFrame RU Bit 9 is set to 1 when the PHY indicates that the received packet is sent in Beta format. A response

8 RSVD R Reserved. Bit 8 returns 0 when read.

7--5 spd RU This field indicates the speed at which the packet was received.

4--0 event code RU For bufferFill mode, possible values are: ack_complete, evt_descriptor_read, evt_data_write, and

match register (see Section 4.46, Isochronous Receive Context Match Register) matches the 13-bit cycleCountfield in the cycleStartpacket, the context begins running. The effects of this bit, however, are impacted by the values of other bits in this register. Once the context has become active, hardware clears this bit. The value of this bit must not be changed while bit 10 (active) or bit 15 (run) is set to 1.

all isochronous channels enabled in the isochronous receive channel mask high register at OHCI offset 70h/74h (see Section 4.19, Isochronous Receive Channel Mask High) and isochronous receive channel mask low register at OHCI offset 78h/7Ch (see Section 4.20, Isochronous Receive Channel Mask Low). The isochronous channel number specified in the isochronous receive context match register (see Section 4.46, Isochronous Receive Context Match Register) is ignored.

When this bit is cleared, the isochronous receive DMA context receives packets for the single channel specified in the isochronous receive context match register (see Section 4.46, Isochronous Receive Context Match Register). Only one isochronous receive DMA context may use the isochronous receive channel mask registers (see Sections 4.19, Isochronous Receive Channel Mask High Register,and 4.20, Isochronous Receive Channel Mask Low Register). If more than one isochronous receive context control register has this bit set, then the results are undefined. The value of this bit must not be changed while bit 10 (active) or bit 15 (run) is set to 1.

independently to the firstBuffer series and secondBuffer series as described in Section 10.2.3 in the 1394 Open Host Controller Interface Specification. Also, when bit 27 is set to 1, both bits 28 (multiChanMode) and 31 (bufferFill) are cleared to 0. The value of this bit does not change when either bit 10 (active) or bit 15 (run) is set to 1.

to stop descriptor processing. The TSB82AA2 device changes this bit only on a system (hardware) or software reset.

processing. The TSB82AA2 device clears this bit on every descriptor fetch.

software clears bit 15 (run).

to a request sent using Beta format also uses Beta format.

000 = 100M bits/s 001 = 200M bits/s 010 = 400M bits/s 011 = 800M bits/s

All other values are reserved.

evt_unknown. Packets with data errors (either dataLength mismatches or dataCRC errors) and packets for which a FIFO overrun occurred are backed out. For packet-per-buffer mode, possible values are: ack_complete, ack_data_error, evt_long_packet, evt_overrun, evt_descriptor_read, evt_data_write, and evt_unknown.

†

On an overflow for each running context, the isochronous transmit DMA supports up to 7 cycle skips, when the following are true:

1. Bit 11 (dead) in either the isochronous transmit or receive context control register is set to 1.

2. Bits 4--0 (eventcode field) in either the isochronous transmit or receive context control register is set to evt_timeout.

3. Bit 24 (unrecoverableError) in the interrupt event register at OHCI offset 80h/84h (see Section 4.21, Interrupt Event Register)issetto1.

4--43

4.45 Isochronous Receive Context Command Pointer Register

The isochronous receive context command pointer register contains a pointer to the address of the first descriptor block that the TSB82AA2 device accesses when software enables an isochronous receive context by setting bit 15 (run) in the isochronous receive context control register (see Section 4.44, Isochronous Receive Context Control Register) to 1. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3).

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Isochronous receive context command pointer

Typ e R R R R R R R R R R R R R R R R

Default X X X X X X X X X X X X X X X X

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Isochronous receive context command pointer

Typ e R R R R R R R R R R R R R R R R

Default X X X X X X X X X X X X X X X X

4--44

4.46 Isochronous Receive Context Match Register

The isochronous receive context match register starts an isochronous receive context running on a specified cycle number, filters incoming isochronous packets based on tag values, and waits for packets with a specified sync value. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3). See Table 4--36 for a complete description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Isochronous receive context match

Typ e R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Default X X X X 0 0 0 X X X X X X X X X

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Isochronous receive context match

Typ e R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W

Default X X X X X X X X 0 X X X X X X X

Table 4--36. Isochronous Receive Context Match Register Description

BIT FIELD NAME TYPE DESCRIPTION

31 tag3 R/W If bit 31 is set to 1, this context matches on isochronous receive packets with a tag field of 11b.

30 tag2 R/W If bit 30 is set to 1, this context matches on isochronous receive packets with a tag field of 10b.

29 tag1 R/W If bit 29 is set to 1, this context matches on isochronous receive packets with a tag field of 01b.

28 tag0 R/W If bit 28 is set to 1, this context matches on isochronous receive packets with a tag field of 00b.

27 RSVD R Reserved. Bit 27 returns 0 when read.

26--12 cycleMatch R/W Contains a 15-bit value, corresponding to the low-order two bits of cycleSeconds and the 13-bit

11- -8 sync R/W This 4-bit field is compared to the sync field of each isochronous packet for this channel when the

7 RSVD R Reserved. Bit 7 returns 0 when read.

6 tag1SyncFilter R/W If bit 6 and bit 29 (tag1) are set to 1, then packets with tag 01b are accepted into the context if the two

5--0 channelNumber R/W This 6-bit field indicates the isochronous channel number for which this isochronous receive DMA

cycleCount field in the cycleStart packet. If bit 29 (cycleMatchEnable) in the isochronous receive context control register (see Section 4.44, Isochronous Receive Context Control Register) is set to 1, then this context is enabled for receives when the two low-order bits of the bus isochronous cycle timer register at OHCI offset F0h (see Section 4.34, Isochronous Cycle Timer Register) cycleSeconds field (bits 31--25) and cycleCount field (bits 24--12) value equal this field (cycleMatch) value.

command descriptor w field is set to 11b.

most significant bits of the pac ket s ync field are 00b. Packets with tag values other than 01b are filtered according to bit 28 (tag0), bit 30 (tag2), and bit 31 (tag3) without any additional restrictions.

If this bit is cleared, then this context matches on isochronous receive packets as specified in bits 28--31 (tag0--tag3) with no additional restrictions.

context accepts packets.

4--45

5 TI Extension Registers

The TI extension base address register provides a method of accessing memory-mapped TI extension registers. The TI extension base address register is programmed with a base address referencing the memory-mapped TI extension registers. See Section 3.10, TI Extension Base Address Register, for register bit field details. See Table 5--1 for the TI extension register listing.

Table 5--1. TI Extension Register Map

Reserved 00h--A7Fh

Isochronous Receive DV Enhancment Set A80h

Isochronous Receive DV Enhancment Clear A84h

Link Enhancement Control Set A88h

Link Enhancement Control Clear A8Ch

Isochronous Transmit Context 0 Timestamp Offset A90h

Isochronous Transmit Context 1 Timestamp Offset A94h

Isochronous Transmit Context 2 Timestamp Offset A98h

Isochronous Transmit Context 3 Timestamp Offset A9Ch

Isochronous Transmit Context 4 Timestamp Offset AA0h

Isochronous Transmit Context 5 Timestamp Offset AA4h

Isochronous Transmit Context 6 Timestamp Offset AA8h

Isochronous Transmit Context 7 Timestamp Offset AA8h

5.1 DV Timestamp Enhancements

The DV timestamp enhancements are enabled by bit 8 (enab_dv_ts) in the link enhancement control register located at PCI offset F4h and are aliased in TI extension register space at offset A88 (set) and A8Ch (clear).

The DV and MPEG transmit enhancements are enabled separately by bits in the link enhancement control register located in PCI configuration space at PCI offset F4h. The link enhancement control register is also aliased as a set/clear register in TI extension space at offset A88h (set) and A8Ch (clear).

Bit 8 (enab_dv_ts) of the link enhancement control register enables DV timestamp support. When enabled, the link calculates a timestamp based on the cycle timer and the timestamp offset register and substitutes it in the SYT field of the CIP once per DV frame.

Bit 10 (enab_mpeg_ts) of the link enhancement control register enables MPEG timestamp support. Two MPEG time stamp modes are supported. The default mode calculates an initial delta that is added to the calculated timestamp in addition to a user-defined offset. The initial offset is calculated as the difference in the intended transmit cycle count and the cycle count field of the timestamp in the first TSP of the MPEG2 stream. The use of the initial delta can be controlled by bit 31 (DisableInitialOffset) in the timestamp offset register (see Section 5.6, Timestamp Offset Register).

5.2 MPEG2 Timestamp Procedure

The MPEG2 timestamp enhancements are enabled by bit 10 (enab_mpeg_ts) in the link enhancement control register located at PCI offset F4h and aliased in TI extension register space at offset A88h (set) and A8Ch (clear).

When bit 10 (enab_mpeg_ts) is set to 1, the hardware applies the timestamp enhancements to isochronous transmit packets that have the tag field equal to 01b in the isochronous packet header and a FMT field equal to 10h.

5--1

5.3 Isochronous Receive Digital Video Enhancements

The DV frame sync and branch enhancement provides a mechanism in buffer-fill mode to synchronize 1394 DV data which is received in the correct order to DV frame-sized data buffers described by several INPUT_MORE descriptors (see 1394 Open Host Controller Interface Specification, Revision 1.1). This is accomplished by waiting for the start-of-frame packet in a DV stream before transferring the received isochronous stream into the memory buffer described by the INPUT_MORE descriptors. This can improve the DV capture application performance by reducing the amount of processing overhead required to strip the CIP header and copy the received packets into frame-sized buffers.

The start of a DV frame is represented in the 1394 packet as a 16-bit pattern of 1FX7h (first byte 1Fh and second byte X7h) received as the first two bytes of the third quadlet in a DV isochronous packet. The TSB12LV23 OHCI-Lynxt used a field match of 1F07h to sync the frame. However, this did not accommodate all camcorder cases. To accommodate these models, the TSB82AA2 uses the pattern 1FX7h.

5.4 Isochronous Receive Digital Video Enhancements Register

The isochronous receive digital video enhancements register enables the DV enhancements in the TSB82AA2 device. The bits in this register may only be modified when both the active (bit 10) and run (bit 15) bits of the corresponding context control register are 0. See Table 5--2 for a complete description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Isochronous receive digital video enhancements

Typ e R R R R R R R R R R R R R R R R

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Isochronous receive digital video enhancements

Typ e R R RSC RSC R R RSC RSC R R RSC RSC R R RSC RSC

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

A84h clear register Type: Read/Set/Clear, Read-only Default: 0000 0000h

Table 5--2. Isochronous Receive Digital Video Enhancements Register Description

BIT FIELD NAME TYPE DESCRIPTION

31--14 RSVD R Reserved. Bits 31--14 return 0s when read.

13 DV_Branch3 RSC When bit 13 is set to 1, the isochronous receive context 3 synchronizes reception to the DV frame start

12 CIP_Strip3 RSC When bit 12 is set to 1, the isochronous receive context 3 strips the first two quadlets of payload. This

11- -10 RSVD R Reserved. Bits 11 and 10 return 0s when read.

9 DV_Branch2 RSC When bit 9 is set to 1, the isochronous receive context 2 synchronizes reception to the DV frame start

8 CIP_Strip2 RSC When bit 8 is set to 1, the isochronous receive context 2 strips the first two quadlets of payload. This

tag in bufferfill mode if input_more.b = 01b, and jumps to the descriptor pointed to by frameBranch if a DV frame start tag is received out of place. This bit is only interpreted when bit 12 (CIP_Strip3) is 1 and bit 30 (isochHeader) in the isochronous receive context control register at OHCI offset 460h/464h (see Section 4.44, Isochronous Receive Context Control Register)is0.

bit is only interpreted when bit 30 (isoc hHeader) in the isochronous receive context control register at OHCI offset 460h/464h (see Section 4.44, Isochronous Receive Context Control Register)is0.

tag in bufferfill mode if input_more.b = 01b, and jumps to the descriptor pointed to by frameBranch if a DV frame start tag is received out of place. This bit is only interpreted when bit 8 (CIP_Strip2) is 1 and bit 30 (isochHeader) in the isochronous receive context control register at OHCI offset 440h/444h (see Section 4.44, Isochronous Receive Context Control Register)is0.

bit is only interpreted when bit 30 (isoc hHeader) in the isochronous receive context control register at OHCI offset 440h/444h (see Section 4.44, Isochronous Receive Context Control Register)is0.

5--2

Table 5--2. Isochronous Receive Digital Video Enhancements Register Description (Continued)

BIT FIELD NAME TYPE DESCRIPTION

7--6 RSVD R Reserved. Bits 7 and 6 return 0s when read.

5 DV_Branch1 RSC When bit 5 is set to 1, the isochronous receive context 1 synchronizes reception to the DV frame start

4 CIP_Strip1 RSC When bit 4 is set to 1, the isochronous receive context 1 strips the first two quadlets of payload. This

3--2 RSVD R Reserved. Bits 3 and 2 return 0s when read.

1 DV_Branch0 RSC When bit 1 is set to 1, the isochronous receive context 0 synchronizes reception to the DV frame start

0 CIP_Strip0 RSC When bit 0 is set to 1, the isochronous receive context 0 strips the first two quadlets of payload. This

tag in bufferfill mode if input_more.b = 01b, and jumps to the descriptor pointed to by frameBranch if a DV frame start tag is received out of place. This bit is only interpreted when bit 4 (CIP_Strip1) is 1 and bit 30 (isochHeader) in the isochronous receive context control register at OHCI offset 420h/424h (see Section 4.44, Isochronous Receive Context Control Register)is0.

bit is only interpreted when bit 30 (isoc hHeader) in the isochronous receive context control register at OHCI offset 420h/424h (see Section 4.44, Isochronous Receive Context Control Register)is0.

tag in bufferfill mode if input_more.b = 01b and jumps to the descriptor pointed to by frameBranch if a DV frame start tag is received out of place. This bit is only interpreted when bit 0 (CIP_Strip0) is 1 and bit 30 (isochHeader) in the isochronous receive context control register at OHCI offset 400h/404h (see Section 4.44, Isochronous Receive Context Control Register)is0.

bit is only interpreted when bit 30 (isochHeader) in the isochronous receive context control register at OHCI offset 400h/404h (see Section 4.44, Isochronous Receive Context Control Register)is0.

5--3

5.5 Link Enhancement Register

This register is a memory-mapped set/clear register that is an alias of the link enhancement control register at PCI offset F4h. These bits may be initialized by software. Some of the bits may also be initialized by a serial EEPROM, if one is present, as noted in the bit descriptions below. If the bits are to be initialized by software, then the bits must be initialized prior to setting bit 19 (LPS) in the host controller control register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control Register). See Table 5--3 for a complete description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Link enhancement

Typ e R R R R R R R R R R R R R R R R

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Link enhancement

Typ e RSC R RSC RSC R R R/W RSC RSC R R R R RSC RSC R

Default 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0

A8Ch clear register Type: Read/Set/Clear, Read/Write, Read-only Default: 0000 0000h

Table 5--3. Link Enhancement Register Description

BIT FIELD NAME TYPE DESCRIPTION

31--16 RSVD R Reserved. Bits 31--16 return 0s when read.

15 dis_at_pipeline RSC Disable AT pipelining. When bit 15 is set to 1, out-of-order AT pipelining is disabled.

14 RSVD R Reserved.

13--12 atx_thresh RSC This field sets the initial AT threshold value, which is used until the AT FIFO is underrun. When the

11 RSVD R Reserved. Bit 11 returns 0 when read.

10 RSVD R Reserved. Bit 10 returns 0 when read.

9 enab_aud_ts R/W Enable audio/music CIP timestamp enhancement. When bit 9 is set to 1, the enhancement is enabled

8 enab_dv_ts RSC Enable DV CIP timestamp enhancement. When bit 8 is set to 1, the enhancement is enabled for DV

TSB82AA2 device retries the packet, it uses a 2-Kbyte threshold, resulting in a store-and-forward operation.

00 = Threshold ~ 4K bytes resulting in a store-and-forward operation (default) 01 = Threshold ~ 1.7K bytes 10 = Threshold ~ 1K bytes 11 = Threshold ~ 512 bytes

These bits fine-tune the asynchronous transmit threshold. For most applications the 1.7-K threshold is optimal. Changing this value may increase or decrease the 1394 latency depending on the average PCI bus latency.

Setting the ATthreshold to 1.7K, 1K, or 512 bytes results in data being transmitted at these thresholds or when an entire packet has been checked into the FIFO. If the packet to be transmitted is larger than the AT threshold, then the remaining data must be received before the AT FIFO is emptied; otherwise, an underrun condition occurs, resulting in a packet error at the receiving node. As a result, the link then commences store-and-forward operation—that is , wait until it has the complete packet in the FIFO before retransmitting it on the second attempt, to ensure delivery.

Note that this device always uses store-and-forward when the asynchronous transmit retries register at OHCI offset 08h (see Section 4.3, Asynchronous Transmit Retries Register) is cleared.

for audio/music CIP transmit streams (FMT = 10h).

CIP transmit streams (FMT = 00h).

5--4

Table 5--3. Link Enhancement Register Description (Continued)

7 enab_unfair RSC Enable asynchronous priority requests. OHCI-Lynx compatible. Setting bit 7 to 1 enables the link

6 RSVD R This bit is not assigned in the TSB82AA2 follow-on products, since this bit location loaded by the

5--3 RSVD R Reserved. Bits 5--3 return 0s when read.

2 enab_insert_idle RSC Enable insert idle. OHCI-Lynx compatible. When the PHY layer has control of the

1 enab_accel RSC Enable acceleration enhancements. OHCI-Lynx compatible. When bit 1 is set to 1, the PHY layer

0 RSVD R Reserved. Bit 0 returns 0 when read.

to respond to requests with priority arbitration. It is recommended that this bit be set to 1.

serial EEPROM from the enhancements field corresponds to bit 23 (programPhyEnable) in the host controller control register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control Register).

PHY_CTL0--PHY_CTL1 internal control lines and PHY_DATA0--PHY_DATA7internal data lines and the link requests control, the PHY layer drives 11b on the PHY_CTL0--PHY_CTL1 internal lines. The link can then start driving these lines immediately. Setting bit 2 to 1 inserts an idle state, so the link waits one clock cycle before it starts driving the lines (turnaround time).

is notified that the link supports the IEEE Std 1394a-2000 acceleration enhancements, that is, ack-accelerated, fly-by concatenation, etc. It is recommended that this bit be set to 1.

5--5

5.6 Timestamp Offset Register

The value of this register is added as an offset to the cycle timer value when using the MPEG, DV, and CIP enhancements. A timestamp offset register is implemented per isochronous transmit context. The n value following the offset indicates the context number (n = 0, 1, 2, 3, …, 7). These registers are programmed by software as appropriate. See Table 5--4 for a complete description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Timestamp offset

Typ e R/W R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Timestamp offset

Typ e R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 5--4. Timestamp Offset Register Description

BIT FIELD NAME TYPE DESCRIPTION

31 DisableInitialOffset R/W Bit 31 disables the use of the initial times tamp offset when the MPEG2 enhancements are enabled.

30--25 RSVD R Reserved. Bits 30--25 return 0s when read.

24--12 CycleCount R/W This field adds an offset to the cycle count field in the timestamp when the DV or MPEG2

11- -0 CycleOffset R/W This field adds an offset to the cycle offset field in the timestamp when the DV or MPEG2

A value of 0 indicates the use of the initial offset, a value of 1 indicates that the initial offset must not be applied to the calculated timestamp. This bit has no meaning for the DV timestamp enhancements.

enhancements are enabled. The cycle count field is incremented modulo 8000; therefore, values in this field must be limited between 0 and 7999.

enhancements are enabled. The cycle offset field is incremented modulo 3072; therefore, values in this field must be limited between 0 and 3071.

5--6

6 GPIO Interface

The general-purpose input/output (GPIO) interface consists of one GPIO port available via the MFUNC terminal by configuring the multifunction configuration register (PCI offset E8h). GPIO powers up as a general-purpose input and is programmable via the GPIO control register. Figure 6--1 shows the logic diagram for GPIO implementation.

GPIO Read Data

GPIO Port

GPIO Write Data

GPIO_Invert

GPIO Enable

Figure 6 --1. GPIO Logic Diagram

6--1

7 Serial EEPROM Interface

The TSB82AA2 device provides a serial bus interface to initialize the 1394 global unique ID register and a few PCI configuration registers through a serial EEPROM. The TSB82AA2 device communicates with the serial EEPROM via the 2-wire serial interface.

After power up the serial interface initializes the locations listed in Table 7--1. While the TSB82AA2 device ac cesses the serial EEPROM, all incoming PCI slave accesses are terminated with retry status. Table 7--1 shows the serial EEPROM memory map required for initializing the TSB82AA2 registers.

NOTE: If a ROM is implemented in the design, it must be programmed. An unprogrammed ROM defaults to all 1s, which could adversely impact device operation.

7--1

Table 7--1. Serial EEPROM Map

BYTE

ADDRESS

00 PCI maximum latency (PCI offset 3Eh) PCI minimum grant (PCI offset 3Fh)

01 PCI subsystem vendor ID alias (lsbyte) (PCI offset F8h)

02 PCI subsystem vendor ID alias (msbyte) (PCI offset F9h)

03 PCI subsystem ID alias (lsbyte) (PCI offset FAh)

04 PCI subsystem ID alias (msbyte) (PCI offset FBh)

[7]

Link_enhancement

Control.enab_unfair

(PCI offset F4h,

bit 7)

[6]

HCControl.

ProgramPhy

Enable

(OHCI offset

50h, bit 23)

[7--6]

RSVD

MiniRom enable

(OHCI offset 04h,

07 1394 GUID high (lsbyte 0) (OHCI offset 24h)

08 1394 GUID high (byte 1) (OHCI offset 25h)

09 1394 GUID high (byte 2) (OHCI offset 26h)

0A 1394 GUID high (msbyte 3) (OHCI offset 27h)

0B 1394 GUID low (lsbyte 0) (OHCI offset 28h)

0C 1394 GUID low (byte 1) (OHCI offset 29h)

0D 1394 GUID low (byte 2) (OHCI offset 30h)

0E 1394 GUID low (msbyte 3) (OHCI offset 31h)

0F Checksum

[15]

Link

Enhancement.dis_

at_pipeline (PCI

offset F4h, bit 15)

[7]

RSVD

[14] Enab_draft (PCI offset

F4h, bit 14)

[6]

MiscConfig.

cardbus

(PCI offset

Enhancement.atx_

thresh (PCI offset

F4h, bits 13--12)

[5]

RSVD

F0h, bit 6)

[15]

MiscConfig.PME_D

3cold (PCI offset

[14--11]

RSVD

F0h, bit 15)

BusOptions.Max_Rec (OHCI offset 20h, bits 15--12)

CIS offset (PCI offset 28h, bits 7-- 3)

[7--4]

[7--3]

15--16

[7--3]

RSVD

18--1F RSVD

BYTE DESCRIPTION

[5--3]

RSVD

†

[5]

bit 5)

[13--12]

Link

[4] MiscConfi g.dis_tgt_

abt (PCI

offset

F0h, bit 4

[3]

RSVD

[7--0]

RSVD

[2]

Link_enhancement

Control.enab_

insert_idle (PCI

offset F4h, bit 2)

Link_enhancement

Control.enab_accel

(PCI offset F4h,

bit 1)

[4--0]

RSVD

[11--8] RSVD

[2]

MiscConfig.disable

_sclkgate (PCI

offset F0h, bit 2)

MiscConfig.disable

_pcigate (PCI offset

F0h, bit 1)

[10]

ignore_IntEvent.

MR_Enhance (PCI offset F0h,

MasterIntEnable_

for_pme (PCI offset

F0h, bit 10)

[3--0]

RSVD

[2--0]

RSVD

[2--0]

MultifunctionSelect.MFunc_Sel (PCI offset E8h,

bits 2--0)

[1]

[0]

RSVD

[0]

MiscConfi

g.keep_pcl

k(PCI

offset F0h,

bit 0)

[9--8]

bits 9--8)

†

If bit 5 at EEPROM byte offset 06h is set, then the MiniRom is enabled and the starting address is 20h.

7--2

8 Electrical Characteristics

8.1 Absolute Maximum Ratings Over Operating Temperature Ranges

Supply voltage range, V Supply voltage range, V Input voltage range for PCI, V Input voltage range for PHY interface, V Output voltage range for PCI, V Output voltage range for PHY interface, V Input clamp current, I Output clamp current, I

CCP

<0orVI>VCC)(seeNote1) ±20 mA.....................................

IK(VI

OK(VO

<0orVO>VCC)(seeNote2) ±20 mA.................................

†

--0.5toV

--0.5toVCC+0.5V........................................

--0.5toVCC+0.5V...............................................

--0.5toVCC+0.5V......................................

--0.5 V to 3.6 V.........................................................

--0.5 V to 5.5 V.......................................................

+0.5V................................................

CCP

Storage temperature range --65°Cto150°C.......................................................

†

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. Applies to external input and bidirectional buffers. V

2. Applies to external output and bidirectional buffers. V

I>VCCP

O>VCCP

8--1

8.2 Recommended Operating Conditions

gpg

OPERATION MIN NOM MAX UNIT

CCP

†

O‡

J§

†

Applies to external inputs and bidirectional buffers without hysteresis.

‡

Applies to external output buffers.

The junction temperatures reflect simulation conditions. Customer is responsible for verifying junction temperature.

Core voltage Commercial 3.3 V 3 3.3 3.6 V

3.3 V 3 3.3 3.6

PCI I/O clamping voltage Commercial

High-level input voltage

PCI

5V 4.5 5 5.5

3.3 V 0.475V

CCP

5V 2 V

PHY interface 2 3.6

3.3 V 0 0.325V

Low-level input voltage

PCI

5V 0 0.8

PHY interface 0 0.8

PCI 3.3 V 0 V

Input voltage

PHY interface

0 3.6

PCI 3.3 V 0 V

Output voltage

PHY interface

0 3.6

Input transition time (trand tf) PCI 0 6 ns

Operating ambient temperature -- 4 0 25 85 °C

Virtual junction temperature 0 25 11 5 °C

CCP

8--2

8.3 Electrical Characteristics Over Recommended Operating Conditions (unless

VPHY

otherwise noted)

OPERATION

PCI

High-level output voltage

interface

PCI

†

Low-level output voltage

PCI_PME

PHY interface IOL=8mA 0.5

†

3-state output high-impedance Output terminals 3.6 V VO=VCCor GND ±20 µA

Low-level input current

High-level input current

Input terminals 3.6 V VI=GND

I/O terminals

†

PCI

Others

†

3.6 V VI=GND

3.6 V VI=V

†

3.6 V VI=V

For I/O terminals, input leakage (IILand IIH) includes IOZof the disabled output.

8.4 Switching Characteristics for PCI Interface

PARAMETER MIN TYP MAX UNIT

Setup time before PCLK 7 ns

Hold time after PCLK 0 ns

Delay time, PCLK to data valid 2 11 ns

val

‡

These parameters are ensured by design.

TEST

CONDITIONS

IOH= -- 0.5 mA 0.9V

MIN MAX UNIT

IOH=--2mA 2.4

IOH=--4mA 2.8

IOH=--8mA VCC-- 0 . 6

IOL= 1.5 mA 0.1V

IOL=6mA 0.55

IOL=4mA 0.5

‡

±20

‡

8.5 Switching Characteristics for PHY-Link Interface

PARAMETER MIN TYP MAX UNIT

Setup time, Dn, CTLn, LREQ to PHY_CLK 6 ns

Hold time, Dn, CTLn, LREQ after PHY_CLK 0 ns

Delay time, PHY_CLK to Dn, CTLn 1 10 ns

‡

These parameters are ensured by design.

‡

8--3

9 Mechanical Information

The TSB82AA2 is packaged in a 144-terminal PGE package. The following shows the mechanical dimensions for the PGE package.

PGE (S-PQFP-G144) PLASTIC QUAD FLATPACK

109

144

1,45 1,35

108

0,27

0,17

0,50

17,50 TYP

20,20

19,80

22,20

21,80

0,05 MIN

0,08

0,25

0,75 0,45

0,13 NOM

Gage Plane

0°-- 7 °

1,60 MAX

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026

Seating Plane

0,08

4040147/C 10/96

9--1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status

TSB82AA2IPGEEP ACTIVE LQFP PGE 144 60 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TSB82AA2IEP

V62/04611-01XE ACTIVE LQFP PGE 144 60 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TSB82AA2IEP

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

Package Type Package

(1)

Drawing

Pins Package

Qty

Eco Plan

(2)

Lead finish/ Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

(2)

RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Samples

Addendum-Page 1

Texas Instruments TSB82AA2 (FireWire 800 PCI ctrl.) TSB82AA2 1394b OHCI-Lynx Controller Data Manual

Specifications and Main Features

Frequently Asked Questions

User Manual