TEXAS INSTRUMENTS TSB82AA2B Technical data

www.ti.com

SLLS828A – MARCH 2007 – REVISED MARCH 2007

1394b OHCI-Lynx™ CONTROLLER

FEATURES

• Single 3.3-V Supply (1.8-V Internal Core • D0, D1, D2, and D3 Power States and PME

Voltage With Regulator) Events Per the PCI Bus Power Management

• 3.3-V and 5-V PCI Signaling Environments

• Serial Bus Data Rates of 100M Bits/s, 200M

Bits/s, 400M Bits/s, and 800M Bits/s

• Physical Write Posting of up to Three
Outstanding Transactions • Out-of-Order Pipelining for Asynchronous

• Serial ROM or Boot ROM Interface Supports
2-Wire Serial EEPROM Devices • Register Access Fail Interrupt When the PHY

• 33-MHz/64-Bit and 33-MHz/32-Bit Selectable
PCI Interface • Initial Bandwidth Available and Initial

• Multifunction Terminal (MFUNC Terminal 1):
– PCI_CLKRUN Protocol Per the PCI Mobile

Design Guide

– General-Purpose I/O
– CYCLEIN/CYCLEOUT for External Cycle

Timer Control for Customized
Synchronization

• PCI Burst Transfers and Deep FIFOs to
Tolerate Large Host Latency:

– Transmit FIFO—5K Asynchronous
– Transmit FIFO—2K Isochronous
– Receive FIFO—2K Asynchronous
– Receive FIFO—2K Isochronous

Interface Specification

• Programmable Asynchronous Transmit

Threshold

• Isochronous Receive Dual-Buffer Mode

Transmit Requests

SYSCLK Is Not Active

Channels Available Registers

• Digital Video and Audio Performance

Enhancements

• Fabricated in Advanced Low-Power CMOS

Process

• Packaged in 144-Terminal LQFP (PGE)

TSB82AA2B

DESCRIPTION

The TSB82AA2B OHCI-Lynx™ Controller is a discrete 1394b link-layer device, which has been designed to
meet the demanding requirements of today’s 1394 bus designs. The TSB82AA2B device is capable of
exceptional 800M bits/s performance; thus, providing the throughput and bandwidth to move data efficiently and
quickly between the PCI and 1394 buses. The TSB82AA2B device also provides outstanding ultra-low power
operation and intelligent power management capabilities. The device provides the IEEE 1394 link function and is
compatible with 100M bits/s, 200M bits/s, 400M bits/s, and 800M bits/s serial bus data rates.

The TSB82AA2B improved throughput and increased bandwidth make it ideal for today’s high-end PCs and
open the door for the development of S800 RAID- and SAN-based peripherals.

The TSB82AA2B OHCI-Lynx Controller operates as the interface between a 33-MHz/64-bit or 33-MHz/32-bit PCI
local bus and a compatible 1394b PHY-layer device (such as the TSB81BA3 device) that is capable of
supporting serial data rates at 98.304M, 196.608M, 393.216M, or 786.432M bits/s (referred to as S100, S200,
S400, or S800 speeds, respectively). When acting as a PCI bus master, the TSB82AA2B device is capable of
multiple cacheline bursts of data, which can transfer at 264M bytes/s for 64-bit transfers or 132M bytes/s for
32-bit transfers after connecting to the memory controller.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

OHCI-Lynx is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Copyright © 2007, Texas Instruments Incorporated

www.ti.com

TSB82AA2B

SLLS828A – MARCH 2007 – REVISED MARCH 2007

Due to the high throughput potential of the TSB82AA2B device, it possible to encounter large PCI and legacy
1394 bus latencies, which can cause the 1394 data to be overrun. To overcome this potential problem, the
TSB82AA2B implements deep transmit and receive FIFOs to buffer the 1394 data, thus preventing possible
problems due to bus latency. This also ensures that the device can transmit and receive sustained maximum
size isochronous or asynchronous data payloads at S800.

The TSB82AA2B device implements other performance enhancements to improve overall performance of the
device, such as: a highly tuned physical data path for enhanced SBP-2 performance, physical post writing
buffers, multiple isochronous contexts, and advanced internal arbitration.

The TSB82AA2B device also implements hardware enhancements to better support digital video (DV) and
MPEG data stream reception and transmission. These enhancements are enabled through the isochronous
receive digital video enhancements register at TI extension offset A80h. These enhancements include automatic
time stamp insertion for transmitted DV and MPEG-formatted streams and common isochronous packet (CIP)
header stripping for received DV streams.

The CIP format is defined by the IEC 61883-1:1998 specification. The enhancements to the isochronous data
contexts are implemented as hardware support for the synchronization timestamp for both DV and audio/video
CIP formats. The TSB82AA2B device supports modification of the synchronization timestamp field to ensure that
the value inserted via software is not stale—that is, less than the current cycle timer when the packet is
transmitted.

The TSB82AA2B performance and enhanced throughput make it an excellent choice for today’s 1394 PC
market; however, the portable, mobile, and even today’s desktop PCs power-management schemes continue to
require devices to use less and less power, and TI’s 1394 OHCI-Lynx product line has continued to raise the bar
by providing the lowest-power 1394 link layers in the industry. The TSB82AA2B device represents the next
evolution of the TI commitment to meet the challenge of power-sensitive applications. The TSB82AA2B device
has ultra-low operational power requirements and intelligent power management capabilities that allow it to
autonomously conserve power based on the device usage.

One of the key elements for reducing the TSB82AA2B operational power requirements is the TI advanced
CMOS process and the implementation of an internal 1.8-V core, which is supplied by an improved integrated

3.3-V to 1.8-V voltage regulator. The TSB82AA2B device implements a next-generation voltage regulator that is

more efficient than its predecessors, thus providing an overall reduction in the device’s operational power
requirements especially when operating in D3
supports D0, D1, D2, and D3

power states as specified in the PC 2001 Design Guide requirements and

hot/cold

the PCI Power Management Specification. PME wake event support is subject to operating system support and
implementation.

As required by the 1394 Open Host Controller Interface Specification (OHCI) and IEEE Std 1394a–2000, internal
control registers are memory-mapped and nonprefetchable. The PCI configuration header is accessed through
configuration cycles as specified by the PCI Local Bus Specification, and provides plug-and-play (PnP)
compatibility. Furthermore, the TSB82AA2B device is fully compliant with the latest PCI Local Bus Specification,

PCI Bus Power Management Interface Specification, IEEE Draft Std 1394b, IEEE Std 1394a–2000, and 1394
Open Host Controller Interface Specification.

using auxiliary power. In fact, the TSB82AA2B device fully

cold

NOTE:

This product is for high-volume PC applications only. For a complete data sheet or
more information, contact [e-mail].

2

Submit Documentation Feedback