TEXAS INSTRUMENTS TSB82AA2 Technical data

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1394b OHCI-Lynx Controller

TSB82AA2

SLLA221 – JUNE 2006

FEATURES

• Single 3.3-V supply (1.8-V internal core

• PCI burst transfers and deep FIFOs to

tolerate large host latency:

voltage with regulator) – Transmit FIFO—5K asynchronous

• 3.3-V and 5-V PCI signaling environments – Transmit FIFO—2K isochronous

• Serial bus data rates of 100M bits/s, 200M – Receive FIFO—2K asynchronous

bits/s, 400M bits/s, and 800M bits/s

• Physical write posting of up to three

outstanding transactions

– Receive FIFO—2K isochronous

• D0, D1, D2, and D3 power states and PME

events per the PCI Bus Power Management

• Serial ROM or boot ROM interface supports Interface Specification

2-wire serial EEPROM devices

• Programmable asynchronous transmit

• 33-MHz/64-bit and 33-MHz/32-bit selectable threshold

PCI interface

• Multifunction terminal (MFUNC terminal 1):

• Isochronous receive dual-buffer mode

• Out-of-order pipelining for asynchronous

– PCI_CLKRUN protocol per the PCI Mobile transmit requests

Design Guide

• Register access fail interrupt when the PHY

– General-purpose I/O SYSCLK is not active – CYCLEIN/CYCLEOUT for external cycle • Initial bandwidth available and initial

timer control for customized channels available registers synchronization

• Digital video and audio performance

enhancements

• Fabricated in advanced low-power CMOS

process

• Packaged in 144-terminal LQFP (PGE) or

176-ball MicroStar BGA (GGW)

DESCRIPTION

The TSB82AA2 OHCI-Lynx is a discrete 1394b link-layer device, which has been designed to meet the demanding requirements of today’s 1394 bus designs. The TSB82AA2 device is capable of exceptional 800M bits/s performance; thus, providing the throughput and bandwidth to move data efficiently and quickly between the PCI and 1394 buses. The TSB82AA2 device also provides outstanding ultra-low power operation and intelligent power management capabilities. The device provides the IEEE 1394 link function and is compatible with 100M bits/s, 200M bits/s, 400M bits/s, and 800M bits/s serial bus data rates.

The TSB82AA2 improved throughput and increased bandwidth make it ideal for today’s high-end PCs and open the door for the development of S800 RAID- and SAN-based peripherals.

The TSB82AA2 OHCI-Lynx operates as the interface between a 33-MHz/64-bit or 33-MHz/32-bit PCI local bus and a compatible 1394b PHY-layer device (such as the TSB81BA3 device) that is capable of supporting serial data rates at 98.304M, 196.608M, 393.216M, or 786.432M bits/s (referred to as S100, S200, S400, or S800 speeds, respectively). When acting as a PCI bus master, the TSB82AA2 device is capable of multiple cacheline bursts of data, which can transfer at 264M bytes/s for 64-bit transfers or 132M bytes/s for 32-bit transfers after connecting to the memory controller.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com

TSB82AA2

SLLA221 – JUNE 2006

Due to the high throughput potential of the TSB82AA2 device, it possible to encounter large PCI and legacy 1394 bus latencies, which can cause the 1394 data to be overrun. To overcome this potential problem, the TSB82AA2 implements deep transmit and receive FIFOs to buffer the 1394 data, thus preventing possible problems due to bus latency. This also ensures that the device can transmit and receive sustained maximum size isochronous or asynchronous data payloads at S800.

The TSB82AA2 device implements other performance enhancements to improve overall performance of the device, such as: a highly tuned physical data path for enhanced SBP-2 performance, physical post writing buffers, multiple isochronous contexts, and advanced internal arbitration.

The TSB82AA2 device also implements hardware enhancements to better support digital video (DV) and MPEG data stream reception and transmission. These enhancements are enabled through the isochronous receive digital video enhancements register at TI extension offset A80h. These enhancements include automatic time stamp insertion for transmitted DV and MPEG-formatted streams and common isochronous packet (CIP) header stripping for received DV streams.

The CIP format is defined by the IEC 61883-1:1998 specification. The enhancements to the isochronous data contexts are implemented as hardware support for the synchronization timestamp for both DV and audio/video CIP formats. The TSB82AA2 device supports modification of the synchronization timestamp field to ensure that the value inserted via software is not stale—that is, less than the current cycle timer when the packet is transmitted.

The TSB82AA2 performance and enhanced throughput make it an excellent choice for today’s 1394 PC market; however, the portable, mobile, and even today’s desktop PCs power management schemes continue to require devices to use less and less power, and Texas Instrument’s 1394 OHCI-Lynx product line has continued to raise the bar by providing the lowest power 1394 link-layers in the industry. The TSB82AA2 device represents the next evolution of Texas Instruments commitment to meet the challenge of power-sensitive applications. The TSB82AA2 device has ultra-low operational power requirements and intelligent power management capabilities that allow it to autonomously conserve power based on the device usage.

One of the key elements for reducing the TSB82AA2 operational power requirements is Texas Instrument’s advanced CMOS process and the implementation of an internal 1.8-V core, which is supplied by an improved integrated 3.3-V to 1.8-V voltage regulator. The TSB82AA2 device implements a next generation voltage regulator which is more efficient than its predecessors, thus providing an overall reduction in the device’s operational power requirements especially when operating in D3 device fully supports D0, D1, D2, and D3

hot/cold

power states as specified in the PC 2001 Design Guide requirements and the PCI Power Management Specification. PME wake event support is subject to operating system support and implementation.

As required by the 1394 Open Host Controller Interface Specification (OHCI) and IEEE Std 1394a–2000, internal control registers are memory-mapped and nonprefetchable. The PCI configuration header is accessed through configuration cycles as specified by the PCI Local Bus Specification, and provides plug-and-play (PnP) compatibility. Furthermore, the TSB82AA2 device is fully compliant with the latest PCI Local Bus Specification,

PCI Bus Power Management Interface Specification, IEEE Draft Std 1394b, IEEE Std 1394a–2000, and 1394 Open Host Controller Interface Specification.

using auxiliary power. In fact, the TSB82AA2

cold

NOTE:

This product is for high-volume PC applications only. For a complete datasheet or more information contact support@ti.com.

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PACKAGE OPTION ADDENDUM

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24-Sep-2007

PACKAGING INFORMATION

Orderable Device Status

TSB82AA2GGW ACTIVE BGA MI

(1)

Package

Type

Package Drawing

Pins Package

Qty

Eco Plan

GGW 176 126 TBD SNPB Level-3-220C-168 HR

CROSTA

TSB82AA2IPGE ACTIVE LQFP PGE 144 60 TBD CU NIPDAU Level-1-235C-UNLIM

TSB82AA2PGE ACTIVE LQFP PGE 144 60 Green (RoHS &

no Sb/Br)

TSB82AA2PGEG4 ACTIVE LQFP PGE 144 60 Green (RoHS &

no Sb/Br)

TSB82AA2ZGW ACTIVE BGA MI

CROSTA

ZGW 176 126 Green (RoHS &

no Sb/Br)

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-3-260C-168 HR

SNAGCU Level-3-260C-168 HR

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

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